arch/arm64/boot/dts/renesas/r9a07g043u.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the RZ/G2UL SoC
   4  *
   5  * Copyright (C) 2022 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 #define SOC_PERIPHERAL_IRQ(nr)          GIC_SPI nr
  11
  12 #include "r9a07g043.dtsi"
  13
  14 / {
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a55";
  21                         reg = <0>;
  22                         device_type = "cpu";
  23                         #cooling-cells = <2>;
  24                         next-level-cache = <&L3_CA55>;
  25                         enable-method = "psci";
  26                         clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
  27                         operating-points-v2 = <&cluster0_opp>;
  28                 };
  29
  30                 L3_CA55: cache-controller-0 {
  31                         compatible = "cache";
  32                         cache-unified;
  33                         cache-size = <0x40000>;
  34                         cache-level = <3>;
  35                 };
  36         };
  37
  38         pmu {
  39                 compatible = "arm,cortex-a55-pmu";
  40                 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
  41         };
  42
  43         psci {
  44                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  45                 method = "smc";
  46         };
  47
  48         timer {
  49                 compatible = "arm,armv8-timer";
  50                 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  51                                       <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  52                                       <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  53                                       <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  54         };
  55 };
  56
  57 &pinctrl {
  58         interrupt-parent = <&irqc>;
  59 };
  60
  61 &soc {
  62         interrupt-parent = <&gic>;
  63
  64         cru: video@10830000 {
  65                 compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru";
  66                 reg = <0 0x10830000 0 0x400>;
  67                 clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
  68                          <&cpg CPG_MOD R9A07G043_CRU_PCLK>,
  69                          <&cpg CPG_MOD R9A07G043_CRU_ACLK>;
  70                 clock-names = "video", "apb", "axi";
  71                 interrupts = <SOC_PERIPHERAL_IRQ(167) IRQ_TYPE_LEVEL_HIGH>,
  72                              <SOC_PERIPHERAL_IRQ(168) IRQ_TYPE_LEVEL_HIGH>,
  73                              <SOC_PERIPHERAL_IRQ(169) IRQ_TYPE_LEVEL_HIGH>;
  74                 interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
  75                 resets = <&cpg R9A07G043_CRU_PRESETN>,
  76                          <&cpg R9A07G043_CRU_ARESETN>;
  77                 reset-names = "presetn", "aresetn";
  78                 power-domains = <&cpg>;
  79                 status = "disabled";
  80
  81                 ports {
  82                         #address-cells = <1>;
  83                         #size-cells = <0>;
  84
  85                         port@1 {
  86                                 #address-cells = <1>;
  87                                 #size-cells = <0>;
  88
  89                                 reg = <1>;
  90                                 crucsi2: endpoint@0 {
  91                                         reg = <0>;
  92                                         remote-endpoint = <&csi2cru>;
  93                                 };
  94                         };
  95                 };
  96         };
  97
  98         csi2: csi2@10830400 {
  99                 compatible = "renesas,r9a07g043-csi2", "renesas,rzg2l-csi2";
 100                 reg = <0 0x10830400 0 0xfc00>;
 101                 interrupts = <SOC_PERIPHERAL_IRQ(166) IRQ_TYPE_LEVEL_HIGH>;
 102                 clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>,
 103                          <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
 104                          <&cpg CPG_MOD R9A07G043_CRU_PCLK>;
 105                 clock-names = "system", "video", "apb";
 106                 resets = <&cpg R9A07G043_CRU_PRESETN>,
 107                          <&cpg R9A07G043_CRU_CMN_RSTB>;
 108                 reset-names = "presetn", "cmn-rstb";
 109                 power-domains = <&cpg>;
 110                 status = "disabled";
 111
 112                 ports {
 113                         #address-cells = <1>;
 114                         #size-cells = <0>;
 115
 116                         port@0 {
 117                                 reg = <0>;
 118                         };
 119
 120                         port@1 {
 121                                 #address-cells = <1>;
 122                                 #size-cells = <0>;
 123                                 reg = <1>;
 124
 125                                 csi2cru: endpoint@0 {
 126                                         reg = <0>;
 127                                         remote-endpoint = <&crucsi2>;
 128                                 };
 129                         };
 130                 };
 131         };
 132
 133         irqc: interrupt-controller@110a0000 {
 134                 compatible = "renesas,r9a07g043u-irqc",
 135                              "renesas,rzg2l-irqc";
 136                 reg = <0 0x110a0000 0 0x10000>;
 137                 #interrupt-cells = <2>;
 138                 #address-cells = <0>;
 139                 interrupt-controller;
 140                 interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>,
 141                              <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
 142                              <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
 143                              <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>,
 144                              <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>,
 145                              <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>,
 146                              <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>,
 147                              <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>,
 148                              <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>,
 149                              <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>,
 150                              <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>,
 151                              <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>,
 152                              <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>,
 153                              <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>,
 154                              <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>,
 155                              <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>,
 156                              <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>,
 157                              <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>,
 158                              <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>,
 159                              <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>,
 160                              <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>,
 161                              <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>,
 162                              <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>,
 163                              <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>,
 164                              <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>,
 165                              <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>,
 166                              <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>,
 167                              <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>,
 168                              <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>,
 169                              <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>,
 170                              <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>,
 171                              <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>,
 172                              <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>,
 173                              <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>,
 174                              <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>,
 175                              <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>,
 176                              <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>,
 177                              <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>,
 178                              <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
 179                              <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
 180                              <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
 181                              <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>,
 182                              <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>,
 183                              <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>,
 184                              <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>,
 185                              <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>,
 186                              <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>,
 187                              <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>;
 188                 interrupt-names = "nmi",
 189                                   "irq0", "irq1", "irq2", "irq3",
 190                                   "irq4", "irq5", "irq6", "irq7",
 191                                   "tint0", "tint1", "tint2", "tint3",
 192                                   "tint4", "tint5", "tint6", "tint7",
 193                                   "tint8", "tint9", "tint10", "tint11",
 194                                   "tint12", "tint13", "tint14", "tint15",
 195                                   "tint16", "tint17", "tint18", "tint19",
 196                                   "tint20", "tint21", "tint22", "tint23",
 197                                   "tint24", "tint25", "tint26", "tint27",
 198                                   "tint28", "tint29", "tint30", "tint31",
 199                                   "bus-err", "ec7tie1-0", "ec7tie2-0",
 200                                   "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
 201                                   "ec7tiovf-1";
 202                 clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
 203                         <&cpg CPG_MOD R9A07G043_IA55_PCLK>;
 204                 clock-names = "clk", "pclk";
 205                 power-domains = <&cpg>;
 206                 resets = <&cpg R9A07G043_IA55_RESETN>;
 207         };
 208
 209         gic: interrupt-controller@11900000 {
 210                 compatible = "arm,gic-v3";
 211                 #interrupt-cells = <3>;
 212                 #address-cells = <0>;
 213                 interrupt-controller;
 214                 reg = <0x0 0x11900000 0 0x40000>,
 215                       <0x0 0x11940000 0 0x60000>;
 216                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 217         };
 218 };
 219
 220 &sysc {
 221         interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
 222                      <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
 223                      <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
 224                      <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
 225         interrupt-names = "lpm_int", "ca55stbydone_int",
 226                           "cm33stbyr_int", "ca55_deny";
 227 };