arch/arm64/boot/dts/renesas/r8a7796.dtsi

   1 /*
   2  * Device Tree Source for the r8a7796 SoC
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/power/r8a7796-sysc.h>
  14
  15 / {
  16         compatible = "renesas,r8a7796";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         psci {
  21                 compatible = "arm,psci-0.2";
  22                 method = "smc";
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 /* 1 core only at this point */
  30                 a57_0: cpu@0 {
  31                         compatible = "arm,cortex-a57", "arm,armv8";
  32                         reg = <0x0>;
  33                         device_type = "cpu";
  34                         power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
  35                         next-level-cache = <&L2_CA57>;
  36                         enable-method = "psci";
  37                 };
  38
  39                 L2_CA57: cache-controller@0 {
  40                         compatible = "cache";
  41                         reg = <0>;
  42                         power-domains = <&sysc R8A7796_PD_CA57_SCU>;
  43                         cache-unified;
  44                         cache-level = <2>;
  45                 };
  46         };
  47
  48         extal_clk: extal {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 /* This value must be overridden by the board */
  52                 clock-frequency = <0>;
  53         };
  54
  55         extalr_clk: extalr {
  56                 compatible = "fixed-clock";
  57                 #clock-cells = <0>;
  58                 /* This value must be overridden by the board */
  59                 clock-frequency = <0>;
  60         };
  61
  62         /* External SCIF clock - to be overridden by boards that provide it */
  63         scif_clk: scif {
  64                 compatible = "fixed-clock";
  65                 #clock-cells = <0>;
  66                 clock-frequency = <0>;
  67         };
  68
  69         soc {
  70                 compatible = "simple-bus";
  71                 interrupt-parent = <&gic>;
  72                 #address-cells = <2>;
  73                 #size-cells = <2>;
  74                 ranges;
  75
  76                 gic: interrupt-controller@f1010000 {
  77                         compatible = "arm,gic-400";
  78                         #interrupt-cells = <3>;
  79                         #address-cells = <0>;
  80                         interrupt-controller;
  81                         reg = <0x0 0xf1010000 0 0x1000>,
  82                               <0x0 0xf1020000 0 0x20000>,
  83                               <0x0 0xf1040000 0 0x20000>,
  84                               <0x0 0xf1060000 0 0x20000>;
  85                         interrupts = <GIC_PPI 9
  86                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  87                 };
  88
  89                 timer {
  90                         compatible = "arm,armv8-timer";
  91                         interrupts = <GIC_PPI 13
  92                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  93                                      <GIC_PPI 14
  94                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  95                                      <GIC_PPI 11
  96                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  97                                      <GIC_PPI 10
  98                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  99                 };
 100
 101                 cpg: clock-controller@e6150000 {
 102                         compatible = "renesas,r8a7796-cpg-mssr";
 103                         reg = <0 0xe6150000 0 0x1000>;
 104                         clocks = <&extal_clk>, <&extalr_clk>;
 105                         clock-names = "extal", "extalr";
 106                         #clock-cells = <2>;
 107                         #power-domain-cells = <0>;
 108                 };
 109
 110                 sysc: system-controller@e6180000 {
 111                         compatible = "renesas,r8a7796-sysc";
 112                         reg = <0 0xe6180000 0 0x0400>;
 113                         #power-domain-cells = <1>;
 114                 };
 115
 116                 scif2: serial@e6e88000 {
 117                         compatible = "renesas,scif-r8a7796",
 118                                      "renesas,rcar-gen3-scif", "renesas,scif";
 119                         reg = <0 0xe6e88000 0 64>;
 120                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 121                         clocks = <&cpg CPG_MOD 310>,
 122                                  <&cpg CPG_CORE R8A7796_CLK_S3D1>,
 123                                  <&scif_clk>;
 124                         clock-names = "fck", "brg_int", "scif_clk";
 125                         power-domains = <&cpg>;
 126                         status = "disabled";
 127                 };
 128         };
 129 };