arch/arm64/boot/dts/qcom/sm8550.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2022, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/clock/qcom,rpmh.h>
   7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
   8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
   9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
  10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
  11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
  12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
  13 #include <dt-bindings/dma/qcom-gpi.h>
  14 #include <dt-bindings/firmware/qcom,scm.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
  18 #include <dt-bindings/mailbox/qcom-ipcc.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/power/qcom,rpmhpd.h>
  21 #include <dt-bindings/soc/qcom,gpr.h>
  22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
  24 #include <dt-bindings/phy/phy-qcom-qmp.h>
  25 #include <dt-bindings/thermal/thermal.h>
  26
  27 / {
  28         interrupt-parent = <&intc>;
  29
  30         #address-cells = <2>;
  31         #size-cells = <2>;
  32
  33         chosen { };
  34
  35         clocks {
  36                 xo_board: xo-board {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                 };
  40
  41                 sleep_clk: sleep-clk {
  42                         compatible = "fixed-clock";
  43                         #clock-cells = <0>;
  44                 };
  45
  46                 bi_tcxo_div2: bi-tcxo-div2-clk {
  47                         #clock-cells = <0>;
  48                         compatible = "fixed-factor-clock";
  49                         clocks = <&rpmhcc RPMH_CXO_CLK>;
  50                         clock-mult = <1>;
  51                         clock-div = <2>;
  52                 };
  53
  54                 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
  55                         #clock-cells = <0>;
  56                         compatible = "fixed-factor-clock";
  57                         clocks = <&rpmhcc RPMH_CXO_CLK_A>;
  58                         clock-mult = <1>;
  59                         clock-div = <2>;
  60                 };
  61
  62                 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
  63                         compatible = "fixed-clock";
  64                         #clock-cells = <0>;
  65                 };
  66         };
  67
  68         cpus {
  69                 #address-cells = <2>;
  70                 #size-cells = <0>;
  71
  72                 CPU0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a510";
  75                         reg = <0 0>;
  76                         clocks = <&cpufreq_hw 0>;
  77                         enable-method = "psci";
  78                         next-level-cache = <&L2_0>;
  79                         power-domains = <&CPU_PD0>;
  80                         power-domain-names = "psci";
  81                         qcom,freq-domain = <&cpufreq_hw 0>;
  82                         capacity-dmips-mhz = <1024>;
  83                         dynamic-power-coefficient = <100>;
  84                         #cooling-cells = <2>;
  85                         L2_0: l2-cache {
  86                                 compatible = "cache";
  87                                 cache-level = <2>;
  88                                 cache-unified;
  89                                 next-level-cache = <&L3_0>;
  90                                 L3_0: l3-cache {
  91                                         compatible = "cache";
  92                                         cache-level = <3>;
  93                                         cache-unified;
  94                                 };
  95                         };
  96                 };
  97
  98                 CPU1: cpu@100 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a510";
 101                         reg = <0 0x100>;
 102                         clocks = <&cpufreq_hw 0>;
 103                         enable-method = "psci";
 104                         next-level-cache = <&L2_100>;
 105                         power-domains = <&CPU_PD1>;
 106                         power-domain-names = "psci";
 107                         qcom,freq-domain = <&cpufreq_hw 0>;
 108                         capacity-dmips-mhz = <1024>;
 109                         dynamic-power-coefficient = <100>;
 110                         #cooling-cells = <2>;
 111                         L2_100: l2-cache {
 112                                 compatible = "cache";
 113                                 cache-level = <2>;
 114                                 cache-unified;
 115                                 next-level-cache = <&L3_0>;
 116                         };
 117                 };
 118
 119                 CPU2: cpu@200 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a510";
 122                         reg = <0 0x200>;
 123                         clocks = <&cpufreq_hw 0>;
 124                         enable-method = "psci";
 125                         next-level-cache = <&L2_200>;
 126                         power-domains = <&CPU_PD2>;
 127                         power-domain-names = "psci";
 128                         qcom,freq-domain = <&cpufreq_hw 0>;
 129                         capacity-dmips-mhz = <1024>;
 130                         dynamic-power-coefficient = <100>;
 131                         #cooling-cells = <2>;
 132                         L2_200: l2-cache {
 133                                 compatible = "cache";
 134                                 cache-level = <2>;
 135                                 cache-unified;
 136                                 next-level-cache = <&L3_0>;
 137                         };
 138                 };
 139
 140                 CPU3: cpu@300 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a715";
 143                         reg = <0 0x300>;
 144                         clocks = <&cpufreq_hw 1>;
 145                         enable-method = "psci";
 146                         next-level-cache = <&L2_300>;
 147                         power-domains = <&CPU_PD3>;
 148                         power-domain-names = "psci";
 149                         qcom,freq-domain = <&cpufreq_hw 1>;
 150                         capacity-dmips-mhz = <1792>;
 151                         dynamic-power-coefficient = <270>;
 152                         #cooling-cells = <2>;
 153                         L2_300: l2-cache {
 154                                 compatible = "cache";
 155                                 cache-level = <2>;
 156                                 cache-unified;
 157                                 next-level-cache = <&L3_0>;
 158                         };
 159                 };
 160
 161                 CPU4: cpu@400 {
 162                         device_type = "cpu";
 163                         compatible = "arm,cortex-a715";
 164                         reg = <0 0x400>;
 165                         clocks = <&cpufreq_hw 1>;
 166                         enable-method = "psci";
 167                         next-level-cache = <&L2_400>;
 168                         power-domains = <&CPU_PD4>;
 169                         power-domain-names = "psci";
 170                         qcom,freq-domain = <&cpufreq_hw 1>;
 171                         capacity-dmips-mhz = <1792>;
 172                         dynamic-power-coefficient = <270>;
 173                         #cooling-cells = <2>;
 174                         L2_400: l2-cache {
 175                                 compatible = "cache";
 176                                 cache-level = <2>;
 177                                 cache-unified;
 178                                 next-level-cache = <&L3_0>;
 179                         };
 180                 };
 181
 182                 CPU5: cpu@500 {
 183                         device_type = "cpu";
 184                         compatible = "arm,cortex-a710";
 185                         reg = <0 0x500>;
 186                         clocks = <&cpufreq_hw 1>;
 187                         enable-method = "psci";
 188                         next-level-cache = <&L2_500>;
 189                         power-domains = <&CPU_PD5>;
 190                         power-domain-names = "psci";
 191                         qcom,freq-domain = <&cpufreq_hw 1>;
 192                         capacity-dmips-mhz = <1792>;
 193                         dynamic-power-coefficient = <270>;
 194                         #cooling-cells = <2>;
 195                         L2_500: l2-cache {
 196                                 compatible = "cache";
 197                                 cache-level = <2>;
 198                                 cache-unified;
 199                                 next-level-cache = <&L3_0>;
 200                         };
 201                 };
 202
 203                 CPU6: cpu@600 {
 204                         device_type = "cpu";
 205                         compatible = "arm,cortex-a710";
 206                         reg = <0 0x600>;
 207                         clocks = <&cpufreq_hw 1>;
 208                         enable-method = "psci";
 209                         next-level-cache = <&L2_600>;
 210                         power-domains = <&CPU_PD6>;
 211                         power-domain-names = "psci";
 212                         qcom,freq-domain = <&cpufreq_hw 1>;
 213                         capacity-dmips-mhz = <1792>;
 214                         dynamic-power-coefficient = <270>;
 215                         #cooling-cells = <2>;
 216                         L2_600: l2-cache {
 217                                 compatible = "cache";
 218                                 cache-level = <2>;
 219                                 cache-unified;
 220                                 next-level-cache = <&L3_0>;
 221                         };
 222                 };
 223
 224                 CPU7: cpu@700 {
 225                         device_type = "cpu";
 226                         compatible = "arm,cortex-x3";
 227                         reg = <0 0x700>;
 228                         clocks = <&cpufreq_hw 2>;
 229                         enable-method = "psci";
 230                         next-level-cache = <&L2_700>;
 231                         power-domains = <&CPU_PD7>;
 232                         power-domain-names = "psci";
 233                         qcom,freq-domain = <&cpufreq_hw 2>;
 234                         capacity-dmips-mhz = <1894>;
 235                         dynamic-power-coefficient = <588>;
 236                         #cooling-cells = <2>;
 237                         L2_700: l2-cache {
 238                                 compatible = "cache";
 239                                 cache-level = <2>;
 240                                 cache-unified;
 241                                 next-level-cache = <&L3_0>;
 242                         };
 243                 };
 244
 245                 cpu-map {
 246                         cluster0 {
 247                                 core0 {
 248                                         cpu = <&CPU0>;
 249                                 };
 250
 251                                 core1 {
 252                                         cpu = <&CPU1>;
 253                                 };
 254
 255                                 core2 {
 256                                         cpu = <&CPU2>;
 257                                 };
 258
 259                                 core3 {
 260                                         cpu = <&CPU3>;
 261                                 };
 262
 263                                 core4 {
 264                                         cpu = <&CPU4>;
 265                                 };
 266
 267                                 core5 {
 268                                         cpu = <&CPU5>;
 269                                 };
 270
 271                                 core6 {
 272                                         cpu = <&CPU6>;
 273                                 };
 274
 275                                 core7 {
 276                                         cpu = <&CPU7>;
 277                                 };
 278                         };
 279                 };
 280
 281                 idle-states {
 282                         entry-method = "psci";
 283
 284                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 285                                 compatible = "arm,idle-state";
 286                                 idle-state-name = "silver-rail-power-collapse";
 287                                 arm,psci-suspend-param = <0x40000004>;
 288                                 entry-latency-us = <550>;
 289                                 exit-latency-us = <750>;
 290                                 min-residency-us = <6700>;
 291                                 local-timer-stop;
 292                         };
 293
 294                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 295                                 compatible = "arm,idle-state";
 296                                 idle-state-name = "gold-rail-power-collapse";
 297                                 arm,psci-suspend-param = <0x40000004>;
 298                                 entry-latency-us = <600>;
 299                                 exit-latency-us = <1300>;
 300                                 min-residency-us = <8136>;
 301                                 local-timer-stop;
 302                         };
 303
 304                         PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
 305                                 compatible = "arm,idle-state";
 306                                 idle-state-name = "goldplus-rail-power-collapse";
 307                                 arm,psci-suspend-param = <0x40000004>;
 308                                 entry-latency-us = <500>;
 309                                 exit-latency-us = <1350>;
 310                                 min-residency-us = <7480>;
 311                                 local-timer-stop;
 312                         };
 313                 };
 314
 315                 domain-idle-states {
 316                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 317                                 compatible = "domain-idle-state";
 318                                 arm,psci-suspend-param = <0x41000044>;
 319                                 entry-latency-us = <750>;
 320                                 exit-latency-us = <2350>;
 321                                 min-residency-us = <9144>;
 322                         };
 323
 324                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 325                                 compatible = "domain-idle-state";
 326                                 arm,psci-suspend-param = <0x4100c344>;
 327                                 entry-latency-us = <2800>;
 328                                 exit-latency-us = <4400>;
 329                                 min-residency-us = <10150>;
 330                         };
 331                 };
 332         };
 333
 334         firmware {
 335                 scm: scm {
 336                         compatible = "qcom,scm-sm8550", "qcom,scm";
 337                         qcom,dload-mode = <&tcsr 0x19000>;
 338                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 339                 };
 340         };
 341
 342         clk_virt: interconnect-0 {
 343                 compatible = "qcom,sm8550-clk-virt";
 344                 #interconnect-cells = <2>;
 345                 qcom,bcm-voters = <&apps_bcm_voter>;
 346         };
 347
 348         mc_virt: interconnect-1 {
 349                 compatible = "qcom,sm8550-mc-virt";
 350                 #interconnect-cells = <2>;
 351                 qcom,bcm-voters = <&apps_bcm_voter>;
 352         };
 353
 354         memory@a0000000 {
 355                 device_type = "memory";
 356                 /* We expect the bootloader to fill in the size */
 357                 reg = <0 0xa0000000 0 0>;
 358         };
 359
 360         pmu {
 361                 compatible = "arm,armv8-pmuv3";
 362                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 363         };
 364
 365         psci {
 366                 compatible = "arm,psci-1.0";
 367                 method = "smc";
 368
 369                 CPU_PD0: power-domain-cpu0 {
 370                         #power-domain-cells = <0>;
 371                         power-domains = <&CLUSTER_PD>;
 372                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 373                 };
 374
 375                 CPU_PD1: power-domain-cpu1 {
 376                         #power-domain-cells = <0>;
 377                         power-domains = <&CLUSTER_PD>;
 378                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 379                 };
 380
 381                 CPU_PD2: power-domain-cpu2 {
 382                         #power-domain-cells = <0>;
 383                         power-domains = <&CLUSTER_PD>;
 384                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 385                 };
 386
 387                 CPU_PD3: power-domain-cpu3 {
 388                         #power-domain-cells = <0>;
 389                         power-domains = <&CLUSTER_PD>;
 390                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 391                 };
 392
 393                 CPU_PD4: power-domain-cpu4 {
 394                         #power-domain-cells = <0>;
 395                         power-domains = <&CLUSTER_PD>;
 396                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 397                 };
 398
 399                 CPU_PD5: power-domain-cpu5 {
 400                         #power-domain-cells = <0>;
 401                         power-domains = <&CLUSTER_PD>;
 402                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 403                 };
 404
 405                 CPU_PD6: power-domain-cpu6 {
 406                         #power-domain-cells = <0>;
 407                         power-domains = <&CLUSTER_PD>;
 408                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 409                 };
 410
 411                 CPU_PD7: power-domain-cpu7 {
 412                         #power-domain-cells = <0>;
 413                         power-domains = <&CLUSTER_PD>;
 414                         domain-idle-states = <&PRIME_CPU_SLEEP_0>;
 415                 };
 416
 417                 CLUSTER_PD: power-domain-cluster {
 418                         #power-domain-cells = <0>;
 419                         domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
 420                 };
 421         };
 422
 423         reserved_memory: reserved-memory {
 424                 #address-cells = <2>;
 425                 #size-cells = <2>;
 426                 ranges;
 427
 428                 hyp_mem: hyp-region@80000000 {
 429                         reg = <0 0x80000000 0 0xa00000>;
 430                         no-map;
 431                 };
 432
 433                 cpusys_vm_mem: cpusys-vm-region@80a00000 {
 434                         reg = <0 0x80a00000 0 0x400000>;
 435                         no-map;
 436                 };
 437
 438                 hyp_tags_mem: hyp-tags-region@80e00000 {
 439                         reg = <0 0x80e00000 0 0x3d0000>;
 440                         no-map;
 441                 };
 442
 443                 xbl_sc_mem: xbl-sc-region@d8100000 {
 444                         reg = <0 0xd8100000 0 0x40000>;
 445                         no-map;
 446                 };
 447
 448                 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
 449                         reg = <0 0x811d0000 0 0x30000>;
 450                         no-map;
 451                 };
 452
 453                 /* merged xbl_dt_log, xbl_ramdump, aop_image */
 454                 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
 455                         reg = <0 0x81a00000 0 0x260000>;
 456                         no-map;
 457                 };
 458
 459                 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
 460                         compatible = "qcom,cmd-db";
 461                         reg = <0 0x81c60000 0 0x20000>;
 462                         no-map;
 463                 };
 464
 465                 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */
 466                 aop_config_merged_mem: aop-config-merged-region@81c80000 {
 467                         reg = <0 0x81c80000 0 0x74000>;
 468                         no-map;
 469                 };
 470
 471                 /* secdata region can be reused by apps */
 472                 smem: smem@81d00000 {
 473                         compatible = "qcom,smem";
 474                         reg = <0 0x81d00000 0 0x200000>;
 475                         hwlocks = <&tcsr_mutex 3>;
 476                         no-map;
 477                 };
 478
 479                 adsp_mhi_mem: adsp-mhi-region@81f00000 {
 480                         reg = <0 0x81f00000 0 0x20000>;
 481                         no-map;
 482                 };
 483
 484                 global_sync_mem: global-sync-region@82600000 {
 485                         reg = <0 0x82600000 0 0x100000>;
 486                         no-map;
 487                 };
 488
 489                 tz_stat_mem: tz-stat-region@82700000 {
 490                         reg = <0 0x82700000 0 0x100000>;
 491                         no-map;
 492                 };
 493
 494                 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
 495                         reg = <0 0x82800000 0 0x4600000>;
 496                         no-map;
 497                 };
 498
 499                 mpss_mem: mpss-region@8a800000 {
 500                         reg = <0 0x8a800000 0 0x10800000>;
 501                         no-map;
 502                 };
 503
 504                 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
 505                         reg = <0 0x9b000000 0 0x80000>;
 506                         no-map;
 507                 };
 508
 509                 ipa_fw_mem: ipa-fw-region@9b080000 {
 510                         reg = <0 0x9b080000 0 0x10000>;
 511                         no-map;
 512                 };
 513
 514                 ipa_gsi_mem: ipa-gsi-region@9b090000 {
 515                         reg = <0 0x9b090000 0 0xa000>;
 516                         no-map;
 517                 };
 518
 519                 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
 520                         reg = <0 0x9b09a000 0 0x2000>;
 521                         no-map;
 522                 };
 523
 524                 spss_region_mem: spss-region@9b100000 {
 525                         reg = <0 0x9b100000 0 0x180000>;
 526                         no-map;
 527                 };
 528
 529                 /* First part of the "SPU secure shared memory" region */
 530                 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
 531                         reg = <0 0x9b280000 0 0x60000>;
 532                         no-map;
 533                 };
 534
 535                 /* Second part of the "SPU secure shared memory" region */
 536                 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
 537                         reg = <0 0x9b2e0000 0 0x20000>;
 538                         no-map;
 539                 };
 540
 541                 camera_mem: camera-region@9b300000 {
 542                         reg = <0 0x9b300000 0 0x800000>;
 543                         no-map;
 544                 };
 545
 546                 video_mem: video-region@9bb00000 {
 547                         reg = <0 0x9bb00000 0 0x700000>;
 548                         no-map;
 549                 };
 550
 551                 cvp_mem: cvp-region@9c200000 {
 552                         reg = <0 0x9c200000 0 0x700000>;
 553                         no-map;
 554                 };
 555
 556                 cdsp_mem: cdsp-region@9c900000 {
 557                         reg = <0 0x9c900000 0 0x2000000>;
 558                         no-map;
 559                 };
 560
 561                 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
 562                         reg = <0 0x9e900000 0 0x80000>;
 563                         no-map;
 564                 };
 565
 566                 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
 567                         reg = <0 0x9e980000 0 0x80000>;
 568                         no-map;
 569                 };
 570
 571                 adspslpi_mem: adspslpi-region@9ea00000 {
 572                         reg = <0 0x9ea00000 0 0x4080000>;
 573                         no-map;
 574                 };
 575
 576                 /* uefi region can be reused by apps */
 577
 578                 /* Linux kernel image is loaded at 0xa8000000 */
 579
 580                 rmtfs_mem: rmtfs-region@d4a80000 {
 581                         compatible = "qcom,rmtfs-mem";
 582                         reg = <0x0 0xd4a80000 0x0 0x280000>;
 583                         no-map;
 584
 585                         qcom,client-id = <1>;
 586                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
 587                 };
 588
 589                 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
 590                         reg = <0 0xd4d00000 0 0x3300000>;
 591                         no-map;
 592                 };
 593
 594                 tz_reserved_mem: tz-reserved-region@d8000000 {
 595                         reg = <0 0xd8000000 0 0x100000>;
 596                         no-map;
 597                 };
 598
 599                 cpucp_fw_mem: cpucp-fw-region@d8140000 {
 600                         reg = <0 0xd8140000 0 0x1c0000>;
 601                         no-map;
 602                 };
 603
 604                 qtee_mem: qtee-region@d8300000 {
 605                         reg = <0 0xd8300000 0 0x500000>;
 606                         no-map;
 607                 };
 608
 609                 ta_mem: ta-region@d8800000 {
 610                         reg = <0 0xd8800000 0 0x8a00000>;
 611                         no-map;
 612                 };
 613
 614                 tz_tags_mem: tz-tags-region@e1200000 {
 615                         reg = <0 0xe1200000 0 0x2740000>;
 616                         no-map;
 617                 };
 618
 619                 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
 620                         reg = <0 0xe6440000 0 0x279000>;
 621                         no-map;
 622                 };
 623
 624                 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
 625                         reg = <0 0xf3600000 0 0x4aee000>;
 626                         no-map;
 627                 };
 628
 629                 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
 630                         reg = <0 0xf80ee000 0 0x1000>;
 631                         no-map;
 632                 };
 633
 634                 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
 635                         reg = <0 0xf80ef000 0 0x9000>;
 636                         no-map;
 637                 };
 638
 639                 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
 640                         reg = <0 0xf80f8000 0 0x4000>;
 641                         no-map;
 642                 };
 643
 644                 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
 645                         reg = <0 0xf80fc000 0 0x4000>;
 646                         no-map;
 647                 };
 648
 649                 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
 650                         reg = <0 0xf8100000 0 0x100000>;
 651                         no-map;
 652                 };
 653
 654                 oem_vm_mem: oem-vm-region@f8400000 {
 655                         reg = <0 0xf8400000 0 0x4800000>;
 656                         no-map;
 657                 };
 658
 659                 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
 660                         reg = <0 0xfcc00000 0 0x4000>;
 661                         no-map;
 662                 };
 663
 664                 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
 665                         reg = <0 0xfcc04000 0 0x100000>;
 666                         no-map;
 667                 };
 668
 669                 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
 670                         reg = <0 0xfce00000 0 0x2900000>;
 671                         no-map;
 672                 };
 673
 674                 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
 675                         reg = <0 0xff700000 0 0x100000>;
 676                         no-map;
 677                 };
 678         };
 679
 680         smp2p-adsp {
 681                 compatible = "qcom,smp2p";
 682                 qcom,smem = <443>, <429>;
 683                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 684                                              IPCC_MPROC_SIGNAL_SMP2P
 685                                              IRQ_TYPE_EDGE_RISING>;
 686                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 687                                 IPCC_MPROC_SIGNAL_SMP2P>;
 688
 689                 qcom,local-pid = <0>;
 690                 qcom,remote-pid = <2>;
 691
 692                 smp2p_adsp_out: master-kernel {
 693                         qcom,entry-name = "master-kernel";
 694                         #qcom,smem-state-cells = <1>;
 695                 };
 696
 697                 smp2p_adsp_in: slave-kernel {
 698                         qcom,entry-name = "slave-kernel";
 699                         interrupt-controller;
 700                         #interrupt-cells = <2>;
 701                 };
 702         };
 703
 704         smp2p-cdsp {
 705                 compatible = "qcom,smp2p";
 706                 qcom,smem = <94>, <432>;
 707                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 708                                              IPCC_MPROC_SIGNAL_SMP2P
 709                                              IRQ_TYPE_EDGE_RISING>;
 710                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 711                                 IPCC_MPROC_SIGNAL_SMP2P>;
 712
 713                 qcom,local-pid = <0>;
 714                 qcom,remote-pid = <5>;
 715
 716                 smp2p_cdsp_out: master-kernel {
 717                         qcom,entry-name = "master-kernel";
 718                         #qcom,smem-state-cells = <1>;
 719                 };
 720
 721                 smp2p_cdsp_in: slave-kernel {
 722                         qcom,entry-name = "slave-kernel";
 723                         interrupt-controller;
 724                         #interrupt-cells = <2>;
 725                 };
 726         };
 727
 728         smp2p-modem {
 729                 compatible = "qcom,smp2p";
 730                 qcom,smem = <435>, <428>;
 731                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 732                                              IPCC_MPROC_SIGNAL_SMP2P
 733                                              IRQ_TYPE_EDGE_RISING>;
 734                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 735                                 IPCC_MPROC_SIGNAL_SMP2P>;
 736
 737                 qcom,local-pid = <0>;
 738                 qcom,remote-pid = <1>;
 739
 740                 smp2p_modem_out: master-kernel {
 741                         qcom,entry-name = "master-kernel";
 742                         #qcom,smem-state-cells = <1>;
 743                 };
 744
 745                 smp2p_modem_in: slave-kernel {
 746                         qcom,entry-name = "slave-kernel";
 747                         interrupt-controller;
 748                         #interrupt-cells = <2>;
 749                 };
 750
 751                 ipa_smp2p_out: ipa-ap-to-modem {
 752                         qcom,entry-name = "ipa";
 753                         #qcom,smem-state-cells = <1>;
 754                 };
 755
 756                 ipa_smp2p_in: ipa-modem-to-ap {
 757                         qcom,entry-name = "ipa";
 758                         interrupt-controller;
 759                         #interrupt-cells = <2>;
 760                 };
 761         };
 762
 763         soc: soc@0 {
 764                 compatible = "simple-bus";
 765                 ranges = <0 0 0 0 0x10 0>;
 766                 dma-ranges = <0 0 0 0 0x10 0>;
 767
 768                 #address-cells = <2>;
 769                 #size-cells = <2>;
 770
 771                 gcc: clock-controller@100000 {
 772                         compatible = "qcom,sm8550-gcc";
 773                         reg = <0 0x00100000 0 0x1f4200>;
 774                         #clock-cells = <1>;
 775                         #reset-cells = <1>;
 776                         #power-domain-cells = <1>;
 777                         clocks = <&bi_tcxo_div2>, <&sleep_clk>,
 778                                  <&pcie0_phy>,
 779                                  <&pcie1_phy>,
 780                                  <&pcie_1_phy_aux_clk>,
 781                                  <&ufs_mem_phy 0>,
 782                                  <&ufs_mem_phy 1>,
 783                                  <&ufs_mem_phy 2>,
 784                                  <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 785                 };
 786
 787                 ipcc: mailbox@408000 {
 788                         compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
 789                         reg = <0 0x00408000 0 0x1000>;
 790                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 791                         interrupt-controller;
 792                         #interrupt-cells = <3>;
 793                         #mbox-cells = <2>;
 794                 };
 795
 796                 gpi_dma2: dma-controller@800000 {
 797                         compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
 798                         #dma-cells = <3>;
 799                         reg = <0 0x00800000 0 0x60000>;
 800                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 801                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 802                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 803                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 804                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 805                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 806                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 807                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 808                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 809                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 810                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 811                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 812                         dma-channels = <12>;
 813                         dma-channel-mask = <0x3e>;
 814                         iommus = <&apps_smmu 0x436 0>;
 815                         status = "disabled";
 816                 };
 817
 818                 qupv3_id_1: geniqup@8c0000 {
 819                         compatible = "qcom,geni-se-qup";
 820                         reg = <0 0x008c0000 0 0x2000>;
 821                         ranges;
 822                         clock-names = "m-ahb", "s-ahb";
 823                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 824                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 825                         iommus = <&apps_smmu 0x423 0>;
 826                         #address-cells = <2>;
 827                         #size-cells = <2>;
 828                         status = "disabled";
 829
 830                         i2c8: i2c@880000 {
 831                                 compatible = "qcom,geni-i2c";
 832                                 reg = <0 0x00880000 0 0x4000>;
 833                                 clock-names = "se";
 834                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 835                                 pinctrl-names = "default";
 836                                 pinctrl-0 = <&qup_i2c8_data_clk>;
 837                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 838                                 #address-cells = <1>;
 839                                 #size-cells = <0>;
 840                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 841                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 842                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 843                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 844                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 845                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 846                                 dma-names = "tx", "rx";
 847                                 status = "disabled";
 848                         };
 849
 850                         spi8: spi@880000 {
 851                                 compatible = "qcom,geni-spi";
 852                                 reg = <0 0x00880000 0 0x4000>;
 853                                 clock-names = "se";
 854                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 855                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 856                                 pinctrl-names = "default";
 857                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
 858                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 859                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 860                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 861                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 862                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 863                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 864                                 dma-names = "tx", "rx";
 865                                 #address-cells = <1>;
 866                                 #size-cells = <0>;
 867                                 status = "disabled";
 868                         };
 869
 870                         i2c9: i2c@884000 {
 871                                 compatible = "qcom,geni-i2c";
 872                                 reg = <0 0x00884000 0 0x4000>;
 873                                 clock-names = "se";
 874                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 875                                 pinctrl-names = "default";
 876                                 pinctrl-0 = <&qup_i2c9_data_clk>;
 877                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 878                                 #address-cells = <1>;
 879                                 #size-cells = <0>;
 880                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 881                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 882                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 883                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 884                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 885                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 886                                 dma-names = "tx", "rx";
 887                                 status = "disabled";
 888                         };
 889
 890                         spi9: spi@884000 {
 891                                 compatible = "qcom,geni-spi";
 892                                 reg = <0 0x00884000 0 0x4000>;
 893                                 clock-names = "se";
 894                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 895                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 896                                 pinctrl-names = "default";
 897                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
 898                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 899                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 900                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 901                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 902                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 903                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 904                                 dma-names = "tx", "rx";
 905                                 #address-cells = <1>;
 906                                 #size-cells = <0>;
 907                                 status = "disabled";
 908                         };
 909
 910                         i2c10: i2c@888000 {
 911                                 compatible = "qcom,geni-i2c";
 912                                 reg = <0 0x00888000 0 0x4000>;
 913                                 clock-names = "se";
 914                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 915                                 pinctrl-names = "default";
 916                                 pinctrl-0 = <&qup_i2c10_data_clk>;
 917                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 918                                 #address-cells = <1>;
 919                                 #size-cells = <0>;
 920                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 921                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 922                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 923                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 924                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 925                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 926                                 dma-names = "tx", "rx";
 927                                 status = "disabled";
 928                         };
 929
 930                         spi10: spi@888000 {
 931                                 compatible = "qcom,geni-spi";
 932                                 reg = <0 0x00888000 0 0x4000>;
 933                                 clock-names = "se";
 934                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 935                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 936                                 pinctrl-names = "default";
 937                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
 938                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 939                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 940                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 941                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 942                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 943                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 944                                 dma-names = "tx", "rx";
 945                                 #address-cells = <1>;
 946                                 #size-cells = <0>;
 947                                 status = "disabled";
 948                         };
 949
 950                         i2c11: i2c@88c000 {
 951                                 compatible = "qcom,geni-i2c";
 952                                 reg = <0 0x0088c000 0 0x4000>;
 953                                 clock-names = "se";
 954                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 955                                 pinctrl-names = "default";
 956                                 pinctrl-0 = <&qup_i2c11_data_clk>;
 957                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 958                                 #address-cells = <1>;
 959                                 #size-cells = <0>;
 960                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 961                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 962                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 963                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 964                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 965                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 966                                 dma-names = "tx", "rx";
 967                                 status = "disabled";
 968                         };
 969
 970                         spi11: spi@88c000 {
 971                                 compatible = "qcom,geni-spi";
 972                                 reg = <0 0x0088c000 0 0x4000>;
 973                                 clock-names = "se";
 974                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 975                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 976                                 pinctrl-names = "default";
 977                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
 978                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 979                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 980                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 981                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 982                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 983                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 984                                 dma-names = "tx", "rx";
 985                                 #address-cells = <1>;
 986                                 #size-cells = <0>;
 987                                 status = "disabled";
 988                         };
 989
 990                         i2c12: i2c@890000 {
 991                                 compatible = "qcom,geni-i2c";
 992                                 reg = <0 0x00890000 0 0x4000>;
 993                                 clock-names = "se";
 994                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 995                                 pinctrl-names = "default";
 996                                 pinctrl-0 = <&qup_i2c12_data_clk>;
 997                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 998                                 #address-cells = <1>;
 999                                 #size-cells = <0>;
1000                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1001                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1002                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1003                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1004                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1005                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1006                                 dma-names = "tx", "rx";
1007                                 status = "disabled";
1008                         };
1009
1010                         spi12: spi@890000 {
1011                                 compatible = "qcom,geni-spi";
1012                                 reg = <0 0x00890000 0 0x4000>;
1013                                 clock-names = "se";
1014                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1015                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1016                                 pinctrl-names = "default";
1017                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1018                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1019                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1020                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1021                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1022                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1023                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1024                                 dma-names = "tx", "rx";
1025                                 #address-cells = <1>;
1026                                 #size-cells = <0>;
1027                                 status = "disabled";
1028                         };
1029
1030                         i2c13: i2c@894000 {
1031                                 compatible = "qcom,geni-i2c";
1032                                 reg = <0 0x00894000 0 0x4000>;
1033                                 clock-names = "se";
1034                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1035                                 pinctrl-names = "default";
1036                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1037                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1038                                 #address-cells = <1>;
1039                                 #size-cells = <0>;
1040                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1041                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1042                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1043                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1044                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1045                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1046                                 dma-names = "tx", "rx";
1047                                 status = "disabled";
1048                         };
1049
1050                         spi13: spi@894000 {
1051                                 compatible = "qcom,geni-spi";
1052                                 reg = <0 0x00894000 0 0x4000>;
1053                                 clock-names = "se";
1054                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1055                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1056                                 pinctrl-names = "default";
1057                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1058                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1059                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1060                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1061                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1062                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1063                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1064                                 dma-names = "tx", "rx";
1065                                 #address-cells = <1>;
1066                                 #size-cells = <0>;
1067                                 status = "disabled";
1068                         };
1069
1070                         uart14: serial@898000 {
1071                                 compatible = "qcom,geni-uart";
1072                                 reg = <0 0x898000 0 0x4000>;
1073                                 clock-names = "se";
1074                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1075                                 pinctrl-names = "default";
1076                                 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1077                                 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1078                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1079                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
1080                                 interconnect-names = "qup-core", "qup-config";
1081                                 status = "disabled";
1082                         };
1083
1084                         i2c15: i2c@89c000 {
1085                                 compatible = "qcom,geni-i2c";
1086                                 reg = <0 0x0089c000 0 0x4000>;
1087                                 clock-names = "se";
1088                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1089                                 pinctrl-names = "default";
1090                                 pinctrl-0 = <&qup_i2c15_data_clk>;
1091                                 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1092                                 #address-cells = <1>;
1093                                 #size-cells = <0>;
1094                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1095                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1096                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1097                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1098                                 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1099                                        <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1100                                 dma-names = "tx", "rx";
1101                                 status = "disabled";
1102                         };
1103
1104                         spi15: spi@89c000 {
1105                                 compatible = "qcom,geni-spi";
1106                                 reg = <0 0x0089c000 0 0x4000>;
1107                                 clock-names = "se";
1108                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1109                                 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1110                                 pinctrl-names = "default";
1111                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1112                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1113                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1114                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1115                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1116                                 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1117                                        <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1118                                 dma-names = "tx", "rx";
1119                                 #address-cells = <1>;
1120                                 #size-cells = <0>;
1121                                 status = "disabled";
1122                         };
1123                 };
1124
1125                 i2c_master_hub_0: geniqup@9c0000 {
1126                         compatible = "qcom,geni-se-i2c-master-hub";
1127                         reg = <0x0 0x009c0000 0x0 0x2000>;
1128                         clock-names = "s-ahb";
1129                         clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
1130                         #address-cells = <2>;
1131                         #size-cells = <2>;
1132                         ranges;
1133                         status = "disabled";
1134
1135                         i2c_hub_0: i2c@980000 {
1136                                 compatible = "qcom,geni-i2c-master-hub";
1137                                 reg = <0x0 0x00980000 0x0 0x4000>;
1138                                 clock-names = "se", "core";
1139                                 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
1140                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1141                                 pinctrl-names = "default";
1142                                 pinctrl-0 = <&hub_i2c0_data_clk>;
1143                                 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
1144                                 #address-cells = <1>;
1145                                 #size-cells = <0>;
1146                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1147                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1148                                 interconnect-names = "qup-core", "qup-config";
1149                                 status = "disabled";
1150                         };
1151
1152                         i2c_hub_1: i2c@984000 {
1153                                 compatible = "qcom,geni-i2c-master-hub";
1154                                 reg = <0x0 0x00984000 0x0 0x4000>;
1155                                 clock-names = "se", "core";
1156                                 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
1157                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1158                                 pinctrl-names = "default";
1159                                 pinctrl-0 = <&hub_i2c1_data_clk>;
1160                                 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
1161                                 #address-cells = <1>;
1162                                 #size-cells = <0>;
1163                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1164                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1165                                 interconnect-names = "qup-core", "qup-config";
1166                                 status = "disabled";
1167                         };
1168
1169                         i2c_hub_2: i2c@988000 {
1170                                 compatible = "qcom,geni-i2c-master-hub";
1171                                 reg = <0x0 0x00988000 0x0 0x4000>;
1172                                 clock-names = "se", "core";
1173                                 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
1174                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1175                                 pinctrl-names = "default";
1176                                 pinctrl-0 = <&hub_i2c2_data_clk>;
1177                                 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1178                                 #address-cells = <1>;
1179                                 #size-cells = <0>;
1180                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1181                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1182                                 interconnect-names = "qup-core", "qup-config";
1183                                 status = "disabled";
1184                         };
1185
1186                         i2c_hub_3: i2c@98c000 {
1187                                 compatible = "qcom,geni-i2c-master-hub";
1188                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1189                                 clock-names = "se", "core";
1190                                 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
1191                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1192                                 pinctrl-names = "default";
1193                                 pinctrl-0 = <&hub_i2c3_data_clk>;
1194                                 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1195                                 #address-cells = <1>;
1196                                 #size-cells = <0>;
1197                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1198                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1199                                 interconnect-names = "qup-core", "qup-config";
1200                                 status = "disabled";
1201                         };
1202
1203                         i2c_hub_4: i2c@990000 {
1204                                 compatible = "qcom,geni-i2c-master-hub";
1205                                 reg = <0x0 0x00990000 0x0 0x4000>;
1206                                 clock-names = "se", "core";
1207                                 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
1208                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1209                                 pinctrl-names = "default";
1210                                 pinctrl-0 = <&hub_i2c4_data_clk>;
1211                                 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1212                                 #address-cells = <1>;
1213                                 #size-cells = <0>;
1214                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1215                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1216                                 interconnect-names = "qup-core", "qup-config";
1217                                 status = "disabled";
1218                         };
1219
1220                         i2c_hub_5: i2c@994000 {
1221                                 compatible = "qcom,geni-i2c-master-hub";
1222                                 reg = <0 0x00994000 0 0x4000>;
1223                                 clock-names = "se", "core";
1224                                 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
1225                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1226                                 pinctrl-names = "default";
1227                                 pinctrl-0 = <&hub_i2c5_data_clk>;
1228                                 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
1229                                 #address-cells = <1>;
1230                                 #size-cells = <0>;
1231                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1232                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1233                                 interconnect-names = "qup-core", "qup-config";
1234                                 status = "disabled";
1235                         };
1236
1237                         i2c_hub_6: i2c@998000 {
1238                                 compatible = "qcom,geni-i2c-master-hub";
1239                                 reg = <0 0x00998000 0 0x4000>;
1240                                 clock-names = "se", "core";
1241                                 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
1242                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1243                                 pinctrl-names = "default";
1244                                 pinctrl-0 = <&hub_i2c6_data_clk>;
1245                                 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
1246                                 #address-cells = <1>;
1247                                 #size-cells = <0>;
1248                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1249                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1250                                 interconnect-names = "qup-core", "qup-config";
1251                                 status = "disabled";
1252                         };
1253
1254                         i2c_hub_7: i2c@99c000 {
1255                                 compatible = "qcom,geni-i2c-master-hub";
1256                                 reg = <0 0x0099c000 0 0x4000>;
1257                                 clock-names = "se", "core";
1258                                 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
1259                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1260                                 pinctrl-names = "default";
1261                                 pinctrl-0 = <&hub_i2c7_data_clk>;
1262                                 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
1263                                 #address-cells = <1>;
1264                                 #size-cells = <0>;
1265                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1266                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1267                                 interconnect-names = "qup-core", "qup-config";
1268                                 status = "disabled";
1269                         };
1270
1271                         i2c_hub_8: i2c@9a0000 {
1272                                 compatible = "qcom,geni-i2c-master-hub";
1273                                 reg = <0 0x009a0000 0 0x4000>;
1274                                 clock-names = "se", "core";
1275                                 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
1276                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1277                                 pinctrl-names = "default";
1278                                 pinctrl-0 = <&hub_i2c8_data_clk>;
1279                                 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
1280                                 #address-cells = <1>;
1281                                 #size-cells = <0>;
1282                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1283                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1284                                 interconnect-names = "qup-core", "qup-config";
1285                                 status = "disabled";
1286                         };
1287
1288                         i2c_hub_9: i2c@9a4000 {
1289                                 compatible = "qcom,geni-i2c-master-hub";
1290                                 reg = <0 0x009a4000 0 0x4000>;
1291                                 clock-names = "se", "core";
1292                                 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
1293                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1294                                 pinctrl-names = "default";
1295                                 pinctrl-0 = <&hub_i2c9_data_clk>;
1296                                 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
1297                                 #address-cells = <1>;
1298                                 #size-cells = <0>;
1299                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1300                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1301                                 interconnect-names = "qup-core", "qup-config";
1302                                 status = "disabled";
1303                         };
1304                 };
1305
1306                 gpi_dma1: dma-controller@a00000 {
1307                         compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1308                         #dma-cells = <3>;
1309                         reg = <0 0x00a00000 0 0x60000>;
1310                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1311                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1312                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1313                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1314                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1315                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1316                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1317                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1318                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1319                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1320                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1321                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1322                         dma-channels = <12>;
1323                         dma-channel-mask = <0x1e>;
1324                         iommus = <&apps_smmu 0xb6 0>;
1325                         status = "disabled";
1326                 };
1327
1328                 qupv3_id_0: geniqup@ac0000 {
1329                         compatible = "qcom,geni-se-qup";
1330                         reg = <0 0x00ac0000 0 0x2000>;
1331                         ranges;
1332                         clock-names = "m-ahb", "s-ahb";
1333                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1334                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1335                         iommus = <&apps_smmu 0xa3 0>;
1336                         interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1337                         interconnect-names = "qup-core";
1338                         #address-cells = <2>;
1339                         #size-cells = <2>;
1340                         status = "disabled";
1341
1342                         i2c0: i2c@a80000 {
1343                                 compatible = "qcom,geni-i2c";
1344                                 reg = <0 0x00a80000 0 0x4000>;
1345                                 clock-names = "se";
1346                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1347                                 pinctrl-names = "default";
1348                                 pinctrl-0 = <&qup_i2c0_data_clk>;
1349                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1350                                 #address-cells = <1>;
1351                                 #size-cells = <0>;
1352                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1353                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1354                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1355                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1356                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1357                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1358                                 dma-names = "tx", "rx";
1359                                 status = "disabled";
1360                         };
1361
1362                         spi0: spi@a80000 {
1363                                 compatible = "qcom,geni-spi";
1364                                 reg = <0 0x00a80000 0 0x4000>;
1365                                 clock-names = "se";
1366                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1367                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1368                                 pinctrl-names = "default";
1369                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1370                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1371                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1372                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1373                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1374                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1375                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1376                                 dma-names = "tx", "rx";
1377                                 #address-cells = <1>;
1378                                 #size-cells = <0>;
1379                                 status = "disabled";
1380                         };
1381
1382                         i2c1: i2c@a84000 {
1383                                 compatible = "qcom,geni-i2c";
1384                                 reg = <0 0x00a84000 0 0x4000>;
1385                                 clock-names = "se";
1386                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1387                                 pinctrl-names = "default";
1388                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1389                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1390                                 #address-cells = <1>;
1391                                 #size-cells = <0>;
1392                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1393                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1394                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1395                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1396                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1397                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1398                                 dma-names = "tx", "rx";
1399                                 status = "disabled";
1400                         };
1401
1402                         spi1: spi@a84000 {
1403                                 compatible = "qcom,geni-spi";
1404                                 reg = <0 0x00a84000 0 0x4000>;
1405                                 clock-names = "se";
1406                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1407                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1408                                 pinctrl-names = "default";
1409                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1410                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1411                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1412                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1413                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1414                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1415                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1416                                 dma-names = "tx", "rx";
1417                                 #address-cells = <1>;
1418                                 #size-cells = <0>;
1419                                 status = "disabled";
1420                         };
1421
1422                         i2c2: i2c@a88000 {
1423                                 compatible = "qcom,geni-i2c";
1424                                 reg = <0 0x00a88000 0 0x4000>;
1425                                 clock-names = "se";
1426                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1427                                 pinctrl-names = "default";
1428                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1429                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1430                                 #address-cells = <1>;
1431                                 #size-cells = <0>;
1432                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1433                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1434                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1435                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1436                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1437                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1438                                 dma-names = "tx", "rx";
1439                                 status = "disabled";
1440                         };
1441
1442                         spi2: spi@a88000 {
1443                                 compatible = "qcom,geni-spi";
1444                                 reg = <0 0x00a88000 0 0x4000>;
1445                                 clock-names = "se";
1446                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1447                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1448                                 pinctrl-names = "default";
1449                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1450                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1451                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1452                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1453                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1454                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1455                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1456                                 dma-names = "tx", "rx";
1457                                 #address-cells = <1>;
1458                                 #size-cells = <0>;
1459                                 status = "disabled";
1460                         };
1461
1462                         i2c3: i2c@a8c000 {
1463                                 compatible = "qcom,geni-i2c";
1464                                 reg = <0 0x00a8c000 0 0x4000>;
1465                                 clock-names = "se";
1466                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1467                                 pinctrl-names = "default";
1468                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1469                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1470                                 #address-cells = <1>;
1471                                 #size-cells = <0>;
1472                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1473                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1474                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1475                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1476                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1477                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1478                                 dma-names = "tx", "rx";
1479                                 status = "disabled";
1480                         };
1481
1482                         spi3: spi@a8c000 {
1483                                 compatible = "qcom,geni-spi";
1484                                 reg = <0 0x00a8c000 0 0x4000>;
1485                                 clock-names = "se";
1486                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1487                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1488                                 pinctrl-names = "default";
1489                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1490                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1491                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1492                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1493                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1494                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1495                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1496                                 dma-names = "tx", "rx";
1497                                 #address-cells = <1>;
1498                                 #size-cells = <0>;
1499                                 status = "disabled";
1500                         };
1501
1502                         i2c4: i2c@a90000 {
1503                                 compatible = "qcom,geni-i2c";
1504                                 reg = <0 0x00a90000 0 0x4000>;
1505                                 clock-names = "se";
1506                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1507                                 pinctrl-names = "default";
1508                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1509                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1510                                 #address-cells = <1>;
1511                                 #size-cells = <0>;
1512                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1513                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1514                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1515                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1516                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1517                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1518                                 dma-names = "tx", "rx";
1519                                 status = "disabled";
1520                         };
1521
1522                         spi4: spi@a90000 {
1523                                 compatible = "qcom,geni-spi";
1524                                 reg = <0 0x00a90000 0 0x4000>;
1525                                 clock-names = "se";
1526                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1527                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1528                                 pinctrl-names = "default";
1529                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1530                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1531                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1532                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1533                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1534                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1535                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1536                                 dma-names = "tx", "rx";
1537                                 #address-cells = <1>;
1538                                 #size-cells = <0>;
1539                                 status = "disabled";
1540                         };
1541
1542                         i2c5: i2c@a94000 {
1543                                 compatible = "qcom,geni-i2c";
1544                                 reg = <0 0x00a94000 0 0x4000>;
1545                                 clock-names = "se";
1546                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1547                                 pinctrl-names = "default";
1548                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1549                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1550                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1551                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1552                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1553                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1554                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1555                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1556                                 dma-names = "tx", "rx";
1557                                 #address-cells = <1>;
1558                                 #size-cells = <0>;
1559                                 status = "disabled";
1560                         };
1561
1562                         spi5: spi@a94000 {
1563                                 compatible = "qcom,geni-spi";
1564                                 reg = <0 0x00a94000 0 0x4000>;
1565                                 clock-names = "se";
1566                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1567                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1568                                 pinctrl-names = "default";
1569                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1570                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1571                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1572                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1573                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1574                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1575                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1576                                 dma-names = "tx", "rx";
1577                                 #address-cells = <1>;
1578                                 #size-cells = <0>;
1579                                 status = "disabled";
1580                         };
1581
1582                         i2c6: i2c@a98000 {
1583                                 compatible = "qcom,geni-i2c";
1584                                 reg = <0 0x00a98000 0 0x4000>;
1585                                 clock-names = "se";
1586                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1587                                 pinctrl-names = "default";
1588                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1589                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1590                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1591                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1592                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1593                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1594                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1595                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1596                                 dma-names = "tx", "rx";
1597                                 #address-cells = <1>;
1598                                 #size-cells = <0>;
1599                                 status = "disabled";
1600                         };
1601
1602                         spi6: spi@a98000 {
1603                                 compatible = "qcom,geni-spi";
1604                                 reg = <0 0x00a98000 0 0x4000>;
1605                                 clock-names = "se";
1606                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1607                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1608                                 pinctrl-names = "default";
1609                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1610                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1611                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1612                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1613                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1614                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1615                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1616                                 dma-names = "tx", "rx";
1617                                 #address-cells = <1>;
1618                                 #size-cells = <0>;
1619                                 status = "disabled";
1620                         };
1621
1622                         uart7: serial@a9c000 {
1623                                 compatible = "qcom,geni-debug-uart";
1624                                 reg = <0 0x00a9c000 0 0x4000>;
1625                                 clock-names = "se";
1626                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1627                                 pinctrl-names = "default";
1628                                 pinctrl-0 = <&qup_uart7_default>;
1629                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1630                                 interconnect-names = "qup-core", "qup-config";
1631                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1632                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1633                                 status = "disabled";
1634                         };
1635                 };
1636
1637                 cnoc_main: interconnect@1500000 {
1638                         compatible = "qcom,sm8550-cnoc-main";
1639                         reg = <0 0x01500000 0 0x13080>;
1640                         #interconnect-cells = <2>;
1641                         qcom,bcm-voters = <&apps_bcm_voter>;
1642                 };
1643
1644                 config_noc: interconnect@1600000 {
1645                         compatible = "qcom,sm8550-config-noc";
1646                         reg = <0 0x01600000 0 0x6200>;
1647                         #interconnect-cells = <2>;
1648                         qcom,bcm-voters = <&apps_bcm_voter>;
1649                 };
1650
1651                 system_noc: interconnect@1680000 {
1652                         compatible = "qcom,sm8550-system-noc";
1653                         reg = <0 0x01680000 0 0x1d080>;
1654                         #interconnect-cells = <2>;
1655                         qcom,bcm-voters = <&apps_bcm_voter>;
1656                 };
1657
1658                 pcie_noc: interconnect@16c0000 {
1659                         compatible = "qcom,sm8550-pcie-anoc";
1660                         reg = <0 0x016c0000 0 0x12200>;
1661                         #interconnect-cells = <2>;
1662                         clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1663                                  <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
1664                         qcom,bcm-voters = <&apps_bcm_voter>;
1665                 };
1666
1667                 aggre1_noc: interconnect@16e0000 {
1668                         compatible = "qcom,sm8550-aggre1-noc";
1669                         reg = <0 0x016e0000 0 0x14400>;
1670                         #interconnect-cells = <2>;
1671                         clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1672                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
1673                         qcom,bcm-voters = <&apps_bcm_voter>;
1674                 };
1675
1676                 aggre2_noc: interconnect@1700000 {
1677                         compatible = "qcom,sm8550-aggre2-noc";
1678                         reg = <0 0x01700000 0 0x1e400>;
1679                         #interconnect-cells = <2>;
1680                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1681                         qcom,bcm-voters = <&apps_bcm_voter>;
1682                 };
1683
1684                 mmss_noc: interconnect@1780000 {
1685                         compatible = "qcom,sm8550-mmss-noc";
1686                         reg = <0 0x01780000 0 0x5b800>;
1687                         #interconnect-cells = <2>;
1688                         qcom,bcm-voters = <&apps_bcm_voter>;
1689                 };
1690
1691                 rng: rng@10c3000 {
1692                         compatible = "qcom,sm8550-trng", "qcom,trng";
1693                         reg = <0 0x010c3000 0 0x1000>;
1694                 };
1695
1696                 pcie0: pcie@1c00000 {
1697                         device_type = "pci";
1698                         compatible = "qcom,pcie-sm8550";
1699                         reg = <0 0x01c00000 0 0x3000>,
1700                               <0 0x60000000 0 0xf1d>,
1701                               <0 0x60000f20 0 0xa8>,
1702                               <0 0x60001000 0 0x1000>,
1703                               <0 0x60100000 0 0x100000>;
1704                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1705                         #address-cells = <3>;
1706                         #size-cells = <2>;
1707                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1708                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1709                         bus-range = <0x00 0xff>;
1710
1711                         dma-coherent;
1712
1713                         linux,pci-domain = <0>;
1714                         num-lanes = <2>;
1715
1716                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1717                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1718                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1719                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1720                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1721                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1722                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1723                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1724                         interrupt-names = "msi0",
1725                                           "msi1",
1726                                           "msi2",
1727                                           "msi3",
1728                                           "msi4",
1729                                           "msi5",
1730                                           "msi6",
1731                                           "msi7";
1732                         #interrupt-cells = <1>;
1733                         interrupt-map-mask = <0 0 0 0x7>;
1734                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1735                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1736                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1737                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1738
1739                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1740                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1741                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1742                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1743                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1744                                  <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1745                                  <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
1746                         clock-names = "aux",
1747                                       "cfg",
1748                                       "bus_master",
1749                                       "bus_slave",
1750                                       "slave_q2a",
1751                                       "ddrss_sf_tbu",
1752                                       "noc_aggr";
1753
1754                         interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1755                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1756                         interconnect-names = "pcie-mem", "cpu-pcie";
1757
1758                         /* Entries are reversed due to the unusual ITS DeviceID encoding */
1759                         msi-map = <0x0 &gic_its 0x1401 0x1>,
1760                                   <0x100 &gic_its 0x1400 0x1>;
1761                         iommu-map = <0x0   &apps_smmu 0x1400 0x1>,
1762                                     <0x100 &apps_smmu 0x1401 0x1>;
1763
1764                         resets = <&gcc GCC_PCIE_0_BCR>;
1765                         reset-names = "pci";
1766
1767                         power-domains = <&gcc PCIE_0_GDSC>;
1768
1769                         phys = <&pcie0_phy>;
1770                         phy-names = "pciephy";
1771
1772                         status = "disabled";
1773                 };
1774
1775                 pcie0_phy: phy@1c06000 {
1776                         compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1777                         reg = <0 0x01c06000 0 0x2000>;
1778
1779                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1780                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1781                                  <&tcsr TCSR_PCIE_0_CLKREF_EN>,
1782                                  <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1783                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
1784                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1785                                       "pipe";
1786
1787                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1788                         reset-names = "phy";
1789
1790                         assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1791                         assigned-clock-rates = <100000000>;
1792
1793                         power-domains = <&gcc PCIE_0_PHY_GDSC>;
1794
1795                         #clock-cells = <0>;
1796                         clock-output-names = "pcie0_pipe_clk";
1797
1798                         #phy-cells = <0>;
1799
1800                         status = "disabled";
1801                 };
1802
1803                 pcie1: pcie@1c08000 {
1804                         device_type = "pci";
1805                         compatible = "qcom,pcie-sm8550";
1806                         reg = <0x0 0x01c08000 0x0 0x3000>,
1807                               <0x0 0x40000000 0x0 0xf1d>,
1808                               <0x0 0x40000f20 0x0 0xa8>,
1809                               <0x0 0x40001000 0x0 0x1000>,
1810                               <0x0 0x40100000 0x0 0x100000>;
1811                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1812                         #address-cells = <3>;
1813                         #size-cells = <2>;
1814                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1815                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1816                         bus-range = <0x00 0xff>;
1817
1818                         dma-coherent;
1819
1820                         linux,pci-domain = <1>;
1821                         num-lanes = <2>;
1822
1823                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1824                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1825                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1826                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1827                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1828                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1829                                      <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1830                                      <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1831                         interrupt-names = "msi0",
1832                                           "msi1",
1833                                           "msi2",
1834                                           "msi3",
1835                                           "msi4",
1836                                           "msi5",
1837                                           "msi6",
1838                                           "msi7";
1839                         #interrupt-cells = <1>;
1840                         interrupt-map-mask = <0 0 0 0x7>;
1841                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1842                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1843                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1844                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1845
1846                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1847                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1848                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1849                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1850                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1851                                  <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1852                                  <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1853                                  <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
1854                         clock-names = "aux",
1855                                       "cfg",
1856                                       "bus_master",
1857                                       "bus_slave",
1858                                       "slave_q2a",
1859                                       "ddrss_sf_tbu",
1860                                       "noc_aggr",
1861                                       "cnoc_sf_axi";
1862
1863                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1864                         assigned-clock-rates = <19200000>;
1865
1866                         interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1867                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1868                         interconnect-names = "pcie-mem", "cpu-pcie";
1869
1870                         /* Entries are reversed due to the unusual ITS DeviceID encoding */
1871                         msi-map = <0x0 &gic_its 0x1481 0x1>,
1872                                   <0x100 &gic_its 0x1480 0x1>;
1873                         iommu-map = <0x0   &apps_smmu 0x1480 0x1>,
1874                                     <0x100 &apps_smmu 0x1481 0x1>;
1875
1876                         resets = <&gcc GCC_PCIE_1_BCR>,
1877                                 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
1878                         reset-names = "pci", "link_down";
1879
1880                         power-domains = <&gcc PCIE_1_GDSC>;
1881
1882                         phys = <&pcie1_phy>;
1883                         phy-names = "pciephy";
1884
1885                         status = "disabled";
1886                 };
1887
1888                 pcie1_phy: phy@1c0e000 {
1889                         compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1890                         reg = <0x0 0x01c0e000 0x0 0x2000>;
1891
1892                         clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1893                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1894                                  <&tcsr TCSR_PCIE_1_CLKREF_EN>,
1895                                  <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1896                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
1897                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1898                                       "pipe";
1899
1900                         resets = <&gcc GCC_PCIE_1_PHY_BCR>,
1901                                  <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
1902                         reset-names = "phy", "phy_nocsr";
1903
1904                         assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1905                         assigned-clock-rates = <100000000>;
1906
1907                         power-domains = <&gcc PCIE_1_PHY_GDSC>;
1908
1909                         #clock-cells = <0>;
1910                         clock-output-names = "pcie1_pipe_clk";
1911
1912                         #phy-cells = <0>;
1913
1914                         status = "disabled";
1915                 };
1916
1917                 cryptobam: dma-controller@1dc4000 {
1918                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1919                         reg = <0x0 0x01dc4000 0x0 0x28000>;
1920                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1921                         #dma-cells = <1>;
1922                         qcom,ee = <0>;
1923                         qcom,controlled-remotely;
1924                         iommus = <&apps_smmu 0x480 0x0>,
1925                                  <&apps_smmu 0x481 0x0>;
1926                 };
1927
1928                 crypto: crypto@1dfa000 {
1929                         compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1930                         reg = <0x0 0x01dfa000 0x0 0x6000>;
1931                         dmas = <&cryptobam 4>, <&cryptobam 5>;
1932                         dma-names = "rx", "tx";
1933                         iommus = <&apps_smmu 0x480 0x0>,
1934                                  <&apps_smmu 0x481 0x0>;
1935                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1936                         interconnect-names = "memory";
1937                 };
1938
1939                 ufs_mem_phy: phy@1d80000 {
1940                         compatible = "qcom,sm8550-qmp-ufs-phy";
1941                         reg = <0x0 0x01d80000 0x0 0x2000>;
1942                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1943                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1944                                  <&tcsr TCSR_UFS_CLKREF_EN>;
1945                         clock-names = "ref",
1946                                       "ref_aux",
1947                                       "qref";
1948
1949                         power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1950
1951                         resets = <&ufs_mem_hc 0>;
1952                         reset-names = "ufsphy";
1953
1954                         #clock-cells = <1>;
1955                         #phy-cells = <0>;
1956
1957                         status = "disabled";
1958                 };
1959
1960                 ufs_mem_hc: ufs@1d84000 {
1961                         compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1962                                      "jedec,ufs-2.0";
1963                         reg = <0x0 0x01d84000 0x0 0x3000>;
1964                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1965                         phys = <&ufs_mem_phy>;
1966                         phy-names = "ufsphy";
1967                         lanes-per-direction = <2>;
1968                         #reset-cells = <1>;
1969                         resets = <&gcc GCC_UFS_PHY_BCR>;
1970                         reset-names = "rst";
1971
1972                         power-domains = <&gcc UFS_PHY_GDSC>;
1973                         required-opps = <&rpmhpd_opp_nom>;
1974
1975                         iommus = <&apps_smmu 0x60 0x0>;
1976                         dma-coherent;
1977
1978                         operating-points-v2 = <&ufs_opp_table>;
1979                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1980                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
1981
1982                         interconnect-names = "ufs-ddr", "cpu-ufs";
1983                         clock-names = "core_clk",
1984                                       "bus_aggr_clk",
1985                                       "iface_clk",
1986                                       "core_clk_unipro",
1987                                       "ref_clk",
1988                                       "tx_lane0_sync_clk",
1989                                       "rx_lane0_sync_clk",
1990                                       "rx_lane1_sync_clk";
1991                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1992                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1993                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
1994                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1995                                  <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
1996                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1997                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1998                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1999                         qcom,ice = <&ice>;
2000
2001                         status = "disabled";
2002
2003                         ufs_opp_table: opp-table {
2004                                 compatible = "operating-points-v2";
2005
2006                                 opp-75000000 {
2007                                         opp-hz = /bits/ 64 <75000000>,
2008                                                  /bits/ 64 <0>,
2009                                                  /bits/ 64 <0>,
2010                                                  /bits/ 64 <75000000>,
2011                                                  /bits/ 64 <0>,
2012                                                  /bits/ 64 <0>,
2013                                                  /bits/ 64 <0>,
2014                                                  /bits/ 64 <0>;
2015                                         required-opps = <&rpmhpd_opp_low_svs>;
2016                                 };
2017
2018                                 opp-150000000 {
2019                                         opp-hz = /bits/ 64 <150000000>,
2020                                                  /bits/ 64 <0>,
2021                                                  /bits/ 64 <0>,
2022                                                  /bits/ 64 <150000000>,
2023                                                  /bits/ 64 <0>,
2024                                                  /bits/ 64 <0>,
2025                                                  /bits/ 64 <0>,
2026                                                  /bits/ 64 <0>;
2027                                         required-opps = <&rpmhpd_opp_svs>;
2028                                 };
2029
2030                                 opp-300000000 {
2031                                         opp-hz = /bits/ 64 <300000000>,
2032                                                  /bits/ 64 <0>,
2033                                                  /bits/ 64 <0>,
2034                                                  /bits/ 64 <300000000>,
2035                                                  /bits/ 64 <0>,
2036                                                  /bits/ 64 <0>,
2037                                                  /bits/ 64 <0>,
2038                                                  /bits/ 64 <0>;
2039                                         required-opps = <&rpmhpd_opp_nom>;
2040                                 };
2041                         };
2042                 };
2043
2044                 ice: crypto@1d88000 {
2045                         compatible = "qcom,sm8550-inline-crypto-engine",
2046                                      "qcom,inline-crypto-engine";
2047                         reg = <0 0x01d88000 0 0x8000>;
2048                         clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2049                 };
2050
2051                 tcsr_mutex: hwlock@1f40000 {
2052                         compatible = "qcom,tcsr-mutex";
2053                         reg = <0 0x01f40000 0 0x20000>;
2054                         #hwlock-cells = <1>;
2055                 };
2056
2057                 tcsr: clock-controller@1fc0000 {
2058                         compatible = "qcom,sm8550-tcsr", "syscon";
2059                         reg = <0 0x01fc0000 0 0x30000>;
2060                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2061                         #clock-cells = <1>;
2062                         #reset-cells = <1>;
2063                 };
2064
2065                 gpu: gpu@3d00000 {
2066                         compatible = "qcom,adreno-43050a01", "qcom,adreno";
2067                         reg = <0x0 0x03d00000 0x0 0x40000>,
2068                               <0x0 0x03d9e000 0x0 0x1000>,
2069                               <0x0 0x03d61000 0x0 0x800>;
2070                         reg-names = "kgsl_3d0_reg_memory",
2071                                     "cx_mem",
2072                                     "cx_dbgc";
2073
2074                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2075
2076                         iommus = <&adreno_smmu 0 0x0>,
2077                                  <&adreno_smmu 1 0x0>;
2078
2079                         operating-points-v2 = <&gpu_opp_table>;
2080
2081                         qcom,gmu = <&gmu>;
2082                         #cooling-cells = <2>;
2083
2084                         status = "disabled";
2085
2086                         zap-shader {
2087                                 memory-region = <&gpu_micro_code_mem>;
2088                         };
2089
2090                         /* Speedbin needs more work on A740+, keep only lower freqs */
2091                         gpu_opp_table: opp-table {
2092                                 compatible = "operating-points-v2";
2093
2094                                 opp-680000000 {
2095                                         opp-hz = /bits/ 64 <680000000>;
2096                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2097                                 };
2098
2099                                 opp-615000000 {
2100                                         opp-hz = /bits/ 64 <615000000>;
2101                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2102                                 };
2103
2104                                 opp-550000000 {
2105                                         opp-hz = /bits/ 64 <550000000>;
2106                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2107                                 };
2108
2109                                 opp-475000000 {
2110                                         opp-hz = /bits/ 64 <475000000>;
2111                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2112                                 };
2113
2114                                 opp-401000000 {
2115                                         opp-hz = /bits/ 64 <401000000>;
2116                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2117                                 };
2118
2119                                 opp-348000000 {
2120                                         opp-hz = /bits/ 64 <348000000>;
2121                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2122                                 };
2123
2124                                 opp-295000000 {
2125                                         opp-hz = /bits/ 64 <295000000>;
2126                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2127                                 };
2128
2129                                 opp-220000000 {
2130                                         opp-hz = /bits/ 64 <220000000>;
2131                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2132                                 };
2133                         };
2134                 };
2135
2136                 gmu: gmu@3d6a000 {
2137                         compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2138                         reg = <0x0 0x03d6a000 0x0 0x35000>,
2139                               <0x0 0x03d50000 0x0 0x10000>,
2140                               <0x0 0x0b280000 0x0 0x10000>;
2141                         reg-names = "gmu", "rscc", "gmu_pdc";
2142
2143                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2144                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2145                         interrupt-names = "hfi", "gmu";
2146
2147                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2148                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2149                                  <&gpucc GPU_CC_CXO_CLK>,
2150                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2151                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2152                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2153                                  <&gpucc GPU_CC_DEMET_CLK>;
2154                         clock-names = "ahb",
2155                                       "gmu",
2156                                       "cxo",
2157                                       "axi",
2158                                       "memnoc",
2159                                       "hub",
2160                                       "demet";
2161
2162                         power-domains = <&gpucc GPU_CC_CX_GDSC>,
2163                                         <&gpucc GPU_CC_GX_GDSC>;
2164                         power-domain-names = "cx",
2165                                              "gx";
2166
2167                         iommus = <&adreno_smmu 5 0x0>;
2168
2169                         qcom,qmp = <&aoss_qmp>;
2170
2171                         operating-points-v2 = <&gmu_opp_table>;
2172
2173                         gmu_opp_table: opp-table {
2174                                 compatible = "operating-points-v2";
2175
2176                                 opp-500000000 {
2177                                         opp-hz = /bits/ 64 <500000000>;
2178                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2179                                 };
2180
2181                                 opp-200000000 {
2182                                         opp-hz = /bits/ 64 <200000000>;
2183                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2184                                 };
2185                         };
2186                 };
2187
2188                 gpucc: clock-controller@3d90000 {
2189                         compatible = "qcom,sm8550-gpucc";
2190                         reg = <0 0x03d90000 0 0xa000>;
2191                         clocks = <&bi_tcxo_div2>,
2192                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2193                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2194                         #clock-cells = <1>;
2195                         #reset-cells = <1>;
2196                         #power-domain-cells = <1>;
2197                 };
2198
2199                 adreno_smmu: iommu@3da0000 {
2200                         compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu",
2201                                      "qcom,smmu-500", "arm,mmu-500";
2202                         reg = <0x0 0x03da0000 0x0 0x40000>;
2203                         #iommu-cells = <2>;
2204                         #global-interrupts = <1>;
2205                         interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2206                                      <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
2207                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2208                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2209                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2210                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2211                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2212                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2213                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2214                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2215                                      <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2216                                      <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2217                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2218                                      <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
2219                                      <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
2220                                      <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
2221                                      <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2222                                      <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
2223                                      <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
2224                                      <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
2225                                      <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
2226                                      <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
2227                                      <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2228                                      <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2229                                      <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2230                                      <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
2231                         clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2232                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2233                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2234                                  <&gpucc GPU_CC_AHB_CLK>;
2235                         clock-names = "hlos",
2236                                       "bus",
2237                                       "iface",
2238                                       "ahb";
2239                         power-domains = <&gpucc GPU_CC_CX_GDSC>;
2240                         dma-coherent;
2241                 };
2242
2243                 ipa: ipa@3f40000 {
2244                         compatible = "qcom,sm8550-ipa";
2245
2246                         iommus = <&apps_smmu 0x4a0 0x0>,
2247                                  <&apps_smmu 0x4a2 0x0>;
2248                         reg = <0 0x3f40000 0 0x10000>,
2249                               <0 0x3f50000 0 0x5000>,
2250                               <0 0x3e04000 0 0xfc000>;
2251                         reg-names = "ipa-reg",
2252                                     "ipa-shared",
2253                                     "gsi";
2254
2255                         interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2256                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2257                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2258                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2259                         interrupt-names = "ipa",
2260                                           "gsi",
2261                                           "ipa-clock-query",
2262                                           "ipa-setup-ready";
2263
2264                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2265                         clock-names = "core";
2266
2267                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2268                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2269                         interconnect-names = "memory",
2270                                              "config";
2271
2272                         qcom,qmp = <&aoss_qmp>;
2273
2274                         qcom,smem-states = <&ipa_smp2p_out 0>,
2275                                            <&ipa_smp2p_out 1>;
2276                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2277                                                 "ipa-clock-enabled";
2278
2279                         status = "disabled";
2280                 };
2281
2282                 remoteproc_mpss: remoteproc@4080000 {
2283                         compatible = "qcom,sm8550-mpss-pas";
2284                         reg = <0x0 0x04080000 0x0 0x4040>;
2285
2286                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2287                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2288                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2289                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2290                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2291                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2292                         interrupt-names = "wdog", "fatal", "ready", "handover",
2293                                           "stop-ack", "shutdown-ack";
2294
2295                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2296                         clock-names = "xo";
2297
2298                         power-domains = <&rpmhpd RPMHPD_CX>,
2299                                         <&rpmhpd RPMHPD_MSS>;
2300                         power-domain-names = "cx", "mss";
2301
2302                         interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2303
2304                         memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2305
2306                         qcom,qmp = <&aoss_qmp>;
2307
2308                         qcom,smem-states = <&smp2p_modem_out 0>;
2309                         qcom,smem-state-names = "stop";
2310
2311                         status = "disabled";
2312
2313                         glink-edge {
2314                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2315                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2316                                                              IRQ_TYPE_EDGE_RISING>;
2317                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2318                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2319                                 label = "mpss";
2320                                 qcom,remote-pid = <1>;
2321                         };
2322                 };
2323
2324                 lpass_wsa2macro: codec@6aa0000 {
2325                         compatible = "qcom,sm8550-lpass-wsa-macro";
2326                         reg = <0 0x06aa0000 0 0x1000>;
2327                         clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2328                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2329                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2330                                  <&lpass_vamacro>;
2331                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2332
2333                         #clock-cells = <0>;
2334                         clock-output-names = "wsa2-mclk";
2335                         #sound-dai-cells = <1>;
2336                 };
2337
2338                 swr3: soundwire@6ab0000 {
2339                         compatible = "qcom,soundwire-v2.0.0";
2340                         reg = <0 0x06ab0000 0 0x10000>;
2341                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2342                         clocks = <&lpass_wsa2macro>;
2343                         clock-names = "iface";
2344                         label = "WSA2";
2345
2346                         pinctrl-0 = <&wsa2_swr_active>;
2347                         pinctrl-names = "default";
2348
2349                         qcom,din-ports = <4>;
2350                         qcom,dout-ports = <9>;
2351
2352                         qcom,ports-sinterval =          /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2353                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2354                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2355                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2356                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2357                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2358                         qcom,ports-block-pack-mode =    /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2359                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2360                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2361
2362                         #address-cells = <2>;
2363                         #size-cells = <0>;
2364                         #sound-dai-cells = <1>;
2365                         status = "disabled";
2366                 };
2367
2368                 lpass_rxmacro: codec@6ac0000 {
2369                         compatible = "qcom,sm8550-lpass-rx-macro";
2370                         reg = <0 0x06ac0000 0 0x1000>;
2371                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2372                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2373                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2374                                  <&lpass_vamacro>;
2375                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2376
2377                         #clock-cells = <0>;
2378                         clock-output-names = "mclk";
2379                         #sound-dai-cells = <1>;
2380                 };
2381
2382                 swr1: soundwire@6ad0000 {
2383                         compatible = "qcom,soundwire-v2.0.0";
2384                         reg = <0 0x06ad0000 0 0x10000>;
2385                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2386                         clocks = <&lpass_rxmacro>;
2387                         clock-names = "iface";
2388                         label = "RX";
2389
2390                         pinctrl-0 = <&rx_swr_active>;
2391                         pinctrl-names = "default";
2392
2393                         qcom,din-ports = <1>;
2394                         qcom,dout-ports = <11>;
2395
2396                         qcom,ports-sinterval =          /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2397                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2398                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2399                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2400                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2401                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2402                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2403                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2404                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2405
2406                         #address-cells = <2>;
2407                         #size-cells = <0>;
2408                         #sound-dai-cells = <1>;
2409                         status = "disabled";
2410                 };
2411
2412                 lpass_txmacro: codec@6ae0000 {
2413                         compatible = "qcom,sm8550-lpass-tx-macro";
2414                         reg = <0 0x06ae0000 0 0x1000>;
2415                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2416                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2417                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2418                                  <&lpass_vamacro>;
2419                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2420
2421                         #clock-cells = <0>;
2422                         clock-output-names = "mclk";
2423                         #sound-dai-cells = <1>;
2424                 };
2425
2426                 lpass_wsamacro: codec@6b00000 {
2427                         compatible = "qcom,sm8550-lpass-wsa-macro";
2428                         reg = <0 0x06b00000 0 0x1000>;
2429                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2430                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2431                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2432                                  <&lpass_vamacro>;
2433                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2434
2435                         #clock-cells = <0>;
2436                         clock-output-names = "mclk";
2437                         #sound-dai-cells = <1>;
2438                 };
2439
2440                 swr0: soundwire@6b10000 {
2441                         compatible = "qcom,soundwire-v2.0.0";
2442                         reg = <0 0x06b10000 0 0x10000>;
2443                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2444                         clocks = <&lpass_wsamacro>;
2445                         clock-names = "iface";
2446                         label = "WSA";
2447
2448                         pinctrl-0 = <&wsa_swr_active>;
2449                         pinctrl-names = "default";
2450
2451                         qcom,din-ports = <4>;
2452                         qcom,dout-ports = <9>;
2453
2454                         qcom,ports-sinterval =          /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2455                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2456                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2457                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2458                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2459                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2460                         qcom,ports-block-pack-mode =    /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2461                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2462                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2463
2464                         #address-cells = <2>;
2465                         #size-cells = <0>;
2466                         #sound-dai-cells = <1>;
2467                         status = "disabled";
2468                 };
2469
2470                 swr2: soundwire@6d30000 {
2471                         compatible = "qcom,soundwire-v2.0.0";
2472                         reg = <0 0x06d30000 0 0x10000>;
2473                         interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2474                                      <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2475                         interrupt-names = "core", "wakeup";
2476                         clocks = <&lpass_txmacro>;
2477                         clock-names = "iface";
2478                         label = "TX";
2479
2480                         pinctrl-0 = <&tx_swr_active>;
2481                         pinctrl-names = "default";
2482
2483                         qcom,din-ports = <4>;
2484                         qcom,dout-ports = <0>;
2485                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x01 0x03 0x03>;
2486                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x01 0x01>;
2487                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
2488                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
2489                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
2490                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff>;
2491                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
2492                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
2493                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x02 0x00 0x00>;
2494
2495                         #address-cells = <2>;
2496                         #size-cells = <0>;
2497                         #sound-dai-cells = <1>;
2498                         status = "disabled";
2499                 };
2500
2501                 lpass_vamacro: codec@6d44000 {
2502                         compatible = "qcom,sm8550-lpass-va-macro";
2503                         reg = <0 0x06d44000 0 0x1000>;
2504                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2505                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2506                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2507                         clock-names = "mclk", "macro", "dcodec";
2508
2509                         #clock-cells = <0>;
2510                         clock-output-names = "fsgen";
2511                         #sound-dai-cells = <1>;
2512                 };
2513
2514                 lpass_tlmm: pinctrl@6e80000 {
2515                         compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2516                         reg = <0 0x06e80000 0 0x20000>,
2517                               <0 0x07250000 0 0x10000>;
2518                         gpio-controller;
2519                         #gpio-cells = <2>;
2520                         gpio-ranges = <&lpass_tlmm 0 0 23>;
2521
2522                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2523                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2524                         clock-names = "core", "audio";
2525
2526                         tx_swr_active: tx-swr-active-state {
2527                                 clk-pins {
2528                                         pins = "gpio0";
2529                                         function = "swr_tx_clk";
2530                                         drive-strength = <2>;
2531                                         slew-rate = <1>;
2532                                         bias-disable;
2533                                 };
2534
2535                                 data-pins {
2536                                         pins = "gpio1", "gpio2", "gpio14";
2537                                         function = "swr_tx_data";
2538                                         drive-strength = <2>;
2539                                         slew-rate = <1>;
2540                                         bias-bus-hold;
2541                                 };
2542                         };
2543
2544                         rx_swr_active: rx-swr-active-state {
2545                                 clk-pins {
2546                                         pins = "gpio3";
2547                                         function = "swr_rx_clk";
2548                                         drive-strength = <2>;
2549                                         slew-rate = <1>;
2550                                         bias-disable;
2551                                 };
2552
2553                                 data-pins {
2554                                         pins = "gpio4", "gpio5";
2555                                         function = "swr_rx_data";
2556                                         drive-strength = <2>;
2557                                         slew-rate = <1>;
2558                                         bias-bus-hold;
2559                                 };
2560                         };
2561
2562                         dmic01_default: dmic01-default-state {
2563                                 clk-pins {
2564                                         pins = "gpio6";
2565                                         function = "dmic1_clk";
2566                                         drive-strength = <8>;
2567                                         output-high;
2568                                 };
2569
2570                                 data-pins {
2571                                         pins = "gpio7";
2572                                         function = "dmic1_data";
2573                                         drive-strength = <8>;
2574                                         input-enable;
2575                                 };
2576                         };
2577
2578                         dmic23_default: dmic23-default-state {
2579                                 clk-pins {
2580                                         pins = "gpio8";
2581                                         function = "dmic2_clk";
2582                                         drive-strength = <8>;
2583                                         output-high;
2584                                 };
2585
2586                                 data-pins {
2587                                         pins = "gpio9";
2588                                         function = "dmic2_data";
2589                                         drive-strength = <8>;
2590                                         input-enable;
2591                                 };
2592                         };
2593
2594                         wsa_swr_active: wsa-swr-active-state {
2595                                 clk-pins {
2596                                         pins = "gpio10";
2597                                         function = "wsa_swr_clk";
2598                                         drive-strength = <2>;
2599                                         slew-rate = <1>;
2600                                         bias-disable;
2601                                 };
2602
2603                                 data-pins {
2604                                         pins = "gpio11";
2605                                         function = "wsa_swr_data";
2606                                         drive-strength = <2>;
2607                                         slew-rate = <1>;
2608                                         bias-bus-hold;
2609                                 };
2610                         };
2611
2612                         wsa2_swr_active: wsa2-swr-active-state {
2613                                 clk-pins {
2614                                         pins = "gpio15";
2615                                         function = "wsa2_swr_clk";
2616                                         drive-strength = <2>;
2617                                         slew-rate = <1>;
2618                                         bias-disable;
2619                                 };
2620
2621                                 data-pins {
2622                                         pins = "gpio16";
2623                                         function = "wsa2_swr_data";
2624                                         drive-strength = <2>;
2625                                         slew-rate = <1>;
2626                                         bias-bus-hold;
2627                                 };
2628                         };
2629                 };
2630
2631                 lpass_lpiaon_noc: interconnect@7400000 {
2632                         compatible = "qcom,sm8550-lpass-lpiaon-noc";
2633                         reg = <0 0x07400000 0 0x19080>;
2634                         #interconnect-cells = <2>;
2635                         qcom,bcm-voters = <&apps_bcm_voter>;
2636                 };
2637
2638                 lpass_lpicx_noc: interconnect@7430000 {
2639                         compatible = "qcom,sm8550-lpass-lpicx-noc";
2640                         reg = <0 0x07430000 0 0x3a200>;
2641                         #interconnect-cells = <2>;
2642                         qcom,bcm-voters = <&apps_bcm_voter>;
2643                 };
2644
2645                 lpass_ag_noc: interconnect@7e40000 {
2646                         compatible = "qcom,sm8550-lpass-ag-noc";
2647                         reg = <0 0x07e40000 0 0xe080>;
2648                         #interconnect-cells = <2>;
2649                         qcom,bcm-voters = <&apps_bcm_voter>;
2650                 };
2651
2652                 sdhc_2: mmc@8804000 {
2653                         compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2654                         reg = <0 0x08804000 0 0x1000>;
2655
2656                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2657                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2658                         interrupt-names = "hc_irq", "pwr_irq";
2659
2660                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2661                                  <&gcc GCC_SDCC2_APPS_CLK>,
2662                                  <&rpmhcc RPMH_CXO_CLK>;
2663                         clock-names = "iface", "core", "xo";
2664                         iommus = <&apps_smmu 0x540 0>;
2665                         qcom,dll-config = <0x0007642c>;
2666                         qcom,ddr-config = <0x80040868>;
2667                         power-domains = <&rpmhpd RPMHPD_CX>;
2668                         operating-points-v2 = <&sdhc2_opp_table>;
2669
2670                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2671                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2672                         interconnect-names = "sdhc-ddr", "cpu-sdhc";
2673                         bus-width = <4>;
2674                         dma-coherent;
2675
2676                         /* Forbid SDR104/SDR50 - broken hw! */
2677                         sdhci-caps-mask = <0x3 0>;
2678
2679                         status = "disabled";
2680
2681                         sdhc2_opp_table: opp-table {
2682                                 compatible = "operating-points-v2";
2683
2684                                 opp-19200000 {
2685                                         opp-hz = /bits/ 64 <19200000>;
2686                                         required-opps = <&rpmhpd_opp_min_svs>;
2687                                 };
2688
2689                                 opp-50000000 {
2690                                         opp-hz = /bits/ 64 <50000000>;
2691                                         required-opps = <&rpmhpd_opp_low_svs>;
2692                                 };
2693
2694                                 opp-100000000 {
2695                                         opp-hz = /bits/ 64 <100000000>;
2696                                         required-opps = <&rpmhpd_opp_svs>;
2697                                 };
2698
2699                                 opp-202000000 {
2700                                         opp-hz = /bits/ 64 <202000000>;
2701                                         required-opps = <&rpmhpd_opp_svs_l1>;
2702                                 };
2703                         };
2704                 };
2705
2706                 videocc: clock-controller@aaf0000 {
2707                         compatible = "qcom,sm8550-videocc";
2708                         reg = <0 0x0aaf0000 0 0x10000>;
2709                         clocks = <&bi_tcxo_div2>,
2710                                  <&gcc GCC_VIDEO_AHB_CLK>;
2711                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2712                         required-opps = <&rpmhpd_opp_low_svs>;
2713                         #clock-cells = <1>;
2714                         #reset-cells = <1>;
2715                         #power-domain-cells = <1>;
2716                 };
2717
2718                 camcc: clock-controller@ade0000 {
2719                         compatible = "qcom,sm8550-camcc";
2720                         reg = <0 0x0ade0000 0 0x20000>;
2721                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2722                                  <&bi_tcxo_div2>,
2723                                  <&bi_tcxo_ao_div2>,
2724                                  <&sleep_clk>;
2725                         power-domains = <&rpmhpd SM8550_MMCX>;
2726                         required-opps = <&rpmhpd_opp_low_svs>;
2727                         #clock-cells = <1>;
2728                         #reset-cells = <1>;
2729                         #power-domain-cells = <1>;
2730                 };
2731
2732                 mdss: display-subsystem@ae00000 {
2733                         compatible = "qcom,sm8550-mdss";
2734                         reg = <0 0x0ae00000 0 0x1000>;
2735                         reg-names = "mdss";
2736
2737                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2738                         interrupt-controller;
2739                         #interrupt-cells = <1>;
2740
2741                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2742                                  <&gcc GCC_DISP_AHB_CLK>,
2743                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2744                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2745
2746                         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2747
2748                         power-domains = <&dispcc MDSS_GDSC>;
2749
2750                         interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
2751                                         <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2752                         interconnect-names = "mdp0-mem", "mdp1-mem";
2753
2754                         iommus = <&apps_smmu 0x1c00 0x2>;
2755
2756                         #address-cells = <2>;
2757                         #size-cells = <2>;
2758                         ranges;
2759
2760                         status = "disabled";
2761
2762                         mdss_mdp: display-controller@ae01000 {
2763                                 compatible = "qcom,sm8550-dpu";
2764                                 reg = <0 0x0ae01000 0 0x8f000>,
2765                                       <0 0x0aeb0000 0 0x2008>;
2766                                 reg-names = "mdp", "vbif";
2767
2768                                 interrupt-parent = <&mdss>;
2769                                 interrupts = <0>;
2770
2771                                 clocks = <&gcc GCC_DISP_AHB_CLK>,
2772                                          <&gcc GCC_DISP_HF_AXI_CLK>,
2773                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2774                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2775                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2776                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2777                                 clock-names = "bus",
2778                                               "nrt_bus",
2779                                               "iface",
2780                                               "lut",
2781                                               "core",
2782                                               "vsync";
2783
2784                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2785
2786                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2787                                 assigned-clock-rates = <19200000>;
2788
2789                                 operating-points-v2 = <&mdp_opp_table>;
2790
2791                                 ports {
2792                                         #address-cells = <1>;
2793                                         #size-cells = <0>;
2794
2795                                         port@0 {
2796                                                 reg = <0>;
2797                                                 dpu_intf1_out: endpoint {
2798                                                         remote-endpoint = <&mdss_dsi0_in>;
2799                                                 };
2800                                         };
2801
2802                                         port@1 {
2803                                                 reg = <1>;
2804                                                 dpu_intf2_out: endpoint {
2805                                                         remote-endpoint = <&mdss_dsi1_in>;
2806                                                 };
2807                                         };
2808
2809                                         port@2 {
2810                                                 reg = <2>;
2811                                                 dpu_intf0_out: endpoint {
2812                                                         remote-endpoint = <&mdss_dp0_in>;
2813                                                 };
2814                                         };
2815                                 };
2816
2817                                 mdp_opp_table: opp-table {
2818                                         compatible = "operating-points-v2";
2819
2820                                         opp-200000000 {
2821                                                 opp-hz = /bits/ 64 <200000000>;
2822                                                 required-opps = <&rpmhpd_opp_low_svs>;
2823                                         };
2824
2825                                         opp-325000000 {
2826                                                 opp-hz = /bits/ 64 <325000000>;
2827                                                 required-opps = <&rpmhpd_opp_svs>;
2828                                         };
2829
2830                                         opp-375000000 {
2831                                                 opp-hz = /bits/ 64 <375000000>;
2832                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2833                                         };
2834
2835                                         opp-514000000 {
2836                                                 opp-hz = /bits/ 64 <514000000>;
2837                                                 required-opps = <&rpmhpd_opp_nom>;
2838                                         };
2839                                 };
2840                         };
2841
2842                         mdss_dp0: displayport-controller@ae90000 {
2843                                 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2844                                 reg = <0 0xae90000 0 0x200>,
2845                                       <0 0xae90200 0 0x200>,
2846                                       <0 0xae90400 0 0xc00>,
2847                                       <0 0xae91000 0 0x400>,
2848                                       <0 0xae91400 0 0x400>;
2849                                 interrupt-parent = <&mdss>;
2850                                 interrupts = <12>;
2851                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2852                                          <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
2853                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
2854                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
2855                                          <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
2856                                 clock-names = "core_iface",
2857                                               "core_aux",
2858                                               "ctrl_link",
2859                                               "ctrl_link_iface",
2860                                               "stream_pixel";
2861
2862                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2863                                                   <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
2864                                 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2865                                                          <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2866
2867                                 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
2868                                 phy-names = "dp";
2869
2870                                 #sound-dai-cells = <0>;
2871
2872                                 operating-points-v2 = <&dp_opp_table>;
2873                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2874
2875                                 status = "disabled";
2876
2877                                 ports {
2878                                         #address-cells = <1>;
2879                                         #size-cells = <0>;
2880
2881                                         port@0 {
2882                                                 reg = <0>;
2883                                                 mdss_dp0_in: endpoint {
2884                                                         remote-endpoint = <&dpu_intf0_out>;
2885                                                 };
2886                                         };
2887
2888                                         port@1 {
2889                                                 reg = <1>;
2890                                                 mdss_dp0_out: endpoint {
2891                                                 };
2892                                         };
2893                                 };
2894
2895                                 dp_opp_table: opp-table {
2896                                         compatible = "operating-points-v2";
2897
2898                                         opp-162000000 {
2899                                                 opp-hz = /bits/ 64 <162000000>;
2900                                                 required-opps = <&rpmhpd_opp_low_svs_d1>;
2901                                         };
2902
2903                                         opp-270000000 {
2904                                                 opp-hz = /bits/ 64 <270000000>;
2905                                                 required-opps = <&rpmhpd_opp_low_svs>;
2906                                         };
2907
2908                                         opp-540000000 {
2909                                                 opp-hz = /bits/ 64 <540000000>;
2910                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2911                                         };
2912
2913                                         opp-810000000 {
2914                                                 opp-hz = /bits/ 64 <810000000>;
2915                                                 required-opps = <&rpmhpd_opp_nom>;
2916                                         };
2917                                 };
2918                         };
2919
2920                         mdss_dsi0: dsi@ae94000 {
2921                                 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2922                                 reg = <0 0x0ae94000 0 0x400>;
2923                                 reg-names = "dsi_ctrl";
2924
2925                                 interrupt-parent = <&mdss>;
2926                                 interrupts = <4>;
2927
2928                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2929                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2930                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2931                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2932                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2933                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2934                                 clock-names = "byte",
2935                                               "byte_intf",
2936                                               "pixel",
2937                                               "core",
2938                                               "iface",
2939                                               "bus";
2940
2941                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2942
2943                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2944                                                   <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2945                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2946                                                          <&mdss_dsi0_phy 1>;
2947
2948                                 operating-points-v2 = <&mdss_dsi_opp_table>;
2949
2950                                 phys = <&mdss_dsi0_phy>;
2951                                 phy-names = "dsi";
2952
2953                                 #address-cells = <1>;
2954                                 #size-cells = <0>;
2955
2956                                 status = "disabled";
2957
2958                                 ports {
2959                                         #address-cells = <1>;
2960                                         #size-cells = <0>;
2961
2962                                         port@0 {
2963                                                 reg = <0>;
2964                                                 mdss_dsi0_in: endpoint {
2965                                                         remote-endpoint = <&dpu_intf1_out>;
2966                                                 };
2967                                         };
2968
2969                                         port@1 {
2970                                                 reg = <1>;
2971                                                 mdss_dsi0_out: endpoint {
2972                                                 };
2973                                         };
2974                                 };
2975
2976                                 mdss_dsi_opp_table: opp-table {
2977                                         compatible = "operating-points-v2";
2978
2979                                         opp-187500000 {
2980                                                 opp-hz = /bits/ 64 <187500000>;
2981                                                 required-opps = <&rpmhpd_opp_low_svs>;
2982                                         };
2983
2984                                         opp-300000000 {
2985                                                 opp-hz = /bits/ 64 <300000000>;
2986                                                 required-opps = <&rpmhpd_opp_svs>;
2987                                         };
2988
2989                                         opp-358000000 {
2990                                                 opp-hz = /bits/ 64 <358000000>;
2991                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2992                                         };
2993                                 };
2994                         };
2995
2996                         mdss_dsi0_phy: phy@ae95000 {
2997                                 compatible = "qcom,sm8550-dsi-phy-4nm";
2998                                 reg = <0 0x0ae95000 0 0x200>,
2999                                       <0 0x0ae95200 0 0x280>,
3000                                       <0 0x0ae95500 0 0x400>;
3001                                 reg-names = "dsi_phy",
3002                                             "dsi_phy_lane",
3003                                             "dsi_pll";
3004
3005                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3006                                          <&rpmhcc RPMH_CXO_CLK>;
3007                                 clock-names = "iface", "ref";
3008
3009                                 #clock-cells = <1>;
3010                                 #phy-cells = <0>;
3011
3012                                 status = "disabled";
3013                         };
3014
3015                         mdss_dsi1: dsi@ae96000 {
3016                                 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3017                                 reg = <0 0x0ae96000 0 0x400>;
3018                                 reg-names = "dsi_ctrl";
3019
3020                                 interrupt-parent = <&mdss>;
3021                                 interrupts = <5>;
3022
3023                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3024                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3025                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3026                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3027                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3028                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3029                                 clock-names = "byte",
3030                                               "byte_intf",
3031                                               "pixel",
3032                                               "core",
3033                                               "iface",
3034                                               "bus";
3035
3036                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
3037
3038                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3039                                                   <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3040                                 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3041                                                          <&mdss_dsi1_phy 1>;
3042
3043                                 operating-points-v2 = <&mdss_dsi_opp_table>;
3044
3045                                 phys = <&mdss_dsi1_phy>;
3046                                 phy-names = "dsi";
3047
3048                                 #address-cells = <1>;
3049                                 #size-cells = <0>;
3050
3051                                 status = "disabled";
3052
3053                                 ports {
3054                                         #address-cells = <1>;
3055                                         #size-cells = <0>;
3056
3057                                         port@0 {
3058                                                 reg = <0>;
3059                                                 mdss_dsi1_in: endpoint {
3060                                                         remote-endpoint = <&dpu_intf2_out>;
3061                                                 };
3062                                         };
3063
3064                                         port@1 {
3065                                                 reg = <1>;
3066                                                 mdss_dsi1_out: endpoint {
3067                                                 };
3068                                         };
3069                                 };
3070                         };
3071
3072                         mdss_dsi1_phy: phy@ae97000 {
3073                                 compatible = "qcom,sm8550-dsi-phy-4nm";
3074                                 reg = <0 0x0ae97000 0 0x200>,
3075                                       <0 0x0ae97200 0 0x280>,
3076                                       <0 0x0ae97500 0 0x400>;
3077                                 reg-names = "dsi_phy",
3078                                             "dsi_phy_lane",
3079                                             "dsi_pll";
3080
3081                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3082                                          <&rpmhcc RPMH_CXO_CLK>;
3083                                 clock-names = "iface", "ref";
3084
3085                                 #clock-cells = <1>;
3086                                 #phy-cells = <0>;
3087
3088                                 status = "disabled";
3089                         };
3090                 };
3091
3092                 dispcc: clock-controller@af00000 {
3093                         compatible = "qcom,sm8550-dispcc";
3094                         reg = <0 0x0af00000 0 0x20000>;
3095                         clocks = <&bi_tcxo_div2>,
3096                                  <&bi_tcxo_ao_div2>,
3097                                  <&gcc GCC_DISP_AHB_CLK>,
3098                                  <&sleep_clk>,
3099                                  <&mdss_dsi0_phy 0>,
3100                                  <&mdss_dsi0_phy 1>,
3101                                  <&mdss_dsi1_phy 0>,
3102                                  <&mdss_dsi1_phy 1>,
3103                                  <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3104                                  <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3105                                  <0>, /* dp1 */
3106                                  <0>,
3107                                  <0>, /* dp2 */
3108                                  <0>,
3109                                  <0>, /* dp3 */
3110                                  <0>;
3111                         power-domains = <&rpmhpd RPMHPD_MMCX>;
3112                         required-opps = <&rpmhpd_opp_low_svs>;
3113                         #clock-cells = <1>;
3114                         #reset-cells = <1>;
3115                         #power-domain-cells = <1>;
3116                 };
3117
3118                 usb_1_hsphy: phy@88e3000 {
3119                         compatible = "qcom,sm8550-snps-eusb2-phy";
3120                         reg = <0x0 0x088e3000 0x0 0x154>;
3121                         #phy-cells = <0>;
3122
3123                         clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
3124                         clock-names = "ref";
3125
3126                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3127
3128                         status = "disabled";
3129                 };
3130
3131                 usb_dp_qmpphy: phy@88e8000 {
3132                         compatible = "qcom,sm8550-qmp-usb3-dp-phy";
3133                         reg = <0x0 0x088e8000 0x0 0x3000>;
3134
3135                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3136                                  <&rpmhcc RPMH_CXO_CLK>,
3137                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3138                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3139                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3140
3141                         power-domains = <&gcc USB3_PHY_GDSC>;
3142
3143                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3144                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
3145                         reset-names = "phy", "common";
3146
3147                         #clock-cells = <1>;
3148                         #phy-cells = <1>;
3149
3150                         status = "disabled";
3151
3152                         ports {
3153                                 #address-cells = <1>;
3154                                 #size-cells = <0>;
3155
3156                                 port@0 {
3157                                         reg = <0>;
3158
3159                                         usb_dp_qmpphy_out: endpoint {
3160                                         };
3161                                 };
3162
3163                                 port@1 {
3164                                         reg = <1>;
3165
3166                                         usb_dp_qmpphy_usb_ss_in: endpoint {
3167                                         };
3168                                 };
3169
3170                                 port@2 {
3171                                         reg = <2>;
3172
3173                                         usb_dp_qmpphy_dp_in: endpoint {
3174                                         };
3175                                 };
3176                         };
3177                 };
3178
3179                 usb_1: usb@a6f8800 {
3180                         compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
3181                         reg = <0x0 0x0a6f8800 0x0 0x400>;
3182                         #address-cells = <2>;
3183                         #size-cells = <2>;
3184                         ranges;
3185
3186                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3187                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3188                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3189                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3190                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3191                                  <&tcsr TCSR_USB3_CLKREF_EN>;
3192                         clock-names = "cfg_noc",
3193                                       "core",
3194                                       "iface",
3195                                       "sleep",
3196                                       "mock_utmi",
3197                                       "xo";
3198
3199                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3200                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3201                         assigned-clock-rates = <19200000>, <200000000>;
3202
3203                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3204                                               <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3205                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3206                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3207                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
3208                         interrupt-names = "pwr_event",
3209                                           "hs_phy_irq",
3210                                           "dp_hs_phy_irq",
3211                                           "dm_hs_phy_irq",
3212                                           "ss_phy_irq";
3213
3214                         power-domains = <&gcc USB30_PRIM_GDSC>;
3215                         required-opps = <&rpmhpd_opp_nom>;
3216
3217                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3218
3219                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3220                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3221                         interconnect-names = "usb-ddr", "apps-usb";
3222
3223                         status = "disabled";
3224
3225                         usb_1_dwc3: usb@a600000 {
3226                                 compatible = "snps,dwc3";
3227                                 reg = <0x0 0x0a600000 0x0 0xcd00>;
3228                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3229                                 iommus = <&apps_smmu 0x40 0x0>;
3230                                 snps,dis_u2_susphy_quirk;
3231                                 snps,dis_enblslpm_quirk;
3232                                 snps,usb3_lpm_capable;
3233                                 phys = <&usb_1_hsphy>,
3234                                        <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
3235                                 phy-names = "usb2-phy", "usb3-phy";
3236
3237                                 ports {
3238                                         #address-cells = <1>;
3239                                         #size-cells = <0>;
3240
3241                                         port@0 {
3242                                                 reg = <0>;
3243
3244                                                 usb_1_dwc3_hs: endpoint {
3245                                                 };
3246                                         };
3247
3248                                         port@1 {
3249                                                 reg = <1>;
3250
3251                                                 usb_1_dwc3_ss: endpoint {
3252                                                 };
3253                                         };
3254                                 };
3255                         };
3256                 };
3257
3258                 pdc: interrupt-controller@b220000 {
3259                         compatible = "qcom,sm8550-pdc", "qcom,pdc";
3260                         reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3261                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3262                                           <125 63 1>, <126 716 12>,
3263                                           <138 251 5>;
3264                         #interrupt-cells = <2>;
3265                         interrupt-parent = <&intc>;
3266                         interrupt-controller;
3267                 };
3268
3269                 tsens0: thermal-sensor@c271000 {
3270                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3271                         reg = <0 0x0c271000 0 0x1000>, /* TM */
3272                               <0 0x0c222000 0 0x1000>; /* SROT */
3273                         #qcom,sensors = <16>;
3274                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3275                                      <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
3276                         interrupt-names = "uplow", "critical";
3277                         #thermal-sensor-cells = <1>;
3278                 };
3279
3280                 tsens1: thermal-sensor@c272000 {
3281                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3282                         reg = <0 0x0c272000 0 0x1000>, /* TM */
3283                               <0 0x0c223000 0 0x1000>; /* SROT */
3284                         #qcom,sensors = <16>;
3285                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3286                                      <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
3287                         interrupt-names = "uplow", "critical";
3288                         #thermal-sensor-cells = <1>;
3289                 };
3290
3291                 tsens2: thermal-sensor@c273000 {
3292                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3293                         reg = <0 0x0c273000 0 0x1000>, /* TM */
3294                               <0 0x0c224000 0 0x1000>; /* SROT */
3295                         #qcom,sensors = <16>;
3296                         interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
3297                                      <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
3298                         interrupt-names = "uplow", "critical";
3299                         #thermal-sensor-cells = <1>;
3300                 };
3301
3302                 aoss_qmp: power-management@c300000 {
3303                         compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3304                         reg = <0 0x0c300000 0 0x400>;
3305                         interrupt-parent = <&ipcc>;
3306                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3307                                                      IRQ_TYPE_EDGE_RISING>;
3308                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3309
3310                         #clock-cells = <0>;
3311                 };
3312
3313                 sram@c3f0000 {
3314                         compatible = "qcom,rpmh-stats";
3315                         reg = <0 0x0c3f0000 0 0x400>;
3316                 };
3317
3318                 spmi_bus: spmi@c400000 {
3319                         compatible = "qcom,spmi-pmic-arb";
3320                         reg = <0 0x0c400000 0 0x3000>,
3321                               <0 0x0c500000 0 0x400000>,
3322                               <0 0x0c440000 0 0x80000>,
3323                               <0 0x0c4c0000 0 0x20000>,
3324                               <0 0x0c42d000 0 0x4000>;
3325                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3326                         interrupt-names = "periph_irq";
3327                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3328                         qcom,ee = <0>;
3329                         qcom,channel = <0>;
3330                         qcom,bus-id = <0>;
3331                         #address-cells = <2>;
3332                         #size-cells = <0>;
3333                         interrupt-controller;
3334                         #interrupt-cells = <4>;
3335                 };
3336
3337                 tlmm: pinctrl@f100000 {
3338                         compatible = "qcom,sm8550-tlmm";
3339                         reg = <0 0x0f100000 0 0x300000>;
3340                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3341                         gpio-controller;
3342                         #gpio-cells = <2>;
3343                         interrupt-controller;
3344                         #interrupt-cells = <2>;
3345                         gpio-ranges = <&tlmm 0 0 211>;
3346                         wakeup-parent = <&pdc>;
3347
3348                         hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3349                                 /* SDA, SCL */
3350                                 pins = "gpio16", "gpio17";
3351                                 function = "i2chub0_se0";
3352                                 drive-strength = <2>;
3353                                 bias-pull-up;
3354                         };
3355
3356                         hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3357                                 /* SDA, SCL */
3358                                 pins = "gpio18", "gpio19";
3359                                 function = "i2chub0_se1";
3360                                 drive-strength = <2>;
3361                                 bias-pull-up;
3362                         };
3363
3364                         hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3365                                 /* SDA, SCL */
3366                                 pins = "gpio20", "gpio21";
3367                                 function = "i2chub0_se2";
3368                                 drive-strength = <2>;
3369                                 bias-pull-up;
3370                         };
3371
3372                         hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3373                                 /* SDA, SCL */
3374                                 pins = "gpio22", "gpio23";
3375                                 function = "i2chub0_se3";
3376                                 drive-strength = <2>;
3377                                 bias-pull-up;
3378                         };
3379
3380                         hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3381                                 /* SDA, SCL */
3382                                 pins = "gpio4", "gpio5";
3383                                 function = "i2chub0_se4";
3384                                 drive-strength = <2>;
3385                                 bias-pull-up;
3386                         };
3387
3388                         hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3389                                 /* SDA, SCL */
3390                                 pins = "gpio6", "gpio7";
3391                                 function = "i2chub0_se5";
3392                                 drive-strength = <2>;
3393                                 bias-pull-up;
3394                         };
3395
3396                         hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3397                                 /* SDA, SCL */
3398                                 pins = "gpio8", "gpio9";
3399                                 function = "i2chub0_se6";
3400                                 drive-strength = <2>;
3401                                 bias-pull-up;
3402                         };
3403
3404                         hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3405                                 /* SDA, SCL */
3406                                 pins = "gpio10", "gpio11";
3407                                 function = "i2chub0_se7";
3408                                 drive-strength = <2>;
3409                                 bias-pull-up;
3410                         };
3411
3412                         hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3413                                 /* SDA, SCL */
3414                                 pins = "gpio206", "gpio207";
3415                                 function = "i2chub0_se8";
3416                                 drive-strength = <2>;
3417                                 bias-pull-up;
3418                         };
3419
3420                         hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3421                                 /* SDA, SCL */
3422                                 pins = "gpio84", "gpio85";
3423                                 function = "i2chub0_se9";
3424                                 drive-strength = <2>;
3425                                 bias-pull-up;
3426                         };
3427
3428                         pcie0_default_state: pcie0-default-state {
3429                                 perst-pins {
3430                                         pins = "gpio94";
3431                                         function = "gpio";
3432                                         drive-strength = <2>;
3433                                         bias-pull-down;
3434                                 };
3435
3436                                 clkreq-pins {
3437                                         pins = "gpio95";
3438                                         function = "pcie0_clk_req_n";
3439                                         drive-strength = <2>;
3440                                         bias-pull-up;
3441                                 };
3442
3443                                 wake-pins {
3444                                         pins = "gpio96";
3445                                         function = "gpio";
3446                                         drive-strength = <2>;
3447                                         bias-pull-up;
3448                                 };
3449                         };
3450
3451                         pcie1_default_state: pcie1-default-state {
3452                                 perst-pins {
3453                                         pins = "gpio97";
3454                                         function = "gpio";
3455                                         drive-strength = <2>;
3456                                         bias-pull-down;
3457                                 };
3458
3459                                 clkreq-pins {
3460                                         pins = "gpio98";
3461                                         function = "pcie1_clk_req_n";
3462                                         drive-strength = <2>;
3463                                         bias-pull-up;
3464                                 };
3465
3466                                 wake-pins {
3467                                         pins = "gpio99";
3468                                         function = "gpio";
3469                                         drive-strength = <2>;
3470                                         bias-pull-up;
3471                                 };
3472                         };
3473
3474                         qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3475                                 /* SDA, SCL */
3476                                 pins = "gpio28", "gpio29";
3477                                 function = "qup1_se0";
3478                                 drive-strength = <2>;
3479                                 bias-pull-up = <2200>;
3480                         };
3481
3482                         qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3483                                 /* SDA, SCL */
3484                                 pins = "gpio32", "gpio33";
3485                                 function = "qup1_se1";
3486                                 drive-strength = <2>;
3487                                 bias-pull-up = <2200>;
3488                         };
3489
3490                         qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3491                                 /* SDA, SCL */
3492                                 pins = "gpio36", "gpio37";
3493                                 function = "qup1_se2";
3494                                 drive-strength = <2>;
3495                                 bias-pull-up = <2200>;
3496                         };
3497
3498                         qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3499                                 /* SDA, SCL */
3500                                 pins = "gpio40", "gpio41";
3501                                 function = "qup1_se3";
3502                                 drive-strength = <2>;
3503                                 bias-pull-up = <2200>;
3504                         };
3505
3506                         qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3507                                 /* SDA, SCL */
3508                                 pins = "gpio44", "gpio45";
3509                                 function = "qup1_se4";
3510                                 drive-strength = <2>;
3511                                 bias-pull-up = <2200>;
3512                         };
3513
3514                         qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3515                                 /* SDA, SCL */
3516                                 pins = "gpio52", "gpio53";
3517                                 function = "qup1_se5";
3518                                 drive-strength = <2>;
3519                                 bias-pull-up = <2200>;
3520                         };
3521
3522                         qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3523                                 /* SDA, SCL */
3524                                 pins = "gpio48", "gpio49";
3525                                 function = "qup1_se6";
3526                                 drive-strength = <2>;
3527                                 bias-pull-up = <2200>;
3528                         };
3529
3530                         qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3531                                 scl-pins {
3532                                         pins = "gpio57";
3533                                         function = "qup2_se0_l1_mira";
3534                                         drive-strength = <2>;
3535                                         bias-pull-up = <2200>;
3536                                 };
3537
3538                                 sda-pins {
3539                                         pins = "gpio56";
3540                                         function = "qup2_se0_l0_mira";
3541                                         drive-strength = <2>;
3542                                         bias-pull-up = <2200>;
3543                                 };
3544                         };
3545
3546                         qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3547                                 /* SDA, SCL */
3548                                 pins = "gpio60", "gpio61";
3549                                 function = "qup2_se1";
3550                                 drive-strength = <2>;
3551                                 bias-pull-up = <2200>;
3552                         };
3553
3554                         qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3555                                 /* SDA, SCL */
3556                                 pins = "gpio64", "gpio65";
3557                                 function = "qup2_se2";
3558                                 drive-strength = <2>;
3559                                 bias-pull-up = <2200>;
3560                         };
3561
3562                         qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3563                                 /* SDA, SCL */
3564                                 pins = "gpio68", "gpio69";
3565                                 function = "qup2_se3";
3566                                 drive-strength = <2>;
3567                                 bias-pull-up = <2200>;
3568                         };
3569
3570                         qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3571                                 /* SDA, SCL */
3572                                 pins = "gpio2", "gpio3";
3573                                 function = "qup2_se4";
3574                                 drive-strength = <2>;
3575                                 bias-pull-up = <2200>;
3576                         };
3577
3578                         qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3579                                 /* SDA, SCL */
3580                                 pins = "gpio80", "gpio81";
3581                                 function = "qup2_se5";
3582                                 drive-strength = <2>;
3583                                 bias-pull-up = <2200>;
3584                         };
3585
3586                         qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3587                                 /* SDA, SCL */
3588                                 pins = "gpio72", "gpio106";
3589                                 function = "qup2_se7";
3590                                 drive-strength = <2>;
3591                                 bias-pull-up = <2200>;
3592                         };
3593
3594                         qup_spi0_cs: qup-spi0-cs-state {
3595                                 pins = "gpio31";
3596                                 function = "qup1_se0";
3597                                 drive-strength = <6>;
3598                                 bias-disable;
3599                         };
3600
3601                         qup_spi0_data_clk: qup-spi0-data-clk-state {
3602                                 /* MISO, MOSI, CLK */
3603                                 pins = "gpio28", "gpio29", "gpio30";
3604                                 function = "qup1_se0";
3605                                 drive-strength = <6>;
3606                                 bias-disable;
3607                         };
3608
3609                         qup_spi1_cs: qup-spi1-cs-state {
3610                                 pins = "gpio35";
3611                                 function = "qup1_se1";
3612                                 drive-strength = <6>;
3613                                 bias-disable;
3614                         };
3615
3616                         qup_spi1_data_clk: qup-spi1-data-clk-state {
3617                                 /* MISO, MOSI, CLK */
3618                                 pins = "gpio32", "gpio33", "gpio34";
3619                                 function = "qup1_se1";
3620                                 drive-strength = <6>;
3621                                 bias-disable;
3622                         };
3623
3624                         qup_spi2_cs: qup-spi2-cs-state {
3625                                 pins = "gpio39";
3626                                 function = "qup1_se2";
3627                                 drive-strength = <6>;
3628                                 bias-disable;
3629                         };
3630
3631                         qup_spi2_data_clk: qup-spi2-data-clk-state {
3632                                 /* MISO, MOSI, CLK */
3633                                 pins = "gpio36", "gpio37", "gpio38";
3634                                 function = "qup1_se2";
3635                                 drive-strength = <6>;
3636                                 bias-disable;
3637                         };
3638
3639                         qup_spi3_cs: qup-spi3-cs-state {
3640                                 pins = "gpio43";
3641                                 function = "qup1_se3";
3642                                 drive-strength = <6>;
3643                                 bias-disable;
3644                         };
3645
3646                         qup_spi3_data_clk: qup-spi3-data-clk-state {
3647                                 /* MISO, MOSI, CLK */
3648                                 pins = "gpio40", "gpio41", "gpio42";
3649                                 function = "qup1_se3";
3650                                 drive-strength = <6>;
3651                                 bias-disable;
3652                         };
3653
3654                         qup_spi4_cs: qup-spi4-cs-state {
3655                                 pins = "gpio47";
3656                                 function = "qup1_se4";
3657                                 drive-strength = <6>;
3658                                 bias-disable;
3659                         };
3660
3661                         qup_spi4_data_clk: qup-spi4-data-clk-state {
3662                                 /* MISO, MOSI, CLK */
3663                                 pins = "gpio44", "gpio45", "gpio46";
3664                                 function = "qup1_se4";
3665                                 drive-strength = <6>;
3666                                 bias-disable;
3667                         };
3668
3669                         qup_spi5_cs: qup-spi5-cs-state {
3670                                 pins = "gpio55";
3671                                 function = "qup1_se5";
3672                                 drive-strength = <6>;
3673                                 bias-disable;
3674                         };
3675
3676                         qup_spi5_data_clk: qup-spi5-data-clk-state {
3677                                 /* MISO, MOSI, CLK */
3678                                 pins = "gpio52", "gpio53", "gpio54";
3679                                 function = "qup1_se5";
3680                                 drive-strength = <6>;
3681                                 bias-disable;
3682                         };
3683
3684                         qup_spi6_cs: qup-spi6-cs-state {
3685                                 pins = "gpio51";
3686                                 function = "qup1_se6";
3687                                 drive-strength = <6>;
3688                                 bias-disable;
3689                         };
3690
3691                         qup_spi6_data_clk: qup-spi6-data-clk-state {
3692                                 /* MISO, MOSI, CLK */
3693                                 pins = "gpio48", "gpio49", "gpio50";
3694                                 function = "qup1_se6";
3695                                 drive-strength = <6>;
3696                                 bias-disable;
3697                         };
3698
3699                         qup_spi8_cs: qup-spi8-cs-state {
3700                                 pins = "gpio59";
3701                                 function = "qup2_se0_l3_mira";
3702                                 drive-strength = <6>;
3703                                 bias-disable;
3704                         };
3705
3706                         qup_spi8_data_clk: qup-spi8-data-clk-state {
3707                                 /* MISO, MOSI, CLK */
3708                                 pins = "gpio56", "gpio57", "gpio58";
3709                                 function = "qup2_se0_l2_mira";
3710                                 drive-strength = <6>;
3711                                 bias-disable;
3712                         };
3713
3714                         qup_spi9_cs: qup-spi9-cs-state {
3715                                 pins = "gpio63";
3716                                 function = "qup2_se1";
3717                                 drive-strength = <6>;
3718                                 bias-disable;
3719                         };
3720
3721                         qup_spi9_data_clk: qup-spi9-data-clk-state {
3722                                 /* MISO, MOSI, CLK */
3723                                 pins = "gpio60", "gpio61", "gpio62";
3724                                 function = "qup2_se1";
3725                                 drive-strength = <6>;
3726                                 bias-disable;
3727                         };
3728
3729                         qup_spi10_cs: qup-spi10-cs-state {
3730                                 pins = "gpio67";
3731                                 function = "qup2_se2";
3732                                 drive-strength = <6>;
3733                                 bias-disable;
3734                         };
3735
3736                         qup_spi10_data_clk: qup-spi10-data-clk-state {
3737                                 /* MISO, MOSI, CLK */
3738                                 pins = "gpio64", "gpio65", "gpio66";
3739                                 function = "qup2_se2";
3740                                 drive-strength = <6>;
3741                                 bias-disable;
3742                         };
3743
3744                         qup_spi11_cs: qup-spi11-cs-state {
3745                                 pins = "gpio71";
3746                                 function = "qup2_se3";
3747                                 drive-strength = <6>;
3748                                 bias-disable;
3749                         };
3750
3751                         qup_spi11_data_clk: qup-spi11-data-clk-state {
3752                                 /* MISO, MOSI, CLK */
3753                                 pins = "gpio68", "gpio69", "gpio70";
3754                                 function = "qup2_se3";
3755                                 drive-strength = <6>;
3756                                 bias-disable;
3757                         };
3758
3759                         qup_spi12_cs: qup-spi12-cs-state {
3760                                 pins = "gpio119";
3761                                 function = "qup2_se4";
3762                                 drive-strength = <6>;
3763                                 bias-disable;
3764                         };
3765
3766                         qup_spi12_data_clk: qup-spi12-data-clk-state {
3767                                 /* MISO, MOSI, CLK */
3768                                 pins = "gpio2", "gpio3", "gpio118";
3769                                 function = "qup2_se4";
3770                                 drive-strength = <6>;
3771                                 bias-disable;
3772                         };
3773
3774                         qup_spi13_cs: qup-spi13-cs-state {
3775                                 pins = "gpio83";
3776                                 function = "qup2_se5";
3777                                 drive-strength = <6>;
3778                                 bias-disable;
3779                         };
3780
3781                         qup_spi13_data_clk: qup-spi13-data-clk-state {
3782                                 /* MISO, MOSI, CLK */
3783                                 pins = "gpio80", "gpio81", "gpio82";
3784                                 function = "qup2_se5";
3785                                 drive-strength = <6>;
3786                                 bias-disable;
3787                         };
3788
3789                         qup_spi15_cs: qup-spi15-cs-state {
3790                                 pins = "gpio75";
3791                                 function = "qup2_se7";
3792                                 drive-strength = <6>;
3793                                 bias-disable;
3794                         };
3795
3796                         qup_spi15_data_clk: qup-spi15-data-clk-state {
3797                                 /* MISO, MOSI, CLK */
3798                                 pins = "gpio72", "gpio106", "gpio74";
3799                                 function = "qup2_se7";
3800                                 drive-strength = <6>;
3801                                 bias-disable;
3802                         };
3803
3804                         qup_uart7_default: qup-uart7-default-state {
3805                                 /* TX, RX */
3806                                 pins = "gpio26", "gpio27";
3807                                 function = "qup1_se7";
3808                                 drive-strength = <2>;
3809                                 bias-disable;
3810                         };
3811
3812                         qup_uart14_default: qup-uart14-default-state {
3813                                 /* TX, RX */
3814                                 pins = "gpio78", "gpio79";
3815                                 function = "qup2_se6";
3816                                 drive-strength = <2>;
3817                                 bias-pull-up;
3818                         };
3819
3820                         qup_uart14_cts_rts: qup-uart14-cts-rts-state {
3821                                 /* CTS, RTS */
3822                                 pins = "gpio76", "gpio77";
3823                                 function = "qup2_se6";
3824                                 drive-strength = <2>;
3825                                 bias-pull-down;
3826                         };
3827
3828                         sdc2_sleep: sdc2-sleep-state {
3829                                 clk-pins {
3830                                         pins = "sdc2_clk";
3831                                         bias-disable;
3832                                         drive-strength = <2>;
3833                                 };
3834
3835                                 cmd-pins {
3836                                         pins = "sdc2_cmd";
3837                                         bias-pull-up;
3838                                         drive-strength = <2>;
3839                                 };
3840
3841                                 data-pins {
3842                                         pins = "sdc2_data";
3843                                         bias-pull-up;
3844                                         drive-strength = <2>;
3845                                 };
3846                         };
3847
3848                         sdc2_default: sdc2-default-state {
3849                                 clk-pins {
3850                                         pins = "sdc2_clk";
3851                                         bias-disable;
3852                                         drive-strength = <16>;
3853                                 };
3854
3855                                 cmd-pins {
3856                                         pins = "sdc2_cmd";
3857                                         bias-pull-up;
3858                                         drive-strength = <10>;
3859                                 };
3860
3861                                 data-pins {
3862                                         pins = "sdc2_data";
3863                                         bias-pull-up;
3864                                         drive-strength = <10>;
3865                                 };
3866                         };
3867                 };
3868
3869                 apps_smmu: iommu@15000000 {
3870                         compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3871                         reg = <0 0x15000000 0 0x100000>;
3872                         #iommu-cells = <2>;
3873                         #global-interrupts = <1>;
3874                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3875                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3876                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3877                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3878                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3879                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3880                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3881                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3882                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3883                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3884                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3885                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3886                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3887                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3888                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3889                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3890                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3891                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3892                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3893                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3894                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3895                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3896                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3897                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3898                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3899                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3900                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3901                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3902                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3903                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3904                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3905                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3906                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3907                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3908                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3909                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3910                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3911                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3912                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3913                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3914                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3915                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3916                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3917                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3918                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3919                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3920                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3921                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3922                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3923                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3924                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3925                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3926                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3927                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3928                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3929                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3930                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3931                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3932                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3933                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3934                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3935                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3936                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3937                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3938                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3939                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3940                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3941                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3942                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3943                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3944                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3945                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3946                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3947                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3948                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3949                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3950                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3951                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3952                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3953                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3954                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3955                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3956                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3957                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3958                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3959                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3960                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3961                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3962                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3963                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
3964                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3965                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3966                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3967                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3968                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3969                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3970                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
3971                 };
3972
3973                 intc: interrupt-controller@17100000 {
3974                         compatible = "arm,gic-v3";
3975                         reg = <0 0x17100000 0 0x10000>,         /* GICD */
3976                               <0 0x17180000 0 0x200000>;        /* GICR * 8 */
3977                         ranges;
3978                         #interrupt-cells = <3>;
3979                         interrupt-controller;
3980                         #redistributor-regions = <1>;
3981                         redistributor-stride = <0 0x40000>;
3982                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
3983                         #address-cells = <2>;
3984                         #size-cells = <2>;
3985
3986                         gic_its: msi-controller@17140000 {
3987                                 compatible = "arm,gic-v3-its";
3988                                 reg = <0 0x17140000 0 0x20000>;
3989                                 msi-controller;
3990                                 #msi-cells = <1>;
3991                         };
3992                 };
3993
3994                 timer@17420000 {
3995                         compatible = "arm,armv7-timer-mem";
3996                         reg = <0 0x17420000 0 0x1000>;
3997                         ranges = <0 0 0 0x20000000>;
3998                         #address-cells = <1>;
3999                         #size-cells = <1>;
4000
4001                         frame@17421000 {
4002                                 reg = <0x17421000 0x1000>,
4003                                       <0x17422000 0x1000>;
4004                                 frame-number = <0>;
4005                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4006                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4007                         };
4008
4009                         frame@17423000 {
4010                                 reg = <0x17423000 0x1000>;
4011                                 frame-number = <1>;
4012                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4013                                 status = "disabled";
4014                         };
4015
4016                         frame@17425000 {
4017                                 reg = <0x17425000 0x1000>;
4018                                 frame-number = <2>;
4019                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4020                                 status = "disabled";
4021                         };
4022
4023                         frame@17427000 {
4024                                 reg = <0x17427000 0x1000>;
4025                                 frame-number = <3>;
4026                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4027                                 status = "disabled";
4028                         };
4029
4030                         frame@17429000 {
4031                                 reg = <0x17429000 0x1000>;
4032                                 frame-number = <4>;
4033                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4034                                 status = "disabled";
4035                         };
4036
4037                         frame@1742b000 {
4038                                 reg = <0x1742b000 0x1000>;
4039                                 frame-number = <5>;
4040                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4041                                 status = "disabled";
4042                         };
4043
4044                         frame@1742d000 {
4045                                 reg = <0x1742d000 0x1000>;
4046                                 frame-number = <6>;
4047                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4048                                 status = "disabled";
4049                         };
4050                 };
4051
4052                 apps_rsc: rsc@17a00000 {
4053                         label = "apps_rsc";
4054                         compatible = "qcom,rpmh-rsc";
4055                         reg = <0 0x17a00000 0 0x10000>,
4056                               <0 0x17a10000 0 0x10000>,
4057                               <0 0x17a20000 0 0x10000>,
4058                               <0 0x17a30000 0 0x10000>;
4059                         reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4060                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4061                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4062                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4063                         qcom,tcs-offset = <0xd00>;
4064                         qcom,drv-id = <2>;
4065                         qcom,tcs-config = <ACTIVE_TCS    3>, <SLEEP_TCS     2>,
4066                                           <WAKE_TCS      2>, <CONTROL_TCS   0>;
4067                         power-domains = <&CLUSTER_PD>;
4068
4069                         apps_bcm_voter: bcm-voter {
4070                                 compatible = "qcom,bcm-voter";
4071                         };
4072
4073                         rpmhcc: clock-controller {
4074                                 compatible = "qcom,sm8550-rpmh-clk";
4075                                 #clock-cells = <1>;
4076                                 clock-names = "xo";
4077                                 clocks = <&xo_board>;
4078                         };
4079
4080                         rpmhpd: power-controller {
4081                                 compatible = "qcom,sm8550-rpmhpd";
4082                                 #power-domain-cells = <1>;
4083                                 operating-points-v2 = <&rpmhpd_opp_table>;
4084
4085                                 rpmhpd_opp_table: opp-table {
4086                                         compatible = "operating-points-v2";
4087
4088                                         rpmhpd_opp_ret: opp-16 {
4089                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4090                                         };
4091
4092                                         rpmhpd_opp_min_svs: opp-48 {
4093                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4094                                         };
4095
4096                                         rpmhpd_opp_low_svs_d2: opp-52 {
4097                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4098                                         };
4099
4100                                         rpmhpd_opp_low_svs_d1: opp-56 {
4101                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4102                                         };
4103
4104                                         rpmhpd_opp_low_svs_d0: opp-60 {
4105                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4106                                         };
4107
4108                                         rpmhpd_opp_low_svs: opp-64 {
4109                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4110                                         };
4111
4112                                         rpmhpd_opp_low_svs_l1: opp-80 {
4113                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4114                                         };
4115
4116                                         rpmhpd_opp_svs: opp-128 {
4117                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4118                                         };
4119
4120                                         rpmhpd_opp_svs_l0: opp-144 {
4121                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4122                                         };
4123
4124                                         rpmhpd_opp_svs_l1: opp-192 {
4125                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4126                                         };
4127
4128                                         rpmhpd_opp_nom: opp-256 {
4129                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4130                                         };
4131
4132                                         rpmhpd_opp_nom_l1: opp-320 {
4133                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4134                                         };
4135
4136                                         rpmhpd_opp_nom_l2: opp-336 {
4137                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4138                                         };
4139
4140                                         rpmhpd_opp_turbo: opp-384 {
4141                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4142                                         };
4143
4144                                         rpmhpd_opp_turbo_l1: opp-416 {
4145                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4146                                         };
4147                                 };
4148                         };
4149                 };
4150
4151                 cpufreq_hw: cpufreq@17d91000 {
4152                         compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
4153                         reg = <0 0x17d91000 0 0x1000>,
4154                               <0 0x17d92000 0 0x1000>,
4155                               <0 0x17d93000 0 0x1000>;
4156                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4157                         clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
4158                         clock-names = "xo", "alternate";
4159                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4160                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4161                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4162                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4163                         #freq-domain-cells = <1>;
4164                         #clock-cells = <1>;
4165                 };
4166
4167                 pmu@24091000 {
4168                         compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4169                         reg = <0 0x24091000 0 0x1000>;
4170                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
4171                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
4172
4173                         operating-points-v2 = <&llcc_bwmon_opp_table>;
4174
4175                         llcc_bwmon_opp_table: opp-table {
4176                                 compatible = "operating-points-v2";
4177
4178                                 opp-0 {
4179                                         opp-peak-kBps = <2086000>;
4180                                 };
4181
4182                                 opp-1 {
4183                                         opp-peak-kBps = <2929000>;
4184                                 };
4185
4186                                 opp-2 {
4187                                         opp-peak-kBps = <5931000>;
4188                                 };
4189
4190                                 opp-3 {
4191                                         opp-peak-kBps = <6515000>;
4192                                 };
4193
4194                                 opp-4 {
4195                                         opp-peak-kBps = <7980000>;
4196                                 };
4197
4198                                 opp-5 {
4199                                         opp-peak-kBps = <10437000>;
4200                                 };
4201
4202                                 opp-6 {
4203                                         opp-peak-kBps = <12157000>;
4204                                 };
4205
4206                                 opp-7 {
4207                                         opp-peak-kBps = <14060000>;
4208                                 };
4209
4210                                 opp-8 {
4211                                         opp-peak-kBps = <16113000>;
4212                                 };
4213                         };
4214                 };
4215
4216                 pmu@240b6400 {
4217                         compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
4218                         reg = <0 0x240b6400 0 0x600>;
4219                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4220                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
4221
4222                         operating-points-v2 = <&cpu_bwmon_opp_table>;
4223
4224                         cpu_bwmon_opp_table: opp-table {
4225                                 compatible = "operating-points-v2";
4226
4227                                 opp-0 {
4228                                         opp-peak-kBps = <4577000>;
4229                                 };
4230
4231                                 opp-1 {
4232                                         opp-peak-kBps = <7110000>;
4233                                 };
4234
4235                                 opp-2 {
4236                                         opp-peak-kBps = <9155000>;
4237                                 };
4238
4239                                 opp-3 {
4240                                         opp-peak-kBps = <12298000>;
4241                                 };
4242
4243                                 opp-4 {
4244                                         opp-peak-kBps = <14236000>;
4245                                 };
4246
4247                                 opp-5 {
4248                                         opp-peak-kBps = <16265000>;
4249                                 };
4250                         };
4251                 };
4252
4253                 gem_noc: interconnect@24100000 {
4254                         compatible = "qcom,sm8550-gem-noc";
4255                         reg = <0 0x24100000 0 0xbb800>;
4256                         #interconnect-cells = <2>;
4257                         qcom,bcm-voters = <&apps_bcm_voter>;
4258                 };
4259
4260                 system-cache-controller@25000000 {
4261                         compatible = "qcom,sm8550-llcc";
4262                         reg = <0 0x25000000 0 0x200000>,
4263                               <0 0x25200000 0 0x200000>,
4264                               <0 0x25400000 0 0x200000>,
4265                               <0 0x25600000 0 0x200000>,
4266                               <0 0x25800000 0 0x200000>;
4267                         reg-names = "llcc0_base",
4268                                     "llcc1_base",
4269                                     "llcc2_base",
4270                                     "llcc3_base",
4271                                     "llcc_broadcast_base";
4272                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4273                 };
4274
4275                 remoteproc_adsp: remoteproc@30000000 {
4276                         compatible = "qcom,sm8550-adsp-pas";
4277                         reg = <0x0 0x30000000 0x0 0x100>;
4278
4279                         interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4280                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4281                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
4282                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
4283                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
4284                         interrupt-names = "wdog", "fatal", "ready",
4285                                           "handover", "stop-ack";
4286
4287                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4288                         clock-names = "xo";
4289
4290                         power-domains = <&rpmhpd RPMHPD_LCX>,
4291                                         <&rpmhpd RPMHPD_LMX>;
4292                         power-domain-names = "lcx", "lmx";
4293
4294                         interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
4295
4296                         memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
4297
4298                         qcom,qmp = <&aoss_qmp>;
4299
4300                         qcom,smem-states = <&smp2p_adsp_out 0>;
4301                         qcom,smem-state-names = "stop";
4302
4303                         status = "disabled";
4304
4305                         remoteproc_adsp_glink: glink-edge {
4306                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4307                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4308                                                              IRQ_TYPE_EDGE_RISING>;
4309                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
4310                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4311
4312                                 label = "lpass";
4313                                 qcom,remote-pid = <2>;
4314
4315                                 fastrpc {
4316                                         compatible = "qcom,fastrpc";
4317                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4318                                         label = "adsp";
4319                                         #address-cells = <1>;
4320                                         #size-cells = <0>;
4321
4322                                         compute-cb@3 {
4323                                                 compatible = "qcom,fastrpc-compute-cb";
4324                                                 reg = <3>;
4325                                                 iommus = <&apps_smmu 0x1003 0x80>,
4326                                                          <&apps_smmu 0x1063 0x0>;
4327                                                 dma-coherent;
4328                                         };
4329
4330                                         compute-cb@4 {
4331                                                 compatible = "qcom,fastrpc-compute-cb";
4332                                                 reg = <4>;
4333                                                 iommus = <&apps_smmu 0x1004 0x80>,
4334                                                          <&apps_smmu 0x1064 0x0>;
4335                                                 dma-coherent;
4336                                         };
4337
4338                                         compute-cb@5 {
4339                                                 compatible = "qcom,fastrpc-compute-cb";
4340                                                 reg = <5>;
4341                                                 iommus = <&apps_smmu 0x1005 0x80>,
4342                                                          <&apps_smmu 0x1065 0x0>;
4343                                                 dma-coherent;
4344                                         };
4345
4346                                         compute-cb@6 {
4347                                                 compatible = "qcom,fastrpc-compute-cb";
4348                                                 reg = <6>;
4349                                                 iommus = <&apps_smmu 0x1006 0x80>,
4350                                                          <&apps_smmu 0x1066 0x0>;
4351                                                 dma-coherent;
4352                                         };
4353
4354                                         compute-cb@7 {
4355                                                 compatible = "qcom,fastrpc-compute-cb";
4356                                                 reg = <7>;
4357                                                 iommus = <&apps_smmu 0x1007 0x80>,
4358                                                          <&apps_smmu 0x1067 0x0>;
4359                                                 dma-coherent;
4360                                         };
4361                                 };
4362
4363                                 gpr {
4364                                         compatible = "qcom,gpr";
4365                                         qcom,glink-channels = "adsp_apps";
4366                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
4367                                         qcom,intents = <512 20>;
4368                                         #address-cells = <1>;
4369                                         #size-cells = <0>;
4370
4371                                         q6apm: service@1 {
4372                                                 compatible = "qcom,q6apm";
4373                                                 reg = <GPR_APM_MODULE_IID>;
4374                                                 #sound-dai-cells = <0>;
4375                                                 qcom,protection-domain = "avs/audio",
4376                                                                          "msm/adsp/audio_pd";
4377
4378                                                 q6apmdai: dais {
4379                                                         compatible = "qcom,q6apm-dais";
4380                                                         iommus = <&apps_smmu 0x1001 0x80>,
4381                                                                  <&apps_smmu 0x1061 0x0>;
4382                                                 };
4383
4384                                                 q6apmbedai: bedais {
4385                                                         compatible = "qcom,q6apm-lpass-dais";
4386                                                         #sound-dai-cells = <1>;
4387                                                 };
4388                                         };
4389
4390                                         q6prm: service@2 {
4391                                                 compatible = "qcom,q6prm";
4392                                                 reg = <GPR_PRM_MODULE_IID>;
4393                                                 qcom,protection-domain = "avs/audio",
4394                                                                          "msm/adsp/audio_pd";
4395
4396                                                 q6prmcc: clock-controller {
4397                                                         compatible = "qcom,q6prm-lpass-clocks";
4398                                                         #clock-cells = <2>;
4399                                                 };
4400                                         };
4401                                 };
4402                         };
4403                 };
4404
4405                 nsp_noc: interconnect@320c0000 {
4406                         compatible = "qcom,sm8550-nsp-noc";
4407                         reg = <0 0x320c0000 0 0xe080>;
4408                         #interconnect-cells = <2>;
4409                         qcom,bcm-voters = <&apps_bcm_voter>;
4410                 };
4411
4412                 remoteproc_cdsp: remoteproc@32300000 {
4413                         compatible = "qcom,sm8550-cdsp-pas";
4414                         reg = <0x0 0x32300000 0x0 0x1400000>;
4415
4416                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4417                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
4418                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
4419                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
4420                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
4421                         interrupt-names = "wdog", "fatal", "ready",
4422                                           "handover", "stop-ack";
4423
4424                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4425                         clock-names = "xo";
4426
4427                         power-domains = <&rpmhpd RPMHPD_CX>,
4428                                         <&rpmhpd RPMHPD_MXC>,
4429                                         <&rpmhpd RPMHPD_NSP>;
4430                         power-domain-names = "cx", "mxc", "nsp";
4431
4432                         interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4433
4434                         memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4435
4436                         qcom,qmp = <&aoss_qmp>;
4437
4438                         qcom,smem-states = <&smp2p_cdsp_out 0>;
4439                         qcom,smem-state-names = "stop";
4440
4441                         status = "disabled";
4442
4443                         glink-edge {
4444                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4445                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4446                                                              IRQ_TYPE_EDGE_RISING>;
4447                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
4448                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4449
4450                                 label = "cdsp";
4451                                 qcom,remote-pid = <5>;
4452
4453                                 fastrpc {
4454                                         compatible = "qcom,fastrpc";
4455                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4456                                         label = "cdsp";
4457                                         #address-cells = <1>;
4458                                         #size-cells = <0>;
4459
4460                                         compute-cb@1 {
4461                                                 compatible = "qcom,fastrpc-compute-cb";
4462                                                 reg = <1>;
4463                                                 iommus = <&apps_smmu 0x1961 0x0>,
4464                                                          <&apps_smmu 0x0c01 0x20>,
4465                                                          <&apps_smmu 0x19c1 0x10>;
4466                                                 dma-coherent;
4467                                         };
4468
4469                                         compute-cb@2 {
4470                                                 compatible = "qcom,fastrpc-compute-cb";
4471                                                 reg = <2>;
4472                                                 iommus = <&apps_smmu 0x1962 0x0>,
4473                                                          <&apps_smmu 0x0c02 0x20>,
4474                                                          <&apps_smmu 0x19c2 0x10>;
4475                                                 dma-coherent;
4476                                         };
4477
4478                                         compute-cb@3 {
4479                                                 compatible = "qcom,fastrpc-compute-cb";
4480                                                 reg = <3>;
4481                                                 iommus = <&apps_smmu 0x1963 0x0>,
4482                                                          <&apps_smmu 0x0c03 0x20>,
4483                                                          <&apps_smmu 0x19c3 0x10>;
4484                                                 dma-coherent;
4485                                         };
4486
4487                                         compute-cb@4 {
4488                                                 compatible = "qcom,fastrpc-compute-cb";
4489                                                 reg = <4>;
4490                                                 iommus = <&apps_smmu 0x1964 0x0>,
4491                                                          <&apps_smmu 0x0c04 0x20>,
4492                                                          <&apps_smmu 0x19c4 0x10>;
4493                                                 dma-coherent;
4494                                         };
4495
4496                                         compute-cb@5 {
4497                                                 compatible = "qcom,fastrpc-compute-cb";
4498                                                 reg = <5>;
4499                                                 iommus = <&apps_smmu 0x1965 0x0>,
4500                                                          <&apps_smmu 0x0c05 0x20>,
4501                                                          <&apps_smmu 0x19c5 0x10>;
4502                                                 dma-coherent;
4503                                         };
4504
4505                                         compute-cb@6 {
4506                                                 compatible = "qcom,fastrpc-compute-cb";
4507                                                 reg = <6>;
4508                                                 iommus = <&apps_smmu 0x1966 0x0>,
4509                                                          <&apps_smmu 0x0c06 0x20>,
4510                                                          <&apps_smmu 0x19c6 0x10>;
4511                                                 dma-coherent;
4512                                         };
4513
4514                                         compute-cb@7 {
4515                                                 compatible = "qcom,fastrpc-compute-cb";
4516                                                 reg = <7>;
4517                                                 iommus = <&apps_smmu 0x1967 0x0>,
4518                                                          <&apps_smmu 0x0c07 0x20>,
4519                                                          <&apps_smmu 0x19c7 0x10>;
4520                                                 dma-coherent;
4521                                         };
4522
4523                                         compute-cb@8 {
4524                                                 compatible = "qcom,fastrpc-compute-cb";
4525                                                 reg = <8>;
4526                                                 iommus = <&apps_smmu 0x1968 0x0>,
4527                                                          <&apps_smmu 0x0c08 0x20>,
4528                                                          <&apps_smmu 0x19c8 0x10>;
4529                                                 dma-coherent;
4530                                         };
4531
4532                                         /* note: secure cb9 in downstream */
4533                                 };
4534                         };
4535                 };
4536         };
4537
4538         thermal-zones {
4539                 aoss0-thermal {
4540                         polling-delay-passive = <0>;
4541                         polling-delay = <0>;
4542                         thermal-sensors = <&tsens0 0>;
4543
4544                         trips {
4545                                 thermal-engine-config {
4546                                         temperature = <125000>;
4547                                         hysteresis = <1000>;
4548                                         type = "passive";
4549                                 };
4550
4551                                 reset-mon-config {
4552                                         temperature = <115000>;
4553                                         hysteresis = <5000>;
4554                                         type = "passive";
4555                                 };
4556                         };
4557                 };
4558
4559                 cpuss0-thermal {
4560                         polling-delay-passive = <0>;
4561                         polling-delay = <0>;
4562                         thermal-sensors = <&tsens0 1>;
4563
4564                         trips {
4565                                 thermal-engine-config {
4566                                         temperature = <125000>;
4567                                         hysteresis = <1000>;
4568                                         type = "passive";
4569                                 };
4570
4571                                 reset-mon-config {
4572                                         temperature = <115000>;
4573                                         hysteresis = <5000>;
4574                                         type = "passive";
4575                                 };
4576                         };
4577                 };
4578
4579                 cpuss1-thermal {
4580                         polling-delay-passive = <0>;
4581                         polling-delay = <0>;
4582                         thermal-sensors = <&tsens0 2>;
4583
4584                         trips {
4585                                 thermal-engine-config {
4586                                         temperature = <125000>;
4587                                         hysteresis = <1000>;
4588                                         type = "passive";
4589                                 };
4590
4591                                 reset-mon-config {
4592                                         temperature = <115000>;
4593                                         hysteresis = <5000>;
4594                                         type = "passive";
4595                                 };
4596                         };
4597                 };
4598
4599                 cpuss2-thermal {
4600                         polling-delay-passive = <0>;
4601                         polling-delay = <0>;
4602                         thermal-sensors = <&tsens0 3>;
4603
4604                         trips {
4605                                 thermal-engine-config {
4606                                         temperature = <125000>;
4607                                         hysteresis = <1000>;
4608                                         type = "passive";
4609                                 };
4610
4611                                 reset-mon-config {
4612                                         temperature = <115000>;
4613                                         hysteresis = <5000>;
4614                                         type = "passive";
4615                                 };
4616                         };
4617                 };
4618
4619                 cpuss3-thermal {
4620                         polling-delay-passive = <0>;
4621                         polling-delay = <0>;
4622                         thermal-sensors = <&tsens0 4>;
4623
4624                         trips {
4625                                 thermal-engine-config {
4626                                         temperature = <125000>;
4627                                         hysteresis = <1000>;
4628                                         type = "passive";
4629                                 };
4630
4631                                 reset-mon-config {
4632                                         temperature = <115000>;
4633                                         hysteresis = <5000>;
4634                                         type = "passive";
4635                                 };
4636                         };
4637                 };
4638
4639                 cpu3-top-thermal {
4640                         polling-delay-passive = <0>;
4641                         polling-delay = <0>;
4642                         thermal-sensors = <&tsens0 5>;
4643
4644                         trips {
4645                                 cpu3_top_alert0: trip-point0 {
4646                                         temperature = <90000>;
4647                                         hysteresis = <2000>;
4648                                         type = "passive";
4649                                 };
4650
4651                                 cpu3_top_alert1: trip-point1 {
4652                                         temperature = <95000>;
4653                                         hysteresis = <2000>;
4654                                         type = "passive";
4655                                 };
4656
4657                                 cpu3_top_crit: cpu-critical {
4658                                         temperature = <110000>;
4659                                         hysteresis = <1000>;
4660                                         type = "critical";
4661                                 };
4662                         };
4663                 };
4664
4665                 cpu3-bottom-thermal {
4666                         polling-delay-passive = <0>;
4667                         polling-delay = <0>;
4668                         thermal-sensors = <&tsens0 6>;
4669
4670                         trips {
4671                                 cpu3_bottom_alert0: trip-point0 {
4672                                         temperature = <90000>;
4673                                         hysteresis = <2000>;
4674                                         type = "passive";
4675                                 };
4676
4677                                 cpu3_bottom_alert1: trip-point1 {
4678                                         temperature = <95000>;
4679                                         hysteresis = <2000>;
4680                                         type = "passive";
4681                                 };
4682
4683                                 cpu3_bottom_crit: cpu-critical {
4684                                         temperature = <110000>;
4685                                         hysteresis = <1000>;
4686                                         type = "critical";
4687                                 };
4688                         };
4689                 };
4690
4691                 cpu4-top-thermal {
4692                         polling-delay-passive = <0>;
4693                         polling-delay = <0>;
4694                         thermal-sensors = <&tsens0 7>;
4695
4696                         trips {
4697                                 cpu4_top_alert0: trip-point0 {
4698                                         temperature = <90000>;
4699                                         hysteresis = <2000>;
4700                                         type = "passive";
4701                                 };
4702
4703                                 cpu4_top_alert1: trip-point1 {
4704                                         temperature = <95000>;
4705                                         hysteresis = <2000>;
4706                                         type = "passive";
4707                                 };
4708
4709                                 cpu4_top_crit: cpu-critical {
4710                                         temperature = <110000>;
4711                                         hysteresis = <1000>;
4712                                         type = "critical";
4713                                 };
4714                         };
4715                 };
4716
4717                 cpu4-bottom-thermal {
4718                         polling-delay-passive = <0>;
4719                         polling-delay = <0>;
4720                         thermal-sensors = <&tsens0 8>;
4721
4722                         trips {
4723                                 cpu4_bottom_alert0: trip-point0 {
4724                                         temperature = <90000>;
4725                                         hysteresis = <2000>;
4726                                         type = "passive";
4727                                 };
4728
4729                                 cpu4_bottom_alert1: trip-point1 {
4730                                         temperature = <95000>;
4731                                         hysteresis = <2000>;
4732                                         type = "passive";
4733                                 };
4734
4735                                 cpu4_bottom_crit: cpu-critical {
4736                                         temperature = <110000>;
4737                                         hysteresis = <1000>;
4738                                         type = "critical";
4739                                 };
4740                         };
4741                 };
4742
4743                 cpu5-top-thermal {
4744                         polling-delay-passive = <0>;
4745                         polling-delay = <0>;
4746                         thermal-sensors = <&tsens0 9>;
4747
4748                         trips {
4749                                 cpu5_top_alert0: trip-point0 {
4750                                         temperature = <90000>;
4751                                         hysteresis = <2000>;
4752                                         type = "passive";
4753                                 };
4754
4755                                 cpu5_top_alert1: trip-point1 {
4756                                         temperature = <95000>;
4757                                         hysteresis = <2000>;
4758                                         type = "passive";
4759                                 };
4760
4761                                 cpu5_top_crit: cpu-critical {
4762                                         temperature = <110000>;
4763                                         hysteresis = <1000>;
4764                                         type = "critical";
4765                                 };
4766                         };
4767                 };
4768
4769                 cpu5-bottom-thermal {
4770                         polling-delay-passive = <0>;
4771                         polling-delay = <0>;
4772                         thermal-sensors = <&tsens0 10>;
4773
4774                         trips {
4775                                 cpu5_bottom_alert0: trip-point0 {
4776                                         temperature = <90000>;
4777                                         hysteresis = <2000>;
4778                                         type = "passive";
4779                                 };
4780
4781                                 cpu5_bottom_alert1: trip-point1 {
4782                                         temperature = <95000>;
4783                                         hysteresis = <2000>;
4784                                         type = "passive";
4785                                 };
4786
4787                                 cpu5_bottom_crit: cpu-critical {
4788                                         temperature = <110000>;
4789                                         hysteresis = <1000>;
4790                                         type = "critical";
4791                                 };
4792                         };
4793                 };
4794
4795                 cpu6-top-thermal {
4796                         polling-delay-passive = <0>;
4797                         polling-delay = <0>;
4798                         thermal-sensors = <&tsens0 11>;
4799
4800                         trips {
4801                                 cpu6_top_alert0: trip-point0 {
4802                                         temperature = <90000>;
4803                                         hysteresis = <2000>;
4804                                         type = "passive";
4805                                 };
4806
4807                                 cpu6_top_alert1: trip-point1 {
4808                                         temperature = <95000>;
4809                                         hysteresis = <2000>;
4810                                         type = "passive";
4811                                 };
4812
4813                                 cpu6_top_crit: cpu-critical {
4814                                         temperature = <110000>;
4815                                         hysteresis = <1000>;
4816                                         type = "critical";
4817                                 };
4818                         };
4819                 };
4820
4821                 cpu6-bottom-thermal {
4822                         polling-delay-passive = <0>;
4823                         polling-delay = <0>;
4824                         thermal-sensors = <&tsens0 12>;
4825
4826                         trips {
4827                                 cpu6_bottom_alert0: trip-point0 {
4828                                         temperature = <90000>;
4829                                         hysteresis = <2000>;
4830                                         type = "passive";
4831                                 };
4832
4833                                 cpu6_bottom_alert1: trip-point1 {
4834                                         temperature = <95000>;
4835                                         hysteresis = <2000>;
4836                                         type = "passive";
4837                                 };
4838
4839                                 cpu6_bottom_crit: cpu-critical {
4840                                         temperature = <110000>;
4841                                         hysteresis = <1000>;
4842                                         type = "critical";
4843                                 };
4844                         };
4845                 };
4846
4847                 cpu7-top-thermal {
4848                         polling-delay-passive = <0>;
4849                         polling-delay = <0>;
4850                         thermal-sensors = <&tsens0 13>;
4851
4852                         trips {
4853                                 cpu7_top_alert0: trip-point0 {
4854                                         temperature = <90000>;
4855                                         hysteresis = <2000>;
4856                                         type = "passive";
4857                                 };
4858
4859                                 cpu7_top_alert1: trip-point1 {
4860                                         temperature = <95000>;
4861                                         hysteresis = <2000>;
4862                                         type = "passive";
4863                                 };
4864
4865                                 cpu7_top_crit: cpu-critical {
4866                                         temperature = <110000>;
4867                                         hysteresis = <1000>;
4868                                         type = "critical";
4869                                 };
4870                         };
4871                 };
4872
4873                 cpu7-middle-thermal {
4874                         polling-delay-passive = <0>;
4875                         polling-delay = <0>;
4876                         thermal-sensors = <&tsens0 14>;
4877
4878                         trips {
4879                                 cpu7_middle_alert0: trip-point0 {
4880                                         temperature = <90000>;
4881                                         hysteresis = <2000>;
4882                                         type = "passive";
4883                                 };
4884
4885                                 cpu7_middle_alert1: trip-point1 {
4886                                         temperature = <95000>;
4887                                         hysteresis = <2000>;
4888                                         type = "passive";
4889                                 };
4890
4891                                 cpu7_middle_crit: cpu-critical {
4892                                         temperature = <110000>;
4893                                         hysteresis = <1000>;
4894                                         type = "critical";
4895                                 };
4896                         };
4897                 };
4898
4899                 cpu7-bottom-thermal {
4900                         polling-delay-passive = <0>;
4901                         polling-delay = <0>;
4902                         thermal-sensors = <&tsens0 15>;
4903
4904                         trips {
4905                                 cpu7_bottom_alert0: trip-point0 {
4906                                         temperature = <90000>;
4907                                         hysteresis = <2000>;
4908                                         type = "passive";
4909                                 };
4910
4911                                 cpu7_bottom_alert1: trip-point1 {
4912                                         temperature = <95000>;
4913                                         hysteresis = <2000>;
4914                                         type = "passive";
4915                                 };
4916
4917                                 cpu7_bottom_crit: cpu-critical {
4918                                         temperature = <110000>;
4919                                         hysteresis = <1000>;
4920                                         type = "critical";
4921                                 };
4922                         };
4923                 };
4924
4925                 aoss1-thermal {
4926                         polling-delay-passive = <0>;
4927                         polling-delay = <0>;
4928                         thermal-sensors = <&tsens1 0>;
4929
4930                         trips {
4931                                 thermal-engine-config {
4932                                         temperature = <125000>;
4933                                         hysteresis = <1000>;
4934                                         type = "passive";
4935                                 };
4936
4937                                 reset-mon-config {
4938                                         temperature = <115000>;
4939                                         hysteresis = <5000>;
4940                                         type = "passive";
4941                                 };
4942                         };
4943                 };
4944
4945                 cpu0-thermal {
4946                         polling-delay-passive = <0>;
4947                         polling-delay = <0>;
4948                         thermal-sensors = <&tsens1 1>;
4949
4950                         trips {
4951                                 cpu0_alert0: trip-point0 {
4952                                         temperature = <90000>;
4953                                         hysteresis = <2000>;
4954                                         type = "passive";
4955                                 };
4956
4957                                 cpu0_alert1: trip-point1 {
4958                                         temperature = <95000>;
4959                                         hysteresis = <2000>;
4960                                         type = "passive";
4961                                 };
4962
4963                                 cpu0_crit: cpu-critical {
4964                                         temperature = <110000>;
4965                                         hysteresis = <1000>;
4966                                         type = "critical";
4967                                 };
4968                         };
4969                 };
4970
4971                 cpu1-thermal {
4972                         polling-delay-passive = <0>;
4973                         polling-delay = <0>;
4974                         thermal-sensors = <&tsens1 2>;
4975
4976                         trips {
4977                                 cpu1_alert0: trip-point0 {
4978                                         temperature = <90000>;
4979                                         hysteresis = <2000>;
4980                                         type = "passive";
4981                                 };
4982
4983                                 cpu1_alert1: trip-point1 {
4984                                         temperature = <95000>;
4985                                         hysteresis = <2000>;
4986                                         type = "passive";
4987                                 };
4988
4989                                 cpu1_crit: cpu-critical {
4990                                         temperature = <110000>;
4991                                         hysteresis = <1000>;
4992                                         type = "critical";
4993                                 };
4994                         };
4995                 };
4996
4997                 cpu2-thermal {
4998                         polling-delay-passive = <0>;
4999                         polling-delay = <0>;
5000                         thermal-sensors = <&tsens1 3>;
5001
5002                         trips {
5003                                 cpu2_alert0: trip-point0 {
5004                                         temperature = <90000>;
5005                                         hysteresis = <2000>;
5006                                         type = "passive";
5007                                 };
5008
5009                                 cpu2_alert1: trip-point1 {
5010                                         temperature = <95000>;
5011                                         hysteresis = <2000>;
5012                                         type = "passive";
5013                                 };
5014
5015                                 cpu2_crit: cpu-critical {
5016                                         temperature = <110000>;
5017                                         hysteresis = <1000>;
5018                                         type = "critical";
5019                                 };
5020                         };
5021                 };
5022
5023                 cdsp0-thermal {
5024                         polling-delay-passive = <10>;
5025                         polling-delay = <0>;
5026                         thermal-sensors = <&tsens2 4>;
5027
5028                         trips {
5029                                 thermal-engine-config {
5030                                         temperature = <125000>;
5031                                         hysteresis = <1000>;
5032                                         type = "passive";
5033                                 };
5034
5035                                 thermal-hal-config {
5036                                         temperature = <125000>;
5037                                         hysteresis = <1000>;
5038                                         type = "passive";
5039                                 };
5040
5041                                 reset-mon-config {
5042                                         temperature = <115000>;
5043                                         hysteresis = <5000>;
5044                                         type = "passive";
5045                                 };
5046
5047                                 cdsp0_junction_config: junction-config {
5048                                         temperature = <95000>;
5049                                         hysteresis = <5000>;
5050                                         type = "passive";
5051                                 };
5052                         };
5053                 };
5054
5055                 cdsp1-thermal {
5056                         polling-delay-passive = <10>;
5057                         polling-delay = <0>;
5058                         thermal-sensors = <&tsens2 5>;
5059
5060                         trips {
5061                                 thermal-engine-config {
5062                                         temperature = <125000>;
5063                                         hysteresis = <1000>;
5064                                         type = "passive";
5065                                 };
5066
5067                                 thermal-hal-config {
5068                                         temperature = <125000>;
5069                                         hysteresis = <1000>;
5070                                         type = "passive";
5071                                 };
5072
5073                                 reset-mon-config {
5074                                         temperature = <115000>;
5075                                         hysteresis = <5000>;
5076                                         type = "passive";
5077                                 };
5078
5079                                 cdsp1_junction_config: junction-config {
5080                                         temperature = <95000>;
5081                                         hysteresis = <5000>;
5082                                         type = "passive";
5083                                 };
5084                         };
5085                 };
5086
5087                 cdsp2-thermal {
5088                         polling-delay-passive = <10>;
5089                         polling-delay = <0>;
5090                         thermal-sensors = <&tsens2 6>;
5091
5092                         trips {
5093                                 thermal-engine-config {
5094                                         temperature = <125000>;
5095                                         hysteresis = <1000>;
5096                                         type = "passive";
5097                                 };
5098
5099                                 thermal-hal-config {
5100                                         temperature = <125000>;
5101                                         hysteresis = <1000>;
5102                                         type = "passive";
5103                                 };
5104
5105                                 reset-mon-config {
5106                                         temperature = <115000>;
5107                                         hysteresis = <5000>;
5108                                         type = "passive";
5109                                 };
5110
5111                                 cdsp2_junction_config: junction-config {
5112                                         temperature = <95000>;
5113                                         hysteresis = <5000>;
5114                                         type = "passive";
5115                                 };
5116                         };
5117                 };
5118
5119                 cdsp3-thermal {
5120                         polling-delay-passive = <10>;
5121                         polling-delay = <0>;
5122                         thermal-sensors = <&tsens2 7>;
5123
5124                         trips {
5125                                 thermal-engine-config {
5126                                         temperature = <125000>;
5127                                         hysteresis = <1000>;
5128                                         type = "passive";
5129                                 };
5130
5131                                 thermal-hal-config {
5132                                         temperature = <125000>;
5133                                         hysteresis = <1000>;
5134                                         type = "passive";
5135                                 };
5136
5137                                 reset-mon-config {
5138                                         temperature = <115000>;
5139                                         hysteresis = <5000>;
5140                                         type = "passive";
5141                                 };
5142
5143                                 cdsp3_junction_config: junction-config {
5144                                         temperature = <95000>;
5145                                         hysteresis = <5000>;
5146                                         type = "passive";
5147                                 };
5148                         };
5149                 };
5150
5151                 video-thermal {
5152                         polling-delay-passive = <0>;
5153                         polling-delay = <0>;
5154                         thermal-sensors = <&tsens1 8>;
5155
5156                         trips {
5157                                 thermal-engine-config {
5158                                         temperature = <125000>;
5159                                         hysteresis = <1000>;
5160                                         type = "passive";
5161                                 };
5162
5163                                 reset-mon-config {
5164                                         temperature = <115000>;
5165                                         hysteresis = <5000>;
5166                                         type = "passive";
5167                                 };
5168                         };
5169                 };
5170
5171                 mem-thermal {
5172                         polling-delay-passive = <10>;
5173                         polling-delay = <0>;
5174                         thermal-sensors = <&tsens1 9>;
5175
5176                         trips {
5177                                 thermal-engine-config {
5178                                         temperature = <125000>;
5179                                         hysteresis = <1000>;
5180                                         type = "passive";
5181                                 };
5182
5183                                 ddr_config0: ddr0-config {
5184                                         temperature = <90000>;
5185                                         hysteresis = <5000>;
5186                                         type = "passive";
5187                                 };
5188
5189                                 reset-mon-config {
5190                                         temperature = <115000>;
5191                                         hysteresis = <5000>;
5192                                         type = "passive";
5193                                 };
5194                         };
5195                 };
5196
5197                 modem0-thermal {
5198                         polling-delay-passive = <0>;
5199                         polling-delay = <0>;
5200                         thermal-sensors = <&tsens1 10>;
5201
5202                         trips {
5203                                 thermal-engine-config {
5204                                         temperature = <125000>;
5205                                         hysteresis = <1000>;
5206                                         type = "passive";
5207                                 };
5208
5209                                 mdmss0_config0: mdmss0-config0 {
5210                                         temperature = <102000>;
5211                                         hysteresis = <3000>;
5212                                         type = "passive";
5213                                 };
5214
5215                                 mdmss0_config1: mdmss0-config1 {
5216                                         temperature = <105000>;
5217                                         hysteresis = <3000>;
5218                                         type = "passive";
5219                                 };
5220
5221                                 reset-mon-config {
5222                                         temperature = <115000>;
5223                                         hysteresis = <5000>;
5224                                         type = "passive";
5225                                 };
5226                         };
5227                 };
5228
5229                 modem1-thermal {
5230                         polling-delay-passive = <0>;
5231                         polling-delay = <0>;
5232                         thermal-sensors = <&tsens1 11>;
5233
5234                         trips {
5235                                 thermal-engine-config {
5236                                         temperature = <125000>;
5237                                         hysteresis = <1000>;
5238                                         type = "passive";
5239                                 };
5240
5241                                 mdmss1_config0: mdmss1-config0 {
5242                                         temperature = <102000>;
5243                                         hysteresis = <3000>;
5244                                         type = "passive";
5245                                 };
5246
5247                                 mdmss1_config1: mdmss1-config1 {
5248                                         temperature = <105000>;
5249                                         hysteresis = <3000>;
5250                                         type = "passive";
5251                                 };
5252
5253                                 reset-mon-config {
5254                                         temperature = <115000>;
5255                                         hysteresis = <5000>;
5256                                         type = "passive";
5257                                 };
5258                         };
5259                 };
5260
5261                 modem2-thermal {
5262                         polling-delay-passive = <0>;
5263                         polling-delay = <0>;
5264                         thermal-sensors = <&tsens1 12>;
5265
5266                         trips {
5267                                 thermal-engine-config {
5268                                         temperature = <125000>;
5269                                         hysteresis = <1000>;
5270                                         type = "passive";
5271                                 };
5272
5273                                 mdmss2_config0: mdmss2-config0 {
5274                                         temperature = <102000>;
5275                                         hysteresis = <3000>;
5276                                         type = "passive";
5277                                 };
5278
5279                                 mdmss2_config1: mdmss2-config1 {
5280                                         temperature = <105000>;
5281                                         hysteresis = <3000>;
5282                                         type = "passive";
5283                                 };
5284
5285                                 reset-mon-config {
5286                                         temperature = <115000>;
5287                                         hysteresis = <5000>;
5288                                         type = "passive";
5289                                 };
5290                         };
5291                 };
5292
5293                 modem3-thermal {
5294                         polling-delay-passive = <0>;
5295                         polling-delay = <0>;
5296                         thermal-sensors = <&tsens1 13>;
5297
5298                         trips {
5299                                 thermal-engine-config {
5300                                         temperature = <125000>;
5301                                         hysteresis = <1000>;
5302                                         type = "passive";
5303                                 };
5304
5305                                 mdmss3_config0: mdmss3-config0 {
5306                                         temperature = <102000>;
5307                                         hysteresis = <3000>;
5308                                         type = "passive";
5309                                 };
5310
5311                                 mdmss3_config1: mdmss3-config1 {
5312                                         temperature = <105000>;
5313                                         hysteresis = <3000>;
5314                                         type = "passive";
5315                                 };
5316
5317                                 reset-mon-config {
5318                                         temperature = <115000>;
5319                                         hysteresis = <5000>;
5320                                         type = "passive";
5321                                 };
5322                         };
5323                 };
5324
5325                 camera0-thermal {
5326                         polling-delay-passive = <0>;
5327                         polling-delay = <0>;
5328                         thermal-sensors = <&tsens1 14>;
5329
5330                         trips {
5331                                 thermal-engine-config {
5332                                         temperature = <125000>;
5333                                         hysteresis = <1000>;
5334                                         type = "passive";
5335                                 };
5336
5337                                 reset-mon-config {
5338                                         temperature = <115000>;
5339                                         hysteresis = <5000>;
5340                                         type = "passive";
5341                                 };
5342                         };
5343                 };
5344
5345                 camera1-thermal {
5346                         polling-delay-passive = <0>;
5347                         polling-delay = <0>;
5348                         thermal-sensors = <&tsens1 15>;
5349
5350                         trips {
5351                                 thermal-engine-config {
5352                                         temperature = <125000>;
5353                                         hysteresis = <1000>;
5354                                         type = "passive";
5355                                 };
5356
5357                                 reset-mon-config {
5358                                         temperature = <115000>;
5359                                         hysteresis = <5000>;
5360                                         type = "passive";
5361                                 };
5362                         };
5363                 };
5364
5365                 aoss2-thermal {
5366                         polling-delay-passive = <0>;
5367                         polling-delay = <0>;
5368                         thermal-sensors = <&tsens2 0>;
5369
5370                         trips {
5371                                 thermal-engine-config {
5372                                         temperature = <125000>;
5373                                         hysteresis = <1000>;
5374                                         type = "passive";
5375                                 };
5376
5377                                 reset-mon-config {
5378                                         temperature = <115000>;
5379                                         hysteresis = <5000>;
5380                                         type = "passive";
5381                                 };
5382                         };
5383                 };
5384
5385                 gpuss-0-thermal {
5386                         polling-delay-passive = <10>;
5387                         polling-delay = <0>;
5388                         thermal-sensors = <&tsens2 1>;
5389
5390                         cooling-maps {
5391                                 map0 {
5392                                         trip = <&gpu0_junction_config>;
5393                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5394                                 };
5395                         };
5396
5397                         trips {
5398                                 thermal-engine-config {
5399                                         temperature = <125000>;
5400                                         hysteresis = <1000>;
5401                                         type = "passive";
5402                                 };
5403
5404                                 thermal-hal-config {
5405                                         temperature = <125000>;
5406                                         hysteresis = <1000>;
5407                                         type = "passive";
5408                                 };
5409
5410                                 reset-mon-config {
5411                                         temperature = <115000>;
5412                                         hysteresis = <5000>;
5413                                         type = "passive";
5414                                 };
5415
5416                                 gpu0_junction_config: junction-config {
5417                                         temperature = <95000>;
5418                                         hysteresis = <5000>;
5419                                         type = "passive";
5420                                 };
5421                         };
5422                 };
5423
5424                 gpuss-1-thermal {
5425                         polling-delay-passive = <10>;
5426                         polling-delay = <0>;
5427                         thermal-sensors = <&tsens2 2>;
5428
5429                         cooling-maps {
5430                                 map0 {
5431                                         trip = <&gpu1_junction_config>;
5432                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5433                                 };
5434                         };
5435
5436                         trips {
5437                                 thermal-engine-config {
5438                                         temperature = <125000>;
5439                                         hysteresis = <1000>;
5440                                         type = "passive";
5441                                 };
5442
5443                                 thermal-hal-config {
5444                                         temperature = <125000>;
5445                                         hysteresis = <1000>;
5446                                         type = "passive";
5447                                 };
5448
5449                                 reset-mon-config {
5450                                         temperature = <115000>;
5451                                         hysteresis = <5000>;
5452                                         type = "passive";
5453                                 };
5454
5455                                 gpu1_junction_config: junction-config {
5456                                         temperature = <95000>;
5457                                         hysteresis = <5000>;
5458                                         type = "passive";
5459                                 };
5460                         };
5461                 };
5462
5463                 gpuss-2-thermal {
5464                         polling-delay-passive = <10>;
5465                         polling-delay = <0>;
5466                         thermal-sensors = <&tsens2 3>;
5467
5468                         cooling-maps {
5469                                 map0 {
5470                                         trip = <&gpu2_junction_config>;
5471                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5472                                 };
5473                         };
5474
5475                         trips {
5476                                 thermal-engine-config {
5477                                         temperature = <125000>;
5478                                         hysteresis = <1000>;
5479                                         type = "passive";
5480                                 };
5481
5482                                 thermal-hal-config {
5483                                         temperature = <125000>;
5484                                         hysteresis = <1000>;
5485                                         type = "passive";
5486                                 };
5487
5488                                 reset-mon-config {
5489                                         temperature = <115000>;
5490                                         hysteresis = <5000>;
5491                                         type = "passive";
5492                                 };
5493
5494                                 gpu2_junction_config: junction-config {
5495                                         temperature = <95000>;
5496                                         hysteresis = <5000>;
5497                                         type = "passive";
5498                                 };
5499                         };
5500                 };
5501
5502                 gpuss-3-thermal {
5503                         polling-delay-passive = <10>;
5504                         polling-delay = <0>;
5505                         thermal-sensors = <&tsens2 4>;
5506
5507                         cooling-maps {
5508                                 map0 {
5509                                         trip = <&gpu3_junction_config>;
5510                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5511                                 };
5512                         };
5513
5514                         trips {
5515                                 thermal-engine-config {
5516                                         temperature = <125000>;
5517                                         hysteresis = <1000>;
5518                                         type = "passive";
5519                                 };
5520
5521                                 thermal-hal-config {
5522                                         temperature = <125000>;
5523                                         hysteresis = <1000>;
5524                                         type = "passive";
5525                                 };
5526
5527                                 reset-mon-config {
5528                                         temperature = <115000>;
5529                                         hysteresis = <5000>;
5530                                         type = "passive";
5531                                 };
5532
5533                                 gpu3_junction_config: junction-config {
5534                                         temperature = <95000>;
5535                                         hysteresis = <5000>;
5536                                         type = "passive";
5537                                 };
5538                         };
5539                 };
5540
5541                 gpuss-4-thermal {
5542                         polling-delay-passive = <10>;
5543                         polling-delay = <0>;
5544                         thermal-sensors = <&tsens2 5>;
5545
5546                         cooling-maps {
5547                                 map0 {
5548                                         trip = <&gpu4_junction_config>;
5549                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5550                                 };
5551                         };
5552
5553                         trips {
5554                                 thermal-engine-config {
5555                                         temperature = <125000>;
5556                                         hysteresis = <1000>;
5557                                         type = "passive";
5558                                 };
5559
5560                                 thermal-hal-config {
5561                                         temperature = <125000>;
5562                                         hysteresis = <1000>;
5563                                         type = "passive";
5564                                 };
5565
5566                                 reset-mon-config {
5567                                         temperature = <115000>;
5568                                         hysteresis = <5000>;
5569                                         type = "passive";
5570                                 };
5571
5572                                 gpu4_junction_config: junction-config {
5573                                         temperature = <95000>;
5574                                         hysteresis = <5000>;
5575                                         type = "passive";
5576                                 };
5577                         };
5578                 };
5579
5580                 gpuss-5-thermal {
5581                         polling-delay-passive = <10>;
5582                         polling-delay = <0>;
5583                         thermal-sensors = <&tsens2 6>;
5584
5585                         cooling-maps {
5586                                 map0 {
5587                                         trip = <&gpu5_junction_config>;
5588                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5589                                 };
5590                         };
5591
5592                         trips {
5593                                 thermal-engine-config {
5594                                         temperature = <125000>;
5595                                         hysteresis = <1000>;
5596                                         type = "passive";
5597                                 };
5598
5599                                 thermal-hal-config {
5600                                         temperature = <125000>;
5601                                         hysteresis = <1000>;
5602                                         type = "passive";
5603                                 };
5604
5605                                 reset-mon-config {
5606                                         temperature = <115000>;
5607                                         hysteresis = <5000>;
5608                                         type = "passive";
5609                                 };
5610
5611                                 gpu5_junction_config: junction-config {
5612                                         temperature = <95000>;
5613                                         hysteresis = <5000>;
5614                                         type = "passive";
5615                                 };
5616                         };
5617                 };
5618
5619                 gpuss-6-thermal {
5620                         polling-delay-passive = <10>;
5621                         polling-delay = <0>;
5622                         thermal-sensors = <&tsens2 7>;
5623
5624                         cooling-maps {
5625                                 map0 {
5626                                         trip = <&gpu6_junction_config>;
5627                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5628                                 };
5629                         };
5630
5631                         trips {
5632                                 thermal-engine-config {
5633                                         temperature = <125000>;
5634                                         hysteresis = <1000>;
5635                                         type = "passive";
5636                                 };
5637
5638                                 thermal-hal-config {
5639                                         temperature = <125000>;
5640                                         hysteresis = <1000>;
5641                                         type = "passive";
5642                                 };
5643
5644                                 reset-mon-config {
5645                                         temperature = <115000>;
5646                                         hysteresis = <5000>;
5647                                         type = "passive";
5648                                 };
5649
5650                                 gpu6_junction_config: junction-config {
5651                                         temperature = <95000>;
5652                                         hysteresis = <5000>;
5653                                         type = "passive";
5654                                 };
5655                         };
5656                 };
5657
5658                 gpuss-7-thermal {
5659                         polling-delay-passive = <10>;
5660                         polling-delay = <0>;
5661                         thermal-sensors = <&tsens2 8>;
5662
5663                         cooling-maps {
5664                                 map0 {
5665                                         trip = <&gpu7_junction_config>;
5666                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5667                                 };
5668                         };
5669
5670                         trips {
5671                                 thermal-engine-config {
5672                                         temperature = <125000>;
5673                                         hysteresis = <1000>;
5674                                         type = "passive";
5675                                 };
5676
5677                                 thermal-hal-config {
5678                                         temperature = <125000>;
5679                                         hysteresis = <1000>;
5680                                         type = "passive";
5681                                 };
5682
5683                                 reset-mon-config {
5684                                         temperature = <115000>;
5685                                         hysteresis = <5000>;
5686                                         type = "passive";
5687                                 };
5688
5689                                 gpu7_junction_config: junction-config {
5690                                         temperature = <95000>;
5691                                         hysteresis = <5000>;
5692                                         type = "passive";
5693                                 };
5694                         };
5695                 };
5696         };
5697
5698         timer {
5699                 compatible = "arm,armv8-timer";
5700                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5701                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5702                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5703                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5704         };
5705 };