1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2021, Linaro Limited
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h>
21 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
23 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h>
29 interrupt-parent = <&intc>;
38 compatible = "fixed-clock";
40 clock-frequency = <76800000>;
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
46 clock-frequency = <32000>;
56 compatible = "qcom,kryo780";
58 enable-method = "psci";
59 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_PD0>;
61 power-domain-names = "psci";
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
69 next-level-cache = <&L3_0>;
80 compatible = "qcom,kryo780";
82 enable-method = "psci";
83 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_PD1>;
85 power-domain-names = "psci";
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
93 next-level-cache = <&L3_0>;
99 compatible = "qcom,kryo780";
101 enable-method = "psci";
102 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_PD2>;
104 power-domain-names = "psci";
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw 0>;
109 compatible = "cache";
112 next-level-cache = <&L3_0>;
118 compatible = "qcom,kryo780";
120 enable-method = "psci";
121 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_PD3>;
123 power-domain-names = "psci";
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw 0>;
128 compatible = "cache";
131 next-level-cache = <&L3_0>;
137 compatible = "qcom,kryo780";
139 enable-method = "psci";
140 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_PD4>;
142 power-domain-names = "psci";
143 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw 1>;
147 compatible = "cache";
150 next-level-cache = <&L3_0>;
156 compatible = "qcom,kryo780";
158 enable-method = "psci";
159 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_PD5>;
161 power-domain-names = "psci";
162 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw 1>;
166 compatible = "cache";
169 next-level-cache = <&L3_0>;
175 compatible = "qcom,kryo780";
177 enable-method = "psci";
178 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_PD6>;
180 power-domain-names = "psci";
181 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw 1>;
185 compatible = "cache";
188 next-level-cache = <&L3_0>;
194 compatible = "qcom,kryo780";
196 enable-method = "psci";
197 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_PD7>;
199 power-domain-names = "psci";
200 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw 2>;
204 compatible = "cache";
207 next-level-cache = <&L3_0>;
248 entry-method = "psci";
250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = "arm,idle-state";
252 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspend-param = <0x40000004>;
254 entry-latency-us = <800>;
255 exit-latency-us = <750>;
256 min-residency-us = <4090>;
260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = "arm,idle-state";
262 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspend-param = <0x40000004>;
264 entry-latency-us = <600>;
265 exit-latency-us = <1550>;
266 min-residency-us = <4791>;
272 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = "domain-idle-state";
274 arm,psci-suspend-param = <0x41000044>;
275 entry-latency-us = <1050>;
276 exit-latency-us = <2500>;
277 min-residency-us = <5309>;
280 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = "domain-idle-state";
282 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency-us = <2700>;
284 exit-latency-us = <3500>;
285 min-residency-us = <13959>;
292 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tcsr 0x13000>;
294 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
299 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_voter>;
305 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_voter>;
312 device_type = "memory";
313 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0>;
318 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
323 compatible = "arm,psci-1.0";
326 CPU_PD0: power-domain-cpu0 {
327 #power-domain-cells = <0>;
328 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
332 CPU_PD1: power-domain-cpu1 {
333 #power-domain-cells = <0>;
334 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
338 CPU_PD2: power-domain-cpu2 {
339 #power-domain-cells = <0>;
340 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
344 CPU_PD3: power-domain-cpu3 {
345 #power-domain-cells = <0>;
346 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
350 CPU_PD4: power-domain-cpu4 {
351 #power-domain-cells = <0>;
352 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = <&BIG_CPU_SLEEP_0>;
356 CPU_PD5: power-domain-cpu5 {
357 #power-domain-cells = <0>;
358 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = <&BIG_CPU_SLEEP_0>;
362 CPU_PD6: power-domain-cpu6 {
363 #power-domain-cells = <0>;
364 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = <&BIG_CPU_SLEEP_0>;
368 CPU_PD7: power-domain-cpu7 {
369 #power-domain-cells = <0>;
370 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = <&BIG_CPU_SLEEP_0>;
374 CLUSTER_PD: power-domain-cpu-cluster0 {
375 #power-domain-cells = <0>;
376 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
380 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points-v2";
384 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmhpd_opp_min_svs>;
389 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmhpd_opp_low_svs>;
394 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmhpd_opp_svs>;
399 reserved_memory: reserved-memory {
400 #address-cells = <2>;
404 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 0x0 0x600000>;
409 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 0x0 0x40000>;
414 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 0x0 0x180000>;
419 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 0x0 0x40000>;
424 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 0x0 0x60000>;
429 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 0x0 0x20000>;
435 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 0x0 0x20000>;
440 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 0x0 0x40000>;
445 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 0x0 0x4000>;
450 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 0x0 0x10000>;
455 /* secdata region can be reused by apps */
456 smem: memory@80900000 {
457 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 3>;
463 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 0x0 0x100000>;
468 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 0x0 0x4600000>;
473 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 0x0 0x700000>;
478 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 0x0 0x2100000>;
483 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 0x0 0x1900000>;
488 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 0x0 0x2000000>;
493 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 0x0 0x10000>;
498 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 0x0 0xa000>;
503 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 0x0 0x2000>;
508 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 0x0 0x180000>;
513 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 0x0 0x60000>;
519 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 0x0 0x20000>;
525 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 0x0 0x13200000>;
530 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 0x0 0x700000>;
535 camera_mem: memory@9f500000 {
536 reg = <0x0 0x9f500000 0x0 0x800000>;
540 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 0x0 0x280000>;
545 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
549 xbl_sc_mem2: memory@a6e00000 {
550 reg = <0x0 0xa6e00000 0x0 0x40000>;
554 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 0x0 0x100000>;
559 /* uefi region can be reused by APPS */
561 /* Linux kernel image is loaded at 0xa0000000 */
563 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 0x0 0x5000000>;
568 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 0x0 0x20000000>;
573 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 0x0 0x600000>;
578 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 0x0 0x400000>;
583 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 0x0 0x100000>;
588 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
593 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 0x0 0x9000>;
598 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 0x0 0x4000>;
603 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 0x0 0x100000>;
608 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 0x0 0x100000>;
613 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 0x0 0x1200000>;
618 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 0x0 0x500000>;
623 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 0x0 0x3900000>;
628 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 0x0 0x3b00000>;
635 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 IPCC_MPROC_SIGNAL_SMP2P
639 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIGNAL_SMP2P>;
643 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>;
646 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells = <1>;
651 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "slave-kernel";
653 interrupt-controller;
654 #interrupt-cells = <2>;
659 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 IPCC_MPROC_SIGNAL_SMP2P
663 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIGNAL_SMP2P>;
667 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>;
670 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells = <1>;
675 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "slave-kernel";
677 interrupt-controller;
678 #interrupt-cells = <2>;
683 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 IPCC_MPROC_SIGNAL_SMP2P
687 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIGNAL_SMP2P>;
691 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>;
694 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells = <1>;
699 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "slave-kernel";
701 interrupt-controller;
702 #interrupt-cells = <2>;
705 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells = <1>;
710 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa";
712 interrupt-controller;
713 #interrupt-cells = <2>;
718 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 IPCC_MPROC_SIGNAL_SMP2P
722 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIGNAL_SMP2P>;
726 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>;
729 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells = <1>;
734 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "slave-kernel";
736 interrupt-controller;
737 #interrupt-cells = <2>;
742 #address-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus";
748 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 0x0 0x1f4200>;
753 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH_CXO_CLK>,
762 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
763 clock-names = "bi_tcxo",
767 "pcie_1_phy_aux_clk",
768 "ufs_phy_rx_symbol_0_clk",
769 "ufs_phy_rx_symbol_1_clk",
770 "ufs_phy_tx_symbol_0_clk",
771 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
774 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
777 reg = <0 0x00800000 0 0x60000>;
778 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
791 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0x496 0x0>;
796 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>;
809 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x00880000 0x0 0x4000>;
812 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names = "default";
814 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells = <1>;
818 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "tx", "rx";
829 compatible = "qcom,geni-spi";
830 reg = <0x0 0x00880000 0x0 0x4000>;
832 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names = "default";
835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "tx", "rx";
842 #address-cells = <1>;
848 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x00884000 0x0 0x4000>;
851 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names = "default";
853 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells = <1>;
857 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "tx", "rx";
868 compatible = "qcom,geni-spi";
869 reg = <0x0 0x00884000 0x0 0x4000>;
871 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names = "default";
874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "tx", "rx";
881 #address-cells = <1>;
887 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x00888000 0x0 0x4000>;
890 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names = "default";
892 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells = <1>;
896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "tx", "rx";
907 compatible = "qcom,geni-spi";
908 reg = <0x0 0x00888000 0x0 0x4000>;
910 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "tx", "rx";
920 #address-cells = <1>;
926 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0088c000 0x0 0x4000>;
929 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names = "default";
931 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells = <1>;
935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "tx", "rx";
946 compatible = "qcom,geni-spi";
947 reg = <0 0x0088c000 0 0x4000>;
949 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names = "default";
952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "tx", "rx";
959 #address-cells = <1>;
965 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x00890000 0x0 0x4000>;
968 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names = "default";
970 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells = <1>;
974 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "tx", "rx";
985 compatible = "qcom,geni-spi";
986 reg = <0 0x00890000 0 0x4000>;
988 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names = "default";
991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "tx", "rx";
998 #address-cells = <1>;
1000 status = "disabled";
1004 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x00894000 0x0 0x4000>;
1007 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names = "default";
1009 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cells = <1>;
1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = "tx", "rx";
1020 status = "disabled";
1023 uart20: serial@894000 {
1024 compatible = "qcom,geni-uart";
1025 reg = <0 0x00894000 0 0x4000>;
1027 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_uart20_default>;
1030 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1032 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1033 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1034 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1035 interconnect-names = "qup-core",
1037 status = "disabled";
1041 compatible = "qcom,geni-spi";
1042 reg = <0 0x00894000 0 0x4000>;
1044 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = "tx", "rx";
1054 #address-cells = <1>;
1056 status = "disabled";
1060 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x00898000 0x0 0x4000>;
1063 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names = "default";
1065 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cells = <1>;
1069 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = "tx", "rx";
1076 status = "disabled";
1080 compatible = "qcom,geni-spi";
1081 reg = <0 0x00898000 0 0x4000>;
1083 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names = "default";
1086 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = "tx", "rx";
1093 #address-cells = <1>;
1095 status = "disabled";
1099 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1102 reg = <0 0x00900000 0 0x60000>;
1103 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>;
1116 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled";
1121 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = "qup-core";
1130 #address-cells = <2>;
1133 status = "disabled";
1136 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x00980000 0x0 0x4000>;
1139 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cells = <1>;
1145 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = "tx", "rx";
1152 status = "disabled";
1156 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x00980000 0x0 0x4000>;
1159 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains = <&rpmhpd RPMHPD_CX>;
1164 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = "tx", "rx";
1172 #address-cells = <1>;
1174 status = "disabled";
1178 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x00984000 0x0 0x4000>;
1181 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names = "default";
1183 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cells = <1>;
1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = "tx", "rx";
1194 status = "disabled";
1198 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x00984000 0x0 0x4000>;
1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names = "default";
1204 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = "tx", "rx";
1212 #address-cells = <1>;
1214 status = "disabled";
1218 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x00988000 0x0 0x4000>;
1221 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cells = <1>;
1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = "tx", "rx";
1234 status = "disabled";
1238 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x00988000 0x0 0x4000>;
1241 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = "tx", "rx";
1252 #address-cells = <1>;
1254 status = "disabled";
1259 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x0098c000 0x0 0x4000>;
1262 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names = "default";
1264 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cells = <1>;
1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = "tx", "rx";
1275 status = "disabled";
1279 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x0098c000 0x0 0x4000>;
1282 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names = "default";
1285 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = "tx", "rx";
1293 #address-cells = <1>;
1295 status = "disabled";
1299 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x00990000 0x0 0x4000>;
1302 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cells = <1>;
1308 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = "tx", "rx";
1315 status = "disabled";
1319 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x00990000 0x0 0x4000>;
1322 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names = "default";
1325 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains = <&rpmhpd RPMHPD_CX>;
1327 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = "tx", "rx";
1335 #address-cells = <1>;
1337 status = "disabled";
1341 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x00994000 0x0 0x4000>;
1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names = "default";
1346 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cells = <1>;
1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = "tx", "rx";
1357 status = "disabled";
1361 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x00994000 0x0 0x4000>;
1364 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names = "default";
1367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = "tx", "rx";
1375 #address-cells = <1>;
1377 status = "disabled";
1382 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x00998000 0x0 0x4000>;
1385 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names = "default";
1387 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cells = <1>;
1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = "tx", "rx";
1398 status = "disabled";
1402 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x00998000 0x0 0x4000>;
1405 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names = "default";
1408 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = "tx", "rx";
1416 #address-cells = <1>;
1418 status = "disabled";
1421 uart7: serial@99c000 {
1422 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x0099c000 0 0x4000>;
1425 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names = "default";
1427 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1430 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1431 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1432 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1433 interconnect-names = "qup-core",
1435 status = "disabled";
1439 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1442 reg = <0 0x00a00000 0 0x60000>;
1443 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>;
1456 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled";
1461 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = "qup-core";
1470 #address-cells = <2>;
1473 status = "disabled";
1476 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x00a80000 0x0 0x4000>;
1479 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names = "default";
1481 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cells = <1>;
1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = "tx", "rx";
1492 status = "disabled";
1496 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x00a80000 0x0 0x4000>;
1499 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names = "default";
1502 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = "tx", "rx";
1510 #address-cells = <1>;
1512 status = "disabled";
1516 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x00a84000 0x0 0x4000>;
1519 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names = "default";
1521 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cells = <1>;
1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = "tx", "rx";
1532 status = "disabled";
1536 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x00a84000 0x0 0x4000>;
1539 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names = "default";
1542 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = "tx", "rx";
1550 #address-cells = <1>;
1552 status = "disabled";
1556 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x00a88000 0x0 0x4000>;
1559 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names = "default";
1561 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cells = <1>;
1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = "tx", "rx";
1572 status = "disabled";
1576 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x00a88000 0x0 0x4000>;
1579 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names = "default";
1582 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = "tx", "rx";
1590 #address-cells = <1>;
1592 status = "disabled";
1596 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x00a8c000 0x0 0x4000>;
1599 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names = "default";
1601 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cells = <1>;
1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = "tx", "rx";
1612 status = "disabled";
1616 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x00a8c000 0x0 0x4000>;
1619 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = "tx", "rx";
1630 #address-cells = <1>;
1632 status = "disabled";
1636 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x00a90000 0x0 0x4000>;
1639 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names = "default";
1641 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cells = <1>;
1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = "tx", "rx";
1652 status = "disabled";
1656 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x00a90000 0x0 0x4000>;
1659 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names = "default";
1662 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = "tx", "rx";
1670 #address-cells = <1>;
1672 status = "disabled";
1676 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00a94000 0 0x4000>;
1679 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names = "default";
1681 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = "tx", "rx";
1690 #address-cells = <1>;
1692 status = "disabled";
1696 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x00a94000 0x0 0x4000>;
1699 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names = "default";
1702 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = "tx", "rx";
1710 #address-cells = <1>;
1712 status = "disabled";
1716 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00a98000 0 0x4000>;
1719 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names = "default";
1721 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = "tx", "rx";
1730 #address-cells = <1>;
1732 status = "disabled";
1736 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x00a98000 0x0 0x4000>;
1739 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names = "default";
1742 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = "tx", "rx";
1750 #address-cells = <1>;
1752 status = "disabled";
1757 compatible = "qcom,sm8450-trng", "qcom,trng";
1758 reg = <0 0x010c3000 0 0x1000>;
1761 pcie0: pcie@1c00000 {
1762 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci";
1770 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xff>;
1774 #address-cells = <3>;
1777 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1780 msi-map = <0x0 &gic_its 0x5980 0x1>,
1781 <0x100 &gic_its 0x5981 0x1>;
1782 msi-map-mask = <0xff00>;
1783 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1784 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1785 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1786 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1787 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1789 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1790 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1791 interrupt-names = "msi0",
1799 #interrupt-cells = <1>;
1800 interrupt-map-mask = <0 0 0 0x7>;
1801 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1806 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1807 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1809 <&rpmhcc RPMH_CXO_CLK>,
1810 <&gcc GCC_PCIE_0_AUX_CLK>,
1811 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1812 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1813 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1814 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1815 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1816 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1817 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1818 clock-names = "pipe",
1831 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1832 <0x100 &apps_smmu 0x1c01 0x1>;
1834 resets = <&gcc GCC_PCIE_0_BCR>;
1835 reset-names = "pci";
1837 power-domains = <&gcc PCIE_0_GDSC>;
1839 phys = <&pcie0_phy>;
1840 phy-names = "pciephy";
1842 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1843 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1845 pinctrl-names = "default";
1846 pinctrl-0 = <&pcie0_default_state>;
1848 status = "disabled";
1851 pcie0_phy: phy@1c06000 {
1852 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1853 reg = <0 0x01c06000 0 0x2000>;
1855 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1856 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1857 <&gcc GCC_PCIE_0_CLKREF_EN>,
1858 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1859 <&gcc GCC_PCIE_0_PIPE_CLK>;
1860 clock-names = "aux",
1866 clock-output-names = "pcie_0_pipe_clk";
1871 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1872 reset-names = "phy";
1874 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1875 assigned-clock-rates = <100000000>;
1877 status = "disabled";
1880 pcie1: pcie@1c08000 {
1881 compatible = "qcom,pcie-sm8450-pcie1";
1882 reg = <0 0x01c08000 0 0x3000>,
1883 <0 0x40000000 0 0xf1d>,
1884 <0 0x40000f20 0 0xa8>,
1885 <0 0x40001000 0 0x1000>,
1886 <0 0x40100000 0 0x100000>;
1887 reg-names = "parf", "dbi", "elbi", "atu", "config";
1888 device_type = "pci";
1889 linux,pci-domain = <1>;
1890 bus-range = <0x00 0xff>;
1893 #address-cells = <3>;
1896 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1897 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1899 msi-map = <0x0 &gic_its 0x5a00 0x1>,
1900 <0x100 &gic_its 0x5a01 0x1>;
1901 msi-map-mask = <0xff00>;
1902 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1903 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1904 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1905 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1906 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1907 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1908 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1909 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1910 interrupt-names = "msi0",
1918 #interrupt-cells = <1>;
1919 interrupt-map-mask = <0 0 0 0x7>;
1920 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1921 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1922 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1923 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1925 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1926 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1928 <&rpmhcc RPMH_CXO_CLK>,
1929 <&gcc GCC_PCIE_1_AUX_CLK>,
1930 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1931 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1932 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1933 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1934 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1935 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1936 clock-names = "pipe",
1948 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1949 <0x100 &apps_smmu 0x1c81 0x1>;
1951 resets = <&gcc GCC_PCIE_1_BCR>;
1952 reset-names = "pci";
1954 power-domains = <&gcc PCIE_1_GDSC>;
1956 phys = <&pcie1_phy>;
1957 phy-names = "pciephy";
1959 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1960 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1962 pinctrl-names = "default";
1963 pinctrl-0 = <&pcie1_default_state>;
1965 status = "disabled";
1968 pcie1_phy: phy@1c0e000 {
1969 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1970 reg = <0 0x01c0e000 0 0x2000>;
1972 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1973 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1974 <&gcc GCC_PCIE_1_CLKREF_EN>,
1975 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1976 <&gcc GCC_PCIE_1_PIPE_CLK>;
1977 clock-names = "aux",
1983 clock-output-names = "pcie_1_pipe_clk";
1988 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1989 reset-names = "phy";
1991 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1992 assigned-clock-rates = <100000000>;
1994 status = "disabled";
1997 config_noc: interconnect@1500000 {
1998 compatible = "qcom,sm8450-config-noc";
1999 reg = <0 0x01500000 0 0x1c000>;
2000 #interconnect-cells = <2>;
2001 qcom,bcm-voters = <&apps_bcm_voter>;
2004 system_noc: interconnect@1680000 {
2005 compatible = "qcom,sm8450-system-noc";
2006 reg = <0 0x01680000 0 0x1e200>;
2007 #interconnect-cells = <2>;
2008 qcom,bcm-voters = <&apps_bcm_voter>;
2011 pcie_noc: interconnect@16c0000 {
2012 compatible = "qcom,sm8450-pcie-anoc";
2013 reg = <0 0x016c0000 0 0xe280>;
2014 #interconnect-cells = <2>;
2015 qcom,bcm-voters = <&apps_bcm_voter>;
2018 aggre1_noc: interconnect@16e0000 {
2019 compatible = "qcom,sm8450-aggre1-noc";
2020 reg = <0 0x016e0000 0 0x1c080>;
2021 #interconnect-cells = <2>;
2022 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2023 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2024 qcom,bcm-voters = <&apps_bcm_voter>;
2027 aggre2_noc: interconnect@1700000 {
2028 compatible = "qcom,sm8450-aggre2-noc";
2029 reg = <0 0x01700000 0 0x31080>;
2030 #interconnect-cells = <2>;
2031 qcom,bcm-voters = <&apps_bcm_voter>;
2032 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2033 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2034 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2035 <&rpmhcc RPMH_IPA_CLK>;
2038 mmss_noc: interconnect@1740000 {
2039 compatible = "qcom,sm8450-mmss-noc";
2040 reg = <0 0x01740000 0 0x1f080>;
2041 #interconnect-cells = <2>;
2042 qcom,bcm-voters = <&apps_bcm_voter>;
2045 tcsr_mutex: hwlock@1f40000 {
2046 compatible = "qcom,tcsr-mutex";
2047 reg = <0x0 0x01f40000 0x0 0x40000>;
2048 #hwlock-cells = <1>;
2051 tcsr: syscon@1fc0000 {
2052 compatible = "qcom,sm8450-tcsr", "syscon";
2053 reg = <0x0 0x1fc0000 0x0 0x30000>;
2057 compatible = "qcom,adreno-730.1", "qcom,adreno";
2058 reg = <0x0 0x03d00000 0x0 0x40000>,
2059 <0x0 0x03d9e000 0x0 0x1000>,
2060 <0x0 0x03d61000 0x0 0x800>;
2061 reg-names = "kgsl_3d0_reg_memory",
2065 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2067 iommus = <&adreno_smmu 0 0x400>,
2068 <&adreno_smmu 1 0x400>;
2070 operating-points-v2 = <&gpu_opp_table>;
2073 #cooling-cells = <2>;
2075 status = "disabled";
2078 memory-region = <&gpu_micro_code_mem>;
2081 gpu_opp_table: opp-table {
2082 compatible = "operating-points-v2";
2085 opp-hz = /bits/ 64 <818000000>;
2086 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2090 opp-hz = /bits/ 64 <791000000>;
2091 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2095 opp-hz = /bits/ 64 <734000000>;
2096 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2100 opp-hz = /bits/ 64 <640000000>;
2101 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2105 opp-hz = /bits/ 64 <599000000>;
2106 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2110 opp-hz = /bits/ 64 <545000000>;
2111 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2115 opp-hz = /bits/ 64 <492000000>;
2116 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2120 opp-hz = /bits/ 64 <421000000>;
2121 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2125 opp-hz = /bits/ 64 <350000000>;
2126 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2130 opp-hz = /bits/ 64 <317000000>;
2131 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2135 opp-hz = /bits/ 64 <285000000>;
2136 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2140 opp-hz = /bits/ 64 <220000000>;
2141 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2147 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2148 reg = <0x0 0x03d6a000 0x0 0x35000>,
2149 <0x0 0x03d50000 0x0 0x10000>,
2150 <0x0 0x0b290000 0x0 0x10000>;
2151 reg-names = "gmu", "rscc", "gmu_pdc";
2153 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2154 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2155 interrupt-names = "hfi", "gmu";
2157 clocks = <&gpucc GPU_CC_AHB_CLK>,
2158 <&gpucc GPU_CC_CX_GMU_CLK>,
2159 <&gpucc GPU_CC_CXO_CLK>,
2160 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2161 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2162 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2163 <&gpucc GPU_CC_DEMET_CLK>;
2164 clock-names = "ahb",
2172 power-domains = <&gpucc GPU_CX_GDSC>,
2173 <&gpucc GPU_GX_GDSC>;
2174 power-domain-names = "cx",
2177 iommus = <&adreno_smmu 5 0x400>;
2179 qcom,qmp = <&aoss_qmp>;
2181 operating-points-v2 = <&gmu_opp_table>;
2183 gmu_opp_table: opp-table {
2184 compatible = "operating-points-v2";
2187 opp-hz = /bits/ 64 <500000000>;
2188 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2192 opp-hz = /bits/ 64 <200000000>;
2193 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2198 gpucc: clock-controller@3d90000 {
2199 compatible = "qcom,sm8450-gpucc";
2200 reg = <0x0 0x03d90000 0x0 0xa000>;
2201 clocks = <&rpmhcc RPMH_CXO_CLK>,
2202 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2203 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2206 #power-domain-cells = <1>;
2209 adreno_smmu: iommu@3da0000 {
2210 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
2211 "qcom,smmu-500", "arm,mmu-500";
2212 reg = <0x0 0x03da0000 0x0 0x40000>;
2214 #global-interrupts = <1>;
2215 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2216 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2217 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2218 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2219 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2220 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2221 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2222 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2223 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2224 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2226 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2227 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
2228 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
2233 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2237 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
2241 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2242 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2243 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2244 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2245 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2246 <&gpucc GPU_CC_AHB_CLK>;
2247 clock-names = "gmu",
2253 power-domains = <&gpucc GPU_CX_GDSC>;
2257 usb_1_hsphy: phy@88e3000 {
2258 compatible = "qcom,sm8450-usb-hs-phy",
2259 "qcom,usb-snps-hs-7nm-phy";
2260 reg = <0 0x088e3000 0 0x400>;
2261 status = "disabled";
2264 clocks = <&rpmhcc RPMH_CXO_CLK>;
2265 clock-names = "ref";
2267 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2270 usb_1_qmpphy: phy@88e8000 {
2271 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2272 reg = <0 0x088e8000 0 0x3000>;
2274 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2275 <&rpmhcc RPMH_CXO_CLK>,
2276 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2277 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2278 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2280 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2281 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2282 reset-names = "phy", "common";
2287 status = "disabled";
2290 #address-cells = <1>;
2296 usb_1_qmpphy_out: endpoint {
2303 usb_1_qmpphy_usb_ss_in: endpoint {
2310 usb_1_qmpphy_dp_in: endpoint {
2316 remoteproc_slpi: remoteproc@2400000 {
2317 compatible = "qcom,sm8450-slpi-pas";
2318 reg = <0 0x02400000 0 0x4000>;
2320 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2321 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2322 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2323 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2324 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2325 interrupt-names = "wdog", "fatal", "ready",
2326 "handover", "stop-ack";
2328 clocks = <&rpmhcc RPMH_CXO_CLK>;
2331 power-domains = <&rpmhpd RPMHPD_LCX>,
2332 <&rpmhpd RPMHPD_LMX>;
2333 power-domain-names = "lcx", "lmx";
2335 memory-region = <&slpi_mem>;
2337 qcom,qmp = <&aoss_qmp>;
2339 qcom,smem-states = <&smp2p_slpi_out 0>;
2340 qcom,smem-state-names = "stop";
2342 status = "disabled";
2345 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2346 IPCC_MPROC_SIGNAL_GLINK_QMP
2347 IRQ_TYPE_EDGE_RISING>;
2348 mboxes = <&ipcc IPCC_CLIENT_SLPI
2349 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2352 qcom,remote-pid = <3>;
2355 compatible = "qcom,fastrpc";
2356 qcom,glink-channels = "fastrpcglink-apps-dsp";
2358 #address-cells = <1>;
2362 compatible = "qcom,fastrpc-compute-cb";
2364 iommus = <&apps_smmu 0x0541 0x0>;
2368 compatible = "qcom,fastrpc-compute-cb";
2370 iommus = <&apps_smmu 0x0542 0x0>;
2374 compatible = "qcom,fastrpc-compute-cb";
2376 iommus = <&apps_smmu 0x0543 0x0>;
2377 /* note: shared-cb = <4> in downstream */
2383 wsa2macro: codec@31e0000 {
2384 compatible = "qcom,sm8450-lpass-wsa-macro";
2385 reg = <0 0x031e0000 0 0x1000>;
2386 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2387 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2388 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2389 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2391 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2394 clock-output-names = "wsa2-mclk";
2395 #sound-dai-cells = <1>;
2398 swr4: soundwire@31f0000 {
2399 compatible = "qcom,soundwire-v1.7.0";
2400 reg = <0 0x031f0000 0 0x2000>;
2401 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2402 clocks = <&wsa2macro>;
2403 clock-names = "iface";
2406 pinctrl-0 = <&wsa2_swr_active>;
2407 pinctrl-names = "default";
2409 qcom,din-ports = <2>;
2410 qcom,dout-ports = <6>;
2412 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2413 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2414 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2415 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2416 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2417 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2418 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2419 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2420 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2422 #address-cells = <2>;
2424 #sound-dai-cells = <1>;
2425 status = "disabled";
2428 rxmacro: codec@3200000 {
2429 compatible = "qcom,sm8450-lpass-rx-macro";
2430 reg = <0 0x03200000 0 0x1000>;
2431 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2432 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2433 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2434 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2436 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2439 clock-output-names = "mclk";
2440 #sound-dai-cells = <1>;
2443 swr1: soundwire@3210000 {
2444 compatible = "qcom,soundwire-v1.7.0";
2445 reg = <0 0x03210000 0 0x2000>;
2446 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2447 clocks = <&rxmacro>;
2448 clock-names = "iface";
2450 qcom,din-ports = <0>;
2451 qcom,dout-ports = <5>;
2453 pinctrl-0 = <&rx_swr_active>;
2454 pinctrl-names = "default";
2456 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2457 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2458 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2459 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2460 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2461 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2462 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2463 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2464 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2466 #address-cells = <2>;
2468 #sound-dai-cells = <1>;
2469 status = "disabled";
2472 txmacro: codec@3220000 {
2473 compatible = "qcom,sm8450-lpass-tx-macro";
2474 reg = <0 0x03220000 0 0x1000>;
2475 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2476 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2477 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2478 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2480 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2483 clock-output-names = "mclk";
2484 #sound-dai-cells = <1>;
2487 wsamacro: codec@3240000 {
2488 compatible = "qcom,sm8450-lpass-wsa-macro";
2489 reg = <0 0x03240000 0 0x1000>;
2490 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2491 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2492 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2493 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2495 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2498 clock-output-names = "mclk";
2499 #sound-dai-cells = <1>;
2502 swr0: soundwire@3250000 {
2503 compatible = "qcom,soundwire-v1.7.0";
2504 reg = <0 0x03250000 0 0x2000>;
2505 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2506 clocks = <&wsamacro>;
2507 clock-names = "iface";
2510 pinctrl-0 = <&wsa_swr_active>;
2511 pinctrl-names = "default";
2513 qcom,din-ports = <2>;
2514 qcom,dout-ports = <6>;
2516 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2517 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2518 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2519 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2520 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2521 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2522 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2523 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2524 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2526 #address-cells = <2>;
2528 #sound-dai-cells = <1>;
2529 status = "disabled";
2532 swr2: soundwire@33b0000 {
2533 compatible = "qcom,soundwire-v1.7.0";
2534 reg = <0 0x033b0000 0 0x2000>;
2535 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2536 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2537 interrupt-names = "core", "wakeup";
2539 clocks = <&txmacro>;
2540 clock-names = "iface";
2543 pinctrl-0 = <&tx_swr_active>;
2544 pinctrl-names = "default";
2546 qcom,din-ports = <4>;
2547 qcom,dout-ports = <0>;
2548 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2549 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2550 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2551 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2552 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2553 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2554 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2555 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2556 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2558 #address-cells = <2>;
2560 #sound-dai-cells = <1>;
2561 status = "disabled";
2564 vamacro: codec@33f0000 {
2565 compatible = "qcom,sm8450-lpass-va-macro";
2566 reg = <0 0x033f0000 0 0x1000>;
2567 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2568 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2569 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2570 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2571 clock-names = "mclk", "macro", "dcodec", "npl";
2574 clock-output-names = "fsgen";
2575 #sound-dai-cells = <1>;
2576 status = "disabled";
2579 remoteproc_adsp: remoteproc@30000000 {
2580 compatible = "qcom,sm8450-adsp-pas";
2581 reg = <0 0x30000000 0 0x100>;
2583 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2584 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2585 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2586 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2587 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2588 interrupt-names = "wdog", "fatal", "ready",
2589 "handover", "stop-ack";
2591 clocks = <&rpmhcc RPMH_CXO_CLK>;
2594 power-domains = <&rpmhpd RPMHPD_LCX>,
2595 <&rpmhpd RPMHPD_LMX>;
2596 power-domain-names = "lcx", "lmx";
2598 memory-region = <&adsp_mem>;
2600 qcom,qmp = <&aoss_qmp>;
2602 qcom,smem-states = <&smp2p_adsp_out 0>;
2603 qcom,smem-state-names = "stop";
2605 status = "disabled";
2607 remoteproc_adsp_glink: glink-edge {
2608 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2609 IPCC_MPROC_SIGNAL_GLINK_QMP
2610 IRQ_TYPE_EDGE_RISING>;
2611 mboxes = <&ipcc IPCC_CLIENT_LPASS
2612 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2615 qcom,remote-pid = <2>;
2618 compatible = "qcom,gpr";
2619 qcom,glink-channels = "adsp_apps";
2620 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2621 qcom,intents = <512 20>;
2622 #address-cells = <1>;
2626 compatible = "qcom,q6apm";
2627 reg = <GPR_APM_MODULE_IID>;
2628 #sound-dai-cells = <0>;
2629 qcom,protection-domain = "avs/audio",
2630 "msm/adsp/audio_pd";
2633 compatible = "qcom,q6apm-dais";
2634 iommus = <&apps_smmu 0x1801 0x0>;
2637 q6apmbedai: bedais {
2638 compatible = "qcom,q6apm-lpass-dais";
2639 #sound-dai-cells = <1>;
2644 compatible = "qcom,q6prm";
2645 reg = <GPR_PRM_MODULE_IID>;
2646 qcom,protection-domain = "avs/audio",
2647 "msm/adsp/audio_pd";
2649 q6prmcc: clock-controller {
2650 compatible = "qcom,q6prm-lpass-clocks";
2657 compatible = "qcom,fastrpc";
2658 qcom,glink-channels = "fastrpcglink-apps-dsp";
2660 #address-cells = <1>;
2664 compatible = "qcom,fastrpc-compute-cb";
2666 iommus = <&apps_smmu 0x1803 0x0>;
2670 compatible = "qcom,fastrpc-compute-cb";
2672 iommus = <&apps_smmu 0x1804 0x0>;
2676 compatible = "qcom,fastrpc-compute-cb";
2678 iommus = <&apps_smmu 0x1805 0x0>;
2684 remoteproc_cdsp: remoteproc@32300000 {
2685 compatible = "qcom,sm8450-cdsp-pas";
2686 reg = <0 0x32300000 0 0x1400000>;
2688 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2689 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2690 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2691 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2692 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2693 interrupt-names = "wdog", "fatal", "ready",
2694 "handover", "stop-ack";
2696 clocks = <&rpmhcc RPMH_CXO_CLK>;
2699 power-domains = <&rpmhpd RPMHPD_CX>,
2700 <&rpmhpd RPMHPD_MXC>;
2701 power-domain-names = "cx", "mxc";
2703 memory-region = <&cdsp_mem>;
2705 qcom,qmp = <&aoss_qmp>;
2707 qcom,smem-states = <&smp2p_cdsp_out 0>;
2708 qcom,smem-state-names = "stop";
2710 status = "disabled";
2713 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2714 IPCC_MPROC_SIGNAL_GLINK_QMP
2715 IRQ_TYPE_EDGE_RISING>;
2716 mboxes = <&ipcc IPCC_CLIENT_CDSP
2717 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2720 qcom,remote-pid = <5>;
2723 compatible = "qcom,fastrpc";
2724 qcom,glink-channels = "fastrpcglink-apps-dsp";
2726 #address-cells = <1>;
2730 compatible = "qcom,fastrpc-compute-cb";
2732 iommus = <&apps_smmu 0x2161 0x0400>,
2733 <&apps_smmu 0x1021 0x1420>;
2737 compatible = "qcom,fastrpc-compute-cb";
2739 iommus = <&apps_smmu 0x2162 0x0400>,
2740 <&apps_smmu 0x1022 0x1420>;
2744 compatible = "qcom,fastrpc-compute-cb";
2746 iommus = <&apps_smmu 0x2163 0x0400>,
2747 <&apps_smmu 0x1023 0x1420>;
2751 compatible = "qcom,fastrpc-compute-cb";
2753 iommus = <&apps_smmu 0x2164 0x0400>,
2754 <&apps_smmu 0x1024 0x1420>;
2758 compatible = "qcom,fastrpc-compute-cb";
2760 iommus = <&apps_smmu 0x2165 0x0400>,
2761 <&apps_smmu 0x1025 0x1420>;
2765 compatible = "qcom,fastrpc-compute-cb";
2767 iommus = <&apps_smmu 0x2166 0x0400>,
2768 <&apps_smmu 0x1026 0x1420>;
2772 compatible = "qcom,fastrpc-compute-cb";
2774 iommus = <&apps_smmu 0x2167 0x0400>,
2775 <&apps_smmu 0x1027 0x1420>;
2779 compatible = "qcom,fastrpc-compute-cb";
2781 iommus = <&apps_smmu 0x2168 0x0400>,
2782 <&apps_smmu 0x1028 0x1420>;
2785 /* note: secure cb9 in downstream */
2790 remoteproc_mpss: remoteproc@4080000 {
2791 compatible = "qcom,sm8450-mpss-pas";
2792 reg = <0x0 0x04080000 0x0 0x4040>;
2794 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2795 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2796 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2797 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2798 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2799 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2800 interrupt-names = "wdog", "fatal", "ready", "handover",
2801 "stop-ack", "shutdown-ack";
2803 clocks = <&rpmhcc RPMH_CXO_CLK>;
2806 power-domains = <&rpmhpd RPMHPD_CX>,
2807 <&rpmhpd RPMHPD_MSS>;
2808 power-domain-names = "cx", "mss";
2810 memory-region = <&mpss_mem>;
2812 qcom,qmp = <&aoss_qmp>;
2814 qcom,smem-states = <&smp2p_modem_out 0>;
2815 qcom,smem-state-names = "stop";
2817 status = "disabled";
2820 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2821 IPCC_MPROC_SIGNAL_GLINK_QMP
2822 IRQ_TYPE_EDGE_RISING>;
2823 mboxes = <&ipcc IPCC_CLIENT_MPSS
2824 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2826 qcom,remote-pid = <1>;
2830 videocc: clock-controller@aaf0000 {
2831 compatible = "qcom,sm8450-videocc";
2832 reg = <0 0x0aaf0000 0 0x10000>;
2833 clocks = <&rpmhcc RPMH_CXO_CLK>,
2834 <&gcc GCC_VIDEO_AHB_CLK>;
2835 power-domains = <&rpmhpd RPMHPD_MMCX>;
2836 required-opps = <&rpmhpd_opp_low_svs>;
2839 #power-domain-cells = <1>;
2843 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2844 reg = <0 0x0ac15000 0 0x1000>;
2845 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2846 power-domains = <&camcc TITAN_TOP_GDSC>;
2848 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2849 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2850 <&camcc CAM_CC_CPAS_AHB_CLK>,
2851 <&camcc CAM_CC_CCI_0_CLK>,
2852 <&camcc CAM_CC_CCI_0_CLK_SRC>;
2853 clock-names = "camnoc_axi",
2858 pinctrl-0 = <&cci0_default &cci1_default>;
2859 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2860 pinctrl-names = "default", "sleep";
2862 status = "disabled";
2863 #address-cells = <1>;
2866 cci0_i2c0: i2c-bus@0 {
2868 clock-frequency = <1000000>;
2869 #address-cells = <1>;
2873 cci0_i2c1: i2c-bus@1 {
2875 clock-frequency = <1000000>;
2876 #address-cells = <1>;
2882 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2883 reg = <0 0x0ac16000 0 0x1000>;
2884 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2885 power-domains = <&camcc TITAN_TOP_GDSC>;
2887 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2888 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2889 <&camcc CAM_CC_CPAS_AHB_CLK>,
2890 <&camcc CAM_CC_CCI_1_CLK>,
2891 <&camcc CAM_CC_CCI_1_CLK_SRC>;
2892 clock-names = "camnoc_axi",
2897 pinctrl-0 = <&cci2_default &cci3_default>;
2898 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
2899 pinctrl-names = "default", "sleep";
2901 status = "disabled";
2902 #address-cells = <1>;
2905 cci1_i2c0: i2c-bus@0 {
2907 clock-frequency = <1000000>;
2908 #address-cells = <1>;
2912 cci1_i2c1: i2c-bus@1 {
2914 clock-frequency = <1000000>;
2915 #address-cells = <1>;
2920 camcc: clock-controller@ade0000 {
2921 compatible = "qcom,sm8450-camcc";
2922 reg = <0 0x0ade0000 0 0x20000>;
2923 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2924 <&rpmhcc RPMH_CXO_CLK>,
2925 <&rpmhcc RPMH_CXO_CLK_A>,
2927 power-domains = <&rpmhpd RPMHPD_MMCX>;
2928 required-opps = <&rpmhpd_opp_low_svs>;
2931 #power-domain-cells = <1>;
2932 status = "disabled";
2935 mdss: display-subsystem@ae00000 {
2936 compatible = "qcom,sm8450-mdss";
2937 reg = <0 0x0ae00000 0 0x1000>;
2940 /* same path used twice */
2941 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2942 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2943 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2944 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
2945 interconnect-names = "mdp0-mem",
2949 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2951 power-domains = <&dispcc MDSS_GDSC>;
2953 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2954 <&gcc GCC_DISP_HF_AXI_CLK>,
2955 <&gcc GCC_DISP_SF_AXI_CLK>,
2956 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2958 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2959 interrupt-controller;
2960 #interrupt-cells = <1>;
2962 iommus = <&apps_smmu 0x2800 0x402>;
2964 #address-cells = <2>;
2968 status = "disabled";
2970 mdss_mdp: display-controller@ae01000 {
2971 compatible = "qcom,sm8450-dpu";
2972 reg = <0 0x0ae01000 0 0x8f000>,
2973 <0 0x0aeb0000 0 0x2008>;
2974 reg-names = "mdp", "vbif";
2976 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2977 <&gcc GCC_DISP_SF_AXI_CLK>,
2978 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2979 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2980 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2981 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2982 clock-names = "bus",
2989 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2990 assigned-clock-rates = <19200000>;
2992 operating-points-v2 = <&mdp_opp_table>;
2993 power-domains = <&rpmhpd RPMHPD_MMCX>;
2995 interrupt-parent = <&mdss>;
2999 #address-cells = <1>;
3004 dpu_intf1_out: endpoint {
3005 remote-endpoint = <&mdss_dsi0_in>;
3011 dpu_intf2_out: endpoint {
3012 remote-endpoint = <&mdss_dsi1_in>;
3018 dpu_intf0_out: endpoint {
3019 remote-endpoint = <&mdss_dp0_in>;
3024 mdp_opp_table: opp-table {
3025 compatible = "operating-points-v2";
3028 opp-hz = /bits/ 64 <172000000>;
3029 required-opps = <&rpmhpd_opp_low_svs_d1>;
3033 opp-hz = /bits/ 64 <200000000>;
3034 required-opps = <&rpmhpd_opp_low_svs>;
3038 opp-hz = /bits/ 64 <325000000>;
3039 required-opps = <&rpmhpd_opp_svs>;
3043 opp-hz = /bits/ 64 <375000000>;
3044 required-opps = <&rpmhpd_opp_svs_l1>;
3048 opp-hz = /bits/ 64 <500000000>;
3049 required-opps = <&rpmhpd_opp_nom>;
3054 mdss_dp0: displayport-controller@ae90000 {
3055 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3056 reg = <0 0xae90000 0 0x200>,
3057 <0 0xae90200 0 0x200>,
3058 <0 0xae90400 0 0xc00>,
3059 <0 0xae91000 0 0x400>,
3060 <0 0xae91400 0 0x400>;
3061 interrupt-parent = <&mdss>;
3063 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3064 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3065 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3066 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3067 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3068 clock-names = "core_iface",
3074 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3075 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3076 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3077 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3079 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3082 #sound-dai-cells = <0>;
3084 operating-points-v2 = <&dp_opp_table>;
3085 power-domains = <&rpmhpd RPMHPD_MMCX>;
3087 status = "disabled";
3090 #address-cells = <1>;
3095 mdss_dp0_in: endpoint {
3096 remote-endpoint = <&dpu_intf0_out>;
3101 dp_opp_table: opp-table {
3102 compatible = "operating-points-v2";
3105 opp-hz = /bits/ 64 <160000000>;
3106 required-opps = <&rpmhpd_opp_low_svs>;
3110 opp-hz = /bits/ 64 <270000000>;
3111 required-opps = <&rpmhpd_opp_svs>;
3115 opp-hz = /bits/ 64 <540000000>;
3116 required-opps = <&rpmhpd_opp_svs_l1>;
3120 opp-hz = /bits/ 64 <810000000>;
3121 required-opps = <&rpmhpd_opp_nom>;
3126 mdss_dsi0: dsi@ae94000 {
3127 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3128 reg = <0 0x0ae94000 0 0x400>;
3129 reg-names = "dsi_ctrl";
3131 interrupt-parent = <&mdss>;
3134 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3135 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3136 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3137 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3138 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3139 <&gcc GCC_DISP_HF_AXI_CLK>;
3140 clock-names = "byte",
3147 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3148 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3150 operating-points-v2 = <&mdss_dsi_opp_table>;
3151 power-domains = <&rpmhpd RPMHPD_MMCX>;
3153 phys = <&mdss_dsi0_phy>;
3156 #address-cells = <1>;
3159 status = "disabled";
3162 #address-cells = <1>;
3167 mdss_dsi0_in: endpoint {
3168 remote-endpoint = <&dpu_intf1_out>;
3174 mdss_dsi0_out: endpoint {
3179 mdss_dsi_opp_table: opp-table {
3180 compatible = "operating-points-v2";
3183 opp-hz = /bits/ 64 <187500000>;
3184 required-opps = <&rpmhpd_opp_low_svs>;
3188 opp-hz = /bits/ 64 <300000000>;
3189 required-opps = <&rpmhpd_opp_svs>;
3193 opp-hz = /bits/ 64 <358000000>;
3194 required-opps = <&rpmhpd_opp_svs_l1>;
3199 mdss_dsi0_phy: phy@ae94400 {
3200 compatible = "qcom,sm8450-dsi-phy-5nm";
3201 reg = <0 0x0ae94400 0 0x200>,
3202 <0 0x0ae94600 0 0x280>,
3203 <0 0x0ae94900 0 0x260>;
3204 reg-names = "dsi_phy",
3211 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3212 <&rpmhcc RPMH_CXO_CLK>;
3213 clock-names = "iface", "ref";
3215 status = "disabled";
3218 mdss_dsi1: dsi@ae96000 {
3219 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3220 reg = <0 0x0ae96000 0 0x400>;
3221 reg-names = "dsi_ctrl";
3223 interrupt-parent = <&mdss>;
3226 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3227 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3228 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3229 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3230 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3231 <&gcc GCC_DISP_HF_AXI_CLK>;
3232 clock-names = "byte",
3239 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3240 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3242 operating-points-v2 = <&mdss_dsi_opp_table>;
3243 power-domains = <&rpmhpd RPMHPD_MMCX>;
3245 phys = <&mdss_dsi1_phy>;
3248 #address-cells = <1>;
3251 status = "disabled";
3254 #address-cells = <1>;
3259 mdss_dsi1_in: endpoint {
3260 remote-endpoint = <&dpu_intf2_out>;
3266 mdss_dsi1_out: endpoint {
3272 mdss_dsi1_phy: phy@ae96400 {
3273 compatible = "qcom,sm8450-dsi-phy-5nm";
3274 reg = <0 0x0ae96400 0 0x200>,
3275 <0 0x0ae96600 0 0x280>,
3276 <0 0x0ae96900 0 0x260>;
3277 reg-names = "dsi_phy",
3284 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3285 <&rpmhcc RPMH_CXO_CLK>;
3286 clock-names = "iface", "ref";
3288 status = "disabled";
3292 dispcc: clock-controller@af00000 {
3293 compatible = "qcom,sm8450-dispcc";
3294 reg = <0 0x0af00000 0 0x20000>;
3295 clocks = <&rpmhcc RPMH_CXO_CLK>,
3296 <&rpmhcc RPMH_CXO_CLK_A>,
3297 <&gcc GCC_DISP_AHB_CLK>,
3303 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3304 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3311 power-domains = <&rpmhpd RPMHPD_MMCX>;
3312 required-opps = <&rpmhpd_opp_low_svs>;
3315 #power-domain-cells = <1>;
3316 status = "disabled";
3319 pdc: interrupt-controller@b220000 {
3320 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3321 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3322 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3323 <94 609 31>, <125 63 1>, <126 716 12>;
3324 #interrupt-cells = <2>;
3325 interrupt-parent = <&intc>;
3326 interrupt-controller;
3329 tsens0: thermal-sensor@c263000 {
3330 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3331 reg = <0 0x0c263000 0 0x1000>, /* TM */
3332 <0 0x0c222000 0 0x1000>; /* SROT */
3333 #qcom,sensors = <16>;
3334 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3335 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3336 interrupt-names = "uplow", "critical";
3337 #thermal-sensor-cells = <1>;
3340 tsens1: thermal-sensor@c265000 {
3341 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3342 reg = <0 0x0c265000 0 0x1000>, /* TM */
3343 <0 0x0c223000 0 0x1000>; /* SROT */
3344 #qcom,sensors = <16>;
3345 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3346 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3347 interrupt-names = "uplow", "critical";
3348 #thermal-sensor-cells = <1>;
3351 aoss_qmp: power-management@c300000 {
3352 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3353 reg = <0 0x0c300000 0 0x400>;
3354 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3355 IRQ_TYPE_EDGE_RISING>;
3356 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3362 compatible = "qcom,rpmh-stats";
3363 reg = <0 0x0c3f0000 0 0x400>;
3366 spmi_bus: spmi@c400000 {
3367 compatible = "qcom,spmi-pmic-arb";
3368 reg = <0 0x0c400000 0 0x00003000>,
3369 <0 0x0c500000 0 0x00400000>,
3370 <0 0x0c440000 0 0x00080000>,
3371 <0 0x0c4c0000 0 0x00010000>,
3372 <0 0x0c42d000 0 0x00010000>;
3378 interrupt-names = "periph_irq";
3379 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3382 interrupt-controller;
3383 #interrupt-cells = <4>;
3384 #address-cells = <2>;
3388 ipcc: mailbox@ed18000 {
3389 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3390 reg = <0 0x0ed18000 0 0x1000>;
3391 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3392 interrupt-controller;
3393 #interrupt-cells = <3>;
3397 tlmm: pinctrl@f100000 {
3398 compatible = "qcom,sm8450-tlmm";
3399 reg = <0 0x0f100000 0 0x300000>;
3400 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3403 interrupt-controller;
3404 #interrupt-cells = <2>;
3405 gpio-ranges = <&tlmm 0 0 211>;
3406 wakeup-parent = <&pdc>;
3408 sdc2_default_state: sdc2-default-state {
3411 drive-strength = <16>;
3417 drive-strength = <16>;
3423 drive-strength = <16>;
3428 sdc2_sleep_state: sdc2-sleep-state {
3431 drive-strength = <2>;
3437 drive-strength = <2>;
3443 drive-strength = <2>;
3448 cci0_default: cci0-default-state {
3450 pins = "gpio110", "gpio111";
3451 function = "cci_i2c";
3452 drive-strength = <2>;
3456 cci0_sleep: cci0-sleep-state {
3458 pins = "gpio110", "gpio111";
3459 function = "cci_i2c";
3460 drive-strength = <2>;
3464 cci1_default: cci1-default-state {
3466 pins = "gpio112", "gpio113";
3467 function = "cci_i2c";
3468 drive-strength = <2>;
3472 cci1_sleep: cci1-sleep-state {
3474 pins = "gpio112", "gpio113";
3475 function = "cci_i2c";
3476 drive-strength = <2>;
3480 cci2_default: cci2-default-state {
3482 pins = "gpio114", "gpio115";
3483 function = "cci_i2c";
3484 drive-strength = <2>;
3488 cci2_sleep: cci2-sleep-state {
3490 pins = "gpio114", "gpio115";
3491 function = "cci_i2c";
3492 drive-strength = <2>;
3496 cci3_default: cci3-default-state {
3498 pins = "gpio208", "gpio209";
3499 function = "cci_i2c";
3500 drive-strength = <2>;
3504 cci3_sleep: cci3-sleep-state {
3506 pins = "gpio208", "gpio209";
3507 function = "cci_i2c";
3508 drive-strength = <2>;
3512 pcie0_default_state: pcie0-default-state {
3516 drive-strength = <2>;
3522 function = "pcie0_clkreqn";
3523 drive-strength = <2>;
3530 drive-strength = <2>;
3535 pcie1_default_state: pcie1-default-state {
3539 drive-strength = <2>;
3545 function = "pcie1_clkreqn";
3546 drive-strength = <2>;
3553 drive-strength = <2>;
3558 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3559 pins = "gpio0", "gpio1";
3563 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3564 pins = "gpio4", "gpio5";
3568 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3569 pins = "gpio8", "gpio9";
3573 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3574 pins = "gpio12", "gpio13";
3578 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3579 pins = "gpio16", "gpio17";
3583 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3584 pins = "gpio206", "gpio207";
3588 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3589 pins = "gpio20", "gpio21";
3593 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3594 pins = "gpio28", "gpio29";
3598 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3599 pins = "gpio32", "gpio33";
3603 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3604 pins = "gpio36", "gpio37";
3608 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3609 pins = "gpio40", "gpio41";
3613 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3614 pins = "gpio44", "gpio45";
3618 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3619 pins = "gpio48", "gpio49";
3621 drive-strength = <2>;
3625 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3626 pins = "gpio52", "gpio53";
3628 drive-strength = <2>;
3632 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3633 pins = "gpio56", "gpio57";
3637 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3638 pins = "gpio60", "gpio61";
3642 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3643 pins = "gpio64", "gpio65";
3647 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3648 pins = "gpio68", "gpio69";
3652 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3653 pins = "gpio72", "gpio73";
3657 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3658 pins = "gpio76", "gpio77";
3662 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3663 pins = "gpio80", "gpio81";
3667 qup_spi0_cs: qup-spi0-cs-state {
3672 qup_spi0_data_clk: qup-spi0-data-clk-state {
3673 pins = "gpio0", "gpio1", "gpio2";
3677 qup_spi1_cs: qup-spi1-cs-state {
3682 qup_spi1_data_clk: qup-spi1-data-clk-state {
3683 pins = "gpio4", "gpio5", "gpio6";
3687 qup_spi2_cs: qup-spi2-cs-state {
3692 qup_spi2_data_clk: qup-spi2-data-clk-state {
3693 pins = "gpio8", "gpio9", "gpio10";
3697 qup_spi3_cs: qup-spi3-cs-state {
3702 qup_spi3_data_clk: qup-spi3-data-clk-state {
3703 pins = "gpio12", "gpio13", "gpio14";
3707 qup_spi4_cs: qup-spi4-cs-state {
3710 drive-strength = <6>;
3714 qup_spi4_data_clk: qup-spi4-data-clk-state {
3715 pins = "gpio16", "gpio17", "gpio18";
3719 qup_spi5_cs: qup-spi5-cs-state {
3724 qup_spi5_data_clk: qup-spi5-data-clk-state {
3725 pins = "gpio206", "gpio207", "gpio84";
3729 qup_spi6_cs: qup-spi6-cs-state {
3734 qup_spi6_data_clk: qup-spi6-data-clk-state {
3735 pins = "gpio20", "gpio21", "gpio22";
3739 qup_spi8_cs: qup-spi8-cs-state {
3744 qup_spi8_data_clk: qup-spi8-data-clk-state {
3745 pins = "gpio28", "gpio29", "gpio30";
3749 qup_spi9_cs: qup-spi9-cs-state {
3754 qup_spi9_data_clk: qup-spi9-data-clk-state {
3755 pins = "gpio32", "gpio33", "gpio34";
3759 qup_spi10_cs: qup-spi10-cs-state {
3764 qup_spi10_data_clk: qup-spi10-data-clk-state {
3765 pins = "gpio36", "gpio37", "gpio38";
3769 qup_spi11_cs: qup-spi11-cs-state {
3774 qup_spi11_data_clk: qup-spi11-data-clk-state {
3775 pins = "gpio40", "gpio41", "gpio42";
3779 qup_spi12_cs: qup-spi12-cs-state {
3784 qup_spi12_data_clk: qup-spi12-data-clk-state {
3785 pins = "gpio44", "gpio45", "gpio46";
3789 qup_spi13_cs: qup-spi13-cs-state {
3794 qup_spi13_data_clk: qup-spi13-data-clk-state {
3795 pins = "gpio48", "gpio49", "gpio50";
3799 qup_spi14_cs: qup-spi14-cs-state {
3804 qup_spi14_data_clk: qup-spi14-data-clk-state {
3805 pins = "gpio52", "gpio53", "gpio54";
3809 qup_spi15_cs: qup-spi15-cs-state {
3814 qup_spi15_data_clk: qup-spi15-data-clk-state {
3815 pins = "gpio56", "gpio57", "gpio58";
3819 qup_spi16_cs: qup-spi16-cs-state {
3824 qup_spi16_data_clk: qup-spi16-data-clk-state {
3825 pins = "gpio60", "gpio61", "gpio62";
3829 qup_spi17_cs: qup-spi17-cs-state {
3834 qup_spi17_data_clk: qup-spi17-data-clk-state {
3835 pins = "gpio64", "gpio65", "gpio66";
3839 qup_spi18_cs: qup-spi18-cs-state {
3842 drive-strength = <6>;
3846 qup_spi18_data_clk: qup-spi18-data-clk-state {
3847 pins = "gpio68", "gpio69", "gpio70";
3849 drive-strength = <6>;
3853 qup_spi19_cs: qup-spi19-cs-state {
3856 drive-strength = <6>;
3860 qup_spi19_data_clk: qup-spi19-data-clk-state {
3861 pins = "gpio72", "gpio73", "gpio74";
3863 drive-strength = <6>;
3867 qup_spi20_cs: qup-spi20-cs-state {
3872 qup_spi20_data_clk: qup-spi20-data-clk-state {
3873 pins = "gpio76", "gpio77", "gpio78";
3877 qup_spi21_cs: qup-spi21-cs-state {
3882 qup_spi21_data_clk: qup-spi21-data-clk-state {
3883 pins = "gpio80", "gpio81", "gpio82";
3887 qup_uart7_rx: qup-uart7-rx-state {
3890 drive-strength = <2>;
3894 qup_uart7_tx: qup-uart7-tx-state {
3897 drive-strength = <2>;
3901 qup_uart20_default: qup-uart20-default-state {
3902 pins = "gpio76", "gpio77", "gpio78", "gpio79";
3907 lpass_tlmm: pinctrl@3440000 {
3908 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
3909 reg = <0 0x03440000 0x0 0x20000>,
3910 <0 0x034d0000 0x0 0x10000>;
3913 gpio-ranges = <&lpass_tlmm 0 0 23>;
3915 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3916 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3917 clock-names = "core", "audio";
3919 tx_swr_active: tx-swr-active-state {
3922 function = "swr_tx_clk";
3923 drive-strength = <2>;
3929 pins = "gpio1", "gpio2", "gpio14";
3930 function = "swr_tx_data";
3931 drive-strength = <2>;
3937 rx_swr_active: rx-swr-active-state {
3940 function = "swr_rx_clk";
3941 drive-strength = <2>;
3947 pins = "gpio4", "gpio5";
3948 function = "swr_rx_data";
3949 drive-strength = <2>;
3955 dmic01_default: dmic01-default-state {
3958 function = "dmic1_clk";
3959 drive-strength = <8>;
3965 function = "dmic1_data";
3966 drive-strength = <8>;
3970 dmic23_default: dmic23-default-state {
3973 function = "dmic2_clk";
3974 drive-strength = <8>;
3980 function = "dmic2_data";
3981 drive-strength = <8>;
3985 wsa_swr_active: wsa-swr-active-state {
3988 function = "wsa_swr_clk";
3989 drive-strength = <2>;
3996 function = "wsa_swr_data";
3997 drive-strength = <2>;
4003 wsa2_swr_active: wsa2-swr-active-state {
4006 function = "wsa2_swr_clk";
4007 drive-strength = <2>;
4014 function = "wsa2_swr_data";
4015 drive-strength = <2>;
4023 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4024 reg = <0 0x146aa000 0 0x1000>;
4025 ranges = <0 0 0x146aa000 0x1000>;
4027 #address-cells = <1>;
4031 compatible = "qcom,pil-reloc-info";
4036 apps_smmu: iommu@15000000 {
4037 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4038 reg = <0 0x15000000 0 0x100000>;
4040 #global-interrupts = <1>;
4041 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4042 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4043 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4044 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4045 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4046 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4047 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4048 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4049 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4050 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4051 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4052 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4053 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4054 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4055 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4056 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4057 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4058 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4059 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4060 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4061 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4062 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4063 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4064 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4065 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4066 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4067 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4068 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4069 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4070 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4071 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4072 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4073 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4074 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4075 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4076 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4077 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4078 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4079 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4080 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4081 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4082 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4083 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4084 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4085 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4086 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4087 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4088 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4089 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4090 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4091 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4092 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4093 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4094 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4095 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4096 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4097 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4098 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4099 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4100 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4101 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4102 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4103 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4104 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4105 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4106 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4107 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4108 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4109 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4110 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4111 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4112 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4113 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4114 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4115 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4116 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4117 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4118 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4119 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4120 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4121 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4122 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4123 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4124 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4125 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4126 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4127 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4128 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4129 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4130 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4131 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4132 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4133 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4134 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4135 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4136 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4137 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4140 intc: interrupt-controller@17100000 {
4141 compatible = "arm,gic-v3";
4142 #interrupt-cells = <3>;
4143 interrupt-controller;
4144 #redistributor-regions = <1>;
4145 redistributor-stride = <0x0 0x40000>;
4146 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4147 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4148 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4149 #address-cells = <2>;
4153 gic_its: msi-controller@17140000 {
4154 compatible = "arm,gic-v3-its";
4155 reg = <0x0 0x17140000 0x0 0x20000>;
4162 compatible = "arm,armv7-timer-mem";
4163 #address-cells = <1>;
4165 ranges = <0 0 0 0x20000000>;
4166 reg = <0x0 0x17420000 0x0 0x1000>;
4167 clock-frequency = <19200000>;
4171 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4172 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4173 reg = <0x17421000 0x1000>,
4174 <0x17422000 0x1000>;
4179 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4180 reg = <0x17423000 0x1000>;
4181 status = "disabled";
4186 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4187 reg = <0x17425000 0x1000>;
4188 status = "disabled";
4193 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4194 reg = <0x17427000 0x1000>;
4195 status = "disabled";
4200 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4201 reg = <0x17429000 0x1000>;
4202 status = "disabled";
4207 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4208 reg = <0x1742b000 0x1000>;
4209 status = "disabled";
4214 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4215 reg = <0x1742d000 0x1000>;
4216 status = "disabled";
4220 apps_rsc: rsc@17a00000 {
4222 compatible = "qcom,rpmh-rsc";
4223 reg = <0x0 0x17a00000 0x0 0x10000>,
4224 <0x0 0x17a10000 0x0 0x10000>,
4225 <0x0 0x17a20000 0x0 0x10000>,
4226 <0x0 0x17a30000 0x0 0x10000>;
4227 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4228 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4231 qcom,tcs-offset = <0xd00>;
4233 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4234 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4235 power-domains = <&CLUSTER_PD>;
4237 apps_bcm_voter: bcm-voter {
4238 compatible = "qcom,bcm-voter";
4241 rpmhcc: clock-controller {
4242 compatible = "qcom,sm8450-rpmh-clk";
4245 clocks = <&xo_board>;
4248 rpmhpd: power-controller {
4249 compatible = "qcom,sm8450-rpmhpd";
4250 #power-domain-cells = <1>;
4251 operating-points-v2 = <&rpmhpd_opp_table>;
4253 rpmhpd_opp_table: opp-table {
4254 compatible = "operating-points-v2";
4256 rpmhpd_opp_ret: opp1 {
4257 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4260 rpmhpd_opp_min_svs: opp2 {
4261 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4264 rpmhpd_opp_low_svs_d1: opp3 {
4265 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4268 rpmhpd_opp_low_svs: opp4 {
4269 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4272 rpmhpd_opp_low_svs_l1: opp5 {
4273 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4276 rpmhpd_opp_svs: opp6 {
4277 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4280 rpmhpd_opp_svs_l0: opp7 {
4281 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4284 rpmhpd_opp_svs_l1: opp8 {
4285 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4288 rpmhpd_opp_svs_l2: opp9 {
4289 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4292 rpmhpd_opp_nom: opp10 {
4293 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4296 rpmhpd_opp_nom_l1: opp11 {
4297 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4300 rpmhpd_opp_nom_l2: opp12 {
4301 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4304 rpmhpd_opp_turbo: opp13 {
4305 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4308 rpmhpd_opp_turbo_l1: opp14 {
4309 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4315 cpufreq_hw: cpufreq@17d91000 {
4316 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4317 reg = <0 0x17d91000 0 0x1000>,
4318 <0 0x17d92000 0 0x1000>,
4319 <0 0x17d93000 0 0x1000>;
4320 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4321 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4322 clock-names = "xo", "alternate";
4323 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4324 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4325 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4326 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4327 #freq-domain-cells = <1>;
4331 gem_noc: interconnect@19100000 {
4332 compatible = "qcom,sm8450-gem-noc";
4333 reg = <0 0x19100000 0 0xbb800>;
4334 #interconnect-cells = <2>;
4335 qcom,bcm-voters = <&apps_bcm_voter>;
4338 system-cache-controller@19200000 {
4339 compatible = "qcom,sm8450-llcc";
4340 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4341 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4342 <0 0x19a00000 0 0x80000>;
4343 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4344 "llcc3_base", "llcc_broadcast_base";
4345 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4348 ufs_mem_hc: ufshc@1d84000 {
4349 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4351 reg = <0 0x01d84000 0 0x3000>;
4352 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4353 phys = <&ufs_mem_phy>;
4354 phy-names = "ufsphy";
4355 lanes-per-direction = <2>;
4357 resets = <&gcc GCC_UFS_PHY_BCR>;
4358 reset-names = "rst";
4360 power-domains = <&gcc UFS_PHY_GDSC>;
4362 iommus = <&apps_smmu 0xe0 0x0>;
4365 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4366 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4367 interconnect-names = "ufs-ddr", "cpu-ufs";
4374 "tx_lane0_sync_clk",
4375 "rx_lane0_sync_clk",
4376 "rx_lane1_sync_clk";
4378 <&gcc GCC_UFS_PHY_AXI_CLK>,
4379 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4380 <&gcc GCC_UFS_PHY_AHB_CLK>,
4381 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4382 <&rpmhcc RPMH_CXO_CLK>,
4383 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4384 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4385 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4387 <75000000 300000000>,
4390 <75000000 300000000>,
4391 <75000000 300000000>,
4397 status = "disabled";
4400 ufs_mem_phy: phy@1d87000 {
4401 compatible = "qcom,sm8450-qmp-ufs-phy";
4402 reg = <0 0x01d87000 0 0x1000>;
4404 clock-names = "ref", "ref_aux", "qref";
4405 clocks = <&rpmhcc RPMH_CXO_CLK>,
4406 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4407 <&gcc GCC_UFS_0_CLKREF_EN>;
4409 resets = <&ufs_mem_hc 0>;
4410 reset-names = "ufsphy";
4415 status = "disabled";
4418 ice: crypto@1d88000 {
4419 compatible = "qcom,sm8450-inline-crypto-engine",
4420 "qcom,inline-crypto-engine";
4421 reg = <0 0x01d88000 0 0x8000>;
4422 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4425 cryptobam: dma-controller@1dc4000 {
4426 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4427 reg = <0 0x01dc4000 0 0x28000>;
4428 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4431 qcom,controlled-remotely;
4432 iommus = <&apps_smmu 0x584 0x11>,
4433 <&apps_smmu 0x588 0x0>,
4434 <&apps_smmu 0x598 0x5>,
4435 <&apps_smmu 0x59a 0x0>,
4436 <&apps_smmu 0x59f 0x0>;
4439 crypto: crypto@1dfa000 {
4440 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4441 reg = <0 0x01dfa000 0 0x6000>;
4442 dmas = <&cryptobam 4>, <&cryptobam 5>;
4443 dma-names = "rx", "tx";
4444 iommus = <&apps_smmu 0x584 0x11>,
4445 <&apps_smmu 0x588 0x0>,
4446 <&apps_smmu 0x598 0x5>,
4447 <&apps_smmu 0x59a 0x0>,
4448 <&apps_smmu 0x59f 0x0>;
4449 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4450 interconnect-names = "memory";
4453 sdhc_2: mmc@8804000 {
4454 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4455 reg = <0 0x08804000 0 0x1000>;
4457 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4458 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4459 interrupt-names = "hc_irq", "pwr_irq";
4461 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4462 <&gcc GCC_SDCC2_APPS_CLK>,
4463 <&rpmhcc RPMH_CXO_CLK>;
4464 clock-names = "iface", "core", "xo";
4465 resets = <&gcc GCC_SDCC2_BCR>;
4466 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4467 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4468 interconnect-names = "sdhc-ddr","cpu-sdhc";
4469 iommus = <&apps_smmu 0x4a0 0x0>;
4470 power-domains = <&rpmhpd RPMHPD_CX>;
4471 operating-points-v2 = <&sdhc2_opp_table>;
4475 /* Forbid SDR104/SDR50 - broken hw! */
4476 sdhci-caps-mask = <0x3 0x0>;
4478 status = "disabled";
4480 sdhc2_opp_table: opp-table {
4481 compatible = "operating-points-v2";
4484 opp-hz = /bits/ 64 <100000000>;
4485 required-opps = <&rpmhpd_opp_low_svs>;
4489 opp-hz = /bits/ 64 <202000000>;
4490 required-opps = <&rpmhpd_opp_svs_l1>;
4495 usb_1: usb@a6f8800 {
4496 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4497 reg = <0 0x0a6f8800 0 0x400>;
4498 status = "disabled";
4499 #address-cells = <2>;
4503 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4504 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4505 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4506 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4507 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4508 <&gcc GCC_USB3_0_CLKREF_EN>;
4509 clock-names = "cfg_noc",
4516 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4517 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4518 assigned-clock-rates = <19200000>, <200000000>;
4520 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4521 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4522 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4523 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4524 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-names = "pwr_event",
4531 power-domains = <&gcc USB30_PRIM_GDSC>;
4533 resets = <&gcc GCC_USB30_PRIM_BCR>;
4535 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4536 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4537 interconnect-names = "usb-ddr", "apps-usb";
4539 usb_1_dwc3: usb@a600000 {
4540 compatible = "snps,dwc3";
4541 reg = <0 0x0a600000 0 0xcd00>;
4542 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4543 iommus = <&apps_smmu 0x0 0x0>;
4544 snps,dis_u2_susphy_quirk;
4545 snps,dis_enblslpm_quirk;
4546 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4547 phy-names = "usb2-phy", "usb3-phy";
4550 #address-cells = <1>;
4556 usb_1_dwc3_hs: endpoint {
4563 usb_1_dwc3_ss: endpoint {
4570 nsp_noc: interconnect@320c0000 {
4571 compatible = "qcom,sm8450-nsp-noc";
4572 reg = <0 0x320c0000 0 0x10000>;
4573 #interconnect-cells = <2>;
4574 qcom,bcm-voters = <&apps_bcm_voter>;
4577 lpass_ag_noc: interconnect@3c40000 {
4578 compatible = "qcom,sm8450-lpass-ag-noc";
4579 reg = <0 0x03c40000 0 0x17200>;
4580 #interconnect-cells = <2>;
4581 qcom,bcm-voters = <&apps_bcm_voter>;
4590 polling-delay-passive = <0>;
4591 polling-delay = <0>;
4592 thermal-sensors = <&tsens0 0>;
4595 thermal-engine-config {
4596 temperature = <125000>;
4597 hysteresis = <1000>;
4602 temperature = <115000>;
4603 hysteresis = <5000>;
4610 polling-delay-passive = <0>;
4611 polling-delay = <0>;
4612 thermal-sensors = <&tsens0 1>;
4615 thermal-engine-config {
4616 temperature = <125000>;
4617 hysteresis = <1000>;
4622 temperature = <115000>;
4623 hysteresis = <5000>;
4630 polling-delay-passive = <0>;
4631 polling-delay = <0>;
4632 thermal-sensors = <&tsens0 2>;
4635 thermal-engine-config {
4636 temperature = <125000>;
4637 hysteresis = <1000>;
4642 temperature = <115000>;
4643 hysteresis = <5000>;
4650 polling-delay-passive = <0>;
4651 polling-delay = <0>;
4652 thermal-sensors = <&tsens0 3>;
4655 thermal-engine-config {
4656 temperature = <125000>;
4657 hysteresis = <1000>;
4662 temperature = <115000>;
4663 hysteresis = <5000>;
4670 polling-delay-passive = <0>;
4671 polling-delay = <0>;
4672 thermal-sensors = <&tsens0 4>;
4675 thermal-engine-config {
4676 temperature = <125000>;
4677 hysteresis = <1000>;
4682 temperature = <115000>;
4683 hysteresis = <5000>;
4690 polling-delay-passive = <0>;
4691 polling-delay = <0>;
4692 thermal-sensors = <&tsens0 5>;
4695 cpu4_top_alert0: trip-point0 {
4696 temperature = <90000>;
4697 hysteresis = <2000>;
4701 cpu4_top_alert1: trip-point1 {
4702 temperature = <95000>;
4703 hysteresis = <2000>;
4707 cpu4_top_crit: cpu-crit {
4708 temperature = <110000>;
4709 hysteresis = <1000>;
4715 cpu4-bottom-thermal {
4716 polling-delay-passive = <0>;
4717 polling-delay = <0>;
4718 thermal-sensors = <&tsens0 6>;
4721 cpu4_bottom_alert0: trip-point0 {
4722 temperature = <90000>;
4723 hysteresis = <2000>;
4727 cpu4_bottom_alert1: trip-point1 {
4728 temperature = <95000>;
4729 hysteresis = <2000>;
4733 cpu4_bottom_crit: cpu-crit {
4734 temperature = <110000>;
4735 hysteresis = <1000>;
4742 polling-delay-passive = <0>;
4743 polling-delay = <0>;
4744 thermal-sensors = <&tsens0 7>;
4747 cpu5_top_alert0: trip-point0 {
4748 temperature = <90000>;
4749 hysteresis = <2000>;
4753 cpu5_top_alert1: trip-point1 {
4754 temperature = <95000>;
4755 hysteresis = <2000>;
4759 cpu5_top_crit: cpu-crit {
4760 temperature = <110000>;
4761 hysteresis = <1000>;
4767 cpu5-bottom-thermal {
4768 polling-delay-passive = <0>;
4769 polling-delay = <0>;
4770 thermal-sensors = <&tsens0 8>;
4773 cpu5_bottom_alert0: trip-point0 {
4774 temperature = <90000>;
4775 hysteresis = <2000>;
4779 cpu5_bottom_alert1: trip-point1 {
4780 temperature = <95000>;
4781 hysteresis = <2000>;
4785 cpu5_bottom_crit: cpu-crit {
4786 temperature = <110000>;
4787 hysteresis = <1000>;
4794 polling-delay-passive = <0>;
4795 polling-delay = <0>;
4796 thermal-sensors = <&tsens0 9>;
4799 cpu6_top_alert0: trip-point0 {
4800 temperature = <90000>;
4801 hysteresis = <2000>;
4805 cpu6_top_alert1: trip-point1 {
4806 temperature = <95000>;
4807 hysteresis = <2000>;
4811 cpu6_top_crit: cpu-crit {
4812 temperature = <110000>;
4813 hysteresis = <1000>;
4819 cpu6-bottom-thermal {
4820 polling-delay-passive = <0>;
4821 polling-delay = <0>;
4822 thermal-sensors = <&tsens0 10>;
4825 cpu6_bottom_alert0: trip-point0 {
4826 temperature = <90000>;
4827 hysteresis = <2000>;
4831 cpu6_bottom_alert1: trip-point1 {
4832 temperature = <95000>;
4833 hysteresis = <2000>;
4837 cpu6_bottom_crit: cpu-crit {
4838 temperature = <110000>;
4839 hysteresis = <1000>;
4846 polling-delay-passive = <0>;
4847 polling-delay = <0>;
4848 thermal-sensors = <&tsens0 11>;
4851 cpu7_top_alert0: trip-point0 {
4852 temperature = <90000>;
4853 hysteresis = <2000>;
4857 cpu7_top_alert1: trip-point1 {
4858 temperature = <95000>;
4859 hysteresis = <2000>;
4863 cpu7_top_crit: cpu-crit {
4864 temperature = <110000>;
4865 hysteresis = <1000>;
4871 cpu7-middle-thermal {
4872 polling-delay-passive = <0>;
4873 polling-delay = <0>;
4874 thermal-sensors = <&tsens0 12>;
4877 cpu7_middle_alert0: trip-point0 {
4878 temperature = <90000>;
4879 hysteresis = <2000>;
4883 cpu7_middle_alert1: trip-point1 {
4884 temperature = <95000>;
4885 hysteresis = <2000>;
4889 cpu7_middle_crit: cpu-crit {
4890 temperature = <110000>;
4891 hysteresis = <1000>;
4897 cpu7-bottom-thermal {
4898 polling-delay-passive = <0>;
4899 polling-delay = <0>;
4900 thermal-sensors = <&tsens0 13>;
4903 cpu7_bottom_alert0: trip-point0 {
4904 temperature = <90000>;
4905 hysteresis = <2000>;
4909 cpu7_bottom_alert1: trip-point1 {
4910 temperature = <95000>;
4911 hysteresis = <2000>;
4915 cpu7_bottom_crit: cpu-crit {
4916 temperature = <110000>;
4917 hysteresis = <1000>;
4924 polling-delay-passive = <10>;
4925 polling-delay = <0>;
4926 thermal-sensors = <&tsens0 14>;
4930 trip = <&gpu_top_alert0>;
4931 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4936 thermal-engine-config {
4937 temperature = <125000>;
4938 hysteresis = <1000>;
4942 thermal-hal-config {
4943 temperature = <125000>;
4944 hysteresis = <1000>;
4949 temperature = <115000>;
4950 hysteresis = <5000>;
4954 gpu_top_alert0: trip-point0 {
4955 temperature = <95000>;
4956 hysteresis = <5000>;
4962 gpu-bottom-thermal {
4963 polling-delay-passive = <10>;
4964 polling-delay = <0>;
4965 thermal-sensors = <&tsens0 15>;
4969 trip = <&gpu_bottom_alert0>;
4970 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4975 thermal-engine-config {
4976 temperature = <125000>;
4977 hysteresis = <1000>;
4981 thermal-hal-config {
4982 temperature = <125000>;
4983 hysteresis = <1000>;
4988 temperature = <115000>;
4989 hysteresis = <5000>;
4993 gpu_bottom_alert0: trip-point0 {
4994 temperature = <95000>;
4995 hysteresis = <5000>;
5002 polling-delay-passive = <0>;
5003 polling-delay = <0>;
5004 thermal-sensors = <&tsens1 0>;
5007 thermal-engine-config {
5008 temperature = <125000>;
5009 hysteresis = <1000>;
5014 temperature = <115000>;
5015 hysteresis = <5000>;
5022 polling-delay-passive = <0>;
5023 polling-delay = <0>;
5024 thermal-sensors = <&tsens1 1>;
5027 cpu0_alert0: trip-point0 {
5028 temperature = <90000>;
5029 hysteresis = <2000>;
5033 cpu0_alert1: trip-point1 {
5034 temperature = <95000>;
5035 hysteresis = <2000>;
5039 cpu0_crit: cpu-crit {
5040 temperature = <110000>;
5041 hysteresis = <1000>;
5048 polling-delay-passive = <0>;
5049 polling-delay = <0>;
5050 thermal-sensors = <&tsens1 2>;
5053 cpu1_alert0: trip-point0 {
5054 temperature = <90000>;
5055 hysteresis = <2000>;
5059 cpu1_alert1: trip-point1 {
5060 temperature = <95000>;
5061 hysteresis = <2000>;
5065 cpu1_crit: cpu-crit {
5066 temperature = <110000>;
5067 hysteresis = <1000>;
5074 polling-delay-passive = <0>;
5075 polling-delay = <0>;
5076 thermal-sensors = <&tsens1 3>;
5079 cpu2_alert0: trip-point0 {
5080 temperature = <90000>;
5081 hysteresis = <2000>;
5085 cpu2_alert1: trip-point1 {
5086 temperature = <95000>;
5087 hysteresis = <2000>;
5091 cpu2_crit: cpu-crit {
5092 temperature = <110000>;
5093 hysteresis = <1000>;
5100 polling-delay-passive = <0>;
5101 polling-delay = <0>;
5102 thermal-sensors = <&tsens1 4>;
5105 cpu3_alert0: trip-point0 {
5106 temperature = <90000>;
5107 hysteresis = <2000>;
5111 cpu3_alert1: trip-point1 {
5112 temperature = <95000>;
5113 hysteresis = <2000>;
5117 cpu3_crit: cpu-crit {
5118 temperature = <110000>;
5119 hysteresis = <1000>;
5126 polling-delay-passive = <10>;
5127 polling-delay = <0>;
5128 thermal-sensors = <&tsens1 5>;
5131 thermal-engine-config {
5132 temperature = <125000>;
5133 hysteresis = <1000>;
5137 thermal-hal-config {
5138 temperature = <125000>;
5139 hysteresis = <1000>;
5144 temperature = <115000>;
5145 hysteresis = <5000>;
5149 cdsp_0_config: junction-config {
5150 temperature = <95000>;
5151 hysteresis = <5000>;
5158 polling-delay-passive = <10>;
5159 polling-delay = <0>;
5160 thermal-sensors = <&tsens1 6>;
5163 thermal-engine-config {
5164 temperature = <125000>;
5165 hysteresis = <1000>;
5169 thermal-hal-config {
5170 temperature = <125000>;
5171 hysteresis = <1000>;
5176 temperature = <115000>;
5177 hysteresis = <5000>;
5181 cdsp_1_config: junction-config {
5182 temperature = <95000>;
5183 hysteresis = <5000>;
5190 polling-delay-passive = <10>;
5191 polling-delay = <0>;
5192 thermal-sensors = <&tsens1 7>;
5195 thermal-engine-config {
5196 temperature = <125000>;
5197 hysteresis = <1000>;
5201 thermal-hal-config {
5202 temperature = <125000>;
5203 hysteresis = <1000>;
5208 temperature = <115000>;
5209 hysteresis = <5000>;
5213 cdsp_2_config: junction-config {
5214 temperature = <95000>;
5215 hysteresis = <5000>;
5222 polling-delay-passive = <0>;
5223 polling-delay = <0>;
5224 thermal-sensors = <&tsens1 8>;
5227 thermal-engine-config {
5228 temperature = <125000>;
5229 hysteresis = <1000>;
5234 temperature = <115000>;
5235 hysteresis = <5000>;
5242 polling-delay-passive = <10>;
5243 polling-delay = <0>;
5244 thermal-sensors = <&tsens1 9>;
5247 thermal-engine-config {
5248 temperature = <125000>;
5249 hysteresis = <1000>;
5253 ddr_config0: ddr0-config {
5254 temperature = <90000>;
5255 hysteresis = <5000>;
5260 temperature = <115000>;
5261 hysteresis = <5000>;
5268 polling-delay-passive = <0>;
5269 polling-delay = <0>;
5270 thermal-sensors = <&tsens1 10>;
5273 thermal-engine-config {
5274 temperature = <125000>;
5275 hysteresis = <1000>;
5279 mdmss0_config0: mdmss0-config0 {
5280 temperature = <102000>;
5281 hysteresis = <3000>;
5285 mdmss0_config1: mdmss0-config1 {
5286 temperature = <105000>;
5287 hysteresis = <3000>;
5292 temperature = <115000>;
5293 hysteresis = <5000>;
5300 polling-delay-passive = <0>;
5301 polling-delay = <0>;
5302 thermal-sensors = <&tsens1 11>;
5305 thermal-engine-config {
5306 temperature = <125000>;
5307 hysteresis = <1000>;
5311 mdmss1_config0: mdmss1-config0 {
5312 temperature = <102000>;
5313 hysteresis = <3000>;
5317 mdmss1_config1: mdmss1-config1 {
5318 temperature = <105000>;
5319 hysteresis = <3000>;
5324 temperature = <115000>;
5325 hysteresis = <5000>;
5332 polling-delay-passive = <0>;
5333 polling-delay = <0>;
5334 thermal-sensors = <&tsens1 12>;
5337 thermal-engine-config {
5338 temperature = <125000>;
5339 hysteresis = <1000>;
5343 mdmss2_config0: mdmss2-config0 {
5344 temperature = <102000>;
5345 hysteresis = <3000>;
5349 mdmss2_config1: mdmss2-config1 {
5350 temperature = <105000>;
5351 hysteresis = <3000>;
5356 temperature = <115000>;
5357 hysteresis = <5000>;
5364 polling-delay-passive = <0>;
5365 polling-delay = <0>;
5366 thermal-sensors = <&tsens1 13>;
5369 thermal-engine-config {
5370 temperature = <125000>;
5371 hysteresis = <1000>;
5375 mdmss3_config0: mdmss3-config0 {
5376 temperature = <102000>;
5377 hysteresis = <3000>;
5381 mdmss3_config1: mdmss3-config1 {
5382 temperature = <105000>;
5383 hysteresis = <3000>;
5388 temperature = <115000>;
5389 hysteresis = <5000>;
5396 polling-delay-passive = <0>;
5397 polling-delay = <0>;
5398 thermal-sensors = <&tsens1 14>;
5401 thermal-engine-config {
5402 temperature = <125000>;
5403 hysteresis = <1000>;
5408 temperature = <115000>;
5409 hysteresis = <5000>;
5416 polling-delay-passive = <0>;
5417 polling-delay = <0>;
5418 thermal-sensors = <&tsens1 15>;
5421 thermal-engine-config {
5422 temperature = <125000>;
5423 hysteresis = <1000>;
5428 temperature = <115000>;
5429 hysteresis = <5000>;
5437 compatible = "arm,armv8-timer";
5438 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5439 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5440 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5441 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5442 clock-frequency = <19200000>;