1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2021, Linaro Limited
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/phy/phy-qcom-qmp.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/interconnect/qcom,icc.h>
21 #include <dt-bindings/interconnect/qcom,sm8450.h>
22 #include <dt-bindings/reset/qcom,sm8450-gpucc.h>
23 #include <dt-bindings/soc/qcom,gpr.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26 #include <dt-bindings/thermal/thermal.h>
29 interrupt-parent = <&intc>;
38 compatible = "fixed-clock";
40 clock-frequency = <76800000>;
43 sleep_clk: sleep-clk {
44 compatible = "fixed-clock";
46 clock-frequency = <32000>;
56 compatible = "qcom,kryo780";
58 enable-method = "psci";
59 next-level-cache = <&L2_0>;
60 power-domains = <&CPU_PD0>;
61 power-domain-names = "psci";
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
69 next-level-cache = <&L3_0>;
80 compatible = "qcom,kryo780";
82 enable-method = "psci";
83 next-level-cache = <&L2_100>;
84 power-domains = <&CPU_PD1>;
85 power-domain-names = "psci";
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
93 next-level-cache = <&L3_0>;
99 compatible = "qcom,kryo780";
101 enable-method = "psci";
102 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_PD2>;
104 power-domain-names = "psci";
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 #cooling-cells = <2>;
107 clocks = <&cpufreq_hw 0>;
109 compatible = "cache";
112 next-level-cache = <&L3_0>;
118 compatible = "qcom,kryo780";
120 enable-method = "psci";
121 next-level-cache = <&L2_300>;
122 power-domains = <&CPU_PD3>;
123 power-domain-names = "psci";
124 qcom,freq-domain = <&cpufreq_hw 0>;
125 #cooling-cells = <2>;
126 clocks = <&cpufreq_hw 0>;
128 compatible = "cache";
131 next-level-cache = <&L3_0>;
137 compatible = "qcom,kryo780";
139 enable-method = "psci";
140 next-level-cache = <&L2_400>;
141 power-domains = <&CPU_PD4>;
142 power-domain-names = "psci";
143 qcom,freq-domain = <&cpufreq_hw 1>;
144 #cooling-cells = <2>;
145 clocks = <&cpufreq_hw 1>;
147 compatible = "cache";
150 next-level-cache = <&L3_0>;
156 compatible = "qcom,kryo780";
158 enable-method = "psci";
159 next-level-cache = <&L2_500>;
160 power-domains = <&CPU_PD5>;
161 power-domain-names = "psci";
162 qcom,freq-domain = <&cpufreq_hw 1>;
163 #cooling-cells = <2>;
164 clocks = <&cpufreq_hw 1>;
166 compatible = "cache";
169 next-level-cache = <&L3_0>;
175 compatible = "qcom,kryo780";
177 enable-method = "psci";
178 next-level-cache = <&L2_600>;
179 power-domains = <&CPU_PD6>;
180 power-domain-names = "psci";
181 qcom,freq-domain = <&cpufreq_hw 1>;
182 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw 1>;
185 compatible = "cache";
188 next-level-cache = <&L3_0>;
194 compatible = "qcom,kryo780";
196 enable-method = "psci";
197 next-level-cache = <&L2_700>;
198 power-domains = <&CPU_PD7>;
199 power-domain-names = "psci";
200 qcom,freq-domain = <&cpufreq_hw 2>;
201 #cooling-cells = <2>;
202 clocks = <&cpufreq_hw 2>;
204 compatible = "cache";
207 next-level-cache = <&L3_0>;
248 entry-method = "psci";
250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251 compatible = "arm,idle-state";
252 idle-state-name = "silver-rail-power-collapse";
253 arm,psci-suspend-param = <0x40000004>;
254 entry-latency-us = <800>;
255 exit-latency-us = <750>;
256 min-residency-us = <4090>;
260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261 compatible = "arm,idle-state";
262 idle-state-name = "gold-rail-power-collapse";
263 arm,psci-suspend-param = <0x40000004>;
264 entry-latency-us = <600>;
265 exit-latency-us = <1550>;
266 min-residency-us = <4791>;
272 CLUSTER_SLEEP_0: cluster-sleep-0 {
273 compatible = "domain-idle-state";
274 arm,psci-suspend-param = <0x41000044>;
275 entry-latency-us = <1050>;
276 exit-latency-us = <2500>;
277 min-residency-us = <5309>;
280 CLUSTER_SLEEP_1: cluster-sleep-1 {
281 compatible = "domain-idle-state";
282 arm,psci-suspend-param = <0x4100c344>;
283 entry-latency-us = <2700>;
284 exit-latency-us = <3500>;
285 min-residency-us = <13959>;
292 compatible = "qcom,scm-sm8450", "qcom,scm";
293 qcom,dload-mode = <&tcsr 0x13000>;
294 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
299 clk_virt: interconnect-0 {
300 compatible = "qcom,sm8450-clk-virt";
301 #interconnect-cells = <2>;
302 qcom,bcm-voters = <&apps_bcm_voter>;
305 mc_virt: interconnect-1 {
306 compatible = "qcom,sm8450-mc-virt";
307 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_voter>;
312 device_type = "memory";
313 /* We expect the bootloader to fill in the size */
314 reg = <0x0 0xa0000000 0x0 0x0>;
318 compatible = "arm,armv8-pmuv3";
319 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
323 compatible = "arm,psci-1.0";
326 CPU_PD0: power-domain-cpu0 {
327 #power-domain-cells = <0>;
328 power-domains = <&CLUSTER_PD>;
329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
332 CPU_PD1: power-domain-cpu1 {
333 #power-domain-cells = <0>;
334 power-domains = <&CLUSTER_PD>;
335 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
338 CPU_PD2: power-domain-cpu2 {
339 #power-domain-cells = <0>;
340 power-domains = <&CLUSTER_PD>;
341 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
344 CPU_PD3: power-domain-cpu3 {
345 #power-domain-cells = <0>;
346 power-domains = <&CLUSTER_PD>;
347 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
350 CPU_PD4: power-domain-cpu4 {
351 #power-domain-cells = <0>;
352 power-domains = <&CLUSTER_PD>;
353 domain-idle-states = <&BIG_CPU_SLEEP_0>;
356 CPU_PD5: power-domain-cpu5 {
357 #power-domain-cells = <0>;
358 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = <&BIG_CPU_SLEEP_0>;
362 CPU_PD6: power-domain-cpu6 {
363 #power-domain-cells = <0>;
364 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = <&BIG_CPU_SLEEP_0>;
368 CPU_PD7: power-domain-cpu7 {
369 #power-domain-cells = <0>;
370 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = <&BIG_CPU_SLEEP_0>;
374 CLUSTER_PD: power-domain-cpu-cluster0 {
375 #power-domain-cells = <0>;
376 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
380 qup_opp_table_100mhz: opp-table-qup {
381 compatible = "operating-points-v2";
384 opp-hz = /bits/ 64 <50000000>;
385 required-opps = <&rpmhpd_opp_min_svs>;
389 opp-hz = /bits/ 64 <75000000>;
390 required-opps = <&rpmhpd_opp_low_svs>;
394 opp-hz = /bits/ 64 <100000000>;
395 required-opps = <&rpmhpd_opp_svs>;
399 reserved_memory: reserved-memory {
400 #address-cells = <2>;
404 hyp_mem: memory@80000000 {
405 reg = <0x0 0x80000000 0x0 0x600000>;
409 xbl_dt_log_mem: memory@80600000 {
410 reg = <0x0 0x80600000 0x0 0x40000>;
414 xbl_ramdump_mem: memory@80640000 {
415 reg = <0x0 0x80640000 0x0 0x180000>;
419 xbl_sc_mem: memory@807c0000 {
420 reg = <0x0 0x807c0000 0x0 0x40000>;
424 aop_image_mem: memory@80800000 {
425 reg = <0x0 0x80800000 0x0 0x60000>;
429 aop_cmd_db_mem: memory@80860000 {
430 compatible = "qcom,cmd-db";
431 reg = <0x0 0x80860000 0x0 0x20000>;
435 aop_config_mem: memory@80880000 {
436 reg = <0x0 0x80880000 0x0 0x20000>;
440 tme_crash_dump_mem: memory@808a0000 {
441 reg = <0x0 0x808a0000 0x0 0x40000>;
445 tme_log_mem: memory@808e0000 {
446 reg = <0x0 0x808e0000 0x0 0x4000>;
450 uefi_log_mem: memory@808e4000 {
451 reg = <0x0 0x808e4000 0x0 0x10000>;
455 /* secdata region can be reused by apps */
456 smem: memory@80900000 {
457 compatible = "qcom,smem";
458 reg = <0x0 0x80900000 0x0 0x200000>;
459 hwlocks = <&tcsr_mutex 3>;
463 cpucp_fw_mem: memory@80b00000 {
464 reg = <0x0 0x80b00000 0x0 0x100000>;
468 cdsp_secure_heap: memory@80c00000 {
469 reg = <0x0 0x80c00000 0x0 0x4600000>;
473 video_mem: memory@85700000 {
474 reg = <0x0 0x85700000 0x0 0x700000>;
478 adsp_mem: memory@85e00000 {
479 reg = <0x0 0x85e00000 0x0 0x2100000>;
483 slpi_mem: memory@88000000 {
484 reg = <0x0 0x88000000 0x0 0x1900000>;
488 cdsp_mem: memory@89900000 {
489 reg = <0x0 0x89900000 0x0 0x2000000>;
493 ipa_fw_mem: memory@8b900000 {
494 reg = <0x0 0x8b900000 0x0 0x10000>;
498 ipa_gsi_mem: memory@8b910000 {
499 reg = <0x0 0x8b910000 0x0 0xa000>;
503 gpu_micro_code_mem: memory@8b91a000 {
504 reg = <0x0 0x8b91a000 0x0 0x2000>;
508 spss_region_mem: memory@8ba00000 {
509 reg = <0x0 0x8ba00000 0x0 0x180000>;
513 /* First part of the "SPU secure shared memory" region */
514 spu_tz_shared_mem: memory@8bb80000 {
515 reg = <0x0 0x8bb80000 0x0 0x60000>;
519 /* Second part of the "SPU secure shared memory" region */
520 spu_modem_shared_mem: memory@8bbe0000 {
521 reg = <0x0 0x8bbe0000 0x0 0x20000>;
525 mpss_mem: memory@8bc00000 {
526 reg = <0x0 0x8bc00000 0x0 0x13200000>;
530 cvp_mem: memory@9ee00000 {
531 reg = <0x0 0x9ee00000 0x0 0x700000>;
535 camera_mem: memory@9f500000 {
536 reg = <0x0 0x9f500000 0x0 0x800000>;
540 rmtfs_mem: memory@9fd00000 {
541 compatible = "qcom,rmtfs-mem";
542 reg = <0x0 0x9fd00000 0x0 0x280000>;
545 qcom,client-id = <1>;
546 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
549 xbl_sc_mem2: memory@a6e00000 {
550 reg = <0x0 0xa6e00000 0x0 0x40000>;
554 global_sync_mem: memory@a6f00000 {
555 reg = <0x0 0xa6f00000 0x0 0x100000>;
559 /* uefi region can be reused by APPS */
561 /* Linux kernel image is loaded at 0xa0000000 */
563 oem_vm_mem: memory@bb000000 {
564 reg = <0x0 0xbb000000 0x0 0x5000000>;
568 mte_mem: memory@c0000000 {
569 reg = <0x0 0xc0000000 0x0 0x20000000>;
573 qheebsp_reserved_mem: memory@e0000000 {
574 reg = <0x0 0xe0000000 0x0 0x600000>;
578 cpusys_vm_mem: memory@e0600000 {
579 reg = <0x0 0xe0600000 0x0 0x400000>;
583 hyp_reserved_mem: memory@e0a00000 {
584 reg = <0x0 0xe0a00000 0x0 0x100000>;
588 trust_ui_vm_mem: memory@e0b00000 {
589 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
593 trust_ui_vm_qrtr: memory@e55f3000 {
594 reg = <0x0 0xe55f3000 0x0 0x9000>;
598 trust_ui_vm_vblk0_ring: memory@e55fc000 {
599 reg = <0x0 0xe55fc000 0x0 0x4000>;
603 trust_ui_vm_swiotlb: memory@e5600000 {
604 reg = <0x0 0xe5600000 0x0 0x100000>;
608 tz_stat_mem: memory@e8800000 {
609 reg = <0x0 0xe8800000 0x0 0x100000>;
613 tags_mem: memory@e8900000 {
614 reg = <0x0 0xe8900000 0x0 0x1200000>;
618 qtee_mem: memory@e9b00000 {
619 reg = <0x0 0xe9b00000 0x0 0x500000>;
623 trusted_apps_mem: memory@ea000000 {
624 reg = <0x0 0xea000000 0x0 0x3900000>;
628 trusted_apps_ext_mem: memory@ed900000 {
629 reg = <0x0 0xed900000 0x0 0x3b00000>;
635 compatible = "qcom,smp2p";
636 qcom,smem = <443>, <429>;
637 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638 IPCC_MPROC_SIGNAL_SMP2P
639 IRQ_TYPE_EDGE_RISING>;
640 mboxes = <&ipcc IPCC_CLIENT_LPASS
641 IPCC_MPROC_SIGNAL_SMP2P>;
643 qcom,local-pid = <0>;
644 qcom,remote-pid = <2>;
646 smp2p_adsp_out: master-kernel {
647 qcom,entry-name = "master-kernel";
648 #qcom,smem-state-cells = <1>;
651 smp2p_adsp_in: slave-kernel {
652 qcom,entry-name = "slave-kernel";
653 interrupt-controller;
654 #interrupt-cells = <2>;
659 compatible = "qcom,smp2p";
660 qcom,smem = <94>, <432>;
661 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662 IPCC_MPROC_SIGNAL_SMP2P
663 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&ipcc IPCC_CLIENT_CDSP
665 IPCC_MPROC_SIGNAL_SMP2P>;
667 qcom,local-pid = <0>;
668 qcom,remote-pid = <5>;
670 smp2p_cdsp_out: master-kernel {
671 qcom,entry-name = "master-kernel";
672 #qcom,smem-state-cells = <1>;
675 smp2p_cdsp_in: slave-kernel {
676 qcom,entry-name = "slave-kernel";
677 interrupt-controller;
678 #interrupt-cells = <2>;
683 compatible = "qcom,smp2p";
684 qcom,smem = <435>, <428>;
685 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686 IPCC_MPROC_SIGNAL_SMP2P
687 IRQ_TYPE_EDGE_RISING>;
688 mboxes = <&ipcc IPCC_CLIENT_MPSS
689 IPCC_MPROC_SIGNAL_SMP2P>;
691 qcom,local-pid = <0>;
692 qcom,remote-pid = <1>;
694 smp2p_modem_out: master-kernel {
695 qcom,entry-name = "master-kernel";
696 #qcom,smem-state-cells = <1>;
699 smp2p_modem_in: slave-kernel {
700 qcom,entry-name = "slave-kernel";
701 interrupt-controller;
702 #interrupt-cells = <2>;
705 ipa_smp2p_out: ipa-ap-to-modem {
706 qcom,entry-name = "ipa";
707 #qcom,smem-state-cells = <1>;
710 ipa_smp2p_in: ipa-modem-to-ap {
711 qcom,entry-name = "ipa";
712 interrupt-controller;
713 #interrupt-cells = <2>;
718 compatible = "qcom,smp2p";
719 qcom,smem = <481>, <430>;
720 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721 IPCC_MPROC_SIGNAL_SMP2P
722 IRQ_TYPE_EDGE_RISING>;
723 mboxes = <&ipcc IPCC_CLIENT_SLPI
724 IPCC_MPROC_SIGNAL_SMP2P>;
726 qcom,local-pid = <0>;
727 qcom,remote-pid = <3>;
729 smp2p_slpi_out: master-kernel {
730 qcom,entry-name = "master-kernel";
731 #qcom,smem-state-cells = <1>;
734 smp2p_slpi_in: slave-kernel {
735 qcom,entry-name = "slave-kernel";
736 interrupt-controller;
737 #interrupt-cells = <2>;
742 #address-cells = <2>;
744 ranges = <0 0 0 0 0x10 0>;
745 dma-ranges = <0 0 0 0 0x10 0>;
746 compatible = "simple-bus";
748 gcc: clock-controller@100000 {
749 compatible = "qcom,gcc-sm8450";
750 reg = <0x0 0x00100000 0x0 0x1f4200>;
753 #power-domain-cells = <1>;
754 clocks = <&rpmhcc RPMH_CXO_CLK>,
762 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
763 clock-names = "bi_tcxo",
767 "pcie_1_phy_aux_clk",
768 "ufs_phy_rx_symbol_0_clk",
769 "ufs_phy_rx_symbol_1_clk",
770 "ufs_phy_tx_symbol_0_clk",
771 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
774 gpi_dma2: dma-controller@800000 {
775 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
777 reg = <0 0x00800000 0 0x60000>;
778 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
791 dma-channel-mask = <0x7e>;
792 iommus = <&apps_smmu 0x496 0x0>;
796 qupv3_id_2: geniqup@8c0000 {
797 compatible = "qcom,geni-se-qup";
798 reg = <0x0 0x008c0000 0x0 0x2000>;
799 clock-names = "m-ahb", "s-ahb";
800 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802 iommus = <&apps_smmu 0x483 0x0>;
803 #address-cells = <2>;
809 compatible = "qcom,geni-i2c";
810 reg = <0x0 0x00880000 0x0 0x4000>;
812 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813 pinctrl-names = "default";
814 pinctrl-0 = <&qup_i2c15_data_clk>;
815 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells = <1>;
818 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821 interconnect-names = "qup-core", "qup-config", "qup-memory";
822 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824 dma-names = "tx", "rx";
829 compatible = "qcom,geni-spi";
830 reg = <0x0 0x00880000 0x0 0x4000>;
832 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834 pinctrl-names = "default";
835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838 interconnect-names = "qup-core", "qup-config";
839 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841 dma-names = "tx", "rx";
842 #address-cells = <1>;
848 compatible = "qcom,geni-i2c";
849 reg = <0x0 0x00884000 0x0 0x4000>;
851 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852 pinctrl-names = "default";
853 pinctrl-0 = <&qup_i2c16_data_clk>;
854 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855 #address-cells = <1>;
857 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863 dma-names = "tx", "rx";
868 compatible = "qcom,geni-spi";
869 reg = <0x0 0x00884000 0x0 0x4000>;
871 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873 pinctrl-names = "default";
874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877 interconnect-names = "qup-core", "qup-config";
878 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880 dma-names = "tx", "rx";
881 #address-cells = <1>;
887 compatible = "qcom,geni-i2c";
888 reg = <0x0 0x00888000 0x0 0x4000>;
890 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891 pinctrl-names = "default";
892 pinctrl-0 = <&qup_i2c17_data_clk>;
893 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894 #address-cells = <1>;
896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899 interconnect-names = "qup-core", "qup-config", "qup-memory";
900 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902 dma-names = "tx", "rx";
907 compatible = "qcom,geni-spi";
908 reg = <0x0 0x00888000 0x0 0x4000>;
910 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916 interconnect-names = "qup-core", "qup-config";
917 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919 dma-names = "tx", "rx";
920 #address-cells = <1>;
926 compatible = "qcom,geni-i2c";
927 reg = <0x0 0x0088c000 0x0 0x4000>;
929 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930 pinctrl-names = "default";
931 pinctrl-0 = <&qup_i2c18_data_clk>;
932 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933 #address-cells = <1>;
935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938 interconnect-names = "qup-core", "qup-config", "qup-memory";
939 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941 dma-names = "tx", "rx";
946 compatible = "qcom,geni-spi";
947 reg = <0 0x0088c000 0 0x4000>;
949 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-names = "default";
952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955 interconnect-names = "qup-core", "qup-config";
956 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958 dma-names = "tx", "rx";
959 #address-cells = <1>;
965 compatible = "qcom,geni-i2c";
966 reg = <0x0 0x00890000 0x0 0x4000>;
968 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969 pinctrl-names = "default";
970 pinctrl-0 = <&qup_i2c19_data_clk>;
971 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972 #address-cells = <1>;
974 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977 interconnect-names = "qup-core", "qup-config", "qup-memory";
978 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980 dma-names = "tx", "rx";
985 compatible = "qcom,geni-spi";
986 reg = <0 0x00890000 0 0x4000>;
988 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names = "default";
991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994 interconnect-names = "qup-core", "qup-config";
995 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997 dma-names = "tx", "rx";
998 #address-cells = <1>;
1000 status = "disabled";
1004 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x00894000 0x0 0x4000>;
1007 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008 pinctrl-names = "default";
1009 pinctrl-0 = <&qup_i2c20_data_clk>;
1010 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cells = <1>;
1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019 dma-names = "tx", "rx";
1020 status = "disabled";
1023 uart20: serial@894000 {
1024 compatible = "qcom,geni-uart";
1025 reg = <0 0x00894000 0 0x4000>;
1027 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_uart20_default>;
1030 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1032 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1033 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1034 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1035 interconnect-names = "qup-core",
1037 status = "disabled";
1041 compatible = "qcom,geni-spi";
1042 reg = <0 0x00894000 0 0x4000>;
1044 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050 interconnect-names = "qup-core", "qup-config";
1051 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053 dma-names = "tx", "rx";
1054 #address-cells = <1>;
1056 status = "disabled";
1060 compatible = "qcom,geni-i2c";
1061 reg = <0x0 0x00898000 0x0 0x4000>;
1063 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064 pinctrl-names = "default";
1065 pinctrl-0 = <&qup_i2c21_data_clk>;
1066 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067 #address-cells = <1>;
1069 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075 dma-names = "tx", "rx";
1076 status = "disabled";
1080 compatible = "qcom,geni-spi";
1081 reg = <0 0x00898000 0 0x4000>;
1083 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085 pinctrl-names = "default";
1086 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089 interconnect-names = "qup-core", "qup-config";
1090 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092 dma-names = "tx", "rx";
1093 #address-cells = <1>;
1095 status = "disabled";
1099 gpi_dma0: dma-controller@900000 {
1100 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1102 reg = <0 0x00900000 0 0x60000>;
1103 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115 dma-channels = <12>;
1116 dma-channel-mask = <0x7e>;
1117 iommus = <&apps_smmu 0x5b6 0x0>;
1118 status = "disabled";
1121 qupv3_id_0: geniqup@9c0000 {
1122 compatible = "qcom,geni-se-qup";
1123 reg = <0x0 0x009c0000 0x0 0x2000>;
1124 clock-names = "m-ahb", "s-ahb";
1125 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127 iommus = <&apps_smmu 0x5a3 0x0>;
1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129 interconnect-names = "qup-core";
1130 #address-cells = <2>;
1133 status = "disabled";
1136 compatible = "qcom,geni-i2c";
1137 reg = <0x0 0x00980000 0x0 0x4000>;
1139 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&qup_i2c0_data_clk>;
1142 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143 #address-cells = <1>;
1145 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151 dma-names = "tx", "rx";
1152 status = "disabled";
1156 compatible = "qcom,geni-spi";
1157 reg = <0x0 0x00980000 0x0 0x4000>;
1159 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163 power-domains = <&rpmhpd RPMHPD_CX>;
1164 operating-points-v2 = <&qup_opp_table_100mhz>;
1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168 interconnect-names = "qup-core", "qup-config", "qup-memory";
1169 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171 dma-names = "tx", "rx";
1172 #address-cells = <1>;
1174 status = "disabled";
1178 compatible = "qcom,geni-i2c";
1179 reg = <0x0 0x00984000 0x0 0x4000>;
1181 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182 pinctrl-names = "default";
1183 pinctrl-0 = <&qup_i2c1_data_clk>;
1184 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185 #address-cells = <1>;
1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190 interconnect-names = "qup-core", "qup-config", "qup-memory";
1191 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193 dma-names = "tx", "rx";
1194 status = "disabled";
1198 compatible = "qcom,geni-spi";
1199 reg = <0x0 0x00984000 0x0 0x4000>;
1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203 pinctrl-names = "default";
1204 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211 dma-names = "tx", "rx";
1212 #address-cells = <1>;
1214 status = "disabled";
1218 compatible = "qcom,geni-i2c";
1219 reg = <0x0 0x00988000 0x0 0x4000>;
1221 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&qup_i2c2_data_clk>;
1224 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cells = <1>;
1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233 dma-names = "tx", "rx";
1234 status = "disabled";
1238 compatible = "qcom,geni-spi";
1239 reg = <0x0 0x00988000 0x0 0x4000>;
1241 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251 dma-names = "tx", "rx";
1252 #address-cells = <1>;
1254 status = "disabled";
1259 compatible = "qcom,geni-i2c";
1260 reg = <0x0 0x0098c000 0x0 0x4000>;
1262 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263 pinctrl-names = "default";
1264 pinctrl-0 = <&qup_i2c3_data_clk>;
1265 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266 #address-cells = <1>;
1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274 dma-names = "tx", "rx";
1275 status = "disabled";
1279 compatible = "qcom,geni-spi";
1280 reg = <0x0 0x0098c000 0x0 0x4000>;
1282 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284 pinctrl-names = "default";
1285 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292 dma-names = "tx", "rx";
1293 #address-cells = <1>;
1295 status = "disabled";
1299 compatible = "qcom,geni-i2c";
1300 reg = <0x0 0x00990000 0x0 0x4000>;
1302 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_i2c4_data_clk>;
1305 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cells = <1>;
1308 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314 dma-names = "tx", "rx";
1315 status = "disabled";
1319 compatible = "qcom,geni-spi";
1320 reg = <0x0 0x00990000 0x0 0x4000>;
1322 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324 pinctrl-names = "default";
1325 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326 power-domains = <&rpmhpd RPMHPD_CX>;
1327 operating-points-v2 = <&qup_opp_table_100mhz>;
1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331 interconnect-names = "qup-core", "qup-config", "qup-memory";
1332 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334 dma-names = "tx", "rx";
1335 #address-cells = <1>;
1337 status = "disabled";
1341 compatible = "qcom,geni-i2c";
1342 reg = <0x0 0x00994000 0x0 0x4000>;
1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345 pinctrl-names = "default";
1346 pinctrl-0 = <&qup_i2c5_data_clk>;
1347 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348 #address-cells = <1>;
1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356 dma-names = "tx", "rx";
1357 status = "disabled";
1361 compatible = "qcom,geni-spi";
1362 reg = <0x0 0x00994000 0x0 0x4000>;
1364 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366 pinctrl-names = "default";
1367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374 dma-names = "tx", "rx";
1375 #address-cells = <1>;
1377 status = "disabled";
1382 compatible = "qcom,geni-i2c";
1383 reg = <0x0 0x00998000 0x0 0x4000>;
1385 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386 pinctrl-names = "default";
1387 pinctrl-0 = <&qup_i2c6_data_clk>;
1388 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389 #address-cells = <1>;
1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394 interconnect-names = "qup-core", "qup-config", "qup-memory";
1395 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397 dma-names = "tx", "rx";
1398 status = "disabled";
1402 compatible = "qcom,geni-spi";
1403 reg = <0x0 0x00998000 0x0 0x4000>;
1405 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407 pinctrl-names = "default";
1408 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415 dma-names = "tx", "rx";
1416 #address-cells = <1>;
1418 status = "disabled";
1421 uart7: serial@99c000 {
1422 compatible = "qcom,geni-debug-uart";
1423 reg = <0 0x0099c000 0 0x4000>;
1425 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426 pinctrl-names = "default";
1427 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1430 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1431 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1432 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1433 interconnect-names = "qup-core",
1435 status = "disabled";
1439 gpi_dma1: dma-controller@a00000 {
1440 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1442 reg = <0 0x00a00000 0 0x60000>;
1443 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455 dma-channels = <12>;
1456 dma-channel-mask = <0x7e>;
1457 iommus = <&apps_smmu 0x56 0x0>;
1458 status = "disabled";
1461 qupv3_id_1: geniqup@ac0000 {
1462 compatible = "qcom,geni-se-qup";
1463 reg = <0x0 0x00ac0000 0x0 0x6000>;
1464 clock-names = "m-ahb", "s-ahb";
1465 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467 iommus = <&apps_smmu 0x43 0x0>;
1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469 interconnect-names = "qup-core";
1470 #address-cells = <2>;
1473 status = "disabled";
1476 compatible = "qcom,geni-i2c";
1477 reg = <0x0 0x00a80000 0x0 0x4000>;
1479 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480 pinctrl-names = "default";
1481 pinctrl-0 = <&qup_i2c8_data_clk>;
1482 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483 #address-cells = <1>;
1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491 dma-names = "tx", "rx";
1492 status = "disabled";
1496 compatible = "qcom,geni-spi";
1497 reg = <0x0 0x00a80000 0x0 0x4000>;
1499 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501 pinctrl-names = "default";
1502 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506 interconnect-names = "qup-core", "qup-config", "qup-memory";
1507 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509 dma-names = "tx", "rx";
1510 #address-cells = <1>;
1512 status = "disabled";
1516 compatible = "qcom,geni-i2c";
1517 reg = <0x0 0x00a84000 0x0 0x4000>;
1519 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520 pinctrl-names = "default";
1521 pinctrl-0 = <&qup_i2c9_data_clk>;
1522 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523 #address-cells = <1>;
1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531 dma-names = "tx", "rx";
1532 status = "disabled";
1536 compatible = "qcom,geni-spi";
1537 reg = <0x0 0x00a84000 0x0 0x4000>;
1539 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541 pinctrl-names = "default";
1542 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546 interconnect-names = "qup-core", "qup-config", "qup-memory";
1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549 dma-names = "tx", "rx";
1550 #address-cells = <1>;
1552 status = "disabled";
1556 compatible = "qcom,geni-i2c";
1557 reg = <0x0 0x00a88000 0x0 0x4000>;
1559 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560 pinctrl-names = "default";
1561 pinctrl-0 = <&qup_i2c10_data_clk>;
1562 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563 #address-cells = <1>;
1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571 dma-names = "tx", "rx";
1572 status = "disabled";
1576 compatible = "qcom,geni-spi";
1577 reg = <0x0 0x00a88000 0x0 0x4000>;
1579 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 pinctrl-names = "default";
1582 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 interconnect-names = "qup-core", "qup-config", "qup-memory";
1587 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589 dma-names = "tx", "rx";
1590 #address-cells = <1>;
1592 status = "disabled";
1596 compatible = "qcom,geni-i2c";
1597 reg = <0x0 0x00a8c000 0x0 0x4000>;
1599 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600 pinctrl-names = "default";
1601 pinctrl-0 = <&qup_i2c11_data_clk>;
1602 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603 #address-cells = <1>;
1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611 dma-names = "tx", "rx";
1612 status = "disabled";
1616 compatible = "qcom,geni-spi";
1617 reg = <0x0 0x00a8c000 0x0 0x4000>;
1619 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626 interconnect-names = "qup-core", "qup-config", "qup-memory";
1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629 dma-names = "tx", "rx";
1630 #address-cells = <1>;
1632 status = "disabled";
1636 compatible = "qcom,geni-i2c";
1637 reg = <0x0 0x00a90000 0x0 0x4000>;
1639 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640 pinctrl-names = "default";
1641 pinctrl-0 = <&qup_i2c12_data_clk>;
1642 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643 #address-cells = <1>;
1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648 interconnect-names = "qup-core", "qup-config", "qup-memory";
1649 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651 dma-names = "tx", "rx";
1652 status = "disabled";
1656 compatible = "qcom,geni-spi";
1657 reg = <0x0 0x00a90000 0x0 0x4000>;
1659 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661 pinctrl-names = "default";
1662 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666 interconnect-names = "qup-core", "qup-config", "qup-memory";
1667 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669 dma-names = "tx", "rx";
1670 #address-cells = <1>;
1672 status = "disabled";
1676 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00a94000 0 0x4000>;
1679 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680 pinctrl-names = "default";
1681 pinctrl-0 = <&qup_i2c13_data_clk>;
1682 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686 interconnect-names = "qup-core", "qup-config", "qup-memory";
1687 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689 dma-names = "tx", "rx";
1690 #address-cells = <1>;
1692 status = "disabled";
1696 compatible = "qcom,geni-spi";
1697 reg = <0x0 0x00a94000 0x0 0x4000>;
1699 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701 pinctrl-names = "default";
1702 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 interconnect-names = "qup-core", "qup-config", "qup-memory";
1707 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709 dma-names = "tx", "rx";
1710 #address-cells = <1>;
1712 status = "disabled";
1716 compatible = "qcom,geni-i2c";
1717 reg = <0 0x00a98000 0 0x4000>;
1719 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720 pinctrl-names = "default";
1721 pinctrl-0 = <&qup_i2c14_data_clk>;
1722 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726 interconnect-names = "qup-core", "qup-config", "qup-memory";
1727 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729 dma-names = "tx", "rx";
1730 #address-cells = <1>;
1732 status = "disabled";
1736 compatible = "qcom,geni-spi";
1737 reg = <0x0 0x00a98000 0x0 0x4000>;
1739 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741 pinctrl-names = "default";
1742 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746 interconnect-names = "qup-core", "qup-config", "qup-memory";
1747 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749 dma-names = "tx", "rx";
1750 #address-cells = <1>;
1752 status = "disabled";
1757 compatible = "qcom,sm8450-trng", "qcom,trng";
1758 reg = <0 0x010c3000 0 0x1000>;
1761 pcie0: pcie@1c00000 {
1762 compatible = "qcom,pcie-sm8450-pcie0";
1763 reg = <0 0x01c00000 0 0x3000>,
1764 <0 0x60000000 0 0xf1d>,
1765 <0 0x60000f20 0 0xa8>,
1766 <0 0x60001000 0 0x1000>,
1767 <0 0x60100000 0 0x100000>;
1768 reg-names = "parf", "dbi", "elbi", "atu", "config";
1769 device_type = "pci";
1770 linux,pci-domain = <0>;
1771 bus-range = <0x00 0xff>;
1774 #address-cells = <3>;
1777 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1781 * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
1782 * Hence, the IDs are swapped.
1784 msi-map = <0x0 &gic_its 0x5981 0x1>,
1785 <0x100 &gic_its 0x5980 0x1>;
1786 msi-map-mask = <0xff00>;
1787 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1789 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1790 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1791 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1792 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1793 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1794 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1795 interrupt-names = "msi0",
1803 #interrupt-cells = <1>;
1804 interrupt-map-mask = <0 0 0 0x7>;
1805 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1806 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1807 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1808 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1810 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1811 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1813 <&rpmhcc RPMH_CXO_CLK>,
1814 <&gcc GCC_PCIE_0_AUX_CLK>,
1815 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1816 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1817 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1818 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1819 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1820 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1821 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1822 clock-names = "pipe",
1835 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1836 <0x100 &apps_smmu 0x1c01 0x1>;
1838 resets = <&gcc GCC_PCIE_0_BCR>;
1839 reset-names = "pci";
1841 power-domains = <&gcc PCIE_0_GDSC>;
1843 phys = <&pcie0_phy>;
1844 phy-names = "pciephy";
1846 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1847 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1849 pinctrl-names = "default";
1850 pinctrl-0 = <&pcie0_default_state>;
1852 status = "disabled";
1855 pcie0_phy: phy@1c06000 {
1856 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1857 reg = <0 0x01c06000 0 0x2000>;
1859 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1860 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1861 <&gcc GCC_PCIE_0_CLKREF_EN>,
1862 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1863 <&gcc GCC_PCIE_0_PIPE_CLK>;
1864 clock-names = "aux",
1870 clock-output-names = "pcie_0_pipe_clk";
1875 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1876 reset-names = "phy";
1878 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1879 assigned-clock-rates = <100000000>;
1881 status = "disabled";
1884 pcie1: pcie@1c08000 {
1885 compatible = "qcom,pcie-sm8450-pcie1";
1886 reg = <0 0x01c08000 0 0x3000>,
1887 <0 0x40000000 0 0xf1d>,
1888 <0 0x40000f20 0 0xa8>,
1889 <0 0x40001000 0 0x1000>,
1890 <0 0x40100000 0 0x100000>;
1891 reg-names = "parf", "dbi", "elbi", "atu", "config";
1892 device_type = "pci";
1893 linux,pci-domain = <1>;
1894 bus-range = <0x00 0xff>;
1897 #address-cells = <3>;
1900 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1901 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1904 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
1905 * Hence, the IDs are swapped.
1907 msi-map = <0x0 &gic_its 0x5a01 0x1>,
1908 <0x100 &gic_its 0x5a00 0x1>;
1909 msi-map-mask = <0xff00>;
1910 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1911 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1912 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1913 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1914 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1915 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1916 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1917 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1918 interrupt-names = "msi0",
1926 #interrupt-cells = <1>;
1927 interrupt-map-mask = <0 0 0 0x7>;
1928 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1929 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1930 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1931 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1933 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1934 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1936 <&rpmhcc RPMH_CXO_CLK>,
1937 <&gcc GCC_PCIE_1_AUX_CLK>,
1938 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1939 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1940 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1941 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1942 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1943 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1944 clock-names = "pipe",
1956 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1957 <0x100 &apps_smmu 0x1c81 0x1>;
1959 resets = <&gcc GCC_PCIE_1_BCR>;
1960 reset-names = "pci";
1962 power-domains = <&gcc PCIE_1_GDSC>;
1964 phys = <&pcie1_phy>;
1965 phy-names = "pciephy";
1967 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1968 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1970 pinctrl-names = "default";
1971 pinctrl-0 = <&pcie1_default_state>;
1973 status = "disabled";
1976 pcie1_phy: phy@1c0e000 {
1977 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1978 reg = <0 0x01c0e000 0 0x2000>;
1980 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1981 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1982 <&gcc GCC_PCIE_1_CLKREF_EN>,
1983 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1984 <&gcc GCC_PCIE_1_PIPE_CLK>;
1985 clock-names = "aux",
1991 clock-output-names = "pcie_1_pipe_clk";
1996 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1997 reset-names = "phy";
1999 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2000 assigned-clock-rates = <100000000>;
2002 status = "disabled";
2005 config_noc: interconnect@1500000 {
2006 compatible = "qcom,sm8450-config-noc";
2007 reg = <0 0x01500000 0 0x1c000>;
2008 #interconnect-cells = <2>;
2009 qcom,bcm-voters = <&apps_bcm_voter>;
2012 system_noc: interconnect@1680000 {
2013 compatible = "qcom,sm8450-system-noc";
2014 reg = <0 0x01680000 0 0x1e200>;
2015 #interconnect-cells = <2>;
2016 qcom,bcm-voters = <&apps_bcm_voter>;
2019 pcie_noc: interconnect@16c0000 {
2020 compatible = "qcom,sm8450-pcie-anoc";
2021 reg = <0 0x016c0000 0 0xe280>;
2022 #interconnect-cells = <2>;
2023 qcom,bcm-voters = <&apps_bcm_voter>;
2026 aggre1_noc: interconnect@16e0000 {
2027 compatible = "qcom,sm8450-aggre1-noc";
2028 reg = <0 0x016e0000 0 0x1c080>;
2029 #interconnect-cells = <2>;
2030 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2031 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2032 qcom,bcm-voters = <&apps_bcm_voter>;
2035 aggre2_noc: interconnect@1700000 {
2036 compatible = "qcom,sm8450-aggre2-noc";
2037 reg = <0 0x01700000 0 0x31080>;
2038 #interconnect-cells = <2>;
2039 qcom,bcm-voters = <&apps_bcm_voter>;
2040 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2041 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2042 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2043 <&rpmhcc RPMH_IPA_CLK>;
2046 mmss_noc: interconnect@1740000 {
2047 compatible = "qcom,sm8450-mmss-noc";
2048 reg = <0 0x01740000 0 0x1f080>;
2049 #interconnect-cells = <2>;
2050 qcom,bcm-voters = <&apps_bcm_voter>;
2053 tcsr_mutex: hwlock@1f40000 {
2054 compatible = "qcom,tcsr-mutex";
2055 reg = <0x0 0x01f40000 0x0 0x40000>;
2056 #hwlock-cells = <1>;
2059 tcsr: syscon@1fc0000 {
2060 compatible = "qcom,sm8450-tcsr", "syscon";
2061 reg = <0x0 0x1fc0000 0x0 0x30000>;
2065 compatible = "qcom,adreno-730.1", "qcom,adreno";
2066 reg = <0x0 0x03d00000 0x0 0x40000>,
2067 <0x0 0x03d9e000 0x0 0x1000>,
2068 <0x0 0x03d61000 0x0 0x800>;
2069 reg-names = "kgsl_3d0_reg_memory",
2073 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2075 iommus = <&adreno_smmu 0 0x400>,
2076 <&adreno_smmu 1 0x400>;
2078 operating-points-v2 = <&gpu_opp_table>;
2081 #cooling-cells = <2>;
2083 status = "disabled";
2086 memory-region = <&gpu_micro_code_mem>;
2089 gpu_opp_table: opp-table {
2090 compatible = "operating-points-v2";
2093 opp-hz = /bits/ 64 <818000000>;
2094 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2098 opp-hz = /bits/ 64 <791000000>;
2099 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2103 opp-hz = /bits/ 64 <734000000>;
2104 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2108 opp-hz = /bits/ 64 <640000000>;
2109 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2113 opp-hz = /bits/ 64 <599000000>;
2114 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2118 opp-hz = /bits/ 64 <545000000>;
2119 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2123 opp-hz = /bits/ 64 <492000000>;
2124 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2128 opp-hz = /bits/ 64 <421000000>;
2129 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2133 opp-hz = /bits/ 64 <350000000>;
2134 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2138 opp-hz = /bits/ 64 <317000000>;
2139 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2143 opp-hz = /bits/ 64 <285000000>;
2144 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2148 opp-hz = /bits/ 64 <220000000>;
2149 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2155 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2156 reg = <0x0 0x03d6a000 0x0 0x35000>,
2157 <0x0 0x03d50000 0x0 0x10000>,
2158 <0x0 0x0b290000 0x0 0x10000>;
2159 reg-names = "gmu", "rscc", "gmu_pdc";
2161 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2162 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2163 interrupt-names = "hfi", "gmu";
2165 clocks = <&gpucc GPU_CC_AHB_CLK>,
2166 <&gpucc GPU_CC_CX_GMU_CLK>,
2167 <&gpucc GPU_CC_CXO_CLK>,
2168 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2169 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2170 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2171 <&gpucc GPU_CC_DEMET_CLK>;
2172 clock-names = "ahb",
2180 power-domains = <&gpucc GPU_CX_GDSC>,
2181 <&gpucc GPU_GX_GDSC>;
2182 power-domain-names = "cx",
2185 iommus = <&adreno_smmu 5 0x400>;
2187 qcom,qmp = <&aoss_qmp>;
2189 operating-points-v2 = <&gmu_opp_table>;
2191 gmu_opp_table: opp-table {
2192 compatible = "operating-points-v2";
2195 opp-hz = /bits/ 64 <500000000>;
2196 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2200 opp-hz = /bits/ 64 <200000000>;
2201 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2206 gpucc: clock-controller@3d90000 {
2207 compatible = "qcom,sm8450-gpucc";
2208 reg = <0x0 0x03d90000 0x0 0xa000>;
2209 clocks = <&rpmhcc RPMH_CXO_CLK>,
2210 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2211 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2214 #power-domain-cells = <1>;
2217 adreno_smmu: iommu@3da0000 {
2218 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
2219 "qcom,smmu-500", "arm,mmu-500";
2220 reg = <0x0 0x03da0000 0x0 0x40000>;
2222 #global-interrupts = <1>;
2223 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2224 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2226 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2227 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2228 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2233 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
2237 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
2242 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
2243 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
2244 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2245 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2246 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
2248 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
2249 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2250 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2251 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2252 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2253 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2254 <&gpucc GPU_CC_AHB_CLK>;
2255 clock-names = "gmu",
2261 power-domains = <&gpucc GPU_CX_GDSC>;
2265 usb_1_hsphy: phy@88e3000 {
2266 compatible = "qcom,sm8450-usb-hs-phy",
2267 "qcom,usb-snps-hs-7nm-phy";
2268 reg = <0 0x088e3000 0 0x400>;
2269 status = "disabled";
2272 clocks = <&rpmhcc RPMH_CXO_CLK>;
2273 clock-names = "ref";
2275 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2278 usb_1_qmpphy: phy@88e8000 {
2279 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2280 reg = <0 0x088e8000 0 0x3000>;
2282 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2283 <&rpmhcc RPMH_CXO_CLK>,
2284 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2285 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2286 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2288 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2289 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2290 reset-names = "phy", "common";
2295 status = "disabled";
2298 #address-cells = <1>;
2304 usb_1_qmpphy_out: endpoint {
2311 usb_1_qmpphy_usb_ss_in: endpoint {
2318 usb_1_qmpphy_dp_in: endpoint {
2324 remoteproc_slpi: remoteproc@2400000 {
2325 compatible = "qcom,sm8450-slpi-pas";
2326 reg = <0 0x02400000 0 0x4000>;
2328 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2329 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2330 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2331 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2332 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2333 interrupt-names = "wdog", "fatal", "ready",
2334 "handover", "stop-ack";
2336 clocks = <&rpmhcc RPMH_CXO_CLK>;
2339 power-domains = <&rpmhpd RPMHPD_LCX>,
2340 <&rpmhpd RPMHPD_LMX>;
2341 power-domain-names = "lcx", "lmx";
2343 memory-region = <&slpi_mem>;
2345 qcom,qmp = <&aoss_qmp>;
2347 qcom,smem-states = <&smp2p_slpi_out 0>;
2348 qcom,smem-state-names = "stop";
2350 status = "disabled";
2353 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2354 IPCC_MPROC_SIGNAL_GLINK_QMP
2355 IRQ_TYPE_EDGE_RISING>;
2356 mboxes = <&ipcc IPCC_CLIENT_SLPI
2357 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2360 qcom,remote-pid = <3>;
2363 compatible = "qcom,fastrpc";
2364 qcom,glink-channels = "fastrpcglink-apps-dsp";
2366 #address-cells = <1>;
2370 compatible = "qcom,fastrpc-compute-cb";
2372 iommus = <&apps_smmu 0x0541 0x0>;
2376 compatible = "qcom,fastrpc-compute-cb";
2378 iommus = <&apps_smmu 0x0542 0x0>;
2382 compatible = "qcom,fastrpc-compute-cb";
2384 iommus = <&apps_smmu 0x0543 0x0>;
2385 /* note: shared-cb = <4> in downstream */
2391 wsa2macro: codec@31e0000 {
2392 compatible = "qcom,sm8450-lpass-wsa-macro";
2393 reg = <0 0x031e0000 0 0x1000>;
2394 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2395 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2396 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2397 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2399 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2402 clock-output-names = "wsa2-mclk";
2403 #sound-dai-cells = <1>;
2406 swr4: soundwire@31f0000 {
2407 compatible = "qcom,soundwire-v1.7.0";
2408 reg = <0 0x031f0000 0 0x2000>;
2409 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2410 clocks = <&wsa2macro>;
2411 clock-names = "iface";
2414 pinctrl-0 = <&wsa2_swr_active>;
2415 pinctrl-names = "default";
2417 qcom,din-ports = <2>;
2418 qcom,dout-ports = <6>;
2420 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2421 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2422 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2423 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2424 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2425 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2426 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2427 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2428 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2430 #address-cells = <2>;
2432 #sound-dai-cells = <1>;
2433 status = "disabled";
2436 rxmacro: codec@3200000 {
2437 compatible = "qcom,sm8450-lpass-rx-macro";
2438 reg = <0 0x03200000 0 0x1000>;
2439 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2440 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2441 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2442 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2444 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2447 clock-output-names = "mclk";
2448 #sound-dai-cells = <1>;
2451 swr1: soundwire@3210000 {
2452 compatible = "qcom,soundwire-v1.7.0";
2453 reg = <0 0x03210000 0 0x2000>;
2454 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2455 clocks = <&rxmacro>;
2456 clock-names = "iface";
2458 qcom,din-ports = <0>;
2459 qcom,dout-ports = <5>;
2461 pinctrl-0 = <&rx_swr_active>;
2462 pinctrl-names = "default";
2464 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2465 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2466 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2467 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2468 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2469 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2470 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2471 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2472 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2474 #address-cells = <2>;
2476 #sound-dai-cells = <1>;
2477 status = "disabled";
2480 txmacro: codec@3220000 {
2481 compatible = "qcom,sm8450-lpass-tx-macro";
2482 reg = <0 0x03220000 0 0x1000>;
2483 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2484 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2485 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2486 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2488 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2491 clock-output-names = "mclk";
2492 #sound-dai-cells = <1>;
2495 wsamacro: codec@3240000 {
2496 compatible = "qcom,sm8450-lpass-wsa-macro";
2497 reg = <0 0x03240000 0 0x1000>;
2498 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2499 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2500 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2501 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2503 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2506 clock-output-names = "mclk";
2507 #sound-dai-cells = <1>;
2510 swr0: soundwire@3250000 {
2511 compatible = "qcom,soundwire-v1.7.0";
2512 reg = <0 0x03250000 0 0x2000>;
2513 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2514 clocks = <&wsamacro>;
2515 clock-names = "iface";
2518 pinctrl-0 = <&wsa_swr_active>;
2519 pinctrl-names = "default";
2521 qcom,din-ports = <2>;
2522 qcom,dout-ports = <6>;
2524 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2525 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2526 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2527 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2528 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2529 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2530 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2531 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2532 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2534 #address-cells = <2>;
2536 #sound-dai-cells = <1>;
2537 status = "disabled";
2540 swr2: soundwire@33b0000 {
2541 compatible = "qcom,soundwire-v1.7.0";
2542 reg = <0 0x033b0000 0 0x2000>;
2543 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2544 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2545 interrupt-names = "core", "wakeup";
2547 clocks = <&txmacro>;
2548 clock-names = "iface";
2551 pinctrl-0 = <&tx_swr_active>;
2552 pinctrl-names = "default";
2554 qcom,din-ports = <4>;
2555 qcom,dout-ports = <0>;
2556 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2557 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2558 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2559 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2560 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2561 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2562 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2563 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2564 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2566 #address-cells = <2>;
2568 #sound-dai-cells = <1>;
2569 status = "disabled";
2572 vamacro: codec@33f0000 {
2573 compatible = "qcom,sm8450-lpass-va-macro";
2574 reg = <0 0x033f0000 0 0x1000>;
2575 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2576 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2577 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2578 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2579 clock-names = "mclk", "macro", "dcodec", "npl";
2582 clock-output-names = "fsgen";
2583 #sound-dai-cells = <1>;
2584 status = "disabled";
2587 remoteproc_adsp: remoteproc@30000000 {
2588 compatible = "qcom,sm8450-adsp-pas";
2589 reg = <0 0x30000000 0 0x100>;
2591 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2592 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2593 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2594 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2595 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2596 interrupt-names = "wdog", "fatal", "ready",
2597 "handover", "stop-ack";
2599 clocks = <&rpmhcc RPMH_CXO_CLK>;
2602 power-domains = <&rpmhpd RPMHPD_LCX>,
2603 <&rpmhpd RPMHPD_LMX>;
2604 power-domain-names = "lcx", "lmx";
2606 memory-region = <&adsp_mem>;
2608 qcom,qmp = <&aoss_qmp>;
2610 qcom,smem-states = <&smp2p_adsp_out 0>;
2611 qcom,smem-state-names = "stop";
2613 status = "disabled";
2615 remoteproc_adsp_glink: glink-edge {
2616 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2617 IPCC_MPROC_SIGNAL_GLINK_QMP
2618 IRQ_TYPE_EDGE_RISING>;
2619 mboxes = <&ipcc IPCC_CLIENT_LPASS
2620 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2623 qcom,remote-pid = <2>;
2626 compatible = "qcom,gpr";
2627 qcom,glink-channels = "adsp_apps";
2628 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2629 qcom,intents = <512 20>;
2630 #address-cells = <1>;
2634 compatible = "qcom,q6apm";
2635 reg = <GPR_APM_MODULE_IID>;
2636 #sound-dai-cells = <0>;
2637 qcom,protection-domain = "avs/audio",
2638 "msm/adsp/audio_pd";
2641 compatible = "qcom,q6apm-dais";
2642 iommus = <&apps_smmu 0x1801 0x0>;
2645 q6apmbedai: bedais {
2646 compatible = "qcom,q6apm-lpass-dais";
2647 #sound-dai-cells = <1>;
2652 compatible = "qcom,q6prm";
2653 reg = <GPR_PRM_MODULE_IID>;
2654 qcom,protection-domain = "avs/audio",
2655 "msm/adsp/audio_pd";
2657 q6prmcc: clock-controller {
2658 compatible = "qcom,q6prm-lpass-clocks";
2665 compatible = "qcom,fastrpc";
2666 qcom,glink-channels = "fastrpcglink-apps-dsp";
2668 #address-cells = <1>;
2672 compatible = "qcom,fastrpc-compute-cb";
2674 iommus = <&apps_smmu 0x1803 0x0>;
2678 compatible = "qcom,fastrpc-compute-cb";
2680 iommus = <&apps_smmu 0x1804 0x0>;
2684 compatible = "qcom,fastrpc-compute-cb";
2686 iommus = <&apps_smmu 0x1805 0x0>;
2692 remoteproc_cdsp: remoteproc@32300000 {
2693 compatible = "qcom,sm8450-cdsp-pas";
2694 reg = <0 0x32300000 0 0x1400000>;
2696 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2697 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2698 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2699 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2700 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2701 interrupt-names = "wdog", "fatal", "ready",
2702 "handover", "stop-ack";
2704 clocks = <&rpmhcc RPMH_CXO_CLK>;
2707 power-domains = <&rpmhpd RPMHPD_CX>,
2708 <&rpmhpd RPMHPD_MXC>;
2709 power-domain-names = "cx", "mxc";
2711 memory-region = <&cdsp_mem>;
2713 qcom,qmp = <&aoss_qmp>;
2715 qcom,smem-states = <&smp2p_cdsp_out 0>;
2716 qcom,smem-state-names = "stop";
2718 status = "disabled";
2721 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2722 IPCC_MPROC_SIGNAL_GLINK_QMP
2723 IRQ_TYPE_EDGE_RISING>;
2724 mboxes = <&ipcc IPCC_CLIENT_CDSP
2725 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2728 qcom,remote-pid = <5>;
2731 compatible = "qcom,fastrpc";
2732 qcom,glink-channels = "fastrpcglink-apps-dsp";
2734 #address-cells = <1>;
2738 compatible = "qcom,fastrpc-compute-cb";
2740 iommus = <&apps_smmu 0x2161 0x0400>,
2741 <&apps_smmu 0x1021 0x1420>;
2745 compatible = "qcom,fastrpc-compute-cb";
2747 iommus = <&apps_smmu 0x2162 0x0400>,
2748 <&apps_smmu 0x1022 0x1420>;
2752 compatible = "qcom,fastrpc-compute-cb";
2754 iommus = <&apps_smmu 0x2163 0x0400>,
2755 <&apps_smmu 0x1023 0x1420>;
2759 compatible = "qcom,fastrpc-compute-cb";
2761 iommus = <&apps_smmu 0x2164 0x0400>,
2762 <&apps_smmu 0x1024 0x1420>;
2766 compatible = "qcom,fastrpc-compute-cb";
2768 iommus = <&apps_smmu 0x2165 0x0400>,
2769 <&apps_smmu 0x1025 0x1420>;
2773 compatible = "qcom,fastrpc-compute-cb";
2775 iommus = <&apps_smmu 0x2166 0x0400>,
2776 <&apps_smmu 0x1026 0x1420>;
2780 compatible = "qcom,fastrpc-compute-cb";
2782 iommus = <&apps_smmu 0x2167 0x0400>,
2783 <&apps_smmu 0x1027 0x1420>;
2787 compatible = "qcom,fastrpc-compute-cb";
2789 iommus = <&apps_smmu 0x2168 0x0400>,
2790 <&apps_smmu 0x1028 0x1420>;
2793 /* note: secure cb9 in downstream */
2798 remoteproc_mpss: remoteproc@4080000 {
2799 compatible = "qcom,sm8450-mpss-pas";
2800 reg = <0x0 0x04080000 0x0 0x4040>;
2802 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2803 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2804 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2805 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2806 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2807 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2808 interrupt-names = "wdog", "fatal", "ready", "handover",
2809 "stop-ack", "shutdown-ack";
2811 clocks = <&rpmhcc RPMH_CXO_CLK>;
2814 power-domains = <&rpmhpd RPMHPD_CX>,
2815 <&rpmhpd RPMHPD_MSS>;
2816 power-domain-names = "cx", "mss";
2818 memory-region = <&mpss_mem>;
2820 qcom,qmp = <&aoss_qmp>;
2822 qcom,smem-states = <&smp2p_modem_out 0>;
2823 qcom,smem-state-names = "stop";
2825 status = "disabled";
2828 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2829 IPCC_MPROC_SIGNAL_GLINK_QMP
2830 IRQ_TYPE_EDGE_RISING>;
2831 mboxes = <&ipcc IPCC_CLIENT_MPSS
2832 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2834 qcom,remote-pid = <1>;
2838 videocc: clock-controller@aaf0000 {
2839 compatible = "qcom,sm8450-videocc";
2840 reg = <0 0x0aaf0000 0 0x10000>;
2841 clocks = <&rpmhcc RPMH_CXO_CLK>,
2842 <&gcc GCC_VIDEO_AHB_CLK>;
2843 power-domains = <&rpmhpd RPMHPD_MMCX>;
2844 required-opps = <&rpmhpd_opp_low_svs>;
2847 #power-domain-cells = <1>;
2851 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2852 reg = <0 0x0ac15000 0 0x1000>;
2853 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2854 power-domains = <&camcc TITAN_TOP_GDSC>;
2856 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2857 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2858 <&camcc CAM_CC_CPAS_AHB_CLK>,
2859 <&camcc CAM_CC_CCI_0_CLK>,
2860 <&camcc CAM_CC_CCI_0_CLK_SRC>;
2861 clock-names = "camnoc_axi",
2866 pinctrl-0 = <&cci0_default &cci1_default>;
2867 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2868 pinctrl-names = "default", "sleep";
2870 status = "disabled";
2871 #address-cells = <1>;
2874 cci0_i2c0: i2c-bus@0 {
2876 clock-frequency = <1000000>;
2877 #address-cells = <1>;
2881 cci0_i2c1: i2c-bus@1 {
2883 clock-frequency = <1000000>;
2884 #address-cells = <1>;
2890 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2891 reg = <0 0x0ac16000 0 0x1000>;
2892 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2893 power-domains = <&camcc TITAN_TOP_GDSC>;
2895 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2896 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2897 <&camcc CAM_CC_CPAS_AHB_CLK>,
2898 <&camcc CAM_CC_CCI_1_CLK>,
2899 <&camcc CAM_CC_CCI_1_CLK_SRC>;
2900 clock-names = "camnoc_axi",
2905 pinctrl-0 = <&cci2_default &cci3_default>;
2906 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
2907 pinctrl-names = "default", "sleep";
2909 status = "disabled";
2910 #address-cells = <1>;
2913 cci1_i2c0: i2c-bus@0 {
2915 clock-frequency = <1000000>;
2916 #address-cells = <1>;
2920 cci1_i2c1: i2c-bus@1 {
2922 clock-frequency = <1000000>;
2923 #address-cells = <1>;
2928 camcc: clock-controller@ade0000 {
2929 compatible = "qcom,sm8450-camcc";
2930 reg = <0 0x0ade0000 0 0x20000>;
2931 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2932 <&rpmhcc RPMH_CXO_CLK>,
2933 <&rpmhcc RPMH_CXO_CLK_A>,
2935 power-domains = <&rpmhpd RPMHPD_MMCX>;
2936 required-opps = <&rpmhpd_opp_low_svs>;
2939 #power-domain-cells = <1>;
2940 status = "disabled";
2943 mdss: display-subsystem@ae00000 {
2944 compatible = "qcom,sm8450-mdss";
2945 reg = <0 0x0ae00000 0 0x1000>;
2948 /* same path used twice */
2949 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2950 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2951 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2952 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
2953 interconnect-names = "mdp0-mem",
2957 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2959 power-domains = <&dispcc MDSS_GDSC>;
2961 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2962 <&gcc GCC_DISP_HF_AXI_CLK>,
2963 <&gcc GCC_DISP_SF_AXI_CLK>,
2964 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2966 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2967 interrupt-controller;
2968 #interrupt-cells = <1>;
2970 iommus = <&apps_smmu 0x2800 0x402>;
2972 #address-cells = <2>;
2976 status = "disabled";
2978 mdss_mdp: display-controller@ae01000 {
2979 compatible = "qcom,sm8450-dpu";
2980 reg = <0 0x0ae01000 0 0x8f000>,
2981 <0 0x0aeb0000 0 0x2008>;
2982 reg-names = "mdp", "vbif";
2984 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2985 <&gcc GCC_DISP_SF_AXI_CLK>,
2986 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2987 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2988 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2989 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2990 clock-names = "bus",
2997 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2998 assigned-clock-rates = <19200000>;
3000 operating-points-v2 = <&mdp_opp_table>;
3001 power-domains = <&rpmhpd RPMHPD_MMCX>;
3003 interrupt-parent = <&mdss>;
3007 #address-cells = <1>;
3012 dpu_intf1_out: endpoint {
3013 remote-endpoint = <&mdss_dsi0_in>;
3019 dpu_intf2_out: endpoint {
3020 remote-endpoint = <&mdss_dsi1_in>;
3026 dpu_intf0_out: endpoint {
3027 remote-endpoint = <&mdss_dp0_in>;
3032 mdp_opp_table: opp-table {
3033 compatible = "operating-points-v2";
3036 opp-hz = /bits/ 64 <172000000>;
3037 required-opps = <&rpmhpd_opp_low_svs_d1>;
3041 opp-hz = /bits/ 64 <200000000>;
3042 required-opps = <&rpmhpd_opp_low_svs>;
3046 opp-hz = /bits/ 64 <325000000>;
3047 required-opps = <&rpmhpd_opp_svs>;
3051 opp-hz = /bits/ 64 <375000000>;
3052 required-opps = <&rpmhpd_opp_svs_l1>;
3056 opp-hz = /bits/ 64 <500000000>;
3057 required-opps = <&rpmhpd_opp_nom>;
3062 mdss_dp0: displayport-controller@ae90000 {
3063 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3064 reg = <0 0xae90000 0 0x200>,
3065 <0 0xae90200 0 0x200>,
3066 <0 0xae90400 0 0xc00>,
3067 <0 0xae91000 0 0x400>,
3068 <0 0xae91400 0 0x400>;
3069 interrupt-parent = <&mdss>;
3071 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3072 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3073 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3074 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3075 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3076 clock-names = "core_iface",
3082 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3083 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3084 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3085 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3087 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3090 #sound-dai-cells = <0>;
3092 operating-points-v2 = <&dp_opp_table>;
3093 power-domains = <&rpmhpd RPMHPD_MMCX>;
3095 status = "disabled";
3098 #address-cells = <1>;
3103 mdss_dp0_in: endpoint {
3104 remote-endpoint = <&dpu_intf0_out>;
3109 dp_opp_table: opp-table {
3110 compatible = "operating-points-v2";
3113 opp-hz = /bits/ 64 <160000000>;
3114 required-opps = <&rpmhpd_opp_low_svs>;
3118 opp-hz = /bits/ 64 <270000000>;
3119 required-opps = <&rpmhpd_opp_svs>;
3123 opp-hz = /bits/ 64 <540000000>;
3124 required-opps = <&rpmhpd_opp_svs_l1>;
3128 opp-hz = /bits/ 64 <810000000>;
3129 required-opps = <&rpmhpd_opp_nom>;
3134 mdss_dsi0: dsi@ae94000 {
3135 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3136 reg = <0 0x0ae94000 0 0x400>;
3137 reg-names = "dsi_ctrl";
3139 interrupt-parent = <&mdss>;
3142 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3143 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3144 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3145 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3146 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3147 <&gcc GCC_DISP_HF_AXI_CLK>;
3148 clock-names = "byte",
3155 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3156 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3158 operating-points-v2 = <&mdss_dsi_opp_table>;
3159 power-domains = <&rpmhpd RPMHPD_MMCX>;
3161 phys = <&mdss_dsi0_phy>;
3164 #address-cells = <1>;
3167 status = "disabled";
3170 #address-cells = <1>;
3175 mdss_dsi0_in: endpoint {
3176 remote-endpoint = <&dpu_intf1_out>;
3182 mdss_dsi0_out: endpoint {
3187 mdss_dsi_opp_table: opp-table {
3188 compatible = "operating-points-v2";
3191 opp-hz = /bits/ 64 <187500000>;
3192 required-opps = <&rpmhpd_opp_low_svs>;
3196 opp-hz = /bits/ 64 <300000000>;
3197 required-opps = <&rpmhpd_opp_svs>;
3201 opp-hz = /bits/ 64 <358000000>;
3202 required-opps = <&rpmhpd_opp_svs_l1>;
3207 mdss_dsi0_phy: phy@ae94400 {
3208 compatible = "qcom,sm8450-dsi-phy-5nm";
3209 reg = <0 0x0ae94400 0 0x200>,
3210 <0 0x0ae94600 0 0x280>,
3211 <0 0x0ae94900 0 0x260>;
3212 reg-names = "dsi_phy",
3219 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3220 <&rpmhcc RPMH_CXO_CLK>;
3221 clock-names = "iface", "ref";
3223 status = "disabled";
3226 mdss_dsi1: dsi@ae96000 {
3227 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3228 reg = <0 0x0ae96000 0 0x400>;
3229 reg-names = "dsi_ctrl";
3231 interrupt-parent = <&mdss>;
3234 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3235 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3236 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3237 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3238 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3239 <&gcc GCC_DISP_HF_AXI_CLK>;
3240 clock-names = "byte",
3247 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3248 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3250 operating-points-v2 = <&mdss_dsi_opp_table>;
3251 power-domains = <&rpmhpd RPMHPD_MMCX>;
3253 phys = <&mdss_dsi1_phy>;
3256 #address-cells = <1>;
3259 status = "disabled";
3262 #address-cells = <1>;
3267 mdss_dsi1_in: endpoint {
3268 remote-endpoint = <&dpu_intf2_out>;
3274 mdss_dsi1_out: endpoint {
3280 mdss_dsi1_phy: phy@ae96400 {
3281 compatible = "qcom,sm8450-dsi-phy-5nm";
3282 reg = <0 0x0ae96400 0 0x200>,
3283 <0 0x0ae96600 0 0x280>,
3284 <0 0x0ae96900 0 0x260>;
3285 reg-names = "dsi_phy",
3292 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3293 <&rpmhcc RPMH_CXO_CLK>;
3294 clock-names = "iface", "ref";
3296 status = "disabled";
3300 dispcc: clock-controller@af00000 {
3301 compatible = "qcom,sm8450-dispcc";
3302 reg = <0 0x0af00000 0 0x20000>;
3303 clocks = <&rpmhcc RPMH_CXO_CLK>,
3304 <&rpmhcc RPMH_CXO_CLK_A>,
3305 <&gcc GCC_DISP_AHB_CLK>,
3311 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3312 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3319 power-domains = <&rpmhpd RPMHPD_MMCX>;
3320 required-opps = <&rpmhpd_opp_low_svs>;
3323 #power-domain-cells = <1>;
3324 status = "disabled";
3327 pdc: interrupt-controller@b220000 {
3328 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3329 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3330 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3331 <94 609 31>, <125 63 1>, <126 716 12>;
3332 #interrupt-cells = <2>;
3333 interrupt-parent = <&intc>;
3334 interrupt-controller;
3337 tsens0: thermal-sensor@c263000 {
3338 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3339 reg = <0 0x0c263000 0 0x1000>, /* TM */
3340 <0 0x0c222000 0 0x1000>; /* SROT */
3341 #qcom,sensors = <16>;
3342 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3343 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3344 interrupt-names = "uplow", "critical";
3345 #thermal-sensor-cells = <1>;
3348 tsens1: thermal-sensor@c265000 {
3349 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3350 reg = <0 0x0c265000 0 0x1000>, /* TM */
3351 <0 0x0c223000 0 0x1000>; /* SROT */
3352 #qcom,sensors = <16>;
3353 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3354 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3355 interrupt-names = "uplow", "critical";
3356 #thermal-sensor-cells = <1>;
3359 aoss_qmp: power-management@c300000 {
3360 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3361 reg = <0 0x0c300000 0 0x400>;
3362 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3363 IRQ_TYPE_EDGE_RISING>;
3364 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3370 compatible = "qcom,rpmh-stats";
3371 reg = <0 0x0c3f0000 0 0x400>;
3374 spmi_bus: spmi@c400000 {
3375 compatible = "qcom,spmi-pmic-arb";
3376 reg = <0 0x0c400000 0 0x00003000>,
3377 <0 0x0c500000 0 0x00400000>,
3378 <0 0x0c440000 0 0x00080000>,
3379 <0 0x0c4c0000 0 0x00010000>,
3380 <0 0x0c42d000 0 0x00010000>;
3386 interrupt-names = "periph_irq";
3387 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3390 interrupt-controller;
3391 #interrupt-cells = <4>;
3392 #address-cells = <2>;
3396 ipcc: mailbox@ed18000 {
3397 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3398 reg = <0 0x0ed18000 0 0x1000>;
3399 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3400 interrupt-controller;
3401 #interrupt-cells = <3>;
3405 tlmm: pinctrl@f100000 {
3406 compatible = "qcom,sm8450-tlmm";
3407 reg = <0 0x0f100000 0 0x300000>;
3408 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3411 interrupt-controller;
3412 #interrupt-cells = <2>;
3413 gpio-ranges = <&tlmm 0 0 211>;
3414 wakeup-parent = <&pdc>;
3416 sdc2_default_state: sdc2-default-state {
3419 drive-strength = <16>;
3425 drive-strength = <16>;
3431 drive-strength = <16>;
3436 sdc2_sleep_state: sdc2-sleep-state {
3439 drive-strength = <2>;
3445 drive-strength = <2>;
3451 drive-strength = <2>;
3456 cci0_default: cci0-default-state {
3458 pins = "gpio110", "gpio111";
3459 function = "cci_i2c";
3460 drive-strength = <2>;
3464 cci0_sleep: cci0-sleep-state {
3466 pins = "gpio110", "gpio111";
3467 function = "cci_i2c";
3468 drive-strength = <2>;
3472 cci1_default: cci1-default-state {
3474 pins = "gpio112", "gpio113";
3475 function = "cci_i2c";
3476 drive-strength = <2>;
3480 cci1_sleep: cci1-sleep-state {
3482 pins = "gpio112", "gpio113";
3483 function = "cci_i2c";
3484 drive-strength = <2>;
3488 cci2_default: cci2-default-state {
3490 pins = "gpio114", "gpio115";
3491 function = "cci_i2c";
3492 drive-strength = <2>;
3496 cci2_sleep: cci2-sleep-state {
3498 pins = "gpio114", "gpio115";
3499 function = "cci_i2c";
3500 drive-strength = <2>;
3504 cci3_default: cci3-default-state {
3506 pins = "gpio208", "gpio209";
3507 function = "cci_i2c";
3508 drive-strength = <2>;
3512 cci3_sleep: cci3-sleep-state {
3514 pins = "gpio208", "gpio209";
3515 function = "cci_i2c";
3516 drive-strength = <2>;
3520 pcie0_default_state: pcie0-default-state {
3524 drive-strength = <2>;
3530 function = "pcie0_clkreqn";
3531 drive-strength = <2>;
3538 drive-strength = <2>;
3543 pcie1_default_state: pcie1-default-state {
3547 drive-strength = <2>;
3553 function = "pcie1_clkreqn";
3554 drive-strength = <2>;
3561 drive-strength = <2>;
3566 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3567 pins = "gpio0", "gpio1";
3571 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3572 pins = "gpio4", "gpio5";
3576 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3577 pins = "gpio8", "gpio9";
3581 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3582 pins = "gpio12", "gpio13";
3586 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3587 pins = "gpio16", "gpio17";
3591 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3592 pins = "gpio206", "gpio207";
3596 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3597 pins = "gpio20", "gpio21";
3601 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3602 pins = "gpio28", "gpio29";
3606 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3607 pins = "gpio32", "gpio33";
3611 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3612 pins = "gpio36", "gpio37";
3616 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3617 pins = "gpio40", "gpio41";
3621 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3622 pins = "gpio44", "gpio45";
3626 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3627 pins = "gpio48", "gpio49";
3629 drive-strength = <2>;
3633 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3634 pins = "gpio52", "gpio53";
3636 drive-strength = <2>;
3640 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3641 pins = "gpio56", "gpio57";
3645 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3646 pins = "gpio60", "gpio61";
3650 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3651 pins = "gpio64", "gpio65";
3655 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3656 pins = "gpio68", "gpio69";
3660 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3661 pins = "gpio72", "gpio73";
3665 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3666 pins = "gpio76", "gpio77";
3670 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3671 pins = "gpio80", "gpio81";
3675 qup_spi0_cs: qup-spi0-cs-state {
3680 qup_spi0_data_clk: qup-spi0-data-clk-state {
3681 pins = "gpio0", "gpio1", "gpio2";
3685 qup_spi1_cs: qup-spi1-cs-state {
3690 qup_spi1_data_clk: qup-spi1-data-clk-state {
3691 pins = "gpio4", "gpio5", "gpio6";
3695 qup_spi2_cs: qup-spi2-cs-state {
3700 qup_spi2_data_clk: qup-spi2-data-clk-state {
3701 pins = "gpio8", "gpio9", "gpio10";
3705 qup_spi3_cs: qup-spi3-cs-state {
3710 qup_spi3_data_clk: qup-spi3-data-clk-state {
3711 pins = "gpio12", "gpio13", "gpio14";
3715 qup_spi4_cs: qup-spi4-cs-state {
3718 drive-strength = <6>;
3722 qup_spi4_data_clk: qup-spi4-data-clk-state {
3723 pins = "gpio16", "gpio17", "gpio18";
3727 qup_spi5_cs: qup-spi5-cs-state {
3732 qup_spi5_data_clk: qup-spi5-data-clk-state {
3733 pins = "gpio206", "gpio207", "gpio84";
3737 qup_spi6_cs: qup-spi6-cs-state {
3742 qup_spi6_data_clk: qup-spi6-data-clk-state {
3743 pins = "gpio20", "gpio21", "gpio22";
3747 qup_spi8_cs: qup-spi8-cs-state {
3752 qup_spi8_data_clk: qup-spi8-data-clk-state {
3753 pins = "gpio28", "gpio29", "gpio30";
3757 qup_spi9_cs: qup-spi9-cs-state {
3762 qup_spi9_data_clk: qup-spi9-data-clk-state {
3763 pins = "gpio32", "gpio33", "gpio34";
3767 qup_spi10_cs: qup-spi10-cs-state {
3772 qup_spi10_data_clk: qup-spi10-data-clk-state {
3773 pins = "gpio36", "gpio37", "gpio38";
3777 qup_spi11_cs: qup-spi11-cs-state {
3782 qup_spi11_data_clk: qup-spi11-data-clk-state {
3783 pins = "gpio40", "gpio41", "gpio42";
3787 qup_spi12_cs: qup-spi12-cs-state {
3792 qup_spi12_data_clk: qup-spi12-data-clk-state {
3793 pins = "gpio44", "gpio45", "gpio46";
3797 qup_spi13_cs: qup-spi13-cs-state {
3802 qup_spi13_data_clk: qup-spi13-data-clk-state {
3803 pins = "gpio48", "gpio49", "gpio50";
3807 qup_spi14_cs: qup-spi14-cs-state {
3812 qup_spi14_data_clk: qup-spi14-data-clk-state {
3813 pins = "gpio52", "gpio53", "gpio54";
3817 qup_spi15_cs: qup-spi15-cs-state {
3822 qup_spi15_data_clk: qup-spi15-data-clk-state {
3823 pins = "gpio56", "gpio57", "gpio58";
3827 qup_spi16_cs: qup-spi16-cs-state {
3832 qup_spi16_data_clk: qup-spi16-data-clk-state {
3833 pins = "gpio60", "gpio61", "gpio62";
3837 qup_spi17_cs: qup-spi17-cs-state {
3842 qup_spi17_data_clk: qup-spi17-data-clk-state {
3843 pins = "gpio64", "gpio65", "gpio66";
3847 qup_spi18_cs: qup-spi18-cs-state {
3850 drive-strength = <6>;
3854 qup_spi18_data_clk: qup-spi18-data-clk-state {
3855 pins = "gpio68", "gpio69", "gpio70";
3857 drive-strength = <6>;
3861 qup_spi19_cs: qup-spi19-cs-state {
3864 drive-strength = <6>;
3868 qup_spi19_data_clk: qup-spi19-data-clk-state {
3869 pins = "gpio72", "gpio73", "gpio74";
3871 drive-strength = <6>;
3875 qup_spi20_cs: qup-spi20-cs-state {
3880 qup_spi20_data_clk: qup-spi20-data-clk-state {
3881 pins = "gpio76", "gpio77", "gpio78";
3885 qup_spi21_cs: qup-spi21-cs-state {
3890 qup_spi21_data_clk: qup-spi21-data-clk-state {
3891 pins = "gpio80", "gpio81", "gpio82";
3895 qup_uart7_rx: qup-uart7-rx-state {
3898 drive-strength = <2>;
3902 qup_uart7_tx: qup-uart7-tx-state {
3905 drive-strength = <2>;
3909 qup_uart20_default: qup-uart20-default-state {
3910 pins = "gpio76", "gpio77", "gpio78", "gpio79";
3915 lpass_tlmm: pinctrl@3440000 {
3916 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
3917 reg = <0 0x03440000 0x0 0x20000>,
3918 <0 0x034d0000 0x0 0x10000>;
3921 gpio-ranges = <&lpass_tlmm 0 0 23>;
3923 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3924 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3925 clock-names = "core", "audio";
3927 tx_swr_active: tx-swr-active-state {
3930 function = "swr_tx_clk";
3931 drive-strength = <2>;
3937 pins = "gpio1", "gpio2", "gpio14";
3938 function = "swr_tx_data";
3939 drive-strength = <2>;
3945 rx_swr_active: rx-swr-active-state {
3948 function = "swr_rx_clk";
3949 drive-strength = <2>;
3955 pins = "gpio4", "gpio5";
3956 function = "swr_rx_data";
3957 drive-strength = <2>;
3963 dmic01_default: dmic01-default-state {
3966 function = "dmic1_clk";
3967 drive-strength = <8>;
3973 function = "dmic1_data";
3974 drive-strength = <8>;
3978 dmic23_default: dmic23-default-state {
3981 function = "dmic2_clk";
3982 drive-strength = <8>;
3988 function = "dmic2_data";
3989 drive-strength = <8>;
3993 wsa_swr_active: wsa-swr-active-state {
3996 function = "wsa_swr_clk";
3997 drive-strength = <2>;
4004 function = "wsa_swr_data";
4005 drive-strength = <2>;
4011 wsa2_swr_active: wsa2-swr-active-state {
4014 function = "wsa2_swr_clk";
4015 drive-strength = <2>;
4022 function = "wsa2_swr_data";
4023 drive-strength = <2>;
4031 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4032 reg = <0 0x146aa000 0 0x1000>;
4033 ranges = <0 0 0x146aa000 0x1000>;
4035 #address-cells = <1>;
4039 compatible = "qcom,pil-reloc-info";
4044 apps_smmu: iommu@15000000 {
4045 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4046 reg = <0 0x15000000 0 0x100000>;
4048 #global-interrupts = <1>;
4049 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4050 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4051 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4052 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4053 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4054 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4055 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4056 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4057 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4058 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4059 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4060 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4061 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4062 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4063 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4064 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4065 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4066 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4067 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4068 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4069 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4070 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4071 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4072 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4073 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4074 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4075 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4076 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4077 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4078 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4079 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4080 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4081 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4082 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4083 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4084 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4085 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4086 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4087 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4088 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4089 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4090 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4091 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4092 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4093 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4094 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4095 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4096 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4097 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4098 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4099 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4100 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4101 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4102 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4103 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4104 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4105 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4106 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4107 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4108 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4109 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4110 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4111 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4112 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4113 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4114 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4115 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4116 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4117 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4118 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4119 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4120 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4121 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4122 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4123 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4124 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4125 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4126 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4127 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4128 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4129 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4130 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4131 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4132 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4133 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4134 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4135 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4136 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4137 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4138 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4139 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4140 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4141 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4142 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4143 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4144 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4145 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4148 intc: interrupt-controller@17100000 {
4149 compatible = "arm,gic-v3";
4150 #interrupt-cells = <3>;
4151 interrupt-controller;
4152 #redistributor-regions = <1>;
4153 redistributor-stride = <0x0 0x40000>;
4154 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
4155 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
4156 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4157 #address-cells = <2>;
4161 gic_its: msi-controller@17140000 {
4162 compatible = "arm,gic-v3-its";
4163 reg = <0x0 0x17140000 0x0 0x20000>;
4170 compatible = "arm,armv7-timer-mem";
4171 #address-cells = <1>;
4173 ranges = <0 0 0 0x20000000>;
4174 reg = <0x0 0x17420000 0x0 0x1000>;
4175 clock-frequency = <19200000>;
4179 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4180 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4181 reg = <0x17421000 0x1000>,
4182 <0x17422000 0x1000>;
4187 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4188 reg = <0x17423000 0x1000>;
4189 status = "disabled";
4194 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4195 reg = <0x17425000 0x1000>;
4196 status = "disabled";
4201 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4202 reg = <0x17427000 0x1000>;
4203 status = "disabled";
4208 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4209 reg = <0x17429000 0x1000>;
4210 status = "disabled";
4215 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4216 reg = <0x1742b000 0x1000>;
4217 status = "disabled";
4222 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4223 reg = <0x1742d000 0x1000>;
4224 status = "disabled";
4228 apps_rsc: rsc@17a00000 {
4230 compatible = "qcom,rpmh-rsc";
4231 reg = <0x0 0x17a00000 0x0 0x10000>,
4232 <0x0 0x17a10000 0x0 0x10000>,
4233 <0x0 0x17a20000 0x0 0x10000>,
4234 <0x0 0x17a30000 0x0 0x10000>;
4235 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4236 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4239 qcom,tcs-offset = <0xd00>;
4241 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4242 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4243 power-domains = <&CLUSTER_PD>;
4245 apps_bcm_voter: bcm-voter {
4246 compatible = "qcom,bcm-voter";
4249 rpmhcc: clock-controller {
4250 compatible = "qcom,sm8450-rpmh-clk";
4253 clocks = <&xo_board>;
4256 rpmhpd: power-controller {
4257 compatible = "qcom,sm8450-rpmhpd";
4258 #power-domain-cells = <1>;
4259 operating-points-v2 = <&rpmhpd_opp_table>;
4261 rpmhpd_opp_table: opp-table {
4262 compatible = "operating-points-v2";
4264 rpmhpd_opp_ret: opp1 {
4265 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4268 rpmhpd_opp_min_svs: opp2 {
4269 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4272 rpmhpd_opp_low_svs_d1: opp3 {
4273 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4276 rpmhpd_opp_low_svs: opp4 {
4277 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4280 rpmhpd_opp_low_svs_l1: opp5 {
4281 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4284 rpmhpd_opp_svs: opp6 {
4285 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4288 rpmhpd_opp_svs_l0: opp7 {
4289 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4292 rpmhpd_opp_svs_l1: opp8 {
4293 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4296 rpmhpd_opp_svs_l2: opp9 {
4297 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4300 rpmhpd_opp_nom: opp10 {
4301 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4304 rpmhpd_opp_nom_l1: opp11 {
4305 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4308 rpmhpd_opp_nom_l2: opp12 {
4309 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4312 rpmhpd_opp_turbo: opp13 {
4313 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4316 rpmhpd_opp_turbo_l1: opp14 {
4317 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4323 cpufreq_hw: cpufreq@17d91000 {
4324 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4325 reg = <0 0x17d91000 0 0x1000>,
4326 <0 0x17d92000 0 0x1000>,
4327 <0 0x17d93000 0 0x1000>;
4328 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4329 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4330 clock-names = "xo", "alternate";
4331 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4332 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4333 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4334 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4335 #freq-domain-cells = <1>;
4339 gem_noc: interconnect@19100000 {
4340 compatible = "qcom,sm8450-gem-noc";
4341 reg = <0 0x19100000 0 0xbb800>;
4342 #interconnect-cells = <2>;
4343 qcom,bcm-voters = <&apps_bcm_voter>;
4346 system-cache-controller@19200000 {
4347 compatible = "qcom,sm8450-llcc";
4348 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4349 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4350 <0 0x19a00000 0 0x80000>;
4351 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4352 "llcc3_base", "llcc_broadcast_base";
4353 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4356 ufs_mem_hc: ufshc@1d84000 {
4357 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4359 reg = <0 0x01d84000 0 0x3000>;
4360 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4361 phys = <&ufs_mem_phy>;
4362 phy-names = "ufsphy";
4363 lanes-per-direction = <2>;
4365 resets = <&gcc GCC_UFS_PHY_BCR>;
4366 reset-names = "rst";
4368 power-domains = <&gcc UFS_PHY_GDSC>;
4370 iommus = <&apps_smmu 0xe0 0x0>;
4373 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4374 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4375 interconnect-names = "ufs-ddr", "cpu-ufs";
4382 "tx_lane0_sync_clk",
4383 "rx_lane0_sync_clk",
4384 "rx_lane1_sync_clk";
4386 <&gcc GCC_UFS_PHY_AXI_CLK>,
4387 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4388 <&gcc GCC_UFS_PHY_AHB_CLK>,
4389 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4390 <&rpmhcc RPMH_CXO_CLK>,
4391 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4392 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4393 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4395 <75000000 300000000>,
4398 <75000000 300000000>,
4399 <75000000 300000000>,
4405 status = "disabled";
4408 ufs_mem_phy: phy@1d87000 {
4409 compatible = "qcom,sm8450-qmp-ufs-phy";
4410 reg = <0 0x01d87000 0 0x1000>;
4412 clock-names = "ref", "ref_aux", "qref";
4413 clocks = <&rpmhcc RPMH_CXO_CLK>,
4414 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4415 <&gcc GCC_UFS_0_CLKREF_EN>;
4417 resets = <&ufs_mem_hc 0>;
4418 reset-names = "ufsphy";
4423 status = "disabled";
4426 ice: crypto@1d88000 {
4427 compatible = "qcom,sm8450-inline-crypto-engine",
4428 "qcom,inline-crypto-engine";
4429 reg = <0 0x01d88000 0 0x8000>;
4430 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4433 cryptobam: dma-controller@1dc4000 {
4434 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4435 reg = <0 0x01dc4000 0 0x28000>;
4436 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4439 qcom,controlled-remotely;
4440 iommus = <&apps_smmu 0x584 0x11>,
4441 <&apps_smmu 0x588 0x0>,
4442 <&apps_smmu 0x598 0x5>,
4443 <&apps_smmu 0x59a 0x0>,
4444 <&apps_smmu 0x59f 0x0>;
4447 crypto: crypto@1dfa000 {
4448 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4449 reg = <0 0x01dfa000 0 0x6000>;
4450 dmas = <&cryptobam 4>, <&cryptobam 5>;
4451 dma-names = "rx", "tx";
4452 iommus = <&apps_smmu 0x584 0x11>,
4453 <&apps_smmu 0x588 0x0>,
4454 <&apps_smmu 0x598 0x5>,
4455 <&apps_smmu 0x59a 0x0>,
4456 <&apps_smmu 0x59f 0x0>;
4457 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4458 interconnect-names = "memory";
4461 sdhc_2: mmc@8804000 {
4462 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4463 reg = <0 0x08804000 0 0x1000>;
4465 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4466 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4467 interrupt-names = "hc_irq", "pwr_irq";
4469 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4470 <&gcc GCC_SDCC2_APPS_CLK>,
4471 <&rpmhcc RPMH_CXO_CLK>;
4472 clock-names = "iface", "core", "xo";
4473 resets = <&gcc GCC_SDCC2_BCR>;
4474 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4475 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4476 interconnect-names = "sdhc-ddr","cpu-sdhc";
4477 iommus = <&apps_smmu 0x4a0 0x0>;
4478 power-domains = <&rpmhpd RPMHPD_CX>;
4479 operating-points-v2 = <&sdhc2_opp_table>;
4483 /* Forbid SDR104/SDR50 - broken hw! */
4484 sdhci-caps-mask = <0x3 0x0>;
4486 status = "disabled";
4488 sdhc2_opp_table: opp-table {
4489 compatible = "operating-points-v2";
4492 opp-hz = /bits/ 64 <100000000>;
4493 required-opps = <&rpmhpd_opp_low_svs>;
4497 opp-hz = /bits/ 64 <202000000>;
4498 required-opps = <&rpmhpd_opp_svs_l1>;
4503 usb_1: usb@a6f8800 {
4504 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4505 reg = <0 0x0a6f8800 0 0x400>;
4506 status = "disabled";
4507 #address-cells = <2>;
4511 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4512 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4513 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4514 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4515 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4516 <&gcc GCC_USB3_0_CLKREF_EN>;
4517 clock-names = "cfg_noc",
4524 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4525 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4526 assigned-clock-rates = <19200000>, <200000000>;
4528 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4529 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4530 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4531 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4532 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4533 interrupt-names = "pwr_event",
4539 power-domains = <&gcc USB30_PRIM_GDSC>;
4541 resets = <&gcc GCC_USB30_PRIM_BCR>;
4543 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4544 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4545 interconnect-names = "usb-ddr", "apps-usb";
4547 usb_1_dwc3: usb@a600000 {
4548 compatible = "snps,dwc3";
4549 reg = <0 0x0a600000 0 0xcd00>;
4550 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4551 iommus = <&apps_smmu 0x0 0x0>;
4552 snps,dis_u2_susphy_quirk;
4553 snps,dis_enblslpm_quirk;
4554 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4555 phy-names = "usb2-phy", "usb3-phy";
4558 #address-cells = <1>;
4564 usb_1_dwc3_hs: endpoint {
4571 usb_1_dwc3_ss: endpoint {
4578 nsp_noc: interconnect@320c0000 {
4579 compatible = "qcom,sm8450-nsp-noc";
4580 reg = <0 0x320c0000 0 0x10000>;
4581 #interconnect-cells = <2>;
4582 qcom,bcm-voters = <&apps_bcm_voter>;
4585 lpass_ag_noc: interconnect@3c40000 {
4586 compatible = "qcom,sm8450-lpass-ag-noc";
4587 reg = <0 0x03c40000 0 0x17200>;
4588 #interconnect-cells = <2>;
4589 qcom,bcm-voters = <&apps_bcm_voter>;
4598 polling-delay-passive = <0>;
4599 polling-delay = <0>;
4600 thermal-sensors = <&tsens0 0>;
4603 thermal-engine-config {
4604 temperature = <125000>;
4605 hysteresis = <1000>;
4610 temperature = <115000>;
4611 hysteresis = <5000>;
4618 polling-delay-passive = <0>;
4619 polling-delay = <0>;
4620 thermal-sensors = <&tsens0 1>;
4623 thermal-engine-config {
4624 temperature = <125000>;
4625 hysteresis = <1000>;
4630 temperature = <115000>;
4631 hysteresis = <5000>;
4638 polling-delay-passive = <0>;
4639 polling-delay = <0>;
4640 thermal-sensors = <&tsens0 2>;
4643 thermal-engine-config {
4644 temperature = <125000>;
4645 hysteresis = <1000>;
4650 temperature = <115000>;
4651 hysteresis = <5000>;
4658 polling-delay-passive = <0>;
4659 polling-delay = <0>;
4660 thermal-sensors = <&tsens0 3>;
4663 thermal-engine-config {
4664 temperature = <125000>;
4665 hysteresis = <1000>;
4670 temperature = <115000>;
4671 hysteresis = <5000>;
4678 polling-delay-passive = <0>;
4679 polling-delay = <0>;
4680 thermal-sensors = <&tsens0 4>;
4683 thermal-engine-config {
4684 temperature = <125000>;
4685 hysteresis = <1000>;
4690 temperature = <115000>;
4691 hysteresis = <5000>;
4698 polling-delay-passive = <0>;
4699 polling-delay = <0>;
4700 thermal-sensors = <&tsens0 5>;
4703 cpu4_top_alert0: trip-point0 {
4704 temperature = <90000>;
4705 hysteresis = <2000>;
4709 cpu4_top_alert1: trip-point1 {
4710 temperature = <95000>;
4711 hysteresis = <2000>;
4715 cpu4_top_crit: cpu-crit {
4716 temperature = <110000>;
4717 hysteresis = <1000>;
4723 cpu4-bottom-thermal {
4724 polling-delay-passive = <0>;
4725 polling-delay = <0>;
4726 thermal-sensors = <&tsens0 6>;
4729 cpu4_bottom_alert0: trip-point0 {
4730 temperature = <90000>;
4731 hysteresis = <2000>;
4735 cpu4_bottom_alert1: trip-point1 {
4736 temperature = <95000>;
4737 hysteresis = <2000>;
4741 cpu4_bottom_crit: cpu-crit {
4742 temperature = <110000>;
4743 hysteresis = <1000>;
4750 polling-delay-passive = <0>;
4751 polling-delay = <0>;
4752 thermal-sensors = <&tsens0 7>;
4755 cpu5_top_alert0: trip-point0 {
4756 temperature = <90000>;
4757 hysteresis = <2000>;
4761 cpu5_top_alert1: trip-point1 {
4762 temperature = <95000>;
4763 hysteresis = <2000>;
4767 cpu5_top_crit: cpu-crit {
4768 temperature = <110000>;
4769 hysteresis = <1000>;
4775 cpu5-bottom-thermal {
4776 polling-delay-passive = <0>;
4777 polling-delay = <0>;
4778 thermal-sensors = <&tsens0 8>;
4781 cpu5_bottom_alert0: trip-point0 {
4782 temperature = <90000>;
4783 hysteresis = <2000>;
4787 cpu5_bottom_alert1: trip-point1 {
4788 temperature = <95000>;
4789 hysteresis = <2000>;
4793 cpu5_bottom_crit: cpu-crit {
4794 temperature = <110000>;
4795 hysteresis = <1000>;
4802 polling-delay-passive = <0>;
4803 polling-delay = <0>;
4804 thermal-sensors = <&tsens0 9>;
4807 cpu6_top_alert0: trip-point0 {
4808 temperature = <90000>;
4809 hysteresis = <2000>;
4813 cpu6_top_alert1: trip-point1 {
4814 temperature = <95000>;
4815 hysteresis = <2000>;
4819 cpu6_top_crit: cpu-crit {
4820 temperature = <110000>;
4821 hysteresis = <1000>;
4827 cpu6-bottom-thermal {
4828 polling-delay-passive = <0>;
4829 polling-delay = <0>;
4830 thermal-sensors = <&tsens0 10>;
4833 cpu6_bottom_alert0: trip-point0 {
4834 temperature = <90000>;
4835 hysteresis = <2000>;
4839 cpu6_bottom_alert1: trip-point1 {
4840 temperature = <95000>;
4841 hysteresis = <2000>;
4845 cpu6_bottom_crit: cpu-crit {
4846 temperature = <110000>;
4847 hysteresis = <1000>;
4854 polling-delay-passive = <0>;
4855 polling-delay = <0>;
4856 thermal-sensors = <&tsens0 11>;
4859 cpu7_top_alert0: trip-point0 {
4860 temperature = <90000>;
4861 hysteresis = <2000>;
4865 cpu7_top_alert1: trip-point1 {
4866 temperature = <95000>;
4867 hysteresis = <2000>;
4871 cpu7_top_crit: cpu-crit {
4872 temperature = <110000>;
4873 hysteresis = <1000>;
4879 cpu7-middle-thermal {
4880 polling-delay-passive = <0>;
4881 polling-delay = <0>;
4882 thermal-sensors = <&tsens0 12>;
4885 cpu7_middle_alert0: trip-point0 {
4886 temperature = <90000>;
4887 hysteresis = <2000>;
4891 cpu7_middle_alert1: trip-point1 {
4892 temperature = <95000>;
4893 hysteresis = <2000>;
4897 cpu7_middle_crit: cpu-crit {
4898 temperature = <110000>;
4899 hysteresis = <1000>;
4905 cpu7-bottom-thermal {
4906 polling-delay-passive = <0>;
4907 polling-delay = <0>;
4908 thermal-sensors = <&tsens0 13>;
4911 cpu7_bottom_alert0: trip-point0 {
4912 temperature = <90000>;
4913 hysteresis = <2000>;
4917 cpu7_bottom_alert1: trip-point1 {
4918 temperature = <95000>;
4919 hysteresis = <2000>;
4923 cpu7_bottom_crit: cpu-crit {
4924 temperature = <110000>;
4925 hysteresis = <1000>;
4932 polling-delay-passive = <10>;
4933 polling-delay = <0>;
4934 thermal-sensors = <&tsens0 14>;
4938 trip = <&gpu_top_alert0>;
4939 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4944 thermal-engine-config {
4945 temperature = <125000>;
4946 hysteresis = <1000>;
4950 thermal-hal-config {
4951 temperature = <125000>;
4952 hysteresis = <1000>;
4957 temperature = <115000>;
4958 hysteresis = <5000>;
4962 gpu_top_alert0: trip-point0 {
4963 temperature = <95000>;
4964 hysteresis = <5000>;
4970 gpu-bottom-thermal {
4971 polling-delay-passive = <10>;
4972 polling-delay = <0>;
4973 thermal-sensors = <&tsens0 15>;
4977 trip = <&gpu_bottom_alert0>;
4978 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4983 thermal-engine-config {
4984 temperature = <125000>;
4985 hysteresis = <1000>;
4989 thermal-hal-config {
4990 temperature = <125000>;
4991 hysteresis = <1000>;
4996 temperature = <115000>;
4997 hysteresis = <5000>;
5001 gpu_bottom_alert0: trip-point0 {
5002 temperature = <95000>;
5003 hysteresis = <5000>;
5010 polling-delay-passive = <0>;
5011 polling-delay = <0>;
5012 thermal-sensors = <&tsens1 0>;
5015 thermal-engine-config {
5016 temperature = <125000>;
5017 hysteresis = <1000>;
5022 temperature = <115000>;
5023 hysteresis = <5000>;
5030 polling-delay-passive = <0>;
5031 polling-delay = <0>;
5032 thermal-sensors = <&tsens1 1>;
5035 cpu0_alert0: trip-point0 {
5036 temperature = <90000>;
5037 hysteresis = <2000>;
5041 cpu0_alert1: trip-point1 {
5042 temperature = <95000>;
5043 hysteresis = <2000>;
5047 cpu0_crit: cpu-crit {
5048 temperature = <110000>;
5049 hysteresis = <1000>;
5056 polling-delay-passive = <0>;
5057 polling-delay = <0>;
5058 thermal-sensors = <&tsens1 2>;
5061 cpu1_alert0: trip-point0 {
5062 temperature = <90000>;
5063 hysteresis = <2000>;
5067 cpu1_alert1: trip-point1 {
5068 temperature = <95000>;
5069 hysteresis = <2000>;
5073 cpu1_crit: cpu-crit {
5074 temperature = <110000>;
5075 hysteresis = <1000>;
5082 polling-delay-passive = <0>;
5083 polling-delay = <0>;
5084 thermal-sensors = <&tsens1 3>;
5087 cpu2_alert0: trip-point0 {
5088 temperature = <90000>;
5089 hysteresis = <2000>;
5093 cpu2_alert1: trip-point1 {
5094 temperature = <95000>;
5095 hysteresis = <2000>;
5099 cpu2_crit: cpu-crit {
5100 temperature = <110000>;
5101 hysteresis = <1000>;
5108 polling-delay-passive = <0>;
5109 polling-delay = <0>;
5110 thermal-sensors = <&tsens1 4>;
5113 cpu3_alert0: trip-point0 {
5114 temperature = <90000>;
5115 hysteresis = <2000>;
5119 cpu3_alert1: trip-point1 {
5120 temperature = <95000>;
5121 hysteresis = <2000>;
5125 cpu3_crit: cpu-crit {
5126 temperature = <110000>;
5127 hysteresis = <1000>;
5134 polling-delay-passive = <10>;
5135 polling-delay = <0>;
5136 thermal-sensors = <&tsens1 5>;
5139 thermal-engine-config {
5140 temperature = <125000>;
5141 hysteresis = <1000>;
5145 thermal-hal-config {
5146 temperature = <125000>;
5147 hysteresis = <1000>;
5152 temperature = <115000>;
5153 hysteresis = <5000>;
5157 cdsp_0_config: junction-config {
5158 temperature = <95000>;
5159 hysteresis = <5000>;
5166 polling-delay-passive = <10>;
5167 polling-delay = <0>;
5168 thermal-sensors = <&tsens1 6>;
5171 thermal-engine-config {
5172 temperature = <125000>;
5173 hysteresis = <1000>;
5177 thermal-hal-config {
5178 temperature = <125000>;
5179 hysteresis = <1000>;
5184 temperature = <115000>;
5185 hysteresis = <5000>;
5189 cdsp_1_config: junction-config {
5190 temperature = <95000>;
5191 hysteresis = <5000>;
5198 polling-delay-passive = <10>;
5199 polling-delay = <0>;
5200 thermal-sensors = <&tsens1 7>;
5203 thermal-engine-config {
5204 temperature = <125000>;
5205 hysteresis = <1000>;
5209 thermal-hal-config {
5210 temperature = <125000>;
5211 hysteresis = <1000>;
5216 temperature = <115000>;
5217 hysteresis = <5000>;
5221 cdsp_2_config: junction-config {
5222 temperature = <95000>;
5223 hysteresis = <5000>;
5230 polling-delay-passive = <0>;
5231 polling-delay = <0>;
5232 thermal-sensors = <&tsens1 8>;
5235 thermal-engine-config {
5236 temperature = <125000>;
5237 hysteresis = <1000>;
5242 temperature = <115000>;
5243 hysteresis = <5000>;
5250 polling-delay-passive = <10>;
5251 polling-delay = <0>;
5252 thermal-sensors = <&tsens1 9>;
5255 thermal-engine-config {
5256 temperature = <125000>;
5257 hysteresis = <1000>;
5261 ddr_config0: ddr0-config {
5262 temperature = <90000>;
5263 hysteresis = <5000>;
5268 temperature = <115000>;
5269 hysteresis = <5000>;
5276 polling-delay-passive = <0>;
5277 polling-delay = <0>;
5278 thermal-sensors = <&tsens1 10>;
5281 thermal-engine-config {
5282 temperature = <125000>;
5283 hysteresis = <1000>;
5287 mdmss0_config0: mdmss0-config0 {
5288 temperature = <102000>;
5289 hysteresis = <3000>;
5293 mdmss0_config1: mdmss0-config1 {
5294 temperature = <105000>;
5295 hysteresis = <3000>;
5300 temperature = <115000>;
5301 hysteresis = <5000>;
5308 polling-delay-passive = <0>;
5309 polling-delay = <0>;
5310 thermal-sensors = <&tsens1 11>;
5313 thermal-engine-config {
5314 temperature = <125000>;
5315 hysteresis = <1000>;
5319 mdmss1_config0: mdmss1-config0 {
5320 temperature = <102000>;
5321 hysteresis = <3000>;
5325 mdmss1_config1: mdmss1-config1 {
5326 temperature = <105000>;
5327 hysteresis = <3000>;
5332 temperature = <115000>;
5333 hysteresis = <5000>;
5340 polling-delay-passive = <0>;
5341 polling-delay = <0>;
5342 thermal-sensors = <&tsens1 12>;
5345 thermal-engine-config {
5346 temperature = <125000>;
5347 hysteresis = <1000>;
5351 mdmss2_config0: mdmss2-config0 {
5352 temperature = <102000>;
5353 hysteresis = <3000>;
5357 mdmss2_config1: mdmss2-config1 {
5358 temperature = <105000>;
5359 hysteresis = <3000>;
5364 temperature = <115000>;
5365 hysteresis = <5000>;
5372 polling-delay-passive = <0>;
5373 polling-delay = <0>;
5374 thermal-sensors = <&tsens1 13>;
5377 thermal-engine-config {
5378 temperature = <125000>;
5379 hysteresis = <1000>;
5383 mdmss3_config0: mdmss3-config0 {
5384 temperature = <102000>;
5385 hysteresis = <3000>;
5389 mdmss3_config1: mdmss3-config1 {
5390 temperature = <105000>;
5391 hysteresis = <3000>;
5396 temperature = <115000>;
5397 hysteresis = <5000>;
5404 polling-delay-passive = <0>;
5405 polling-delay = <0>;
5406 thermal-sensors = <&tsens1 14>;
5409 thermal-engine-config {
5410 temperature = <125000>;
5411 hysteresis = <1000>;
5416 temperature = <115000>;
5417 hysteresis = <5000>;
5424 polling-delay-passive = <0>;
5425 polling-delay = <0>;
5426 thermal-sensors = <&tsens1 15>;
5429 thermal-engine-config {
5430 temperature = <125000>;
5431 hysteresis = <1000>;
5436 temperature = <115000>;
5437 hysteresis = <5000>;
5445 compatible = "arm,armv8-timer";
5446 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5447 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5448 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5449 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5450 clock-frequency = <19200000>;