1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2021, Linaro Limited
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/mailbox/qcom-ipcc.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/interconnect/qcom,sm8450.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&intc>;
27 compatible = "fixed-clock";
29 clock-frequency = <76800000>;
32 sleep_clk: sleep-clk {
33 compatible = "fixed-clock";
35 clock-frequency = <32000>;
45 compatible = "qcom,kryo780";
47 enable-method = "psci";
48 next-level-cache = <&L2_0>;
49 power-domains = <&CPU_PD0>;
50 power-domain-names = "psci";
51 qcom,freq-domain = <&cpufreq_hw 0>;
55 next-level-cache = <&L3_0>;
64 compatible = "qcom,kryo780";
66 enable-method = "psci";
67 next-level-cache = <&L2_100>;
68 power-domains = <&CPU_PD1>;
69 power-domain-names = "psci";
70 qcom,freq-domain = <&cpufreq_hw 0>;
74 next-level-cache = <&L3_0>;
80 compatible = "qcom,kryo780";
82 enable-method = "psci";
83 next-level-cache = <&L2_200>;
84 power-domains = <&CPU_PD2>;
85 power-domain-names = "psci";
86 qcom,freq-domain = <&cpufreq_hw 0>;
90 next-level-cache = <&L3_0>;
96 compatible = "qcom,kryo780";
98 enable-method = "psci";
99 next-level-cache = <&L2_300>;
100 power-domains = <&CPU_PD3>;
101 power-domain-names = "psci";
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 #cooling-cells = <2>;
105 compatible = "cache";
106 next-level-cache = <&L3_0>;
112 compatible = "qcom,kryo780";
114 enable-method = "psci";
115 next-level-cache = <&L2_400>;
116 power-domains = <&CPU_PD4>;
117 power-domain-names = "psci";
118 qcom,freq-domain = <&cpufreq_hw 1>;
119 #cooling-cells = <2>;
121 compatible = "cache";
122 next-level-cache = <&L3_0>;
128 compatible = "qcom,kryo780";
130 enable-method = "psci";
131 next-level-cache = <&L2_500>;
132 power-domains = <&CPU_PD5>;
133 power-domain-names = "psci";
134 qcom,freq-domain = <&cpufreq_hw 1>;
135 #cooling-cells = <2>;
137 compatible = "cache";
138 next-level-cache = <&L3_0>;
145 compatible = "qcom,kryo780";
147 enable-method = "psci";
148 next-level-cache = <&L2_600>;
149 power-domains = <&CPU_PD6>;
150 power-domain-names = "psci";
151 qcom,freq-domain = <&cpufreq_hw 1>;
152 #cooling-cells = <2>;
154 compatible = "cache";
155 next-level-cache = <&L3_0>;
161 compatible = "qcom,kryo780";
163 enable-method = "psci";
164 next-level-cache = <&L2_700>;
165 power-domains = <&CPU_PD7>;
166 power-domain-names = "psci";
167 qcom,freq-domain = <&cpufreq_hw 2>;
168 #cooling-cells = <2>;
170 compatible = "cache";
171 next-level-cache = <&L3_0>;
212 entry-method = "psci";
214 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
215 compatible = "arm,idle-state";
216 idle-state-name = "silver-rail-power-collapse";
217 arm,psci-suspend-param = <0x40000004>;
218 entry-latency-us = <800>;
219 exit-latency-us = <750>;
220 min-residency-us = <4090>;
224 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
225 compatible = "arm,idle-state";
226 idle-state-name = "gold-rail-power-collapse";
227 arm,psci-suspend-param = <0x40000004>;
228 entry-latency-us = <600>;
229 exit-latency-us = <1550>;
230 min-residency-us = <4791>;
236 CLUSTER_SLEEP_0: cluster-sleep-0 {
237 compatible = "domain-idle-state";
238 idle-state-name = "cluster-l3-off";
239 arm,psci-suspend-param = <0x41000044>;
240 entry-latency-us = <1050>;
241 exit-latency-us = <2500>;
242 min-residency-us = <5309>;
246 CLUSTER_SLEEP_1: cluster-sleep-1 {
247 compatible = "domain-idle-state";
248 idle-state-name = "cluster-power-collapse";
249 arm,psci-suspend-param = <0x4100c344>;
250 entry-latency-us = <2700>;
251 exit-latency-us = <3500>;
252 min-residency-us = <13959>;
260 compatible = "qcom,scm-sm8450", "qcom,scm";
265 clk_virt: interconnect@0 {
266 compatible = "qcom,sm8450-clk-virt";
267 #interconnect-cells = <2>;
268 qcom,bcm-voters = <&apps_bcm_voter>;
271 mc_virt: interconnect@1 {
272 compatible = "qcom,sm8450-mc-virt";
273 #interconnect-cells = <2>;
274 qcom,bcm-voters = <&apps_bcm_voter>;
278 device_type = "memory";
279 /* We expect the bootloader to fill in the size */
280 reg = <0x0 0xa0000000 0x0 0x0>;
284 compatible = "arm,armv8-pmuv3";
285 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
289 compatible = "arm,psci-1.0";
293 #power-domain-cells = <0>;
294 power-domains = <&CLUSTER_PD>;
295 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
299 #power-domain-cells = <0>;
300 power-domains = <&CLUSTER_PD>;
301 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
305 #power-domain-cells = <0>;
306 power-domains = <&CLUSTER_PD>;
307 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
311 #power-domain-cells = <0>;
312 power-domains = <&CLUSTER_PD>;
313 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
317 #power-domain-cells = <0>;
318 power-domains = <&CLUSTER_PD>;
319 domain-idle-states = <&BIG_CPU_SLEEP_0>;
323 #power-domain-cells = <0>;
324 power-domains = <&CLUSTER_PD>;
325 domain-idle-states = <&BIG_CPU_SLEEP_0>;
329 #power-domain-cells = <0>;
330 power-domains = <&CLUSTER_PD>;
331 domain-idle-states = <&BIG_CPU_SLEEP_0>;
335 #power-domain-cells = <0>;
336 power-domains = <&CLUSTER_PD>;
337 domain-idle-states = <&BIG_CPU_SLEEP_0>;
340 CLUSTER_PD: cpu-cluster0 {
341 #power-domain-cells = <0>;
342 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
346 qup_opp_table_100mhz: qup-100mhz-opp-table {
347 compatible = "operating-points-v2";
350 opp-hz = /bits/ 64 <50000000>;
351 required-opps = <&rpmhpd_opp_min_svs>;
355 opp-hz = /bits/ 64 <75000000>;
356 required-opps = <&rpmhpd_opp_low_svs>;
360 opp-hz = /bits/ 64 <100000000>;
361 required-opps = <&rpmhpd_opp_svs>;
365 reserved_memory: reserved-memory {
366 #address-cells = <2>;
370 hyp_mem: memory@80000000 {
371 reg = <0x0 0x80000000 0x0 0x600000>;
375 xbl_dt_log_mem: memory@80600000 {
376 reg = <0x0 0x80600000 0x0 0x40000>;
380 xbl_ramdump_mem: memory@80640000 {
381 reg = <0x0 0x80640000 0x0 0x180000>;
385 xbl_sc_mem: memory@807c0000 {
386 reg = <0x0 0x807c0000 0x0 0x40000>;
390 aop_image_mem: memory@80800000 {
391 reg = <0x0 0x80800000 0x0 0x60000>;
395 aop_cmd_db_mem: memory@80860000 {
396 compatible = "qcom,cmd-db";
397 reg = <0x0 0x80860000 0x0 0x20000>;
401 aop_config_mem: memory@80880000 {
402 reg = <0x0 0x80880000 0x0 0x20000>;
406 tme_crash_dump_mem: memory@808a0000 {
407 reg = <0x0 0x808a0000 0x0 0x40000>;
411 tme_log_mem: memory@808e0000 {
412 reg = <0x0 0x808e0000 0x0 0x4000>;
416 uefi_log_mem: memory@808e4000 {
417 reg = <0x0 0x808e4000 0x0 0x10000>;
421 /* secdata region can be reused by apps */
422 smem: memory@80900000 {
423 compatible = "qcom,smem";
424 reg = <0x0 0x80900000 0x0 0x200000>;
425 hwlocks = <&tcsr_mutex 3>;
429 cpucp_fw_mem: memory@80b00000 {
430 reg = <0x0 0x80b00000 0x0 0x100000>;
434 cdsp_secure_heap: memory@80c00000 {
435 reg = <0x0 0x80c00000 0x0 0x4600000>;
439 camera_mem: memory@85200000 {
440 reg = <0x0 0x85200000 0x0 0x500000>;
444 video_mem: memory@85700000 {
445 reg = <0x0 0x85700000 0x0 0x700000>;
449 adsp_mem: memory@85e00000 {
450 reg = <0x0 0x85e00000 0x0 0x2100000>;
454 slpi_mem: memory@88000000 {
455 reg = <0x0 0x88000000 0x0 0x1900000>;
459 cdsp_mem: memory@89900000 {
460 reg = <0x0 0x89900000 0x0 0x2000000>;
464 ipa_fw_mem: memory@8b900000 {
465 reg = <0x0 0x8b900000 0x0 0x10000>;
469 ipa_gsi_mem: memory@8b910000 {
470 reg = <0x0 0x8b910000 0x0 0xa000>;
474 gpu_micro_code_mem: memory@8b91a000 {
475 reg = <0x0 0x8b91a000 0x0 0x2000>;
479 spss_region_mem: memory@8ba00000 {
480 reg = <0x0 0x8ba00000 0x0 0x180000>;
484 /* First part of the "SPU secure shared memory" region */
485 spu_tz_shared_mem: memory@8bb80000 {
486 reg = <0x0 0x8bb80000 0x0 0x60000>;
490 /* Second part of the "SPU secure shared memory" region */
491 spu_modem_shared_mem: memory@8bbe0000 {
492 reg = <0x0 0x8bbe0000 0x0 0x20000>;
496 mpss_mem: memory@8bc00000 {
497 reg = <0x0 0x8bc00000 0x0 0x13200000>;
501 cvp_mem: memory@9ee00000 {
502 reg = <0x0 0x9ee00000 0x0 0x700000>;
506 rmtfs_mem: memory@9fd00000 {
507 compatible = "qcom,rmtfs-mem";
508 reg = <0x0 0x9fd00000 0x0 0x280000>;
511 qcom,client-id = <1>;
515 global_sync_mem: memory@a6f00000 {
516 reg = <0x0 0xa6f00000 0x0 0x100000>;
520 /* uefi region can be reused by APPS */
522 /* Linux kernel image is loaded at 0xa0000000 */
524 oem_vm_mem: memory@bb000000 {
525 reg = <0x0 0xbb000000 0x0 0x5000000>;
529 mte_mem: memory@c0000000 {
530 reg = <0x0 0xc0000000 0x0 0x20000000>;
534 qheebsp_reserved_mem: memory@e0000000 {
535 reg = <0x0 0xe0000000 0x0 0x600000>;
539 cpusys_vm_mem: memory@e0600000 {
540 reg = <0x0 0xe0600000 0x0 0x400000>;
544 hyp_reserved_mem: memory@e0a00000 {
545 reg = <0x0 0xe0a00000 0x0 0x100000>;
549 trust_ui_vm_mem: memory@e0b00000 {
550 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
554 trust_ui_vm_qrtr: memory@e55f3000 {
555 reg = <0x0 0xe55f3000 0x0 0x9000>;
559 trust_ui_vm_vblk0_ring: memory@e55fc000 {
560 reg = <0x0 0xe55fc000 0x0 0x4000>;
564 trust_ui_vm_swiotlb: memory@e5600000 {
565 reg = <0x0 0xe5600000 0x0 0x100000>;
569 tz_stat_mem: memory@e8800000 {
570 reg = <0x0 0xe8800000 0x0 0x100000>;
574 tags_mem: memory@e8900000 {
575 reg = <0x0 0xe8900000 0x0 0x1200000>;
579 qtee_mem: memory@e9b00000 {
580 reg = <0x0 0xe9b00000 0x0 0x500000>;
584 trusted_apps_mem: memory@ea000000 {
585 reg = <0x0 0xea000000 0x0 0x3900000>;
589 trusted_apps_ext_mem: memory@ed900000 {
590 reg = <0x0 0xed900000 0x0 0x3b00000>;
596 compatible = "qcom,smp2p";
597 qcom,smem = <443>, <429>;
598 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
599 IPCC_MPROC_SIGNAL_SMP2P
600 IRQ_TYPE_EDGE_RISING>;
601 mboxes = <&ipcc IPCC_CLIENT_LPASS
602 IPCC_MPROC_SIGNAL_SMP2P>;
604 qcom,local-pid = <0>;
605 qcom,remote-pid = <2>;
607 smp2p_adsp_out: master-kernel {
608 qcom,entry-name = "master-kernel";
609 #qcom,smem-state-cells = <1>;
612 smp2p_adsp_in: slave-kernel {
613 qcom,entry-name = "slave-kernel";
614 interrupt-controller;
615 #interrupt-cells = <2>;
620 compatible = "qcom,smp2p";
621 qcom,smem = <94>, <432>;
622 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
623 IPCC_MPROC_SIGNAL_SMP2P
624 IRQ_TYPE_EDGE_RISING>;
625 mboxes = <&ipcc IPCC_CLIENT_CDSP
626 IPCC_MPROC_SIGNAL_SMP2P>;
628 qcom,local-pid = <0>;
629 qcom,remote-pid = <5>;
631 smp2p_cdsp_out: master-kernel {
632 qcom,entry-name = "master-kernel";
633 #qcom,smem-state-cells = <1>;
636 smp2p_cdsp_in: slave-kernel {
637 qcom,entry-name = "slave-kernel";
638 interrupt-controller;
639 #interrupt-cells = <2>;
644 compatible = "qcom,smp2p";
645 qcom,smem = <435>, <428>;
646 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
647 IPCC_MPROC_SIGNAL_SMP2P
648 IRQ_TYPE_EDGE_RISING>;
649 mboxes = <&ipcc IPCC_CLIENT_MPSS
650 IPCC_MPROC_SIGNAL_SMP2P>;
652 qcom,local-pid = <0>;
653 qcom,remote-pid = <1>;
655 smp2p_modem_out: master-kernel {
656 qcom,entry-name = "master-kernel";
657 #qcom,smem-state-cells = <1>;
660 smp2p_modem_in: slave-kernel {
661 qcom,entry-name = "slave-kernel";
662 interrupt-controller;
663 #interrupt-cells = <2>;
666 ipa_smp2p_out: ipa-ap-to-modem {
667 qcom,entry-name = "ipa";
668 #qcom,smem-state-cells = <1>;
671 ipa_smp2p_in: ipa-modem-to-ap {
672 qcom,entry-name = "ipa";
673 interrupt-controller;
674 #interrupt-cells = <2>;
679 compatible = "qcom,smp2p";
680 qcom,smem = <481>, <430>;
681 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
682 IPCC_MPROC_SIGNAL_SMP2P
683 IRQ_TYPE_EDGE_RISING>;
684 mboxes = <&ipcc IPCC_CLIENT_SLPI
685 IPCC_MPROC_SIGNAL_SMP2P>;
687 qcom,local-pid = <0>;
688 qcom,remote-pid = <3>;
690 smp2p_slpi_out: master-kernel {
691 qcom,entry-name = "master-kernel";
692 #qcom,smem-state-cells = <1>;
695 smp2p_slpi_in: slave-kernel {
696 qcom,entry-name = "slave-kernel";
697 interrupt-controller;
698 #interrupt-cells = <2>;
703 #address-cells = <2>;
705 ranges = <0 0 0 0 0x10 0>;
706 dma-ranges = <0 0 0 0 0x10 0>;
707 compatible = "simple-bus";
709 gcc: clock-controller@100000 {
710 compatible = "qcom,gcc-sm8450";
711 reg = <0x0 0x00100000 0x0 0x1f4200>;
714 #power-domain-cells = <1>;
715 clocks = <&rpmhcc RPMH_CXO_CLK>,
719 clock-names = "bi_tcxo",
725 gpi_dma2: dma-controller@800000 {
726 compatible = "qcom,sm8450-gpi-dma";
728 reg = <0 0x800000 0 0x60000>;
729 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
742 dma-channel-mask = <0x7e>;
743 iommus = <&apps_smmu 0x496 0x0>;
747 qupv3_id_2: geniqup@8c0000 {
748 compatible = "qcom,geni-se-qup";
749 reg = <0x0 0x008c0000 0x0 0x2000>;
750 clock-names = "m-ahb", "s-ahb";
751 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
752 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
753 iommus = <&apps_smmu 0x483 0x0>;
754 #address-cells = <2>;
760 compatible = "qcom,geni-i2c";
761 reg = <0x0 0x00880000 0x0 0x4000>;
763 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&qup_i2c15_data_clk>;
766 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
767 #address-cells = <1>;
769 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
770 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
771 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
772 interconnect-names = "qup-core", "qup-config", "qup-memory";
773 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
774 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
775 dma-names = "tx", "rx";
780 compatible = "qcom,geni-spi";
781 reg = <0x0 0x00880000 0x0 0x4000>;
783 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
784 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
785 pinctrl-names = "default";
786 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
787 spi-max-frequency = <50000000>;
788 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
789 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
790 interconnect-names = "qup-core", "qup-config";
791 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
792 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
793 dma-names = "tx", "rx";
794 #address-cells = <1>;
800 compatible = "qcom,geni-i2c";
801 reg = <0x0 0x00884000 0x0 0x4000>;
803 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
804 pinctrl-names = "default";
805 pinctrl-0 = <&qup_i2c16_data_clk>;
806 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
807 #address-cells = <1>;
809 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
810 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
811 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
812 interconnect-names = "qup-core", "qup-config", "qup-memory";
813 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
814 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
815 dma-names = "tx", "rx";
820 compatible = "qcom,geni-spi";
821 reg = <0x0 0x00884000 0x0 0x4000>;
823 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
824 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
825 pinctrl-names = "default";
826 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
827 spi-max-frequency = <50000000>;
828 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
829 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
830 interconnect-names = "qup-core", "qup-config";
831 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
832 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
833 dma-names = "tx", "rx";
834 #address-cells = <1>;
840 compatible = "qcom,geni-i2c";
841 reg = <0x0 0x00888000 0x0 0x4000>;
843 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
844 pinctrl-names = "default";
845 pinctrl-0 = <&qup_i2c17_data_clk>;
846 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
847 #address-cells = <1>;
849 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
850 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
851 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
852 interconnect-names = "qup-core", "qup-config", "qup-memory";
853 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
854 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
855 dma-names = "tx", "rx";
860 compatible = "qcom,geni-spi";
861 reg = <0x0 0x00888000 0x0 0x4000>;
863 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
864 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
865 pinctrl-names = "default";
866 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
867 spi-max-frequency = <50000000>;
868 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
869 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
870 interconnect-names = "qup-core", "qup-config";
871 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
872 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
873 dma-names = "tx", "rx";
874 #address-cells = <1>;
880 compatible = "qcom,geni-i2c";
881 reg = <0x0 0x0088c000 0x0 0x4000>;
883 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
884 pinctrl-names = "default";
885 pinctrl-0 = <&qup_i2c18_data_clk>;
886 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
887 #address-cells = <1>;
889 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
890 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
891 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
892 interconnect-names = "qup-core", "qup-config", "qup-memory";
893 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
894 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
895 dma-names = "tx", "rx";
900 compatible = "qcom,geni-spi";
901 reg = <0 0x0088c000 0 0x4000>;
903 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
904 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
905 pinctrl-names = "default";
906 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
907 spi-max-frequency = <50000000>;
908 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
909 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
910 interconnect-names = "qup-core", "qup-config";
911 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
912 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
913 dma-names = "tx", "rx";
914 #address-cells = <1>;
920 compatible = "qcom,geni-i2c";
921 reg = <0x0 0x00890000 0x0 0x4000>;
923 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
924 pinctrl-names = "default";
925 pinctrl-0 = <&qup_i2c19_data_clk>;
926 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
927 #address-cells = <1>;
929 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
930 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
931 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
932 interconnect-names = "qup-core", "qup-config", "qup-memory";
933 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
934 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
935 dma-names = "tx", "rx";
940 compatible = "qcom,geni-spi";
941 reg = <0 0x00890000 0 0x4000>;
943 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
944 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
945 pinctrl-names = "default";
946 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
947 spi-max-frequency = <50000000>;
948 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
949 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
950 interconnect-names = "qup-core", "qup-config";
951 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
952 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
953 dma-names = "tx", "rx";
954 #address-cells = <1>;
960 compatible = "qcom,geni-i2c";
961 reg = <0x0 0x00894000 0x0 0x4000>;
963 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
964 pinctrl-names = "default";
965 pinctrl-0 = <&qup_i2c20_data_clk>;
966 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
967 #address-cells = <1>;
969 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
970 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
971 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
972 interconnect-names = "qup-core", "qup-config", "qup-memory";
973 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
974 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
975 dma-names = "tx", "rx";
980 compatible = "qcom,geni-spi";
981 reg = <0 0x00894000 0 0x4000>;
983 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
984 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
985 pinctrl-names = "default";
986 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
987 spi-max-frequency = <50000000>;
988 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
989 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
990 interconnect-names = "qup-core", "qup-config";
991 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
992 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
993 dma-names = "tx", "rx";
994 #address-cells = <1>;
1000 compatible = "qcom,geni-i2c";
1001 reg = <0x0 0x00898000 0x0 0x4000>;
1003 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1004 pinctrl-names = "default";
1005 pinctrl-0 = <&qup_i2c21_data_clk>;
1006 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1007 #address-cells = <1>;
1009 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1010 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1011 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1012 interconnect-names = "qup-core", "qup-config", "qup-memory";
1013 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1014 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1015 dma-names = "tx", "rx";
1016 status = "disabled";
1020 compatible = "qcom,geni-spi";
1021 reg = <0 0x00898000 0 0x4000>;
1023 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1024 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1027 spi-max-frequency = <50000000>;
1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1029 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1030 interconnect-names = "qup-core", "qup-config";
1031 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1032 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1033 dma-names = "tx", "rx";
1034 #address-cells = <1>;
1036 status = "disabled";
1040 gpi_dma0: dma-controller@900000 {
1041 compatible = "qcom,sm8450-gpi-dma";
1043 reg = <0 0x900000 0 0x60000>;
1044 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1045 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1046 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1048 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1049 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1050 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1051 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1052 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1053 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1054 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1055 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1056 dma-channels = <12>;
1057 dma-channel-mask = <0x7e>;
1058 iommus = <&apps_smmu 0x5b6 0x0>;
1059 status = "disabled";
1062 qupv3_id_0: geniqup@9c0000 {
1063 compatible = "qcom,geni-se-qup";
1064 reg = <0x0 0x009c0000 0x0 0x2000>;
1065 clock-names = "m-ahb", "s-ahb";
1066 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1067 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1068 iommus = <&apps_smmu 0x5a3 0x0>;
1069 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1070 interconnect-names = "qup-core";
1071 #address-cells = <2>;
1074 status = "disabled";
1077 compatible = "qcom,geni-i2c";
1078 reg = <0x0 0x00980000 0x0 0x4000>;
1080 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1081 pinctrl-names = "default";
1082 pinctrl-0 = <&qup_i2c0_data_clk>;
1083 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1084 #address-cells = <1>;
1086 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1087 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1088 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1089 interconnect-names = "qup-core", "qup-config", "qup-memory";
1090 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1091 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1092 dma-names = "tx", "rx";
1093 status = "disabled";
1097 compatible = "qcom,geni-spi";
1098 reg = <0x0 0x00980000 0x0 0x4000>;
1100 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1101 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1102 pinctrl-names = "default";
1103 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1104 power-domains = <&rpmhpd SM8450_CX>;
1105 operating-points-v2 = <&qup_opp_table_100mhz>;
1106 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1107 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1108 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1109 interconnect-names = "qup-core", "qup-config", "qup-memory";
1110 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1111 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1112 dma-names = "tx", "rx";
1113 #address-cells = <1>;
1115 status = "disabled";
1119 compatible = "qcom,geni-i2c";
1120 reg = <0x0 0x00984000 0x0 0x4000>;
1122 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1123 pinctrl-names = "default";
1124 pinctrl-0 = <&qup_i2c1_data_clk>;
1125 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1126 #address-cells = <1>;
1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1129 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1130 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1131 interconnect-names = "qup-core", "qup-config", "qup-memory";
1132 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1133 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1134 dma-names = "tx", "rx";
1135 status = "disabled";
1139 compatible = "qcom,geni-spi";
1140 reg = <0x0 0x00984000 0x0 0x4000>;
1142 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1143 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1144 pinctrl-names = "default";
1145 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1146 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1147 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1148 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1149 interconnect-names = "qup-core", "qup-config", "qup-memory";
1150 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1151 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1152 dma-names = "tx", "rx";
1153 #address-cells = <1>;
1155 status = "disabled";
1159 compatible = "qcom,geni-i2c";
1160 reg = <0x0 0x00988000 0x0 0x4000>;
1162 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&qup_i2c2_data_clk>;
1165 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1166 #address-cells = <1>;
1168 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1169 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1170 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1171 interconnect-names = "qup-core", "qup-config", "qup-memory";
1172 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1173 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1174 dma-names = "tx", "rx";
1175 status = "disabled";
1179 compatible = "qcom,geni-spi";
1180 reg = <0x0 0x00988000 0x0 0x4000>;
1182 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1183 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1184 pinctrl-names = "default";
1185 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1186 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1187 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1188 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1189 interconnect-names = "qup-core", "qup-config", "qup-memory";
1190 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1191 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1192 dma-names = "tx", "rx";
1193 #address-cells = <1>;
1195 status = "disabled";
1200 compatible = "qcom,geni-i2c";
1201 reg = <0x0 0x0098c000 0x0 0x4000>;
1203 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1204 pinctrl-names = "default";
1205 pinctrl-0 = <&qup_i2c3_data_clk>;
1206 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1207 #address-cells = <1>;
1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1210 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1211 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1212 interconnect-names = "qup-core", "qup-config", "qup-memory";
1213 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1214 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1215 dma-names = "tx", "rx";
1216 status = "disabled";
1220 compatible = "qcom,geni-spi";
1221 reg = <0x0 0x0098c000 0x0 0x4000>;
1223 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1224 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1225 pinctrl-names = "default";
1226 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1232 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1233 dma-names = "tx", "rx";
1234 #address-cells = <1>;
1236 status = "disabled";
1240 compatible = "qcom,geni-i2c";
1241 reg = <0x0 0x00990000 0x0 0x4000>;
1243 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1244 pinctrl-names = "default";
1245 pinctrl-0 = <&qup_i2c4_data_clk>;
1246 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1247 #address-cells = <1>;
1249 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1250 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1251 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1252 interconnect-names = "qup-core", "qup-config", "qup-memory";
1253 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1254 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1255 dma-names = "tx", "rx";
1256 status = "disabled";
1260 compatible = "qcom,geni-spi";
1261 reg = <0x0 0x00990000 0x0 0x4000>;
1263 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1264 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1267 power-domains = <&rpmhpd SM8450_CX>;
1268 operating-points-v2 = <&qup_opp_table_100mhz>;
1269 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1270 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1271 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1272 interconnect-names = "qup-core", "qup-config", "qup-memory";
1273 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1274 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1275 dma-names = "tx", "rx";
1276 #address-cells = <1>;
1278 status = "disabled";
1282 compatible = "qcom,geni-i2c";
1283 reg = <0x0 0x00994000 0x0 0x4000>;
1285 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1286 pinctrl-names = "default";
1287 pinctrl-0 = <&qup_i2c5_data_clk>;
1288 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1289 #address-cells = <1>;
1291 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1292 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1293 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1294 interconnect-names = "qup-core", "qup-config", "qup-memory";
1295 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1296 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1297 dma-names = "tx", "rx";
1298 status = "disabled";
1302 compatible = "qcom,geni-spi";
1303 reg = <0x0 0x00994000 0x0 0x4000>;
1305 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1306 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1307 pinctrl-names = "default";
1308 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1309 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1310 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1311 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1312 interconnect-names = "qup-core", "qup-config", "qup-memory";
1313 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1314 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1315 dma-names = "tx", "rx";
1316 #address-cells = <1>;
1318 status = "disabled";
1323 compatible = "qcom,geni-i2c";
1324 reg = <0x0 0x998000 0x0 0x4000>;
1326 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1327 pinctrl-names = "default";
1328 pinctrl-0 = <&qup_i2c6_data_clk>;
1329 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1330 #address-cells = <1>;
1332 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1333 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1334 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1335 interconnect-names = "qup-core", "qup-config", "qup-memory";
1336 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1337 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1338 dma-names = "tx", "rx";
1339 status = "disabled";
1343 compatible = "qcom,geni-spi";
1344 reg = <0x0 0x998000 0x0 0x4000>;
1346 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1347 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1348 pinctrl-names = "default";
1349 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1355 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1356 dma-names = "tx", "rx";
1357 #address-cells = <1>;
1359 status = "disabled";
1362 uart7: serial@99c000 {
1363 compatible = "qcom,geni-debug-uart";
1364 reg = <0 0x0099c000 0 0x4000>;
1366 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1367 pinctrl-names = "default";
1368 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1369 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1370 #address-cells = <1>;
1372 status = "disabled";
1376 gpi_dma1: dma-controller@a00000 {
1377 compatible = "qcom,sm8450-gpi-dma";
1379 reg = <0 0xa00000 0 0x60000>;
1380 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1392 dma-channels = <12>;
1393 dma-channel-mask = <0x7e>;
1394 iommus = <&apps_smmu 0x56 0x0>;
1395 status = "disabled";
1398 qupv3_id_1: geniqup@ac0000 {
1399 compatible = "qcom,geni-se-qup";
1400 reg = <0x0 0x00ac0000 0x0 0x6000>;
1401 clock-names = "m-ahb", "s-ahb";
1402 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1403 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1404 iommus = <&apps_smmu 0x43 0x0>;
1405 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1406 interconnect-names = "qup-core";
1407 #address-cells = <2>;
1410 status = "disabled";
1413 compatible = "qcom,geni-i2c";
1414 reg = <0x0 0x00a80000 0x0 0x4000>;
1416 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1417 pinctrl-names = "default";
1418 pinctrl-0 = <&qup_i2c8_data_clk>;
1419 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cells = <1>;
1422 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1423 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1424 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1425 interconnect-names = "qup-core", "qup-config", "qup-memory";
1426 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1427 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1428 dma-names = "tx", "rx";
1429 status = "disabled";
1433 compatible = "qcom,geni-spi";
1434 reg = <0x0 0x00a80000 0x0 0x4000>;
1436 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1437 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1438 pinctrl-names = "default";
1439 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1440 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1441 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1442 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1443 interconnect-names = "qup-core", "qup-config", "qup-memory";
1444 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1445 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1446 dma-names = "tx", "rx";
1447 #address-cells = <1>;
1449 status = "disabled";
1453 compatible = "qcom,geni-i2c";
1454 reg = <0x0 0x00a84000 0x0 0x4000>;
1456 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1457 pinctrl-names = "default";
1458 pinctrl-0 = <&qup_i2c9_data_clk>;
1459 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1460 #address-cells = <1>;
1462 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1463 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1464 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1465 interconnect-names = "qup-core", "qup-config", "qup-memory";
1466 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1467 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1468 dma-names = "tx", "rx";
1469 status = "disabled";
1473 compatible = "qcom,geni-spi";
1474 reg = <0x0 0x00a84000 0x0 0x4000>;
1476 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1477 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1478 pinctrl-names = "default";
1479 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1480 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1481 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1482 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1483 interconnect-names = "qup-core", "qup-config", "qup-memory";
1484 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1485 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1486 dma-names = "tx", "rx";
1487 #address-cells = <1>;
1489 status = "disabled";
1493 compatible = "qcom,geni-i2c";
1494 reg = <0x0 0x00a88000 0x0 0x4000>;
1496 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1497 pinctrl-names = "default";
1498 pinctrl-0 = <&qup_i2c10_data_clk>;
1499 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1500 #address-cells = <1>;
1502 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1503 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1504 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1505 interconnect-names = "qup-core", "qup-config", "qup-memory";
1506 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1507 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1508 dma-names = "tx", "rx";
1509 status = "disabled";
1513 compatible = "qcom,geni-spi";
1514 reg = <0x0 0x00a88000 0x0 0x4000>;
1516 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1517 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1518 pinctrl-names = "default";
1519 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1521 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1522 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1523 interconnect-names = "qup-core", "qup-config", "qup-memory";
1524 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1525 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1526 dma-names = "tx", "rx";
1527 #address-cells = <1>;
1529 status = "disabled";
1533 compatible = "qcom,geni-i2c";
1534 reg = <0x0 0x00a8c000 0x0 0x4000>;
1536 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1537 pinctrl-names = "default";
1538 pinctrl-0 = <&qup_i2c11_data_clk>;
1539 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1540 #address-cells = <1>;
1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1543 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1544 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1545 interconnect-names = "qup-core", "qup-config", "qup-memory";
1546 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1547 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1548 dma-names = "tx", "rx";
1549 status = "disabled";
1553 compatible = "qcom,geni-spi";
1554 reg = <0x0 0x00a8c000 0x0 0x4000>;
1556 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1557 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1558 pinctrl-names = "default";
1559 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1560 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1561 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1562 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1563 interconnect-names = "qup-core", "qup-config", "qup-memory";
1564 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1565 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1566 dma-names = "tx", "rx";
1567 #address-cells = <1>;
1569 status = "disabled";
1573 compatible = "qcom,geni-i2c";
1574 reg = <0x0 0x00a90000 0x0 0x4000>;
1576 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1577 pinctrl-names = "default";
1578 pinctrl-0 = <&qup_i2c12_data_clk>;
1579 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1580 #address-cells = <1>;
1582 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1583 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1584 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1585 interconnect-names = "qup-core", "qup-config", "qup-memory";
1586 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1587 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1588 dma-names = "tx", "rx";
1589 status = "disabled";
1593 compatible = "qcom,geni-spi";
1594 reg = <0x0 0x00a90000 0x0 0x4000>;
1596 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1597 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1598 pinctrl-names = "default";
1599 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1600 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1601 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1602 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1603 interconnect-names = "qup-core", "qup-config", "qup-memory";
1604 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1605 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1606 dma-names = "tx", "rx";
1607 #address-cells = <1>;
1609 status = "disabled";
1613 compatible = "qcom,geni-i2c";
1614 reg = <0 0x00a94000 0 0x4000>;
1616 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1617 pinctrl-names = "default";
1618 pinctrl-0 = <&qup_i2c13_data_clk>;
1619 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1621 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1622 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1623 interconnect-names = "qup-core", "qup-config", "qup-memory";
1624 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1625 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1626 dma-names = "tx", "rx";
1627 #address-cells = <1>;
1629 status = "disabled";
1633 compatible = "qcom,geni-spi";
1634 reg = <0x0 0x00a94000 0x0 0x4000>;
1636 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1637 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1638 pinctrl-names = "default";
1639 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1640 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1641 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1642 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1643 interconnect-names = "qup-core", "qup-config", "qup-memory";
1644 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1645 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1646 dma-names = "tx", "rx";
1647 #address-cells = <1>;
1649 status = "disabled";
1653 compatible = "qcom,geni-i2c";
1654 reg = <0 0x00a98000 0 0x4000>;
1656 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1657 pinctrl-names = "default";
1658 pinctrl-0 = <&qup_i2c14_data_clk>;
1659 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1661 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1663 interconnect-names = "qup-core", "qup-config", "qup-memory";
1664 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1665 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1666 dma-names = "tx", "rx";
1667 #address-cells = <1>;
1669 status = "disabled";
1673 compatible = "qcom,geni-spi";
1674 reg = <0x0 0x00a98000 0x0 0x4000>;
1676 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1677 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1678 pinctrl-names = "default";
1679 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1681 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1683 interconnect-names = "qup-core", "qup-config", "qup-memory";
1684 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1685 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1686 dma-names = "tx", "rx";
1687 #address-cells = <1>;
1689 status = "disabled";
1693 pcie0: pci@1c00000 {
1694 compatible = "qcom,pcie-sm8450-pcie0";
1695 reg = <0 0x01c00000 0 0x3000>,
1696 <0 0x60000000 0 0xf1d>,
1697 <0 0x60000f20 0 0xa8>,
1698 <0 0x60001000 0 0x1000>,
1699 <0 0x60100000 0 0x100000>;
1700 reg-names = "parf", "dbi", "elbi", "atu", "config";
1701 device_type = "pci";
1702 linux,pci-domain = <0>;
1703 bus-range = <0x00 0xff>;
1706 #address-cells = <3>;
1709 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1710 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1712 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1713 interrupt-names = "msi";
1714 #interrupt-cells = <1>;
1715 interrupt-map-mask = <0 0 0 0x7>;
1716 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1717 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1718 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1719 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1721 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1722 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1724 <&rpmhcc RPMH_CXO_CLK>,
1725 <&gcc GCC_PCIE_0_AUX_CLK>,
1726 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1727 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1728 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1729 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1730 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1731 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1732 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1733 clock-names = "pipe",
1746 iommus = <&apps_smmu 0x1c00 0x7f>;
1747 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1748 <0x100 &apps_smmu 0x1c01 0x1>;
1750 resets = <&gcc GCC_PCIE_0_BCR>;
1751 reset-names = "pci";
1753 power-domains = <&gcc PCIE_0_GDSC>;
1754 power-domain-names = "gdsc";
1756 phys = <&pcie0_lane>;
1757 phy-names = "pciephy";
1759 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1760 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1762 pinctrl-names = "default";
1763 pinctrl-0 = <&pcie0_default_state>;
1765 status = "disabled";
1768 pcie0_phy: phy@1c06000 {
1769 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1770 reg = <0 0x01c06000 0 0x200>;
1771 #address-cells = <2>;
1774 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1775 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1776 <&gcc GCC_PCIE_0_CLKREF_EN>,
1777 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1778 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1780 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1781 reset-names = "phy";
1783 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1784 assigned-clock-rates = <100000000>;
1786 status = "disabled";
1788 pcie0_lane: phy@1c06200 {
1789 reg = <0 0x1c06e00 0 0x200>, /* tx */
1790 <0 0x1c07000 0 0x200>, /* rx */
1791 <0 0x1c06200 0 0x200>, /* pcs */
1792 <0 0x1c06600 0 0x200>; /* pcs_pcie */
1793 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1794 clock-names = "pipe0";
1798 clock-output-names = "pcie_0_pipe_clk";
1802 pcie1: pci@1c08000 {
1803 compatible = "qcom,pcie-sm8450-pcie1";
1804 reg = <0 0x01c08000 0 0x3000>,
1805 <0 0x40000000 0 0xf1d>,
1806 <0 0x40000f20 0 0xa8>,
1807 <0 0x40001000 0 0x1000>,
1808 <0 0x40100000 0 0x100000>;
1809 reg-names = "parf", "dbi", "elbi", "atu", "config";
1810 device_type = "pci";
1811 linux,pci-domain = <1>;
1812 bus-range = <0x00 0xff>;
1815 #address-cells = <3>;
1818 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
1819 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
1821 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1822 interrupt-names = "msi";
1823 #interrupt-cells = <1>;
1824 interrupt-map-mask = <0 0 0 0x7>;
1825 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1826 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1827 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1828 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1830 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1831 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1833 <&rpmhcc RPMH_CXO_CLK>,
1834 <&gcc GCC_PCIE_1_AUX_CLK>,
1835 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1836 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1837 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1838 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1839 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1840 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1841 clock-names = "pipe",
1853 iommus = <&apps_smmu 0x1c80 0x7f>;
1854 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1855 <0x100 &apps_smmu 0x1c81 0x1>;
1857 resets = <&gcc GCC_PCIE_1_BCR>;
1858 reset-names = "pci";
1860 power-domains = <&gcc PCIE_1_GDSC>;
1861 power-domain-names = "gdsc";
1863 phys = <&pcie1_lane>;
1864 phy-names = "pciephy";
1866 perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>;
1867 enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1869 pinctrl-names = "default";
1870 pinctrl-0 = <&pcie1_default_state>;
1872 status = "disabled";
1875 pcie1_phy: phy@1c0f000 {
1876 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1877 reg = <0 0x01c0f000 0 0x200>;
1878 #address-cells = <2>;
1881 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1882 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1883 <&gcc GCC_PCIE_1_CLKREF_EN>,
1884 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1885 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1887 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1888 reset-names = "phy";
1890 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1891 assigned-clock-rates = <100000000>;
1893 status = "disabled";
1895 pcie1_lane: phy@1c0e000 {
1896 reg = <0 0x1c0e000 0 0x200>, /* tx */
1897 <0 0x1c0e200 0 0x300>, /* rx */
1898 <0 0x1c0f200 0 0x200>, /* pcs */
1899 <0 0x1c0e800 0 0x200>, /* tx */
1900 <0 0x1c0ea00 0 0x300>, /* rx */
1901 <0 0x1c0f400 0 0xc00>; /* pcs_pcie */
1902 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1903 clock-names = "pipe0";
1907 clock-output-names = "pcie_1_pipe_clk";
1911 config_noc: interconnect@1500000 {
1912 compatible = "qcom,sm8450-config-noc";
1913 reg = <0 0x01500000 0 0x1c000>;
1914 #interconnect-cells = <2>;
1915 qcom,bcm-voters = <&apps_bcm_voter>;
1918 system_noc: interconnect@1680000 {
1919 compatible = "qcom,sm8450-system-noc";
1920 reg = <0 0x01680000 0 0x1e200>;
1921 #interconnect-cells = <2>;
1922 qcom,bcm-voters = <&apps_bcm_voter>;
1925 pcie_noc: interconnect@16c0000 {
1926 compatible = "qcom,sm8450-pcie-anoc";
1927 reg = <0 0x016c0000 0 0xe280>;
1928 #interconnect-cells = <2>;
1929 qcom,bcm-voters = <&apps_bcm_voter>;
1932 aggre1_noc: interconnect@16e0000 {
1933 compatible = "qcom,sm8450-aggre1-noc";
1934 reg = <0 0x016e0000 0 0x1c080>;
1935 #interconnect-cells = <2>;
1936 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1937 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
1938 qcom,bcm-voters = <&apps_bcm_voter>;
1941 aggre2_noc: interconnect@1700000 {
1942 compatible = "qcom,sm8450-aggre2-noc";
1943 reg = <0 0x01700000 0 0x31080>;
1944 #interconnect-cells = <2>;
1945 qcom,bcm-voters = <&apps_bcm_voter>;
1946 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1947 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1948 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1949 <&rpmhcc RPMH_IPA_CLK>;
1952 mmss_noc: interconnect@1740000 {
1953 compatible = "qcom,sm8450-mmss-noc";
1954 reg = <0 0x01740000 0 0x1f080>;
1955 #interconnect-cells = <2>;
1956 qcom,bcm-voters = <&apps_bcm_voter>;
1959 tcsr_mutex: hwlock@1f40000 {
1960 compatible = "qcom,tcsr-mutex";
1961 reg = <0x0 0x01f40000 0x0 0x40000>;
1962 #hwlock-cells = <1>;
1965 usb_1_hsphy: phy@88e3000 {
1966 compatible = "qcom,sm8450-usb-hs-phy",
1967 "qcom,usb-snps-hs-7nm-phy";
1968 reg = <0 0x088e3000 0 0x400>;
1969 status = "disabled";
1972 clocks = <&rpmhcc RPMH_CXO_CLK>;
1973 clock-names = "ref";
1975 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1978 usb_1_qmpphy: phy-wrapper@88e9000 {
1979 compatible = "qcom,sm8450-qmp-usb3-phy";
1980 reg = <0 0x088e9000 0 0x200>,
1981 <0 0x088e8000 0 0x20>;
1982 status = "disabled";
1983 #address-cells = <2>;
1987 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1988 <&rpmhcc RPMH_CXO_CLK>,
1989 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1990 clock-names = "aux", "ref_clk_src", "com_aux";
1992 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1993 <&gcc GCC_USB3_PHY_PRIM_BCR>;
1994 reset-names = "phy", "common";
1996 usb_1_ssphy: phy@88e9200 {
1997 reg = <0 0x088e9200 0 0x200>,
1998 <0 0x088e9400 0 0x200>,
1999 <0 0x088e9c00 0 0x400>,
2000 <0 0x088e9600 0 0x200>,
2001 <0 0x088e9800 0 0x200>,
2002 <0 0x088e9a00 0 0x100>;
2005 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2006 clock-names = "pipe0";
2007 clock-output-names = "usb3_phy_pipe_clk_src";
2011 remoteproc_slpi: remoteproc@2400000 {
2012 compatible = "qcom,sm8450-slpi-pas";
2013 reg = <0 0x02400000 0 0x4000>;
2015 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2016 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2017 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2018 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2019 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2020 interrupt-names = "wdog", "fatal", "ready",
2021 "handover", "stop-ack";
2023 clocks = <&rpmhcc RPMH_CXO_CLK>;
2026 power-domains = <&rpmhpd SM8450_LCX>,
2027 <&rpmhpd SM8450_LMX>;
2028 power-domain-names = "lcx", "lmx";
2030 memory-region = <&slpi_mem>;
2032 qcom,qmp = <&aoss_qmp>;
2034 qcom,smem-states = <&smp2p_slpi_out 0>;
2035 qcom,smem-state-names = "stop";
2037 status = "disabled";
2040 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2041 IPCC_MPROC_SIGNAL_GLINK_QMP
2042 IRQ_TYPE_EDGE_RISING>;
2043 mboxes = <&ipcc IPCC_CLIENT_SLPI
2044 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2047 qcom,remote-pid = <3>;
2050 compatible = "qcom,fastrpc";
2051 qcom,glink-channels = "fastrpcglink-apps-dsp";
2053 #address-cells = <1>;
2057 compatible = "qcom,fastrpc-compute-cb";
2059 iommus = <&apps_smmu 0x0541 0x0>;
2063 compatible = "qcom,fastrpc-compute-cb";
2065 iommus = <&apps_smmu 0x0542 0x0>;
2069 compatible = "qcom,fastrpc-compute-cb";
2071 iommus = <&apps_smmu 0x0543 0x0>;
2072 /* note: shared-cb = <4> in downstream */
2078 remoteproc_adsp: remoteproc@30000000 {
2079 compatible = "qcom,sm8450-adsp-pas";
2080 reg = <0 0x030000000 0 0x100>;
2082 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2083 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2084 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2085 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2086 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2087 interrupt-names = "wdog", "fatal", "ready",
2088 "handover", "stop-ack";
2090 clocks = <&rpmhcc RPMH_CXO_CLK>;
2093 power-domains = <&rpmhpd SM8450_LCX>,
2094 <&rpmhpd SM8450_LMX>;
2095 power-domain-names = "lcx", "lmx";
2097 memory-region = <&adsp_mem>;
2099 qcom,qmp = <&aoss_qmp>;
2101 qcom,smem-states = <&smp2p_adsp_out 0>;
2102 qcom,smem-state-names = "stop";
2104 status = "disabled";
2106 remoteproc_adsp_glink: glink-edge {
2107 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2108 IPCC_MPROC_SIGNAL_GLINK_QMP
2109 IRQ_TYPE_EDGE_RISING>;
2110 mboxes = <&ipcc IPCC_CLIENT_LPASS
2111 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2114 qcom,remote-pid = <2>;
2117 compatible = "qcom,fastrpc";
2118 qcom,glink-channels = "fastrpcglink-apps-dsp";
2120 #address-cells = <1>;
2124 compatible = "qcom,fastrpc-compute-cb";
2126 iommus = <&apps_smmu 0x1803 0x0>;
2130 compatible = "qcom,fastrpc-compute-cb";
2132 iommus = <&apps_smmu 0x1804 0x0>;
2136 compatible = "qcom,fastrpc-compute-cb";
2138 iommus = <&apps_smmu 0x1805 0x0>;
2144 remoteproc_cdsp: remoteproc@32300000 {
2145 compatible = "qcom,sm8450-cdsp-pas";
2146 reg = <0 0x032300000 0 0x1400000>;
2148 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2149 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2150 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2151 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2152 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2153 interrupt-names = "wdog", "fatal", "ready",
2154 "handover", "stop-ack";
2156 clocks = <&rpmhcc RPMH_CXO_CLK>;
2159 power-domains = <&rpmhpd SM8450_CX>,
2160 <&rpmhpd SM8450_MXC>;
2161 power-domain-names = "cx", "mxc";
2163 memory-region = <&cdsp_mem>;
2165 qcom,qmp = <&aoss_qmp>;
2167 qcom,smem-states = <&smp2p_cdsp_out 0>;
2168 qcom,smem-state-names = "stop";
2170 status = "disabled";
2173 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2174 IPCC_MPROC_SIGNAL_GLINK_QMP
2175 IRQ_TYPE_EDGE_RISING>;
2176 mboxes = <&ipcc IPCC_CLIENT_CDSP
2177 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2180 qcom,remote-pid = <5>;
2183 compatible = "qcom,fastrpc";
2184 qcom,glink-channels = "fastrpcglink-apps-dsp";
2186 #address-cells = <1>;
2190 compatible = "qcom,fastrpc-compute-cb";
2192 iommus = <&apps_smmu 0x2161 0x0400>,
2193 <&apps_smmu 0x1021 0x1420>;
2197 compatible = "qcom,fastrpc-compute-cb";
2199 iommus = <&apps_smmu 0x2162 0x0400>,
2200 <&apps_smmu 0x1022 0x1420>;
2204 compatible = "qcom,fastrpc-compute-cb";
2206 iommus = <&apps_smmu 0x2163 0x0400>,
2207 <&apps_smmu 0x1023 0x1420>;
2211 compatible = "qcom,fastrpc-compute-cb";
2213 iommus = <&apps_smmu 0x2164 0x0400>,
2214 <&apps_smmu 0x1024 0x1420>;
2218 compatible = "qcom,fastrpc-compute-cb";
2220 iommus = <&apps_smmu 0x2165 0x0400>,
2221 <&apps_smmu 0x1025 0x1420>;
2225 compatible = "qcom,fastrpc-compute-cb";
2227 iommus = <&apps_smmu 0x2166 0x0400>,
2228 <&apps_smmu 0x1026 0x1420>;
2232 compatible = "qcom,fastrpc-compute-cb";
2234 iommus = <&apps_smmu 0x2167 0x0400>,
2235 <&apps_smmu 0x1027 0x1420>;
2239 compatible = "qcom,fastrpc-compute-cb";
2241 iommus = <&apps_smmu 0x2168 0x0400>,
2242 <&apps_smmu 0x1028 0x1420>;
2245 /* note: secure cb9 in downstream */
2250 remoteproc_mpss: remoteproc@4080000 {
2251 compatible = "qcom,sm8450-mpss-pas";
2252 reg = <0x0 0x04080000 0x0 0x4040>;
2254 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
2255 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2256 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2257 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2258 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2259 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2260 interrupt-names = "wdog", "fatal", "ready", "handover",
2261 "stop-ack", "shutdown-ack";
2263 clocks = <&rpmhcc RPMH_CXO_CLK>;
2266 power-domains = <&rpmhpd 0>,
2268 power-domain-names = "cx", "mss";
2270 memory-region = <&mpss_mem>;
2272 qcom,qmp = <&aoss_qmp>;
2274 qcom,smem-states = <&smp2p_modem_out 0>;
2275 qcom,smem-state-names = "stop";
2277 status = "disabled";
2280 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2281 IPCC_MPROC_SIGNAL_GLINK_QMP
2282 IRQ_TYPE_EDGE_RISING>;
2283 mboxes = <&ipcc IPCC_CLIENT_MPSS
2284 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2285 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2287 qcom,remote-pid = <1>;
2291 pdc: interrupt-controller@b220000 {
2292 compatible = "qcom,sm8450-pdc", "qcom,pdc";
2293 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
2294 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
2295 <94 609 31>, <125 63 1>, <126 716 12>;
2296 #interrupt-cells = <2>;
2297 interrupt-parent = <&intc>;
2298 interrupt-controller;
2301 tsens0: thermal-sensor@c263000 {
2302 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
2303 reg = <0 0x0c263000 0 0x1000>, /* TM */
2304 <0 0x0c222000 0 0x1000>; /* SROT */
2305 #qcom,sensors = <16>;
2306 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2307 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2308 interrupt-names = "uplow", "critical";
2309 #thermal-sensor-cells = <1>;
2312 tsens1: thermal-sensor@c265000 {
2313 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
2314 reg = <0 0x0c265000 0 0x1000>, /* TM */
2315 <0 0x0c223000 0 0x1000>; /* SROT */
2316 #qcom,sensors = <16>;
2317 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2318 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2319 interrupt-names = "uplow", "critical";
2320 #thermal-sensor-cells = <1>;
2323 aoss_qmp: power-controller@c300000 {
2324 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
2325 reg = <0 0x0c300000 0 0x400>;
2326 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2327 IRQ_TYPE_EDGE_RISING>;
2328 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2333 ipcc: mailbox@ed18000 {
2334 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
2335 reg = <0 0x0ed18000 0 0x1000>;
2336 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
2337 interrupt-controller;
2338 #interrupt-cells = <3>;
2342 tlmm: pinctrl@f100000 {
2343 compatible = "qcom,sm8450-tlmm";
2344 reg = <0 0x0f100000 0 0x300000>;
2345 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2348 interrupt-controller;
2349 #interrupt-cells = <2>;
2350 gpio-ranges = <&tlmm 0 0 211>;
2351 wakeup-parent = <&pdc>;
2353 pcie0_default_state: pcie0-default-state {
2357 drive-strength = <2>;
2363 function = "pcie0_clkreqn";
2364 drive-strength = <2>;
2371 drive-strength = <2>;
2376 pcie1_default_state: pcie1-default-state {
2380 drive-strength = <2>;
2386 function = "pcie1_clkreqn";
2387 drive-strength = <2>;
2394 drive-strength = <2>;
2399 qup_i2c0_data_clk: qup-i2c0-data-clk {
2400 pins = "gpio0", "gpio1";
2404 qup_i2c1_data_clk: qup-i2c1-data-clk {
2405 pins = "gpio4", "gpio5";
2409 qup_i2c2_data_clk: qup-i2c2-data-clk {
2410 pins = "gpio8", "gpio9";
2414 qup_i2c3_data_clk: qup-i2c3-data-clk {
2415 pins = "gpio12", "gpio13";
2419 qup_i2c4_data_clk: qup-i2c4-data-clk {
2420 pins = "gpio16", "gpio17";
2424 qup_i2c5_data_clk: qup-i2c5-data-clk {
2425 pins = "gpio206", "gpio207";
2429 qup_i2c6_data_clk: qup-i2c6-data-clk {
2430 pins = "gpio20", "gpio21";
2434 qup_i2c8_data_clk: qup-i2c8-data-clk {
2435 pins = "gpio28", "gpio29";
2439 qup_i2c9_data_clk: qup-i2c9-data-clk {
2440 pins = "gpio32", "gpio33";
2444 qup_i2c10_data_clk: qup-i2c10-data-clk {
2445 pins = "gpio36", "gpio37";
2449 qup_i2c11_data_clk: qup-i2c11-data-clk {
2450 pins = "gpio40", "gpio41";
2454 qup_i2c12_data_clk: qup-i2c12-data-clk {
2455 pins = "gpio44", "gpio45";
2459 qup_i2c13_data_clk: qup-i2c13-data-clk {
2460 pins = "gpio48", "gpio49";
2462 drive-strength = <2>;
2466 qup_i2c14_data_clk: qup-i2c14-data-clk {
2467 pins = "gpio52", "gpio53";
2469 drive-strength = <2>;
2473 qup_i2c15_data_clk: qup-i2c15-data-clk {
2474 pins = "gpio56", "gpio57";
2478 qup_i2c16_data_clk: qup-i2c16-data-clk {
2479 pins = "gpio60", "gpio61";
2483 qup_i2c17_data_clk: qup-i2c17-data-clk {
2484 pins = "gpio64", "gpio65";
2488 qup_i2c18_data_clk: qup-i2c18-data-clk {
2489 pins = "gpio68", "gpio69";
2493 qup_i2c19_data_clk: qup-i2c19-data-clk {
2494 pins = "gpio72", "gpio73";
2498 qup_i2c20_data_clk: qup-i2c20-data-clk {
2499 pins = "gpio76", "gpio77";
2503 qup_i2c21_data_clk: qup-i2c21-data-clk {
2504 pins = "gpio80", "gpio81";
2508 qup_spi0_cs: qup-spi0-cs {
2513 qup_spi0_data_clk: qup-spi0-data-clk {
2514 pins = "gpio0", "gpio1", "gpio2";
2518 qup_spi1_cs: qup-spi1-cs {
2523 qup_spi1_data_clk: qup-spi1-data-clk {
2524 pins = "gpio4", "gpio5", "gpio6";
2528 qup_spi2_cs: qup-spi2-cs {
2533 qup_spi2_data_clk: qup-spi2-data-clk {
2534 pins = "gpio8", "gpio9", "gpio10";
2538 qup_spi3_cs: qup-spi3-cs {
2543 qup_spi3_data_clk: qup-spi3-data-clk {
2544 pins = "gpio12", "gpio13", "gpio14";
2548 qup_spi4_cs: qup-spi4-cs {
2551 drive-strength = <6>;
2555 qup_spi4_data_clk: qup-spi4-data-clk {
2556 pins = "gpio16", "gpio17", "gpio18";
2560 qup_spi5_cs: qup-spi5-cs {
2565 qup_spi5_data_clk: qup-spi5-data-clk {
2566 pins = "gpio206", "gpio207", "gpio84";
2570 qup_spi6_cs: qup-spi6-cs {
2575 qup_spi6_data_clk: qup-spi6-data-clk {
2576 pins = "gpio20", "gpio21", "gpio22";
2580 qup_spi8_cs: qup-spi8-cs {
2585 qup_spi8_data_clk: qup-spi8-data-clk {
2586 pins = "gpio28", "gpio29", "gpio30";
2590 qup_spi9_cs: qup-spi9-cs {
2595 qup_spi9_data_clk: qup-spi9-data-clk {
2596 pins = "gpio32", "gpio33", "gpio34";
2600 qup_spi10_cs: qup-spi10-cs {
2605 qup_spi10_data_clk: qup-spi10-data-clk {
2606 pins = "gpio36", "gpio37", "gpio38";
2610 qup_spi11_cs: qup-spi11-cs {
2615 qup_spi11_data_clk: qup-spi11-data-clk {
2616 pins = "gpio40", "gpio41", "gpio42";
2620 qup_spi12_cs: qup-spi12-cs {
2625 qup_spi12_data_clk: qup-spi12-data-clk {
2626 pins = "gpio44", "gpio45", "gpio46";
2630 qup_spi13_cs: qup-spi13-cs {
2635 qup_spi13_data_clk: qup-spi13-data-clk {
2636 pins = "gpio48", "gpio49", "gpio50";
2640 qup_spi14_cs: qup-spi14-cs {
2645 qup_spi14_data_clk: qup-spi14-data-clk {
2646 pins = "gpio52", "gpio53", "gpio54";
2650 qup_spi15_cs: qup-spi15-cs {
2655 qup_spi15_data_clk: qup-spi15-data-clk {
2656 pins = "gpio56", "gpio57", "gpio58";
2660 qup_spi16_cs: qup-spi16-cs {
2665 qup_spi16_data_clk: qup-spi16-data-clk {
2666 pins = "gpio60", "gpio61", "gpio62";
2670 qup_spi17_cs: qup-spi17-cs {
2675 qup_spi17_data_clk: qup-spi17-data-clk {
2676 pins = "gpio64", "gpio65", "gpio66";
2680 qup_spi18_cs: qup-spi18-cs {
2683 drive-strength = <6>;
2687 qup_spi18_data_clk: qup-spi18-data-clk {
2688 pins = "gpio68", "gpio69", "gpio70";
2690 drive-strength = <6>;
2694 qup_spi19_cs: qup-spi19-cs {
2697 drive-strength = <6>;
2701 qup_spi19_data_clk: qup-spi19-data-clk {
2702 pins = "gpio72", "gpio73", "gpio74";
2704 drive-strength = <6>;
2708 qup_spi20_cs: qup-spi20-cs {
2713 qup_spi20_data_clk: qup-spi20-data-clk {
2714 pins = "gpio76", "gpio77", "gpio78";
2718 qup_spi21_cs: qup-spi21-cs {
2723 qup_spi21_data_clk: qup-spi21-data-clk {
2724 pins = "gpio80", "gpio81", "gpio82";
2728 qup_uart7_rx: qup-uart7-rx {
2731 drive-strength = <2>;
2735 qup_uart7_tx: qup-uart7-tx {
2738 drive-strength = <2>;
2743 apps_smmu: iommu@15000000 {
2744 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
2745 reg = <0 0x15000000 0 0x100000>;
2747 #global-interrupts = <1>;
2748 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2749 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2750 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2751 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2752 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2753 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2754 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2755 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2756 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2757 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2758 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2759 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2760 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2761 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2762 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2763 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2764 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2765 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2766 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2767 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2768 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2769 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2770 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2771 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2772 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2773 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2774 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2775 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2776 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2777 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2778 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2779 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2780 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2781 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2782 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2783 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2784 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2785 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2786 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2787 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2788 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2789 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2790 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2791 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2792 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2793 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2794 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2795 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2796 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2797 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2798 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2799 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2800 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2801 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2802 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2803 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2804 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2805 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2806 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2807 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2808 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2809 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2810 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2811 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2812 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2813 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2814 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2815 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2816 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2817 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2818 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2819 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2820 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2821 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2822 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2823 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2824 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2825 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2826 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2827 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2828 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2829 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2830 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2831 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2832 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2833 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
2834 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2835 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2836 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2837 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2838 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2839 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2840 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2841 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2842 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2843 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2844 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
2847 intc: interrupt-controller@17100000 {
2848 compatible = "arm,gic-v3";
2849 #interrupt-cells = <3>;
2850 interrupt-controller;
2851 #redistributor-regions = <1>;
2852 redistributor-stride = <0x0 0x40000>;
2853 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
2854 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
2855 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2859 compatible = "arm,armv7-timer-mem";
2860 #address-cells = <2>;
2863 reg = <0x0 0x17420000 0x0 0x1000>;
2864 clock-frequency = <19200000>;
2868 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2869 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2870 reg = <0x0 0x17421000 0x0 0x1000>,
2871 <0x0 0x17422000 0x0 0x1000>;
2876 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2877 reg = <0x0 0x17423000 0x0 0x1000>;
2878 status = "disabled";
2883 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2884 reg = <0x0 0x17425000 0x0 0x1000>;
2885 status = "disabled";
2890 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2891 reg = <0x0 0x17427000 0x0 0x1000>;
2892 status = "disabled";
2897 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2898 reg = <0x0 0x17429000 0x0 0x1000>;
2899 status = "disabled";
2904 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2905 reg = <0x0 0x1742b000 0x0 0x1000>;
2906 status = "disabled";
2911 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2912 reg = <0x0 0x1742d000 0x0 0x1000>;
2913 status = "disabled";
2917 apps_rsc: rsc@17a00000 {
2919 compatible = "qcom,rpmh-rsc";
2920 reg = <0x0 0x17a00000 0x0 0x10000>,
2921 <0x0 0x17a10000 0x0 0x10000>,
2922 <0x0 0x17a20000 0x0 0x10000>,
2923 <0x0 0x17a30000 0x0 0x10000>;
2924 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
2925 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2926 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2927 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2928 qcom,tcs-offset = <0xd00>;
2930 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
2931 <WAKE_TCS 2>, <CONTROL_TCS 0>;
2933 apps_bcm_voter: bcm-voter {
2934 compatible = "qcom,bcm-voter";
2937 rpmhcc: clock-controller {
2938 compatible = "qcom,sm8450-rpmh-clk";
2941 clocks = <&xo_board>;
2944 rpmhpd: power-controller {
2945 compatible = "qcom,sm8450-rpmhpd";
2946 #power-domain-cells = <1>;
2947 operating-points-v2 = <&rpmhpd_opp_table>;
2949 rpmhpd_opp_table: opp-table {
2950 compatible = "operating-points-v2";
2952 rpmhpd_opp_ret: opp1 {
2953 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2956 rpmhpd_opp_min_svs: opp2 {
2957 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2960 rpmhpd_opp_low_svs: opp3 {
2961 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2964 rpmhpd_opp_svs: opp4 {
2965 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2968 rpmhpd_opp_svs_l1: opp5 {
2969 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2972 rpmhpd_opp_nom: opp6 {
2973 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2976 rpmhpd_opp_nom_l1: opp7 {
2977 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2980 rpmhpd_opp_nom_l2: opp8 {
2981 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2984 rpmhpd_opp_turbo: opp9 {
2985 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2988 rpmhpd_opp_turbo_l1: opp10 {
2989 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2995 cpufreq_hw: cpufreq@17d91000 {
2996 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
2997 reg = <0 0x17d91000 0 0x1000>,
2998 <0 0x17d92000 0 0x1000>,
2999 <0 0x17d93000 0 0x1000>;
3000 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3001 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3002 clock-names = "xo", "alternate";
3003 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
3004 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3005 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
3006 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3007 #freq-domain-cells = <1>;
3010 gem_noc: interconnect@19100000 {
3011 compatible = "qcom,sm8450-gem-noc";
3012 reg = <0 0x19100000 0 0xbb800>;
3013 #interconnect-cells = <2>;
3014 qcom,bcm-voters = <&apps_bcm_voter>;
3017 system-cache-controller@19200000 {
3018 compatible = "qcom,sm8450-llcc";
3019 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
3020 reg-names = "llcc_base", "llcc_broadcast_base";
3021 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
3024 ufs_mem_hc: ufshc@1d84000 {
3025 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
3027 reg = <0 0x01d84000 0 0x3000>;
3028 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
3029 phys = <&ufs_mem_phy_lanes>;
3030 phy-names = "ufsphy";
3031 lanes-per-direction = <2>;
3033 resets = <&gcc GCC_UFS_PHY_BCR>;
3034 reset-names = "rst";
3036 power-domains = <&gcc UFS_PHY_GDSC>;
3038 iommus = <&apps_smmu 0xe0 0x0>;
3040 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
3041 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
3042 interconnect-names = "ufs-ddr", "cpu-ufs";
3049 "tx_lane0_sync_clk",
3050 "rx_lane0_sync_clk",
3051 "rx_lane1_sync_clk";
3053 <&gcc GCC_UFS_PHY_AXI_CLK>,
3054 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
3055 <&gcc GCC_UFS_PHY_AHB_CLK>,
3056 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
3057 <&rpmhcc RPMH_CXO_CLK>,
3058 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
3059 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
3060 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
3062 <75000000 300000000>,
3065 <75000000 300000000>,
3066 <75000000 300000000>,
3070 status = "disabled";
3073 ufs_mem_phy: phy@1d87000 {
3074 compatible = "qcom,sm8450-qmp-ufs-phy";
3075 reg = <0 0x01d87000 0 0xe10>;
3076 #address-cells = <2>;
3079 clock-names = "ref", "ref_aux", "qref";
3080 clocks = <&rpmhcc RPMH_CXO_CLK>,
3081 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
3082 <&gcc GCC_UFS_0_CLKREF_EN>;
3084 resets = <&ufs_mem_hc 0>;
3085 reset-names = "ufsphy";
3086 status = "disabled";
3088 ufs_mem_phy_lanes: phy@1d87400 {
3089 reg = <0 0x01d87400 0 0x108>,
3090 <0 0x01d87600 0 0x1e0>,
3091 <0 0x01d87c00 0 0x1dc>,
3092 <0 0x01d87800 0 0x108>,
3093 <0 0x01d87a00 0 0x1e0>;
3099 usb_1: usb@a6f8800 {
3100 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
3101 reg = <0 0x0a6f8800 0 0x400>;
3102 status = "disabled";
3103 #address-cells = <2>;
3107 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3108 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3109 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3110 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3111 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3112 <&gcc GCC_USB3_0_CLKREF_EN>;
3113 clock-names = "cfg_noc",
3120 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3121 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3122 assigned-clock-rates = <19200000>, <200000000>;
3124 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3125 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
3126 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3127 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
3128 interrupt-names = "hs_phy_irq",
3133 power-domains = <&gcc USB30_PRIM_GDSC>;
3135 resets = <&gcc GCC_USB30_PRIM_BCR>;
3137 usb_1_dwc3: usb@a600000 {
3138 compatible = "snps,dwc3";
3139 reg = <0 0x0a600000 0 0xcd00>;
3140 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3141 iommus = <&apps_smmu 0x0 0x0>;
3142 snps,dis_u2_susphy_quirk;
3143 snps,dis_enblslpm_quirk;
3144 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3145 phy-names = "usb2-phy", "usb3-phy";
3149 nsp_noc: interconnect@320c0000 {
3150 compatible = "qcom,sm8450-nsp-noc";
3151 reg = <0 0x320c0000 0 0x10000>;
3152 #interconnect-cells = <2>;
3153 qcom,bcm-voters = <&apps_bcm_voter>;
3156 lpass_ag_noc: interconnect@3c40000 {
3157 compatible = "qcom,sm8450-lpass-ag-noc";
3158 reg = <0 0x3c40000 0 0x17200>;
3159 #interconnect-cells = <2>;
3160 qcom,bcm-voters = <&apps_bcm_voter>;
3166 polling-delay-passive = <0>;
3167 polling-delay = <0>;
3168 thermal-sensors = <&tsens0 0>;
3171 thermal-engine-config {
3172 temperature = <125000>;
3173 hysteresis = <1000>;
3178 temperature = <115000>;
3179 hysteresis = <5000>;
3186 polling-delay-passive = <0>;
3187 polling-delay = <0>;
3188 thermal-sensors = <&tsens0 1>;
3191 thermal-engine-config {
3192 temperature = <125000>;
3193 hysteresis = <1000>;
3198 temperature = <115000>;
3199 hysteresis = <5000>;
3206 polling-delay-passive = <0>;
3207 polling-delay = <0>;
3208 thermal-sensors = <&tsens0 2>;
3211 thermal-engine-config {
3212 temperature = <125000>;
3213 hysteresis = <1000>;
3218 temperature = <115000>;
3219 hysteresis = <5000>;
3226 polling-delay-passive = <0>;
3227 polling-delay = <0>;
3228 thermal-sensors = <&tsens0 3>;
3231 thermal-engine-config {
3232 temperature = <125000>;
3233 hysteresis = <1000>;
3238 temperature = <115000>;
3239 hysteresis = <5000>;
3246 polling-delay-passive = <0>;
3247 polling-delay = <0>;
3248 thermal-sensors = <&tsens0 4>;
3251 thermal-engine-config {
3252 temperature = <125000>;
3253 hysteresis = <1000>;
3258 temperature = <115000>;
3259 hysteresis = <5000>;
3266 polling-delay-passive = <0>;
3267 polling-delay = <0>;
3268 thermal-sensors = <&tsens0 5>;
3271 cpu4_top_alert0: trip-point0 {
3272 temperature = <90000>;
3273 hysteresis = <2000>;
3277 cpu4_top_alert1: trip-point1 {
3278 temperature = <95000>;
3279 hysteresis = <2000>;
3283 cpu4_top_crit: cpu_crit {
3284 temperature = <110000>;
3285 hysteresis = <1000>;
3291 cpu4-bottom-thermal {
3292 polling-delay-passive = <0>;
3293 polling-delay = <0>;
3294 thermal-sensors = <&tsens0 6>;
3297 cpu4_bottom_alert0: trip-point0 {
3298 temperature = <90000>;
3299 hysteresis = <2000>;
3303 cpu4_bottom_alert1: trip-point1 {
3304 temperature = <95000>;
3305 hysteresis = <2000>;
3309 cpu4_bottom_crit: cpu_crit {
3310 temperature = <110000>;
3311 hysteresis = <1000>;
3318 polling-delay-passive = <0>;
3319 polling-delay = <0>;
3320 thermal-sensors = <&tsens0 7>;
3323 cpu5_top_alert0: trip-point0 {
3324 temperature = <90000>;
3325 hysteresis = <2000>;
3329 cpu5_top_alert1: trip-point1 {
3330 temperature = <95000>;
3331 hysteresis = <2000>;
3335 cpu5_top_crit: cpu_crit {
3336 temperature = <110000>;
3337 hysteresis = <1000>;
3343 cpu5-bottom-thermal {
3344 polling-delay-passive = <0>;
3345 polling-delay = <0>;
3346 thermal-sensors = <&tsens0 8>;
3349 cpu5_bottom_alert0: trip-point0 {
3350 temperature = <90000>;
3351 hysteresis = <2000>;
3355 cpu5_bottom_alert1: trip-point1 {
3356 temperature = <95000>;
3357 hysteresis = <2000>;
3361 cpu5_bottom_crit: cpu_crit {
3362 temperature = <110000>;
3363 hysteresis = <1000>;
3370 polling-delay-passive = <0>;
3371 polling-delay = <0>;
3372 thermal-sensors = <&tsens0 9>;
3375 cpu6_top_alert0: trip-point0 {
3376 temperature = <90000>;
3377 hysteresis = <2000>;
3381 cpu6_top_alert1: trip-point1 {
3382 temperature = <95000>;
3383 hysteresis = <2000>;
3387 cpu6_top_crit: cpu_crit {
3388 temperature = <110000>;
3389 hysteresis = <1000>;
3395 cpu6-bottom-thermal {
3396 polling-delay-passive = <0>;
3397 polling-delay = <0>;
3398 thermal-sensors = <&tsens0 10>;
3401 cpu6_bottom_alert0: trip-point0 {
3402 temperature = <90000>;
3403 hysteresis = <2000>;
3407 cpu6_bottom_alert1: trip-point1 {
3408 temperature = <95000>;
3409 hysteresis = <2000>;
3413 cpu6_bottom_crit: cpu_crit {
3414 temperature = <110000>;
3415 hysteresis = <1000>;
3422 polling-delay-passive = <0>;
3423 polling-delay = <0>;
3424 thermal-sensors = <&tsens0 11>;
3427 cpu7_top_alert0: trip-point0 {
3428 temperature = <90000>;
3429 hysteresis = <2000>;
3433 cpu7_top_alert1: trip-point1 {
3434 temperature = <95000>;
3435 hysteresis = <2000>;
3439 cpu7_top_crit: cpu_crit {
3440 temperature = <110000>;
3441 hysteresis = <1000>;
3447 cpu7-middle-thermal {
3448 polling-delay-passive = <0>;
3449 polling-delay = <0>;
3450 thermal-sensors = <&tsens0 12>;
3453 cpu7_middle_alert0: trip-point0 {
3454 temperature = <90000>;
3455 hysteresis = <2000>;
3459 cpu7_middle_alert1: trip-point1 {
3460 temperature = <95000>;
3461 hysteresis = <2000>;
3465 cpu7_middle_crit: cpu_crit {
3466 temperature = <110000>;
3467 hysteresis = <1000>;
3473 cpu7-bottom-thermal {
3474 polling-delay-passive = <0>;
3475 polling-delay = <0>;
3476 thermal-sensors = <&tsens0 13>;
3479 cpu7_bottom_alert0: trip-point0 {
3480 temperature = <90000>;
3481 hysteresis = <2000>;
3485 cpu7_bottom_alert1: trip-point1 {
3486 temperature = <95000>;
3487 hysteresis = <2000>;
3491 cpu7_bottom_crit: cpu_crit {
3492 temperature = <110000>;
3493 hysteresis = <1000>;
3500 polling-delay-passive = <10>;
3501 polling-delay = <0>;
3502 thermal-sensors = <&tsens0 14>;
3505 thermal-engine-config {
3506 temperature = <125000>;
3507 hysteresis = <1000>;
3511 thermal-hal-config {
3512 temperature = <125000>;
3513 hysteresis = <1000>;
3518 temperature = <115000>;
3519 hysteresis = <5000>;
3523 gpu0_tj_cfg: tj_cfg {
3524 temperature = <95000>;
3525 hysteresis = <5000>;
3531 gpu-bottom-thermal {
3532 polling-delay-passive = <10>;
3533 polling-delay = <0>;
3534 thermal-sensors = <&tsens0 15>;
3537 thermal-engine-config {
3538 temperature = <125000>;
3539 hysteresis = <1000>;
3543 thermal-hal-config {
3544 temperature = <125000>;
3545 hysteresis = <1000>;
3550 temperature = <115000>;
3551 hysteresis = <5000>;
3555 gpu1_tj_cfg: tj_cfg {
3556 temperature = <95000>;
3557 hysteresis = <5000>;
3564 polling-delay-passive = <0>;
3565 polling-delay = <0>;
3566 thermal-sensors = <&tsens1 0>;
3569 thermal-engine-config {
3570 temperature = <125000>;
3571 hysteresis = <1000>;
3576 temperature = <115000>;
3577 hysteresis = <5000>;
3584 polling-delay-passive = <0>;
3585 polling-delay = <0>;
3586 thermal-sensors = <&tsens1 1>;
3589 cpu0_alert0: trip-point0 {
3590 temperature = <90000>;
3591 hysteresis = <2000>;
3595 cpu0_alert1: trip-point1 {
3596 temperature = <95000>;
3597 hysteresis = <2000>;
3601 cpu0_crit: cpu_crit {
3602 temperature = <110000>;
3603 hysteresis = <1000>;
3610 polling-delay-passive = <0>;
3611 polling-delay = <0>;
3612 thermal-sensors = <&tsens1 2>;
3615 cpu1_alert0: trip-point0 {
3616 temperature = <90000>;
3617 hysteresis = <2000>;
3621 cpu1_alert1: trip-point1 {
3622 temperature = <95000>;
3623 hysteresis = <2000>;
3627 cpu1_crit: cpu_crit {
3628 temperature = <110000>;
3629 hysteresis = <1000>;
3636 polling-delay-passive = <0>;
3637 polling-delay = <0>;
3638 thermal-sensors = <&tsens1 3>;
3641 cpu2_alert0: trip-point0 {
3642 temperature = <90000>;
3643 hysteresis = <2000>;
3647 cpu2_alert1: trip-point1 {
3648 temperature = <95000>;
3649 hysteresis = <2000>;
3653 cpu2_crit: cpu_crit {
3654 temperature = <110000>;
3655 hysteresis = <1000>;
3662 polling-delay-passive = <0>;
3663 polling-delay = <0>;
3664 thermal-sensors = <&tsens1 4>;
3667 cpu3_alert0: trip-point0 {
3668 temperature = <90000>;
3669 hysteresis = <2000>;
3673 cpu3_alert1: trip-point1 {
3674 temperature = <95000>;
3675 hysteresis = <2000>;
3679 cpu3_crit: cpu_crit {
3680 temperature = <110000>;
3681 hysteresis = <1000>;
3688 polling-delay-passive = <10>;
3689 polling-delay = <0>;
3690 thermal-sensors = <&tsens1 5>;
3693 thermal-engine-config {
3694 temperature = <125000>;
3695 hysteresis = <1000>;
3699 thermal-hal-config {
3700 temperature = <125000>;
3701 hysteresis = <1000>;
3706 temperature = <115000>;
3707 hysteresis = <5000>;
3711 cdsp_0_config: junction-config {
3712 temperature = <95000>;
3713 hysteresis = <5000>;
3720 polling-delay-passive = <10>;
3721 polling-delay = <0>;
3722 thermal-sensors = <&tsens1 6>;
3725 thermal-engine-config {
3726 temperature = <125000>;
3727 hysteresis = <1000>;
3731 thermal-hal-config {
3732 temperature = <125000>;
3733 hysteresis = <1000>;
3738 temperature = <115000>;
3739 hysteresis = <5000>;
3743 cdsp_1_config: junction-config {
3744 temperature = <95000>;
3745 hysteresis = <5000>;
3752 polling-delay-passive = <10>;
3753 polling-delay = <0>;
3754 thermal-sensors = <&tsens1 7>;
3757 thermal-engine-config {
3758 temperature = <125000>;
3759 hysteresis = <1000>;
3763 thermal-hal-config {
3764 temperature = <125000>;
3765 hysteresis = <1000>;
3770 temperature = <115000>;
3771 hysteresis = <5000>;
3775 cdsp_2_config: junction-config {
3776 temperature = <95000>;
3777 hysteresis = <5000>;
3784 polling-delay-passive = <0>;
3785 polling-delay = <0>;
3786 thermal-sensors = <&tsens1 8>;
3789 thermal-engine-config {
3790 temperature = <125000>;
3791 hysteresis = <1000>;
3796 temperature = <115000>;
3797 hysteresis = <5000>;
3804 polling-delay-passive = <10>;
3805 polling-delay = <0>;
3806 thermal-sensors = <&tsens1 9>;
3809 thermal-engine-config {
3810 temperature = <125000>;
3811 hysteresis = <1000>;
3815 ddr_config0: ddr0-config {
3816 temperature = <90000>;
3817 hysteresis = <5000>;
3822 temperature = <115000>;
3823 hysteresis = <5000>;
3830 polling-delay-passive = <0>;
3831 polling-delay = <0>;
3832 thermal-sensors = <&tsens1 10>;
3835 thermal-engine-config {
3836 temperature = <125000>;
3837 hysteresis = <1000>;
3841 mdmss0_config0: mdmss0-config0 {
3842 temperature = <102000>;
3843 hysteresis = <3000>;
3847 mdmss0_config1: mdmss0-config1 {
3848 temperature = <105000>;
3849 hysteresis = <3000>;
3854 temperature = <115000>;
3855 hysteresis = <5000>;
3862 polling-delay-passive = <0>;
3863 polling-delay = <0>;
3864 thermal-sensors = <&tsens1 11>;
3867 thermal-engine-config {
3868 temperature = <125000>;
3869 hysteresis = <1000>;
3873 mdmss1_config0: mdmss1-config0 {
3874 temperature = <102000>;
3875 hysteresis = <3000>;
3879 mdmss1_config1: mdmss1-config1 {
3880 temperature = <105000>;
3881 hysteresis = <3000>;
3886 temperature = <115000>;
3887 hysteresis = <5000>;
3894 polling-delay-passive = <0>;
3895 polling-delay = <0>;
3896 thermal-sensors = <&tsens1 12>;
3899 thermal-engine-config {
3900 temperature = <125000>;
3901 hysteresis = <1000>;
3905 mdmss2_config0: mdmss2-config0 {
3906 temperature = <102000>;
3907 hysteresis = <3000>;
3911 mdmss2_config1: mdmss2-config1 {
3912 temperature = <105000>;
3913 hysteresis = <3000>;
3918 temperature = <115000>;
3919 hysteresis = <5000>;
3926 polling-delay-passive = <0>;
3927 polling-delay = <0>;
3928 thermal-sensors = <&tsens1 13>;
3931 thermal-engine-config {
3932 temperature = <125000>;
3933 hysteresis = <1000>;
3937 mdmss3_config0: mdmss3-config0 {
3938 temperature = <102000>;
3939 hysteresis = <3000>;
3943 mdmss3_config1: mdmss3-config1 {
3944 temperature = <105000>;
3945 hysteresis = <3000>;
3950 temperature = <115000>;
3951 hysteresis = <5000>;
3958 polling-delay-passive = <0>;
3959 polling-delay = <0>;
3960 thermal-sensors = <&tsens1 14>;
3963 thermal-engine-config {
3964 temperature = <125000>;
3965 hysteresis = <1000>;
3970 temperature = <115000>;
3971 hysteresis = <5000>;
3978 polling-delay-passive = <0>;
3979 polling-delay = <0>;
3980 thermal-sensors = <&tsens1 15>;
3983 thermal-engine-config {
3984 temperature = <125000>;
3985 hysteresis = <1000>;
3990 temperature = <115000>;
3991 hysteresis = <5000>;
3999 compatible = "arm,armv8-timer";
4000 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4001 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4002 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4003 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
4004 clock-frequency = <19200000>;