arch/arm64/boot/dts/qcom/sm8350.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interconnect/qcom,sm8350.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
   9 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
  11 #include <dt-bindings/clock/qcom,rpmh.h>
  12 #include <dt-bindings/dma/qcom-gpi.h>
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interconnect/qcom,sm8350.h>
  15 #include <dt-bindings/mailbox/qcom-ipcc.h>
  16 #include <dt-bindings/phy/phy-qcom-qmp.h>
  17 #include <dt-bindings/power/qcom-rpmpd.h>
  18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  19 #include <dt-bindings/thermal/thermal.h>
  20 #include <dt-bindings/interconnect/qcom,sm8350.h>
  21
  22 / {
  23         interrupt-parent = <&intc>;
  24
  25         #address-cells = <2>;
  26         #size-cells = <2>;
  27
  28         chosen { };
  29
  30         clocks {
  31                 xo_board: xo-board {
  32                         compatible = "fixed-clock";
  33                         #clock-cells = <0>;
  34                         clock-frequency = <38400000>;
  35                         clock-output-names = "xo_board";
  36                 };
  37
  38                 sleep_clk: sleep-clk {
  39                         compatible = "fixed-clock";
  40                         clock-frequency = <32000>;
  41                         #clock-cells = <0>;
  42                 };
  43         };
  44
  45         cpus {
  46                 #address-cells = <2>;
  47                 #size-cells = <0>;
  48
  49                 CPU0: cpu@0 {
  50                         device_type = "cpu";
  51                         compatible = "qcom,kryo685";
  52                         reg = <0x0 0x0>;
  53                         clocks = <&cpufreq_hw 0>;
  54                         enable-method = "psci";
  55                         next-level-cache = <&L2_0>;
  56                         qcom,freq-domain = <&cpufreq_hw 0>;
  57                         power-domains = <&CPU_PD0>;
  58                         power-domain-names = "psci";
  59                         #cooling-cells = <2>;
  60                         L2_0: l2-cache {
  61                               compatible = "cache";
  62                               cache-level = <2>;
  63                               next-level-cache = <&L3_0>;
  64                                 L3_0: l3-cache {
  65                                       compatible = "cache";
  66                                       cache-level = <3>;
  67                                 };
  68                         };
  69                 };
  70
  71                 CPU1: cpu@100 {
  72                         device_type = "cpu";
  73                         compatible = "qcom,kryo685";
  74                         reg = <0x0 0x100>;
  75                         clocks = <&cpufreq_hw 0>;
  76                         enable-method = "psci";
  77                         next-level-cache = <&L2_100>;
  78                         qcom,freq-domain = <&cpufreq_hw 0>;
  79                         power-domains = <&CPU_PD1>;
  80                         power-domain-names = "psci";
  81                         #cooling-cells = <2>;
  82                         L2_100: l2-cache {
  83                               compatible = "cache";
  84                               cache-level = <2>;
  85                               next-level-cache = <&L3_0>;
  86                         };
  87                 };
  88
  89                 CPU2: cpu@200 {
  90                         device_type = "cpu";
  91                         compatible = "qcom,kryo685";
  92                         reg = <0x0 0x200>;
  93                         clocks = <&cpufreq_hw 0>;
  94                         enable-method = "psci";
  95                         next-level-cache = <&L2_200>;
  96                         qcom,freq-domain = <&cpufreq_hw 0>;
  97                         power-domains = <&CPU_PD2>;
  98                         power-domain-names = "psci";
  99                         #cooling-cells = <2>;
 100                         L2_200: l2-cache {
 101                               compatible = "cache";
 102                               cache-level = <2>;
 103                               next-level-cache = <&L3_0>;
 104                         };
 105                 };
 106
 107                 CPU3: cpu@300 {
 108                         device_type = "cpu";
 109                         compatible = "qcom,kryo685";
 110                         reg = <0x0 0x300>;
 111                         clocks = <&cpufreq_hw 0>;
 112                         enable-method = "psci";
 113                         next-level-cache = <&L2_300>;
 114                         qcom,freq-domain = <&cpufreq_hw 0>;
 115                         power-domains = <&CPU_PD3>;
 116                         power-domain-names = "psci";
 117                         #cooling-cells = <2>;
 118                         L2_300: l2-cache {
 119                               compatible = "cache";
 120                               cache-level = <2>;
 121                               next-level-cache = <&L3_0>;
 122                         };
 123                 };
 124
 125                 CPU4: cpu@400 {
 126                         device_type = "cpu";
 127                         compatible = "qcom,kryo685";
 128                         reg = <0x0 0x400>;
 129                         clocks = <&cpufreq_hw 1>;
 130                         enable-method = "psci";
 131                         next-level-cache = <&L2_400>;
 132                         qcom,freq-domain = <&cpufreq_hw 1>;
 133                         power-domains = <&CPU_PD4>;
 134                         power-domain-names = "psci";
 135                         #cooling-cells = <2>;
 136                         L2_400: l2-cache {
 137                               compatible = "cache";
 138                               cache-level = <2>;
 139                               next-level-cache = <&L3_0>;
 140                         };
 141                 };
 142
 143                 CPU5: cpu@500 {
 144                         device_type = "cpu";
 145                         compatible = "qcom,kryo685";
 146                         reg = <0x0 0x500>;
 147                         clocks = <&cpufreq_hw 1>;
 148                         enable-method = "psci";
 149                         next-level-cache = <&L2_500>;
 150                         qcom,freq-domain = <&cpufreq_hw 1>;
 151                         power-domains = <&CPU_PD5>;
 152                         power-domain-names = "psci";
 153                         #cooling-cells = <2>;
 154                         L2_500: l2-cache {
 155                               compatible = "cache";
 156                               cache-level = <2>;
 157                               next-level-cache = <&L3_0>;
 158                         };
 159                 };
 160
 161                 CPU6: cpu@600 {
 162                         device_type = "cpu";
 163                         compatible = "qcom,kryo685";
 164                         reg = <0x0 0x600>;
 165                         clocks = <&cpufreq_hw 1>;
 166                         enable-method = "psci";
 167                         next-level-cache = <&L2_600>;
 168                         qcom,freq-domain = <&cpufreq_hw 1>;
 169                         power-domains = <&CPU_PD6>;
 170                         power-domain-names = "psci";
 171                         #cooling-cells = <2>;
 172                         L2_600: l2-cache {
 173                               compatible = "cache";
 174                               cache-level = <2>;
 175                               next-level-cache = <&L3_0>;
 176                         };
 177                 };
 178
 179                 CPU7: cpu@700 {
 180                         device_type = "cpu";
 181                         compatible = "qcom,kryo685";
 182                         reg = <0x0 0x700>;
 183                         clocks = <&cpufreq_hw 2>;
 184                         enable-method = "psci";
 185                         next-level-cache = <&L2_700>;
 186                         qcom,freq-domain = <&cpufreq_hw 2>;
 187                         power-domains = <&CPU_PD7>;
 188                         power-domain-names = "psci";
 189                         #cooling-cells = <2>;
 190                         L2_700: l2-cache {
 191                               compatible = "cache";
 192                               cache-level = <2>;
 193                               next-level-cache = <&L3_0>;
 194                         };
 195                 };
 196
 197                 cpu-map {
 198                         cluster0 {
 199                                 core0 {
 200                                         cpu = <&CPU0>;
 201                                 };
 202
 203                                 core1 {
 204                                         cpu = <&CPU1>;
 205                                 };
 206
 207                                 core2 {
 208                                         cpu = <&CPU2>;
 209                                 };
 210
 211                                 core3 {
 212                                         cpu = <&CPU3>;
 213                                 };
 214
 215                                 core4 {
 216                                         cpu = <&CPU4>;
 217                                 };
 218
 219                                 core5 {
 220                                         cpu = <&CPU5>;
 221                                 };
 222
 223                                 core6 {
 224                                         cpu = <&CPU6>;
 225                                 };
 226
 227                                 core7 {
 228                                         cpu = <&CPU7>;
 229                                 };
 230                         };
 231                 };
 232
 233                 idle-states {
 234                         entry-method = "psci";
 235
 236                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 237                                 compatible = "arm,idle-state";
 238                                 idle-state-name = "silver-rail-power-collapse";
 239                                 arm,psci-suspend-param = <0x40000004>;
 240                                 entry-latency-us = <355>;
 241                                 exit-latency-us = <909>;
 242                                 min-residency-us = <3934>;
 243                                 local-timer-stop;
 244                         };
 245
 246                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 247                                 compatible = "arm,idle-state";
 248                                 idle-state-name = "gold-rail-power-collapse";
 249                                 arm,psci-suspend-param = <0x40000004>;
 250                                 entry-latency-us = <241>;
 251                                 exit-latency-us = <1461>;
 252                                 min-residency-us = <4488>;
 253                                 local-timer-stop;
 254                         };
 255                 };
 256
 257                 domain-idle-states {
 258                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 259                                 compatible = "domain-idle-state";
 260                                 idle-state-name = "cluster-power-collapse";
 261                                 arm,psci-suspend-param = <0x4100c344>;
 262                                 entry-latency-us = <3263>;
 263                                 exit-latency-us = <6562>;
 264                                 min-residency-us = <9987>;
 265                                 local-timer-stop;
 266                         };
 267                 };
 268         };
 269
 270         firmware {
 271                 scm: scm {
 272                         compatible = "qcom,scm-sm8350", "qcom,scm";
 273                         #reset-cells = <1>;
 274                 };
 275         };
 276
 277         memory@80000000 {
 278                 device_type = "memory";
 279                 /* We expect the bootloader to fill in the size */
 280                 reg = <0x0 0x80000000 0x0 0x0>;
 281         };
 282
 283         pmu {
 284                 compatible = "arm,armv8-pmuv3";
 285                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 286         };
 287
 288         psci {
 289                 compatible = "arm,psci-1.0";
 290                 method = "smc";
 291
 292                 CPU_PD0: power-domain-cpu0 {
 293                         #power-domain-cells = <0>;
 294                         power-domains = <&CLUSTER_PD>;
 295                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 296                 };
 297
 298                 CPU_PD1: power-domain-cpu1 {
 299                         #power-domain-cells = <0>;
 300                         power-domains = <&CLUSTER_PD>;
 301                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 302                 };
 303
 304                 CPU_PD2: power-domain-cpu2 {
 305                         #power-domain-cells = <0>;
 306                         power-domains = <&CLUSTER_PD>;
 307                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 308                 };
 309
 310                 CPU_PD3: power-domain-cpu3 {
 311                         #power-domain-cells = <0>;
 312                         power-domains = <&CLUSTER_PD>;
 313                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 314                 };
 315
 316                 CPU_PD4: power-domain-cpu4 {
 317                         #power-domain-cells = <0>;
 318                         power-domains = <&CLUSTER_PD>;
 319                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 320                 };
 321
 322                 CPU_PD5: power-domain-cpu5 {
 323                         #power-domain-cells = <0>;
 324                         power-domains = <&CLUSTER_PD>;
 325                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 326                 };
 327
 328                 CPU_PD6: power-domain-cpu6 {
 329                         #power-domain-cells = <0>;
 330                         power-domains = <&CLUSTER_PD>;
 331                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 332                 };
 333
 334                 CPU_PD7: power-domain-cpu7 {
 335                         #power-domain-cells = <0>;
 336                         power-domains = <&CLUSTER_PD>;
 337                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 338                 };
 339
 340                 CLUSTER_PD: power-domain-cpu-cluster0 {
 341                         #power-domain-cells = <0>;
 342                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 343                 };
 344         };
 345
 346         qup_opp_table_100mhz: opp-table-qup100mhz {
 347                 compatible = "operating-points-v2";
 348
 349                 opp-50000000 {
 350                         opp-hz = /bits/ 64 <50000000>;
 351                         required-opps = <&rpmhpd_opp_min_svs>;
 352                 };
 353
 354                 opp-75000000 {
 355                         opp-hz = /bits/ 64 <75000000>;
 356                         required-opps = <&rpmhpd_opp_low_svs>;
 357                 };
 358
 359                 opp-100000000 {
 360                         opp-hz = /bits/ 64 <100000000>;
 361                         required-opps = <&rpmhpd_opp_svs>;
 362                 };
 363         };
 364
 365         qup_opp_table_120mhz: opp-table-qup120mhz {
 366                 compatible = "operating-points-v2";
 367
 368                 opp-50000000 {
 369                         opp-hz = /bits/ 64 <50000000>;
 370                         required-opps = <&rpmhpd_opp_min_svs>;
 371                 };
 372
 373                 opp-75000000 {
 374                         opp-hz = /bits/ 64 <75000000>;
 375                         required-opps = <&rpmhpd_opp_low_svs>;
 376                 };
 377
 378                 opp-120000000 {
 379                         opp-hz = /bits/ 64 <120000000>;
 380                         required-opps = <&rpmhpd_opp_svs>;
 381                 };
 382         };
 383
 384         reserved_memory: reserved-memory {
 385                 #address-cells = <2>;
 386                 #size-cells = <2>;
 387                 ranges;
 388
 389                 hyp_mem: memory@80000000 {
 390                         reg = <0x0 0x80000000 0x0 0x600000>;
 391                         no-map;
 392                 };
 393
 394                 xbl_aop_mem: memory@80700000 {
 395                         no-map;
 396                         reg = <0x0 0x80700000 0x0 0x160000>;
 397                 };
 398
 399                 cmd_db: memory@80860000 {
 400                         compatible = "qcom,cmd-db";
 401                         reg = <0x0 0x80860000 0x0 0x20000>;
 402                         no-map;
 403                 };
 404
 405                 reserved_xbl_uefi_log: memory@80880000 {
 406                         reg = <0x0 0x80880000 0x0 0x14000>;
 407                         no-map;
 408                 };
 409
 410                 smem@80900000 {
 411                         compatible = "qcom,smem";
 412                         reg = <0x0 0x80900000 0x0 0x200000>;
 413                         hwlocks = <&tcsr_mutex 3>;
 414                         no-map;
 415                 };
 416
 417                 cpucp_fw_mem: memory@80b00000 {
 418                         reg = <0x0 0x80b00000 0x0 0x100000>;
 419                         no-map;
 420                 };
 421
 422                 cdsp_secure_heap: memory@80c00000 {
 423                         reg = <0x0 0x80c00000 0x0 0x4600000>;
 424                         no-map;
 425                 };
 426
 427                 pil_camera_mem: mmeory@85200000 {
 428                         reg = <0x0 0x85200000 0x0 0x500000>;
 429                         no-map;
 430                 };
 431
 432                 pil_video_mem: memory@85700000 {
 433                         reg = <0x0 0x85700000 0x0 0x500000>;
 434                         no-map;
 435                 };
 436
 437                 pil_cvp_mem: memory@85c00000 {
 438                         reg = <0x0 0x85c00000 0x0 0x500000>;
 439                         no-map;
 440                 };
 441
 442                 pil_adsp_mem: memory@86100000 {
 443                         reg = <0x0 0x86100000 0x0 0x2100000>;
 444                         no-map;
 445                 };
 446
 447                 pil_slpi_mem: memory@88200000 {
 448                         reg = <0x0 0x88200000 0x0 0x1500000>;
 449                         no-map;
 450                 };
 451
 452                 pil_cdsp_mem: memory@89700000 {
 453                         reg = <0x0 0x89700000 0x0 0x1e00000>;
 454                         no-map;
 455                 };
 456
 457                 pil_ipa_fw_mem: memory@8b500000 {
 458                         reg = <0x0 0x8b500000 0x0 0x10000>;
 459                         no-map;
 460                 };
 461
 462                 pil_ipa_gsi_mem: memory@8b510000 {
 463                         reg = <0x0 0x8b510000 0x0 0xa000>;
 464                         no-map;
 465                 };
 466
 467                 pil_gpu_mem: memory@8b51a000 {
 468                         reg = <0x0 0x8b51a000 0x0 0x2000>;
 469                         no-map;
 470                 };
 471
 472                 pil_spss_mem: memory@8b600000 {
 473                         reg = <0x0 0x8b600000 0x0 0x100000>;
 474                         no-map;
 475                 };
 476
 477                 pil_modem_mem: memory@8b800000 {
 478                         reg = <0x0 0x8b800000 0x0 0x10000000>;
 479                         no-map;
 480                 };
 481
 482                 rmtfs_mem: memory@9b800000 {
 483                         compatible = "qcom,rmtfs-mem";
 484                         reg = <0x0 0x9b800000 0x0 0x280000>;
 485                         no-map;
 486
 487                         qcom,client-id = <1>;
 488                         qcom,vmid = <15>;
 489                 };
 490
 491                 hyp_reserved_mem: memory@d0000000 {
 492                         reg = <0x0 0xd0000000 0x0 0x800000>;
 493                         no-map;
 494                 };
 495
 496                 pil_trustedvm_mem: memory@d0800000 {
 497                         reg = <0x0 0xd0800000 0x0 0x76f7000>;
 498                         no-map;
 499                 };
 500
 501                 qrtr_shbuf: memory@d7ef7000 {
 502                         reg = <0x0 0xd7ef7000 0x0 0x9000>;
 503                         no-map;
 504                 };
 505
 506                 chan0_shbuf: memory@d7f00000 {
 507                         reg = <0x0 0xd7f00000 0x0 0x80000>;
 508                         no-map;
 509                 };
 510
 511                 chan1_shbuf: memory@d7f80000 {
 512                         reg = <0x0 0xd7f80000 0x0 0x80000>;
 513                         no-map;
 514                 };
 515
 516                 removed_mem: memory@d8800000 {
 517                         reg = <0x0 0xd8800000 0x0 0x6800000>;
 518                         no-map;
 519                 };
 520         };
 521
 522         smp2p-adsp {
 523                 compatible = "qcom,smp2p";
 524                 qcom,smem = <443>, <429>;
 525                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 526                                              IPCC_MPROC_SIGNAL_SMP2P
 527                                              IRQ_TYPE_EDGE_RISING>;
 528                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 529                                 IPCC_MPROC_SIGNAL_SMP2P>;
 530
 531                 qcom,local-pid = <0>;
 532                 qcom,remote-pid = <2>;
 533
 534                 smp2p_adsp_out: master-kernel {
 535                         qcom,entry-name = "master-kernel";
 536                         #qcom,smem-state-cells = <1>;
 537                 };
 538
 539                 smp2p_adsp_in: slave-kernel {
 540                         qcom,entry-name = "slave-kernel";
 541                         interrupt-controller;
 542                         #interrupt-cells = <2>;
 543                 };
 544         };
 545
 546         smp2p-cdsp {
 547                 compatible = "qcom,smp2p";
 548                 qcom,smem = <94>, <432>;
 549                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 550                                              IPCC_MPROC_SIGNAL_SMP2P
 551                                              IRQ_TYPE_EDGE_RISING>;
 552                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 553                                 IPCC_MPROC_SIGNAL_SMP2P>;
 554
 555                 qcom,local-pid = <0>;
 556                 qcom,remote-pid = <5>;
 557
 558                 smp2p_cdsp_out: master-kernel {
 559                         qcom,entry-name = "master-kernel";
 560                         #qcom,smem-state-cells = <1>;
 561                 };
 562
 563                 smp2p_cdsp_in: slave-kernel {
 564                         qcom,entry-name = "slave-kernel";
 565                         interrupt-controller;
 566                         #interrupt-cells = <2>;
 567                 };
 568         };
 569
 570         smp2p-modem {
 571                 compatible = "qcom,smp2p";
 572                 qcom,smem = <435>, <428>;
 573                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 574                                              IPCC_MPROC_SIGNAL_SMP2P
 575                                              IRQ_TYPE_EDGE_RISING>;
 576                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 577                                 IPCC_MPROC_SIGNAL_SMP2P>;
 578
 579                 qcom,local-pid = <0>;
 580                 qcom,remote-pid = <1>;
 581
 582                 smp2p_modem_out: master-kernel {
 583                         qcom,entry-name = "master-kernel";
 584                         #qcom,smem-state-cells = <1>;
 585                 };
 586
 587                 smp2p_modem_in: slave-kernel {
 588                         qcom,entry-name = "slave-kernel";
 589                         interrupt-controller;
 590                         #interrupt-cells = <2>;
 591                 };
 592
 593                 ipa_smp2p_out: ipa-ap-to-modem {
 594                         qcom,entry-name = "ipa";
 595                         #qcom,smem-state-cells = <1>;
 596                 };
 597
 598                 ipa_smp2p_in: ipa-modem-to-ap {
 599                         qcom,entry-name = "ipa";
 600                         interrupt-controller;
 601                         #interrupt-cells = <2>;
 602                 };
 603         };
 604
 605         smp2p-slpi {
 606                 compatible = "qcom,smp2p";
 607                 qcom,smem = <481>, <430>;
 608                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 609                                              IPCC_MPROC_SIGNAL_SMP2P
 610                                              IRQ_TYPE_EDGE_RISING>;
 611                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 612                                 IPCC_MPROC_SIGNAL_SMP2P>;
 613
 614                 qcom,local-pid = <0>;
 615                 qcom,remote-pid = <3>;
 616
 617                 smp2p_slpi_out: master-kernel {
 618                         qcom,entry-name = "master-kernel";
 619                         #qcom,smem-state-cells = <1>;
 620                 };
 621
 622                 smp2p_slpi_in: slave-kernel {
 623                         qcom,entry-name = "slave-kernel";
 624                         interrupt-controller;
 625                         #interrupt-cells = <2>;
 626                 };
 627         };
 628
 629         soc: soc@0 {
 630                 #address-cells = <2>;
 631                 #size-cells = <2>;
 632                 ranges = <0 0 0 0 0x10 0>;
 633                 dma-ranges = <0 0 0 0 0x10 0>;
 634                 compatible = "simple-bus";
 635
 636                 gcc: clock-controller@100000 {
 637                         compatible = "qcom,gcc-sm8350";
 638                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 639                         #clock-cells = <1>;
 640                         #reset-cells = <1>;
 641                         #power-domain-cells = <1>;
 642                         clock-names = "bi_tcxo",
 643                                       "sleep_clk",
 644                                       "pcie_0_pipe_clk",
 645                                       "pcie_1_pipe_clk",
 646                                       "ufs_card_rx_symbol_0_clk",
 647                                       "ufs_card_rx_symbol_1_clk",
 648                                       "ufs_card_tx_symbol_0_clk",
 649                                       "ufs_phy_rx_symbol_0_clk",
 650                                       "ufs_phy_rx_symbol_1_clk",
 651                                       "ufs_phy_tx_symbol_0_clk",
 652                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk",
 653                                       "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
 654                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 655                                  <&sleep_clk>,
 656                                  <&pcie0_phy>,
 657                                  <&pcie1_phy>,
 658                                  <0>,
 659                                  <0>,
 660                                  <0>,
 661                                  <&ufs_mem_phy_lanes 0>,
 662                                  <&ufs_mem_phy_lanes 1>,
 663                                  <&ufs_mem_phy_lanes 2>,
 664                                  <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 665                                  <0>;
 666                 };
 667
 668                 ipcc: mailbox@408000 {
 669                         compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
 670                         reg = <0 0x00408000 0 0x1000>;
 671                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 672                         interrupt-controller;
 673                         #interrupt-cells = <3>;
 674                         #mbox-cells = <2>;
 675                 };
 676
 677                 gpi_dma2: dma-controller@800000 {
 678                         compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
 679                         reg = <0 0x00800000 0 0x60000>;
 680                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 681                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 682                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 683                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 686                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 687                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 688                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 689                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 690                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 692                         dma-channels = <12>;
 693                         dma-channel-mask = <0xff>;
 694                         iommus = <&apps_smmu 0x5f6 0x0>;
 695                         #dma-cells = <3>;
 696                         status = "disabled";
 697                 };
 698
 699                 qupv3_id_2: geniqup@8c0000 {
 700                         compatible = "qcom,geni-se-qup";
 701                         reg = <0x0 0x008c0000 0x0 0x6000>;
 702                         clock-names = "m-ahb", "s-ahb";
 703                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 704                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 705                         iommus = <&apps_smmu 0x5e3 0x0>;
 706                         #address-cells = <2>;
 707                         #size-cells = <2>;
 708                         ranges;
 709                         status = "disabled";
 710
 711                         i2c14: i2c@880000 {
 712                                 compatible = "qcom,geni-i2c";
 713                                 reg = <0 0x00880000 0 0x4000>;
 714                                 clock-names = "se";
 715                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 716                                 pinctrl-names = "default";
 717                                 pinctrl-0 = <&qup_i2c14_default>;
 718                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 719                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 720                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 721                                 dma-names = "tx", "rx";
 722                                 #address-cells = <1>;
 723                                 #size-cells = <0>;
 724                                 status = "disabled";
 725                         };
 726
 727                         spi14: spi@880000 {
 728                                 compatible = "qcom,geni-spi";
 729                                 reg = <0 0x00880000 0 0x4000>;
 730                                 clock-names = "se";
 731                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 732                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 733                                 power-domains = <&rpmhpd SM8350_CX>;
 734                                 operating-points-v2 = <&qup_opp_table_120mhz>;
 735                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 736                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 737                                 dma-names = "tx", "rx";
 738                                 #address-cells = <1>;
 739                                 #size-cells = <0>;
 740                                 status = "disabled";
 741                         };
 742
 743                         i2c15: i2c@884000 {
 744                                 compatible = "qcom,geni-i2c";
 745                                 reg = <0 0x00884000 0 0x4000>;
 746                                 clock-names = "se";
 747                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 748                                 pinctrl-names = "default";
 749                                 pinctrl-0 = <&qup_i2c15_default>;
 750                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 751                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 752                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 753                                 dma-names = "tx", "rx";
 754                                 #address-cells = <1>;
 755                                 #size-cells = <0>;
 756                                 status = "disabled";
 757                         };
 758
 759                         spi15: spi@884000 {
 760                                 compatible = "qcom,geni-spi";
 761                                 reg = <0 0x00884000 0 0x4000>;
 762                                 clock-names = "se";
 763                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 764                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 765                                 power-domains = <&rpmhpd SM8350_CX>;
 766                                 operating-points-v2 = <&qup_opp_table_120mhz>;
 767                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 768                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 769                                 dma-names = "tx", "rx";
 770                                 #address-cells = <1>;
 771                                 #size-cells = <0>;
 772                                 status = "disabled";
 773                         };
 774
 775                         i2c16: i2c@888000 {
 776                                 compatible = "qcom,geni-i2c";
 777                                 reg = <0 0x00888000 0 0x4000>;
 778                                 clock-names = "se";
 779                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 780                                 pinctrl-names = "default";
 781                                 pinctrl-0 = <&qup_i2c16_default>;
 782                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 783                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 784                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 785                                 dma-names = "tx", "rx";
 786                                 #address-cells = <1>;
 787                                 #size-cells = <0>;
 788                                 status = "disabled";
 789                         };
 790
 791                         spi16: spi@888000 {
 792                                 compatible = "qcom,geni-spi";
 793                                 reg = <0 0x00888000 0 0x4000>;
 794                                 clock-names = "se";
 795                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 796                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 797                                 power-domains = <&rpmhpd SM8350_CX>;
 798                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 799                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 800                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 801                                 dma-names = "tx", "rx";
 802                                 #address-cells = <1>;
 803                                 #size-cells = <0>;
 804                                 status = "disabled";
 805                         };
 806
 807                         i2c17: i2c@88c000 {
 808                                 compatible = "qcom,geni-i2c";
 809                                 reg = <0 0x0088c000 0 0x4000>;
 810                                 clock-names = "se";
 811                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 812                                 pinctrl-names = "default";
 813                                 pinctrl-0 = <&qup_i2c17_default>;
 814                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 815                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 816                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 817                                 dma-names = "tx", "rx";
 818                                 #address-cells = <1>;
 819                                 #size-cells = <0>;
 820                                 status = "disabled";
 821                         };
 822
 823                         spi17: spi@88c000 {
 824                                 compatible = "qcom,geni-spi";
 825                                 reg = <0 0x0088c000 0 0x4000>;
 826                                 clock-names = "se";
 827                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 828                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 829                                 power-domains = <&rpmhpd SM8350_CX>;
 830                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 831                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
 832                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
 833                                 dma-names = "tx", "rx";
 834                                 #address-cells = <1>;
 835                                 #size-cells = <0>;
 836                                 status = "disabled";
 837                         };
 838
 839                         /* QUP no. 18 seems to be strictly SPI/UART-only */
 840
 841                         spi18: spi@890000 {
 842                                 compatible = "qcom,geni-spi";
 843                                 reg = <0 0x00890000 0 0x4000>;
 844                                 clock-names = "se";
 845                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 846                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 847                                 power-domains = <&rpmhpd SM8350_CX>;
 848                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 849                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
 850                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
 851                                 dma-names = "tx", "rx";
 852                                 #address-cells = <1>;
 853                                 #size-cells = <0>;
 854                                 status = "disabled";
 855                         };
 856
 857                         uart18: serial@890000 {
 858                                 compatible = "qcom,geni-uart";
 859                                 reg = <0 0x00890000 0 0x4000>;
 860                                 clock-names = "se";
 861                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 862                                 pinctrl-names = "default";
 863                                 pinctrl-0 = <&qup_uart18_default>;
 864                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 865                                 power-domains = <&rpmhpd SM8350_CX>;
 866                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 867                                 status = "disabled";
 868                         };
 869
 870                         i2c19: i2c@894000 {
 871                                 compatible = "qcom,geni-i2c";
 872                                 reg = <0 0x00894000 0 0x4000>;
 873                                 clock-names = "se";
 874                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 875                                 pinctrl-names = "default";
 876                                 pinctrl-0 = <&qup_i2c19_default>;
 877                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 878                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
 879                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
 880                                 dma-names = "tx", "rx";
 881                                 #address-cells = <1>;
 882                                 #size-cells = <0>;
 883                                 status = "disabled";
 884                         };
 885
 886                         spi19: spi@894000 {
 887                                 compatible = "qcom,geni-spi";
 888                                 reg = <0 0x00894000 0 0x4000>;
 889                                 clock-names = "se";
 890                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 891                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 892                                 power-domains = <&rpmhpd SM8350_CX>;
 893                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 894                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
 895                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
 896                                 dma-names = "tx", "rx";
 897                                 #address-cells = <1>;
 898                                 #size-cells = <0>;
 899                                 status = "disabled";
 900                         };
 901                 };
 902
 903                 gpi_dma0: dma-controller@900000 {
 904                         compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
 905                         reg = <0 0x09800000 0 0x60000>;
 906                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 907                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 908                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 909                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 910                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 911                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 912                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 913                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 914                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 915                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 916                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 917                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 918                         dma-channels = <12>;
 919                         dma-channel-mask = <0x7e>;
 920                         iommus = <&apps_smmu 0x5b6 0x0>;
 921                         #dma-cells = <3>;
 922                         status = "disabled";
 923                 };
 924
 925                 qupv3_id_0: geniqup@9c0000 {
 926                         compatible = "qcom,geni-se-qup";
 927                         reg = <0x0 0x009c0000 0x0 0x6000>;
 928                         clock-names = "m-ahb", "s-ahb";
 929                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 930                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 931                         iommus = <&apps_smmu 0x5a3 0>;
 932                         #address-cells = <2>;
 933                         #size-cells = <2>;
 934                         ranges;
 935                         status = "disabled";
 936
 937                         i2c0: i2c@980000 {
 938                                 compatible = "qcom,geni-i2c";
 939                                 reg = <0 0x00980000 0 0x4000>;
 940                                 clock-names = "se";
 941                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 942                                 pinctrl-names = "default";
 943                                 pinctrl-0 = <&qup_i2c0_default>;
 944                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 945                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 946                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 947                                 dma-names = "tx", "rx";
 948                                 #address-cells = <1>;
 949                                 #size-cells = <0>;
 950                                 status = "disabled";
 951                         };
 952
 953                         spi0: spi@980000 {
 954                                 compatible = "qcom,geni-spi";
 955                                 reg = <0 0x00980000 0 0x4000>;
 956                                 clock-names = "se";
 957                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 958                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 959                                 power-domains = <&rpmhpd SM8350_CX>;
 960                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 961                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 962                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 963                                 dma-names = "tx", "rx";
 964                                 #address-cells = <1>;
 965                                 #size-cells = <0>;
 966                                 status = "disabled";
 967                         };
 968
 969                         i2c1: i2c@984000 {
 970                                 compatible = "qcom,geni-i2c";
 971                                 reg = <0 0x00984000 0 0x4000>;
 972                                 clock-names = "se";
 973                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 974                                 pinctrl-names = "default";
 975                                 pinctrl-0 = <&qup_i2c1_default>;
 976                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 977                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 978                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 979                                 dma-names = "tx", "rx";
 980                                 #address-cells = <1>;
 981                                 #size-cells = <0>;
 982                                 status = "disabled";
 983                         };
 984
 985                         spi1: spi@984000 {
 986                                 compatible = "qcom,geni-spi";
 987                                 reg = <0 0x00984000 0 0x4000>;
 988                                 clock-names = "se";
 989                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 990                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 991                                 power-domains = <&rpmhpd SM8350_CX>;
 992                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 993                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
 994                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
 995                                 dma-names = "tx", "rx";
 996                                 #address-cells = <1>;
 997                                 #size-cells = <0>;
 998                                 status = "disabled";
 999                         };
1000
1001                         i2c2: i2c@988000 {
1002                                 compatible = "qcom,geni-i2c";
1003                                 reg = <0 0x00988000 0 0x4000>;
1004                                 clock-names = "se";
1005                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1006                                 pinctrl-names = "default";
1007                                 pinctrl-0 = <&qup_i2c2_default>;
1008                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1009                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1010                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1011                                 dma-names = "tx", "rx";
1012                                 #address-cells = <1>;
1013                                 #size-cells = <0>;
1014                                 status = "disabled";
1015                         };
1016
1017                         spi2: spi@988000 {
1018                                 compatible = "qcom,geni-spi";
1019                                 reg = <0 0x00988000 0 0x4000>;
1020                                 clock-names = "se";
1021                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1023                                 power-domains = <&rpmhpd SM8350_CX>;
1024                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1025                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1026                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1027                                 dma-names = "tx", "rx";
1028                                 #address-cells = <1>;
1029                                 #size-cells = <0>;
1030                                 status = "disabled";
1031                         };
1032
1033                         uart2: serial@98c000 {
1034                                 compatible = "qcom,geni-debug-uart";
1035                                 reg = <0 0x0098c000 0 0x4000>;
1036                                 clock-names = "se";
1037                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038                                 pinctrl-names = "default";
1039                                 pinctrl-0 = <&qup_uart3_default_state>;
1040                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041                                 power-domains = <&rpmhpd SM8350_CX>;
1042                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1043                                 status = "disabled";
1044                         };
1045
1046                         /* QUP no. 3 seems to be strictly SPI-only */
1047
1048                         spi3: spi@98c000 {
1049                                 compatible = "qcom,geni-spi";
1050                                 reg = <0 0x0098c000 0 0x4000>;
1051                                 clock-names = "se";
1052                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1053                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1054                                 power-domains = <&rpmhpd SM8350_CX>;
1055                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1056                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1057                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1058                                 dma-names = "tx", "rx";
1059                                 #address-cells = <1>;
1060                                 #size-cells = <0>;
1061                                 status = "disabled";
1062                         };
1063
1064                         i2c4: i2c@990000 {
1065                                 compatible = "qcom,geni-i2c";
1066                                 reg = <0 0x00990000 0 0x4000>;
1067                                 clock-names = "se";
1068                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1069                                 pinctrl-names = "default";
1070                                 pinctrl-0 = <&qup_i2c4_default>;
1071                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1072                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1073                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1074                                 dma-names = "tx", "rx";
1075                                 #address-cells = <1>;
1076                                 #size-cells = <0>;
1077                                 status = "disabled";
1078                         };
1079
1080                         spi4: spi@990000 {
1081                                 compatible = "qcom,geni-spi";
1082                                 reg = <0 0x00990000 0 0x4000>;
1083                                 clock-names = "se";
1084                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1085                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1086                                 power-domains = <&rpmhpd SM8350_CX>;
1087                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1088                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1089                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1090                                 dma-names = "tx", "rx";
1091                                 #address-cells = <1>;
1092                                 #size-cells = <0>;
1093                                 status = "disabled";
1094                         };
1095
1096                         i2c5: i2c@994000 {
1097                                 compatible = "qcom,geni-i2c";
1098                                 reg = <0 0x00994000 0 0x4000>;
1099                                 clock-names = "se";
1100                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1101                                 pinctrl-names = "default";
1102                                 pinctrl-0 = <&qup_i2c5_default>;
1103                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1104                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1105                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1106                                 dma-names = "tx", "rx";
1107                                 #address-cells = <1>;
1108                                 #size-cells = <0>;
1109                                 status = "disabled";
1110                         };
1111
1112                         spi5: spi@994000 {
1113                                 compatible = "qcom,geni-spi";
1114                                 reg = <0 0x00994000 0 0x4000>;
1115                                 clock-names = "se";
1116                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1117                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1118                                 power-domains = <&rpmhpd SM8350_CX>;
1119                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1120                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1121                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1122                                 dma-names = "tx", "rx";
1123                                 #address-cells = <1>;
1124                                 #size-cells = <0>;
1125                                 status = "disabled";
1126                         };
1127
1128                         i2c6: i2c@998000 {
1129                                 compatible = "qcom,geni-i2c";
1130                                 reg = <0 0x00998000 0 0x4000>;
1131                                 clock-names = "se";
1132                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1133                                 pinctrl-names = "default";
1134                                 pinctrl-0 = <&qup_i2c6_default>;
1135                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1136                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1137                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1138                                 dma-names = "tx", "rx";
1139                                 #address-cells = <1>;
1140                                 #size-cells = <0>;
1141                                 status = "disabled";
1142                         };
1143
1144                         spi6: spi@998000 {
1145                                 compatible = "qcom,geni-spi";
1146                                 reg = <0 0x00998000 0 0x4000>;
1147                                 clock-names = "se";
1148                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1149                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1150                                 power-domains = <&rpmhpd SM8350_CX>;
1151                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1152                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1153                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1154                                 dma-names = "tx", "rx";
1155                                 #address-cells = <1>;
1156                                 #size-cells = <0>;
1157                                 status = "disabled";
1158                         };
1159
1160                         uart6: serial@998000 {
1161                                 compatible = "qcom,geni-uart";
1162                                 reg = <0 0x00998000 0 0x4000>;
1163                                 clock-names = "se";
1164                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1165                                 pinctrl-names = "default";
1166                                 pinctrl-0 = <&qup_uart6_default>;
1167                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1168                                 power-domains = <&rpmhpd SM8350_CX>;
1169                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1170                                 status = "disabled";
1171                         };
1172
1173                         i2c7: i2c@99c000 {
1174                                 compatible = "qcom,geni-i2c";
1175                                 reg = <0 0x0099c000 0 0x4000>;
1176                                 clock-names = "se";
1177                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1178                                 pinctrl-names = "default";
1179                                 pinctrl-0 = <&qup_i2c7_default>;
1180                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1181                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1182                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1183                                 dma-names = "tx", "rx";
1184                                 #address-cells = <1>;
1185                                 #size-cells = <0>;
1186                                 status = "disabled";
1187                         };
1188
1189                         spi7: spi@99c000 {
1190                                 compatible = "qcom,geni-spi";
1191                                 reg = <0 0x0099c000 0 0x4000>;
1192                                 clock-names = "se";
1193                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1194                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1195                                 power-domains = <&rpmhpd SM8350_CX>;
1196                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1197                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1198                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1199                                 dma-names = "tx", "rx";
1200                                 #address-cells = <1>;
1201                                 #size-cells = <0>;
1202                                 status = "disabled";
1203                         };
1204                 };
1205
1206                 gpi_dma1: dma-controller@a00000 {
1207                         compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
1208                         reg = <0 0x00a00000 0 0x60000>;
1209                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1210                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1211                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1212                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1213                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1214                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1215                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1216                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1217                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1218                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1219                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1220                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1221                         dma-channels = <12>;
1222                         dma-channel-mask = <0xff>;
1223                         iommus = <&apps_smmu 0x56 0x0>;
1224                         #dma-cells = <3>;
1225                         status = "disabled";
1226                 };
1227
1228                 qupv3_id_1: geniqup@ac0000 {
1229                         compatible = "qcom,geni-se-qup";
1230                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1231                         clock-names = "m-ahb", "s-ahb";
1232                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1233                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1234                         iommus = <&apps_smmu 0x43 0>;
1235                         #address-cells = <2>;
1236                         #size-cells = <2>;
1237                         ranges;
1238                         status = "disabled";
1239
1240                         i2c8: i2c@a80000 {
1241                                 compatible = "qcom,geni-i2c";
1242                                 reg = <0 0x00a80000 0 0x4000>;
1243                                 clock-names = "se";
1244                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1245                                 pinctrl-names = "default";
1246                                 pinctrl-0 = <&qup_i2c8_default>;
1247                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1248                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1249                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1250                                 dma-names = "tx", "rx";
1251                                 #address-cells = <1>;
1252                                 #size-cells = <0>;
1253                                 status = "disabled";
1254                         };
1255
1256                         spi8: spi@a80000 {
1257                                 compatible = "qcom,geni-spi";
1258                                 reg = <0 0x00a80000 0 0x4000>;
1259                                 clock-names = "se";
1260                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1261                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1262                                 power-domains = <&rpmhpd SM8350_CX>;
1263                                 operating-points-v2 = <&qup_opp_table_120mhz>;
1264                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1265                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1266                                 dma-names = "tx", "rx";
1267                                 #address-cells = <1>;
1268                                 #size-cells = <0>;
1269                                 status = "disabled";
1270                         };
1271
1272                         i2c9: i2c@a84000 {
1273                                 compatible = "qcom,geni-i2c";
1274                                 reg = <0 0x00a84000 0 0x4000>;
1275                                 clock-names = "se";
1276                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1277                                 pinctrl-names = "default";
1278                                 pinctrl-0 = <&qup_i2c9_default>;
1279                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1280                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1281                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1282                                 dma-names = "tx", "rx";
1283                                 #address-cells = <1>;
1284                                 #size-cells = <0>;
1285                                 status = "disabled";
1286                         };
1287
1288                         spi9: spi@a84000 {
1289                                 compatible = "qcom,geni-spi";
1290                                 reg = <0 0x00a84000 0 0x4000>;
1291                                 clock-names = "se";
1292                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1293                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1294                                 power-domains = <&rpmhpd SM8350_CX>;
1295                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1296                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1297                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1298                                 dma-names = "tx", "rx";
1299                                 #address-cells = <1>;
1300                                 #size-cells = <0>;
1301                                 status = "disabled";
1302                         };
1303
1304                         i2c10: i2c@a88000 {
1305                                 compatible = "qcom,geni-i2c";
1306                                 reg = <0 0x00a88000 0 0x4000>;
1307                                 clock-names = "se";
1308                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1309                                 pinctrl-names = "default";
1310                                 pinctrl-0 = <&qup_i2c10_default>;
1311                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1312                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1313                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1314                                 dma-names = "tx", "rx";
1315                                 #address-cells = <1>;
1316                                 #size-cells = <0>;
1317                                 status = "disabled";
1318                         };
1319
1320                         spi10: spi@a88000 {
1321                                 compatible = "qcom,geni-spi";
1322                                 reg = <0 0x00a88000 0 0x4000>;
1323                                 clock-names = "se";
1324                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1325                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326                                 power-domains = <&rpmhpd SM8350_CX>;
1327                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1328                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1329                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1330                                 dma-names = "tx", "rx";
1331                                 #address-cells = <1>;
1332                                 #size-cells = <0>;
1333                                 status = "disabled";
1334                         };
1335
1336                         i2c11: i2c@a8c000 {
1337                                 compatible = "qcom,geni-i2c";
1338                                 reg = <0 0x00a8c000 0 0x4000>;
1339                                 clock-names = "se";
1340                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1341                                 pinctrl-names = "default";
1342                                 pinctrl-0 = <&qup_i2c11_default>;
1343                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1344                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1345                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1346                                 dma-names = "tx", "rx";
1347                                 #address-cells = <1>;
1348                                 #size-cells = <0>;
1349                                 status = "disabled";
1350                         };
1351
1352                         spi11: spi@a8c000 {
1353                                 compatible = "qcom,geni-spi";
1354                                 reg = <0 0x00a8c000 0 0x4000>;
1355                                 clock-names = "se";
1356                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1357                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1358                                 power-domains = <&rpmhpd SM8350_CX>;
1359                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1360                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1361                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1362                                 dma-names = "tx", "rx";
1363                                 #address-cells = <1>;
1364                                 #size-cells = <0>;
1365                                 status = "disabled";
1366                         };
1367
1368                         i2c12: i2c@a90000 {
1369                                 compatible = "qcom,geni-i2c";
1370                                 reg = <0 0x00a90000 0 0x4000>;
1371                                 clock-names = "se";
1372                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1373                                 pinctrl-names = "default";
1374                                 pinctrl-0 = <&qup_i2c12_default>;
1375                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1376                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1377                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1378                                 dma-names = "tx", "rx";
1379                                 #address-cells = <1>;
1380                                 #size-cells = <0>;
1381                                 status = "disabled";
1382                         };
1383
1384                         spi12: spi@a90000 {
1385                                 compatible = "qcom,geni-spi";
1386                                 reg = <0 0x00a90000 0 0x4000>;
1387                                 clock-names = "se";
1388                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1389                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1390                                 power-domains = <&rpmhpd SM8350_CX>;
1391                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1392                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1393                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1394                                 dma-names = "tx", "rx";
1395                                 #address-cells = <1>;
1396                                 #size-cells = <0>;
1397                                 status = "disabled";
1398                         };
1399
1400                         i2c13: i2c@a94000 {
1401                                 compatible = "qcom,geni-i2c";
1402                                 reg = <0 0x00a94000 0 0x4000>;
1403                                 clock-names = "se";
1404                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1405                                 pinctrl-names = "default";
1406                                 pinctrl-0 = <&qup_i2c13_default>;
1407                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1408                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1409                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1410                                 dma-names = "tx", "rx";
1411                                 #address-cells = <1>;
1412                                 #size-cells = <0>;
1413                                 status = "disabled";
1414                         };
1415
1416                         spi13: spi@a94000 {
1417                                 compatible = "qcom,geni-spi";
1418                                 reg = <0 0x00a94000 0 0x4000>;
1419                                 clock-names = "se";
1420                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1421                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1422                                 power-domains = <&rpmhpd SM8350_CX>;
1423                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1424                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1425                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1426                                 dma-names = "tx", "rx";
1427                                 #address-cells = <1>;
1428                                 #size-cells = <0>;
1429                                 status = "disabled";
1430                         };
1431                 };
1432
1433                 rng: rng@10d3000 {
1434                         compatible = "qcom,prng-ee";
1435                         reg = <0 0x010d3000 0 0x1000>;
1436                         clocks = <&rpmhcc RPMH_HWKM_CLK>;
1437                         clock-names = "core";
1438                 };
1439
1440                 config_noc: interconnect@1500000 {
1441                         compatible = "qcom,sm8350-config-noc";
1442                         reg = <0 0x01500000 0 0xa580>;
1443                         #interconnect-cells = <2>;
1444                         qcom,bcm-voters = <&apps_bcm_voter>;
1445                 };
1446
1447                 mc_virt: interconnect@1580000 {
1448                         compatible = "qcom,sm8350-mc-virt";
1449                         reg = <0 0x01580000 0 0x1000>;
1450                         #interconnect-cells = <2>;
1451                         qcom,bcm-voters = <&apps_bcm_voter>;
1452                 };
1453
1454                 system_noc: interconnect@1680000 {
1455                         compatible = "qcom,sm8350-system-noc";
1456                         reg = <0 0x01680000 0 0x1c200>;
1457                         #interconnect-cells = <2>;
1458                         qcom,bcm-voters = <&apps_bcm_voter>;
1459                 };
1460
1461                 aggre1_noc: interconnect@16e0000 {
1462                         compatible = "qcom,sm8350-aggre1-noc";
1463                         reg = <0 0x016e0000 0 0x1f180>;
1464                         #interconnect-cells = <2>;
1465                         qcom,bcm-voters = <&apps_bcm_voter>;
1466                 };
1467
1468                 aggre2_noc: interconnect@1700000 {
1469                         compatible = "qcom,sm8350-aggre2-noc";
1470                         reg = <0 0x01700000 0 0x33000>;
1471                         #interconnect-cells = <2>;
1472                         qcom,bcm-voters = <&apps_bcm_voter>;
1473                 };
1474
1475                 mmss_noc: interconnect@1740000 {
1476                         compatible = "qcom,sm8350-mmss-noc";
1477                         reg = <0 0x01740000 0 0x1f080>;
1478                         #interconnect-cells = <2>;
1479                         qcom,bcm-voters = <&apps_bcm_voter>;
1480                 };
1481
1482                 pcie0: pci@1c00000 {
1483                         compatible = "qcom,pcie-sm8350";
1484                         reg = <0 0x01c00000 0 0x3000>,
1485                               <0 0x60000000 0 0xf1d>,
1486                               <0 0x60000f20 0 0xa8>,
1487                               <0 0x60001000 0 0x1000>,
1488                               <0 0x60100000 0 0x100000>;
1489                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1490                         device_type = "pci";
1491                         linux,pci-domain = <0>;
1492                         bus-range = <0x00 0xff>;
1493                         num-lanes = <1>;
1494
1495                         #address-cells = <3>;
1496                         #size-cells = <2>;
1497
1498                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1499                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1500
1501                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1502                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1503                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1504                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1505                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1506                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1507                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1508                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1509                         interrupt-names = "msi0", "msi1", "msi2", "msi3",
1510                                           "msi4", "msi5", "msi6", "msi7";
1511                         #interrupt-cells = <1>;
1512                         interrupt-map-mask = <0 0 0 0x7>;
1513                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1514                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1515                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1516                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1517
1518                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1519                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1520                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1521                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1522                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1523                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1524                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1525                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1526                                  <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
1527                         clock-names = "aux",
1528                                       "cfg",
1529                                       "bus_master",
1530                                       "bus_slave",
1531                                       "slave_q2a",
1532                                       "tbu",
1533                                       "ddrss_sf_tbu",
1534                                       "aggre1",
1535                                       "aggre0";
1536
1537                         iommus = <&apps_smmu 0x1c00 0x7f>;
1538                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1539                                     <0x100 &apps_smmu 0x1c01 0x1>;
1540
1541                         resets = <&gcc GCC_PCIE_0_BCR>;
1542                         reset-names = "pci";
1543
1544                         power-domains = <&gcc PCIE_0_GDSC>;
1545
1546                         phys = <&pcie0_phy>;
1547                         phy-names = "pciephy";
1548
1549                         status = "disabled";
1550                 };
1551
1552                 pcie0_phy: phy@1c06000 {
1553                         compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1554                         reg = <0 0x01c06000 0 0x2000>;
1555                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1556                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1557                                  <&gcc GCC_PCIE_0_CLKREF_EN>,
1558                                  <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
1559                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
1560                         clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1561
1562                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1563                         reset-names = "phy";
1564
1565                         assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1566                         assigned-clock-rates = <100000000>;
1567
1568                         #clock-cells = <0>;
1569                         clock-output-names = "pcie_0_pipe_clk";
1570
1571                         #phy-cells = <0>;
1572
1573                         status = "disabled";
1574                 };
1575
1576                 pcie1: pci@1c08000 {
1577                         compatible = "qcom,pcie-sm8350";
1578                         reg = <0 0x01c08000 0 0x3000>,
1579                               <0 0x40000000 0 0xf1d>,
1580                               <0 0x40000f20 0 0xa8>,
1581                               <0 0x40001000 0 0x1000>,
1582                               <0 0x40100000 0 0x100000>;
1583                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1584                         device_type = "pci";
1585                         linux,pci-domain = <1>;
1586                         bus-range = <0x00 0xff>;
1587                         num-lanes = <2>;
1588
1589                         #address-cells = <3>;
1590                         #size-cells = <2>;
1591
1592                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1593                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1594
1595                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1596                         interrupt-names = "msi";
1597                         #interrupt-cells = <1>;
1598                         interrupt-map-mask = <0 0 0 0x7>;
1599                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1600                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1601                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1602                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1603
1604                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1605                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1606                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1607                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1608                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1609                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1610                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1611                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1612                         clock-names = "aux",
1613                                       "cfg",
1614                                       "bus_master",
1615                                       "bus_slave",
1616                                       "slave_q2a",
1617                                       "tbu",
1618                                       "ddrss_sf_tbu",
1619                                       "aggre1";
1620
1621                         iommus = <&apps_smmu 0x1c80 0x7f>;
1622                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1623                                     <0x100 &apps_smmu 0x1c81 0x1>;
1624
1625                         resets = <&gcc GCC_PCIE_1_BCR>;
1626                         reset-names = "pci";
1627
1628                         power-domains = <&gcc PCIE_1_GDSC>;
1629
1630                         phys = <&pcie1_phy>;
1631                         phy-names = "pciephy";
1632
1633                         status = "disabled";
1634                 };
1635
1636                 pcie1_phy: phy@1c0f000 {
1637                         compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1638                         reg = <0 0x01c0e000 0 0x2000>;
1639                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1640                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1641                                  <&gcc GCC_PCIE_1_CLKREF_EN>,
1642                                  <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
1643                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
1644                         clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1645
1646                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1647                         reset-names = "phy";
1648
1649                         assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1650                         assigned-clock-rates = <100000000>;
1651
1652                         #clock-cells = <0>;
1653                         clock-output-names = "pcie_1_pipe_clk";
1654
1655                         #phy-cells = <0>;
1656
1657                         status = "disabled";
1658                 };
1659
1660                 ufs_mem_hc: ufshc@1d84000 {
1661                         compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1662                                      "jedec,ufs-2.0";
1663                         reg = <0 0x01d84000 0 0x3000>;
1664                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1665                         phys = <&ufs_mem_phy_lanes>;
1666                         phy-names = "ufsphy";
1667                         lanes-per-direction = <2>;
1668                         #reset-cells = <1>;
1669                         resets = <&gcc GCC_UFS_PHY_BCR>;
1670                         reset-names = "rst";
1671
1672                         power-domains = <&gcc UFS_PHY_GDSC>;
1673
1674                         iommus = <&apps_smmu 0xe0 0x0>;
1675
1676                         clock-names =
1677                                 "core_clk",
1678                                 "bus_aggr_clk",
1679                                 "iface_clk",
1680                                 "core_clk_unipro",
1681                                 "ref_clk",
1682                                 "tx_lane0_sync_clk",
1683                                 "rx_lane0_sync_clk",
1684                                 "rx_lane1_sync_clk";
1685                         clocks =
1686                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1687                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1688                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1689                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1690                                 <&rpmhcc RPMH_CXO_CLK>,
1691                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1692                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1693                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1694                         freq-table-hz =
1695                                 <75000000 300000000>,
1696                                 <0 0>,
1697                                 <0 0>,
1698                                 <75000000 300000000>,
1699                                 <0 0>,
1700                                 <0 0>,
1701                                 <0 0>,
1702                                 <0 0>;
1703                         status = "disabled";
1704                 };
1705
1706                 ufs_mem_phy: phy@1d87000 {
1707                         compatible = "qcom,sm8350-qmp-ufs-phy";
1708                         reg = <0 0x01d87000 0 0x1c4>;
1709                         #address-cells = <2>;
1710                         #size-cells = <2>;
1711                         ranges;
1712                         clock-names = "ref",
1713                                       "ref_aux";
1714                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1715                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1716
1717                         resets = <&ufs_mem_hc 0>;
1718                         reset-names = "ufsphy";
1719                         status = "disabled";
1720
1721                         ufs_mem_phy_lanes: phy@1d87400 {
1722                                 reg = <0 0x01d87400 0 0x188>,
1723                                       <0 0x01d87600 0 0x200>,
1724                                       <0 0x01d87c00 0 0x200>,
1725                                       <0 0x01d87800 0 0x188>,
1726                                       <0 0x01d87a00 0 0x200>;
1727                                 #clock-cells = <1>;
1728                                 #phy-cells = <0>;
1729                         };
1730                 };
1731
1732                 ipa: ipa@1e40000 {
1733                         compatible = "qcom,sm8350-ipa";
1734
1735                         iommus = <&apps_smmu 0x5c0 0x0>,
1736                                  <&apps_smmu 0x5c2 0x0>;
1737                         reg = <0 0x01e40000 0 0x8000>,
1738                               <0 0x01e50000 0 0x4b20>,
1739                               <0 0x01e04000 0 0x23000>;
1740                         reg-names = "ipa-reg",
1741                                     "ipa-shared",
1742                                     "gsi";
1743
1744                         interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1745                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1746                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1747                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1748                         interrupt-names = "ipa",
1749                                           "gsi",
1750                                           "ipa-clock-query",
1751                                           "ipa-setup-ready";
1752
1753                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1754                         clock-names = "core";
1755
1756                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1757                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1758                         interconnect-names = "memory",
1759                                              "config";
1760
1761                         qcom,qmp = <&aoss_qmp>;
1762
1763                         qcom,smem-states = <&ipa_smp2p_out 0>,
1764                                            <&ipa_smp2p_out 1>;
1765                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1766                                                 "ipa-clock-enabled";
1767
1768                         status = "disabled";
1769                 };
1770
1771                 tcsr_mutex: hwlock@1f40000 {
1772                         compatible = "qcom,tcsr-mutex";
1773                         reg = <0x0 0x01f40000 0x0 0x40000>;
1774                         #hwlock-cells = <1>;
1775                 };
1776
1777                 gpu: gpu@3d00000 {
1778                         compatible = "qcom,adreno-660.1", "qcom,adreno";
1779
1780                         reg = <0 0x03d00000 0 0x40000>,
1781                               <0 0x03d9e000 0 0x1000>,
1782                               <0 0x03d61000 0 0x800>;
1783                         reg-names = "kgsl_3d0_reg_memory",
1784                                     "cx_mem",
1785                                     "cx_dbgc";
1786
1787                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1788
1789                         iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
1790
1791                         operating-points-v2 = <&gpu_opp_table>;
1792
1793                         qcom,gmu = <&gmu>;
1794
1795                         status = "disabled";
1796
1797                         zap-shader {
1798                                 memory-region = <&pil_gpu_mem>;
1799                         };
1800
1801                         /* note: downstream checks gpu binning for 670 Mhz */
1802                         gpu_opp_table: opp-table {
1803                                 compatible = "operating-points-v2";
1804
1805                                 opp-840000000 {
1806                                         opp-hz = /bits/ 64 <840000000>;
1807                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1808                                 };
1809
1810                                 opp-778000000 {
1811                                         opp-hz = /bits/ 64 <778000000>;
1812                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1813                                 };
1814
1815                                 opp-738000000 {
1816                                         opp-hz = /bits/ 64 <738000000>;
1817                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1818                                 };
1819
1820                                 opp-676000000 {
1821                                         opp-hz = /bits/ 64 <676000000>;
1822                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1823                                 };
1824
1825                                 opp-608000000 {
1826                                         opp-hz = /bits/ 64 <608000000>;
1827                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1828                                 };
1829
1830                                 opp-540000000 {
1831                                         opp-hz = /bits/ 64 <540000000>;
1832                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1833                                 };
1834
1835                                 opp-491000000 {
1836                                         opp-hz = /bits/ 64 <491000000>;
1837                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1838                                 };
1839
1840                                 opp-443000000 {
1841                                         opp-hz = /bits/ 64 <443000000>;
1842                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1843                                 };
1844
1845                                 opp-379000000 {
1846                                         opp-hz = /bits/ 64 <379000000>;
1847                                         opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
1848                                 };
1849
1850                                 opp-315000000 {
1851                                         opp-hz = /bits/ 64 <315000000>;
1852                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1853                                 };
1854                         };
1855                 };
1856
1857                 gmu: gmu@3d6a000 {
1858                         compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1859
1860                         reg = <0 0x03d6a000 0 0x34000>,
1861                               <0 0x03de0000 0 0x10000>,
1862                               <0 0x0b290000 0 0x10000>;
1863                         reg-names = "gmu", "rscc", "gmu_pdc";
1864
1865                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1866                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1867                         interrupt-names = "hfi", "gmu";
1868
1869                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
1870                                  <&gpucc GPU_CC_CXO_CLK>,
1871                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1872                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1873                                  <&gpucc GPU_CC_AHB_CLK>,
1874                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1875                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
1876                         clock-names = "gmu",
1877                                       "cxo",
1878                                       "axi",
1879                                       "memnoc",
1880                                       "ahb",
1881                                       "hub",
1882                                       "smmu_vote";
1883
1884                         power-domains = <&gpucc GPU_CX_GDSC>,
1885                                         <&gpucc GPU_GX_GDSC>;
1886                         power-domain-names = "cx",
1887                                              "gx";
1888
1889                         iommus = <&adreno_smmu 5 0x400>;
1890
1891                         operating-points-v2 = <&gmu_opp_table>;
1892
1893                         gmu_opp_table: opp-table {
1894                                 compatible = "operating-points-v2";
1895
1896                                 opp-200000000 {
1897                                         opp-hz = /bits/ 64 <200000000>;
1898                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1899                                 };
1900                         };
1901                 };
1902
1903                 gpucc: clock-controller@3d90000 {
1904                         compatible = "qcom,sm8350-gpucc";
1905                         reg = <0 0x03d90000 0 0x9000>;
1906                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1907                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1908                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1909                         clock-names = "bi_tcxo",
1910                                       "gcc_gpu_gpll0_clk_src",
1911                                       "gcc_gpu_gpll0_div_clk_src";
1912                         #clock-cells = <1>;
1913                         #reset-cells = <1>;
1914                         #power-domain-cells = <1>;
1915                 };
1916
1917                 adreno_smmu: iommu@3da0000 {
1918                         compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
1919                                      "qcom,smmu-500", "arm,mmu-500";
1920                         reg = <0 0x03da0000 0 0x20000>;
1921                         #iommu-cells = <2>;
1922                         #global-interrupts = <2>;
1923                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1924                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1925                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1926                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1927                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1928                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1929                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1930                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1931                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1932                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
1933                                      <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
1934                                      <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
1935
1936                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1937                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
1938                                  <&gpucc GPU_CC_AHB_CLK>,
1939                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1940                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1941                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1942                                  <&gpucc GPU_CC_HUB_AON_CLK>;
1943                         clock-names = "bus",
1944                                       "iface",
1945                                       "ahb",
1946                                       "hlos1_vote_gpu_smmu",
1947                                       "cx_gmu",
1948                                       "hub_cx_int",
1949                                       "hub_aon";
1950
1951                         power-domains = <&gpucc GPU_CX_GDSC>;
1952                         dma-coherent;
1953                 };
1954
1955                 lpass_ag_noc: interconnect@3c40000 {
1956                         compatible = "qcom,sm8350-lpass-ag-noc";
1957                         reg = <0 0x03c40000 0 0xf080>;
1958                         #interconnect-cells = <2>;
1959                         qcom,bcm-voters = <&apps_bcm_voter>;
1960                 };
1961
1962                 mpss: remoteproc@4080000 {
1963                         compatible = "qcom,sm8350-mpss-pas";
1964                         reg = <0x0 0x04080000 0x0 0x4040>;
1965
1966                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1967                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1968                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1969                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1970                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1971                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1972                         interrupt-names = "wdog", "fatal", "ready", "handover",
1973                                           "stop-ack", "shutdown-ack";
1974
1975                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1976                         clock-names = "xo";
1977
1978                         power-domains = <&rpmhpd SM8350_CX>,
1979                                         <&rpmhpd SM8350_MSS>;
1980                         power-domain-names = "cx", "mss";
1981
1982                         interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
1983
1984                         memory-region = <&pil_modem_mem>;
1985
1986                         qcom,qmp = <&aoss_qmp>;
1987
1988                         qcom,smem-states = <&smp2p_modem_out 0>;
1989                         qcom,smem-state-names = "stop";
1990
1991                         status = "disabled";
1992
1993                         glink-edge {
1994                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1995                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1996                                                              IRQ_TYPE_EDGE_RISING>;
1997                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
1998                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1999                                 label = "modem";
2000                                 qcom,remote-pid = <1>;
2001                         };
2002                 };
2003
2004                 slpi: remoteproc@5c00000 {
2005                         compatible = "qcom,sm8350-slpi-pas";
2006                         reg = <0 0x05c00000 0 0x4000>;
2007
2008                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2009                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2010                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2011                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2012                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2013                         interrupt-names = "wdog", "fatal", "ready",
2014                                           "handover", "stop-ack";
2015
2016                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2017                         clock-names = "xo";
2018
2019                         power-domains = <&rpmhpd SM8350_LCX>,
2020                                         <&rpmhpd SM8350_LMX>;
2021                         power-domain-names = "lcx", "lmx";
2022
2023                         memory-region = <&pil_slpi_mem>;
2024
2025                         qcom,qmp = <&aoss_qmp>;
2026
2027                         qcom,smem-states = <&smp2p_slpi_out 0>;
2028                         qcom,smem-state-names = "stop";
2029
2030                         status = "disabled";
2031
2032                         glink-edge {
2033                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2034                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2035                                                              IRQ_TYPE_EDGE_RISING>;
2036                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2037                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2038
2039                                 label = "slpi";
2040                                 qcom,remote-pid = <3>;
2041
2042                                 fastrpc {
2043                                         compatible = "qcom,fastrpc";
2044                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2045                                         label = "sdsp";
2046                                         qcom,non-secure-domain;
2047                                         #address-cells = <1>;
2048                                         #size-cells = <0>;
2049
2050                                         compute-cb@1 {
2051                                                 compatible = "qcom,fastrpc-compute-cb";
2052                                                 reg = <1>;
2053                                                 iommus = <&apps_smmu 0x0541 0x0>;
2054                                         };
2055
2056                                         compute-cb@2 {
2057                                                 compatible = "qcom,fastrpc-compute-cb";
2058                                                 reg = <2>;
2059                                                 iommus = <&apps_smmu 0x0542 0x0>;
2060                                         };
2061
2062                                         compute-cb@3 {
2063                                                 compatible = "qcom,fastrpc-compute-cb";
2064                                                 reg = <3>;
2065                                                 iommus = <&apps_smmu 0x0543 0x0>;
2066                                                 /* note: shared-cb = <4> in downstream */
2067                                         };
2068                                 };
2069                         };
2070                 };
2071
2072                 sdhc_2: mmc@8804000 {
2073                         compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2074                         reg = <0 0x08804000 0 0x1000>;
2075
2076                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2077                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2078                         interrupt-names = "hc_irq", "pwr_irq";
2079
2080                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2081                                  <&gcc GCC_SDCC2_APPS_CLK>,
2082                                  <&rpmhcc RPMH_CXO_CLK>;
2083                         clock-names = "iface", "core", "xo";
2084                         resets = <&gcc GCC_SDCC2_BCR>;
2085                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2086                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2087                         interconnect-names = "sdhc-ddr","cpu-sdhc";
2088                         iommus = <&apps_smmu 0x4a0 0x0>;
2089                         power-domains = <&rpmhpd SM8350_CX>;
2090                         operating-points-v2 = <&sdhc2_opp_table>;
2091                         bus-width = <4>;
2092                         dma-coherent;
2093
2094                         status = "disabled";
2095
2096                         sdhc2_opp_table: opp-table {
2097                                 compatible = "operating-points-v2";
2098
2099                                 opp-100000000 {
2100                                         opp-hz = /bits/ 64 <100000000>;
2101                                         required-opps = <&rpmhpd_opp_low_svs>;
2102                                 };
2103
2104                                 opp-202000000 {
2105                                         opp-hz = /bits/ 64 <202000000>;
2106                                         required-opps = <&rpmhpd_opp_svs_l1>;
2107                                 };
2108                         };
2109                 };
2110
2111                 usb_1_hsphy: phy@88e3000 {
2112                         compatible = "qcom,sm8350-usb-hs-phy",
2113                                      "qcom,usb-snps-hs-7nm-phy";
2114                         reg = <0 0x088e3000 0 0x400>;
2115                         status = "disabled";
2116                         #phy-cells = <0>;
2117
2118                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2119                         clock-names = "ref";
2120
2121                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2122                 };
2123
2124                 usb_2_hsphy: phy@88e4000 {
2125                         compatible = "qcom,sm8250-usb-hs-phy",
2126                                      "qcom,usb-snps-hs-7nm-phy";
2127                         reg = <0 0x088e4000 0 0x400>;
2128                         status = "disabled";
2129                         #phy-cells = <0>;
2130
2131                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2132                         clock-names = "ref";
2133
2134                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2135                 };
2136
2137                 usb_1_qmpphy: phy@88e9000 {
2138                         compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2139                         reg = <0 0x088e8000 0 0x3000>;
2140
2141                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2142                                  <&rpmhcc RPMH_CXO_CLK>,
2143                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2144                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2145                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2146
2147                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2148                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2149                         reset-names = "phy", "common";
2150
2151                         #clock-cells = <1>;
2152                         #phy-cells = <1>;
2153
2154                         status = "disabled";
2155                 };
2156
2157                 usb_2_qmpphy: phy-wrapper@88eb000 {
2158                         compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2159                         reg = <0 0x088eb000 0 0x200>;
2160                         status = "disabled";
2161                         #address-cells = <2>;
2162                         #size-cells = <2>;
2163                         ranges;
2164
2165                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2166                                  <&rpmhcc RPMH_CXO_CLK>,
2167                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
2168                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2169                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2170
2171                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2172                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2173                         reset-names = "phy", "common";
2174
2175                         usb_2_ssphy: phy@88ebe00 {
2176                                 reg = <0 0x088ebe00 0 0x200>,
2177                                       <0 0x088ec000 0 0x200>,
2178                                       <0 0x088eb200 0 0x1100>;
2179                                 #phy-cells = <0>;
2180                                 #clock-cells = <0>;
2181                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2182                                 clock-names = "pipe0";
2183                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2184                         };
2185                 };
2186
2187                 dc_noc: interconnect@90c0000 {
2188                         compatible = "qcom,sm8350-dc-noc";
2189                         reg = <0 0x090c0000 0 0x4200>;
2190                         #interconnect-cells = <2>;
2191                         qcom,bcm-voters = <&apps_bcm_voter>;
2192                 };
2193
2194                 gem_noc: interconnect@9100000 {
2195                         compatible = "qcom,sm8350-gem-noc";
2196                         reg = <0 0x09100000 0 0xb4000>;
2197                         #interconnect-cells = <2>;
2198                         qcom,bcm-voters = <&apps_bcm_voter>;
2199                 };
2200
2201                 system-cache-controller@9200000 {
2202                         compatible = "qcom,sm8350-llcc";
2203                         reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2204                               <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2205                               <0 0x09600000 0 0x58000>;
2206                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2207                                     "llcc3_base", "llcc_broadcast_base";
2208                 };
2209
2210                 compute_noc: interconnect@a0c0000 {
2211                         compatible = "qcom,sm8350-compute-noc";
2212                         reg = <0 0x0a0c0000 0 0xa180>;
2213                         #interconnect-cells = <2>;
2214                         qcom,bcm-voters = <&apps_bcm_voter>;
2215                 };
2216
2217                 usb_1: usb@a6f8800 {
2218                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2219                         reg = <0 0x0a6f8800 0 0x400>;
2220                         status = "disabled";
2221                         #address-cells = <2>;
2222                         #size-cells = <2>;
2223                         ranges;
2224
2225                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2226                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2227                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2228                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2229                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2230                         clock-names = "cfg_noc",
2231                                       "core",
2232                                       "iface",
2233                                       "sleep",
2234                                       "mock_utmi";
2235
2236                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2237                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2238                         assigned-clock-rates = <19200000>, <200000000>;
2239
2240                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2241                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
2242                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2243                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
2244                         interrupt-names = "hs_phy_irq",
2245                                           "ss_phy_irq",
2246                                           "dm_hs_phy_irq",
2247                                           "dp_hs_phy_irq";
2248
2249                         power-domains = <&gcc USB30_PRIM_GDSC>;
2250
2251                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2252
2253                         usb_1_dwc3: usb@a600000 {
2254                                 compatible = "snps,dwc3";
2255                                 reg = <0 0x0a600000 0 0xcd00>;
2256                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2257                                 iommus = <&apps_smmu 0x0 0x0>;
2258                                 snps,dis_u2_susphy_quirk;
2259                                 snps,dis_enblslpm_quirk;
2260                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
2261                                 phy-names = "usb2-phy", "usb3-phy";
2262
2263                                 ports {
2264                                         #address-cells = <1>;
2265                                         #size-cells = <0>;
2266
2267                                         port@0 {
2268                                                 reg = <0>;
2269
2270                                                 usb_1_dwc3_hs: endpoint {
2271                                                 };
2272                                         };
2273
2274                                         port@1 {
2275                                                 reg = <1>;
2276
2277                                                 usb_1_dwc3_ss: endpoint {
2278                                                 };
2279                                         };
2280                                 };
2281                         };
2282                 };
2283
2284                 usb_2: usb@a8f8800 {
2285                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2286                         reg = <0 0x0a8f8800 0 0x400>;
2287                         status = "disabled";
2288                         #address-cells = <2>;
2289                         #size-cells = <2>;
2290                         ranges;
2291
2292                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2293                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2294                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2295                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2296                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2297                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
2298                         clock-names = "cfg_noc",
2299                                       "core",
2300                                       "iface",
2301                                       "sleep",
2302                                       "mock_utmi",
2303                                       "xo";
2304
2305                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2306                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2307                         assigned-clock-rates = <19200000>, <200000000>;
2308
2309                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2310                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
2311                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2312                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
2313                         interrupt-names = "hs_phy_irq",
2314                                           "ss_phy_irq",
2315                                           "dm_hs_phy_irq",
2316                                           "dp_hs_phy_irq";
2317
2318                         power-domains = <&gcc USB30_SEC_GDSC>;
2319
2320                         resets = <&gcc GCC_USB30_SEC_BCR>;
2321
2322                         usb_2_dwc3: usb@a800000 {
2323                                 compatible = "snps,dwc3";
2324                                 reg = <0 0x0a800000 0 0xcd00>;
2325                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2326                                 iommus = <&apps_smmu 0x20 0x0>;
2327                                 snps,dis_u2_susphy_quirk;
2328                                 snps,dis_enblslpm_quirk;
2329                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2330                                 phy-names = "usb2-phy", "usb3-phy";
2331                         };
2332                 };
2333
2334                 mdss: display-subsystem@ae00000 {
2335                         compatible = "qcom,sm8350-mdss";
2336                         reg = <0 0x0ae00000 0 0x1000>;
2337                         reg-names = "mdss";
2338
2339                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2340                                         <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
2341                         interconnect-names = "mdp0-mem", "mdp1-mem";
2342
2343                         power-domains = <&dispcc MDSS_GDSC>;
2344                         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2345
2346                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2347                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2348                                  <&gcc GCC_DISP_SF_AXI_CLK>,
2349                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2350                         clock-names = "iface", "bus", "nrt_bus", "core";
2351
2352                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2353                         interrupt-controller;
2354                         #interrupt-cells = <1>;
2355
2356                         iommus = <&apps_smmu 0x820 0x402>;
2357
2358                         status = "disabled";
2359
2360                         #address-cells = <2>;
2361                         #size-cells = <2>;
2362                         ranges;
2363
2364                         dpu_opp_table: opp-table {
2365                                 compatible = "operating-points-v2";
2366
2367                                 /* TODO: opp-200000000 should work with
2368                                  * &rpmhpd_opp_low_svs, but one some of
2369                                  * sm8350_hdk boards reboot using this
2370                                  * opp.
2371                                  */
2372                                 opp-200000000 {
2373                                         opp-hz = /bits/ 64 <200000000>;
2374                                         required-opps = <&rpmhpd_opp_svs>;
2375                                 };
2376
2377                                 opp-300000000 {
2378                                         opp-hz = /bits/ 64 <300000000>;
2379                                         required-opps = <&rpmhpd_opp_svs>;
2380                                 };
2381
2382                                 opp-345000000 {
2383                                         opp-hz = /bits/ 64 <345000000>;
2384                                         required-opps = <&rpmhpd_opp_svs_l1>;
2385                                 };
2386
2387                                 opp-460000000 {
2388                                         opp-hz = /bits/ 64 <460000000>;
2389                                         required-opps = <&rpmhpd_opp_nom>;
2390                                 };
2391                         };
2392
2393                         mdss_mdp: display-controller@ae01000 {
2394                                 compatible = "qcom,sm8350-dpu";
2395                                 reg = <0 0x0ae01000 0 0x8f000>,
2396                                       <0 0x0aeb0000 0 0x2008>;
2397                                 reg-names = "mdp", "vbif";
2398
2399                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2400                                         <&gcc GCC_DISP_SF_AXI_CLK>,
2401                                         <&dispcc DISP_CC_MDSS_AHB_CLK>,
2402                                         <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2403                                         <&dispcc DISP_CC_MDSS_MDP_CLK>,
2404                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2405                                 clock-names = "bus",
2406                                               "nrt_bus",
2407                                               "iface",
2408                                               "lut",
2409                                               "core",
2410                                               "vsync";
2411
2412                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2413                                 assigned-clock-rates = <19200000>;
2414
2415                                 operating-points-v2 = <&dpu_opp_table>;
2416                                 power-domains = <&rpmhpd SM8350_MMCX>;
2417
2418                                 interrupt-parent = <&mdss>;
2419                                 interrupts = <0>;
2420
2421                                 ports {
2422                                         #address-cells = <1>;
2423                                         #size-cells = <0>;
2424
2425                                         port@0 {
2426                                                 reg = <0>;
2427                                                 dpu_intf1_out: endpoint {
2428                                                         remote-endpoint = <&mdss_dsi0_in>;
2429                                                 };
2430                                         };
2431
2432                                         port@1 {
2433                                                 reg = <1>;
2434                                                 dpu_intf2_out: endpoint {
2435                                                         remote-endpoint = <&mdss_dsi1_in>;
2436                                                 };
2437                                         };
2438                                 };
2439                         };
2440
2441                         mdss_dsi0: dsi@ae94000 {
2442                                 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2443                                 reg = <0 0x0ae94000 0 0x400>;
2444                                 reg-names = "dsi_ctrl";
2445
2446                                 interrupt-parent = <&mdss>;
2447                                 interrupts = <4>;
2448
2449                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2450                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2451                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2452                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2453                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2454                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2455                                 clock-names = "byte",
2456                                               "byte_intf",
2457                                               "pixel",
2458                                               "core",
2459                                               "iface",
2460                                               "bus";
2461
2462                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2463                                                   <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2464                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2465                                                          <&mdss_dsi0_phy 1>;
2466
2467                                 operating-points-v2 = <&dsi0_opp_table>;
2468                                 power-domains = <&rpmhpd SM8350_MMCX>;
2469
2470                                 phys = <&mdss_dsi0_phy>;
2471
2472                                 #address-cells = <1>;
2473                                 #size-cells = <0>;
2474
2475                                 status = "disabled";
2476
2477                                 dsi0_opp_table: opp-table {
2478                                         compatible = "operating-points-v2";
2479
2480                                         /* TODO: opp-187500000 should work with
2481                                          * &rpmhpd_opp_low_svs, but one some of
2482                                          * sm8350_hdk boards reboot using this
2483                                          * opp.
2484                                          */
2485                                         opp-187500000 {
2486                                                 opp-hz = /bits/ 64 <187500000>;
2487                                                 required-opps = <&rpmhpd_opp_svs>;
2488                                         };
2489
2490                                         opp-300000000 {
2491                                                 opp-hz = /bits/ 64 <300000000>;
2492                                                 required-opps = <&rpmhpd_opp_svs>;
2493                                         };
2494
2495                                         opp-358000000 {
2496                                                 opp-hz = /bits/ 64 <358000000>;
2497                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2498                                         };
2499                                 };
2500
2501                                 ports {
2502                                         #address-cells = <1>;
2503                                         #size-cells = <0>;
2504
2505                                         port@0 {
2506                                                 reg = <0>;
2507                                                 mdss_dsi0_in: endpoint {
2508                                                         remote-endpoint = <&dpu_intf1_out>;
2509                                                 };
2510                                         };
2511
2512                                         port@1 {
2513                                                 reg = <1>;
2514                                                 mdss_dsi0_out: endpoint {
2515                                                 };
2516                                         };
2517                                 };
2518                         };
2519
2520                         mdss_dsi0_phy: phy@ae94400 {
2521                                 compatible = "qcom,sm8350-dsi-phy-5nm";
2522                                 reg = <0 0x0ae94400 0 0x200>,
2523                                       <0 0x0ae94600 0 0x280>,
2524                                       <0 0x0ae94900 0 0x27c>;
2525                                 reg-names = "dsi_phy",
2526                                             "dsi_phy_lane",
2527                                             "dsi_pll";
2528
2529                                 #clock-cells = <1>;
2530                                 #phy-cells = <0>;
2531
2532                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2533                                          <&rpmhcc RPMH_CXO_CLK>;
2534                                 clock-names = "iface", "ref";
2535
2536                                 status = "disabled";
2537                         };
2538
2539                         mdss_dsi1: dsi@ae96000 {
2540                                 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2541                                 reg = <0 0x0ae96000 0 0x400>;
2542                                 reg-names = "dsi_ctrl";
2543
2544                                 interrupt-parent = <&mdss>;
2545                                 interrupts = <5>;
2546
2547                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2548                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2549                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2550                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2551                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2552                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2553                                 clock-names = "byte",
2554                                               "byte_intf",
2555                                               "pixel",
2556                                               "core",
2557                                               "iface",
2558                                               "bus";
2559
2560                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2561                                                   <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2562                                 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2563                                                          <&mdss_dsi1_phy 1>;
2564
2565                                 operating-points-v2 = <&dsi1_opp_table>;
2566                                 power-domains = <&rpmhpd SM8350_MMCX>;
2567
2568                                 phys = <&mdss_dsi1_phy>;
2569
2570                                 #address-cells = <1>;
2571                                 #size-cells = <0>;
2572
2573                                 status = "disabled";
2574
2575                                 dsi1_opp_table: opp-table {
2576                                         compatible = "operating-points-v2";
2577
2578                                         /* TODO: opp-187500000 should work with
2579                                          * &rpmhpd_opp_low_svs, but one some of
2580                                          * sm8350_hdk boards reboot using this
2581                                          * opp.
2582                                          */
2583                                         opp-187500000 {
2584                                                 opp-hz = /bits/ 64 <187500000>;
2585                                                 required-opps = <&rpmhpd_opp_svs>;
2586                                         };
2587
2588                                         opp-300000000 {
2589                                                 opp-hz = /bits/ 64 <300000000>;
2590                                                 required-opps = <&rpmhpd_opp_svs>;
2591                                         };
2592
2593                                         opp-358000000 {
2594                                                 opp-hz = /bits/ 64 <358000000>;
2595                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2596                                         };
2597                                 };
2598
2599                                 ports {
2600                                         #address-cells = <1>;
2601                                         #size-cells = <0>;
2602
2603                                         port@0 {
2604                                                 reg = <0>;
2605                                                 mdss_dsi1_in: endpoint {
2606                                                         remote-endpoint = <&dpu_intf2_out>;
2607                                                 };
2608                                         };
2609
2610                                         port@1 {
2611                                                 reg = <1>;
2612                                                 mdss_dsi1_out: endpoint {
2613                                                 };
2614                                         };
2615                                 };
2616                         };
2617
2618                         mdss_dsi1_phy: phy@ae96400 {
2619                                 compatible = "qcom,sm8350-dsi-phy-5nm";
2620                                 reg = <0 0x0ae96400 0 0x200>,
2621                                       <0 0x0ae96600 0 0x280>,
2622                                       <0 0x0ae96900 0 0x27c>;
2623                                 reg-names = "dsi_phy",
2624                                             "dsi_phy_lane",
2625                                             "dsi_pll";
2626
2627                                 #clock-cells = <1>;
2628                                 #phy-cells = <0>;
2629
2630                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2631                                          <&rpmhcc RPMH_CXO_CLK>;
2632                                 clock-names = "iface", "ref";
2633
2634                                 status = "disabled";
2635                         };
2636                 };
2637
2638                 dispcc: clock-controller@af00000 {
2639                         compatible = "qcom,sm8350-dispcc";
2640                         reg = <0 0x0af00000 0 0x10000>;
2641                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2642                                  <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2643                                  <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2644                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2645                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2646                         clock-names = "bi_tcxo",
2647                                       "dsi0_phy_pll_out_byteclk",
2648                                       "dsi0_phy_pll_out_dsiclk",
2649                                       "dsi1_phy_pll_out_byteclk",
2650                                       "dsi1_phy_pll_out_dsiclk",
2651                                       "dp_phy_pll_link_clk",
2652                                       "dp_phy_pll_vco_div_clk";
2653                         #clock-cells = <1>;
2654                         #reset-cells = <1>;
2655                         #power-domain-cells = <1>;
2656
2657                         power-domains = <&rpmhpd SM8350_MMCX>;
2658                 };
2659
2660                 pdc: interrupt-controller@b220000 {
2661                         compatible = "qcom,sm8350-pdc", "qcom,pdc";
2662                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2663                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,   <55 306 4>,
2664                                           <59 312 3>, <62 374 2>,  <64 434 2>,   <66 438 3>,
2665                                           <69 86 1>,  <70 520 54>, <124 609 31>, <155 63 1>,
2666                                           <156 716 12>;
2667                         #interrupt-cells = <2>;
2668                         interrupt-parent = <&intc>;
2669                         interrupt-controller;
2670                 };
2671
2672                 tsens0: thermal-sensor@c263000 {
2673                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2674                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
2675                               <0 0x0c222000 0 0x8>; /* SROT */
2676                         #qcom,sensors = <15>;
2677                         interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2678                                      <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2679                         interrupt-names = "uplow", "critical";
2680                         #thermal-sensor-cells = <1>;
2681                 };
2682
2683                 tsens1: thermal-sensor@c265000 {
2684                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2685                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
2686                               <0 0x0c223000 0 0x8>; /* SROT */
2687                         #qcom,sensors = <14>;
2688                         interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2689                                      <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2690                         interrupt-names = "uplow", "critical";
2691                         #thermal-sensor-cells = <1>;
2692                 };
2693
2694                 aoss_qmp: power-management@c300000 {
2695                         compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
2696                         reg = <0 0x0c300000 0 0x400>;
2697                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2698                                                      IRQ_TYPE_EDGE_RISING>;
2699                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2700
2701                         #clock-cells = <0>;
2702                 };
2703
2704                 sram@c3f0000 {
2705                         compatible = "qcom,rpmh-stats";
2706                         reg = <0 0x0c3f0000 0 0x400>;
2707                 };
2708
2709                 spmi_bus: spmi@c440000 {
2710                         compatible = "qcom,spmi-pmic-arb";
2711                         reg = <0x0 0x0c440000 0x0 0x1100>,
2712                               <0x0 0x0c600000 0x0 0x2000000>,
2713                               <0x0 0x0e600000 0x0 0x100000>,
2714                               <0x0 0x0e700000 0x0 0xa0000>,
2715                               <0x0 0x0c40a000 0x0 0x26000>;
2716                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2717                         interrupt-names = "periph_irq";
2718                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2719                         qcom,ee = <0>;
2720                         qcom,channel = <0>;
2721                         #address-cells = <2>;
2722                         #size-cells = <0>;
2723                         interrupt-controller;
2724                         #interrupt-cells = <4>;
2725                 };
2726
2727                 tlmm: pinctrl@f100000 {
2728                         compatible = "qcom,sm8350-tlmm";
2729                         reg = <0 0x0f100000 0 0x300000>;
2730                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2731                         gpio-controller;
2732                         #gpio-cells = <2>;
2733                         interrupt-controller;
2734                         #interrupt-cells = <2>;
2735                         gpio-ranges = <&tlmm 0 0 204>;
2736                         wakeup-parent = <&pdc>;
2737
2738                         sdc2_default_state: sdc2-default-state {
2739                                 clk-pins {
2740                                         pins = "sdc2_clk";
2741                                         drive-strength = <16>;
2742                                         bias-disable;
2743                                 };
2744
2745                                 cmd-pins {
2746                                         pins = "sdc2_cmd";
2747                                         drive-strength = <16>;
2748                                         bias-pull-up;
2749                                 };
2750
2751                                 data-pins {
2752                                         pins = "sdc2_data";
2753                                         drive-strength = <16>;
2754                                         bias-pull-up;
2755                                 };
2756                         };
2757
2758                         sdc2_sleep_state: sdc2-sleep-state {
2759                                 clk-pins {
2760                                         pins = "sdc2_clk";
2761                                         drive-strength = <2>;
2762                                         bias-disable;
2763                                 };
2764
2765                                 cmd-pins {
2766                                         pins = "sdc2_cmd";
2767                                         drive-strength = <2>;
2768                                         bias-pull-up;
2769                                 };
2770
2771                                 data-pins {
2772                                         pins = "sdc2_data";
2773                                         drive-strength = <2>;
2774                                         bias-pull-up;
2775                                 };
2776                         };
2777
2778                         qup_uart3_default_state: qup-uart3-default-state {
2779                                 rx-pins {
2780                                         pins = "gpio18";
2781                                         function = "qup3";
2782                                 };
2783                                 tx-pins {
2784                                         pins = "gpio19";
2785                                         function = "qup3";
2786                                 };
2787                         };
2788
2789                         qup_uart6_default: qup-uart6-default-state {
2790                                 pins = "gpio30", "gpio31";
2791                                 function = "qup6";
2792                                 drive-strength = <2>;
2793                                 bias-disable;
2794                         };
2795
2796                         qup_uart18_default: qup-uart18-default-state {
2797                                 pins = "gpio58", "gpio59";
2798                                 function = "qup18";
2799                                 drive-strength = <2>;
2800                                 bias-disable;
2801                         };
2802
2803                         qup_i2c0_default: qup-i2c0-default-state {
2804                                 pins = "gpio4", "gpio5";
2805                                 function = "qup0";
2806                                 drive-strength = <2>;
2807                                 bias-pull-up;
2808                         };
2809
2810                         qup_i2c1_default: qup-i2c1-default-state {
2811                                 pins = "gpio8", "gpio9";
2812                                 function = "qup1";
2813                                 drive-strength = <2>;
2814                                 bias-pull-up;
2815                         };
2816
2817                         qup_i2c2_default: qup-i2c2-default-state {
2818                                 pins = "gpio12", "gpio13";
2819                                 function = "qup2";
2820                                 drive-strength = <2>;
2821                                 bias-pull-up;
2822                         };
2823
2824                         qup_i2c4_default: qup-i2c4-default-state {
2825                                 pins = "gpio20", "gpio21";
2826                                 function = "qup4";
2827                                 drive-strength = <2>;
2828                                 bias-pull-up;
2829                         };
2830
2831                         qup_i2c5_default: qup-i2c5-default-state {
2832                                 pins = "gpio24", "gpio25";
2833                                 function = "qup5";
2834                                 drive-strength = <2>;
2835                                 bias-pull-up;
2836                         };
2837
2838                         qup_i2c6_default: qup-i2c6-default-state {
2839                                 pins = "gpio28", "gpio29";
2840                                 function = "qup6";
2841                                 drive-strength = <2>;
2842                                 bias-pull-up;
2843                         };
2844
2845                         qup_i2c7_default: qup-i2c7-default-state {
2846                                 pins = "gpio32", "gpio33";
2847                                 function = "qup7";
2848                                 drive-strength = <2>;
2849                                 bias-disable;
2850                         };
2851
2852                         qup_i2c8_default: qup-i2c8-default-state {
2853                                 pins = "gpio36", "gpio37";
2854                                 function = "qup8";
2855                                 drive-strength = <2>;
2856                                 bias-pull-up;
2857                         };
2858
2859                         qup_i2c9_default: qup-i2c9-default-state {
2860                                 pins = "gpio40", "gpio41";
2861                                 function = "qup9";
2862                                 drive-strength = <2>;
2863                                 bias-pull-up;
2864                         };
2865
2866                         qup_i2c10_default: qup-i2c10-default-state {
2867                                 pins = "gpio44", "gpio45";
2868                                 function = "qup10";
2869                                 drive-strength = <2>;
2870                                 bias-pull-up;
2871                         };
2872
2873                         qup_i2c11_default: qup-i2c11-default-state {
2874                                 pins = "gpio48", "gpio49";
2875                                 function = "qup11";
2876                                 drive-strength = <2>;
2877                                 bias-pull-up;
2878                         };
2879
2880                         qup_i2c12_default: qup-i2c12-default-state {
2881                                 pins = "gpio52", "gpio53";
2882                                 function = "qup12";
2883                                 drive-strength = <2>;
2884                                 bias-pull-up;
2885                         };
2886
2887                         qup_i2c13_default: qup-i2c13-default-state {
2888                                 pins = "gpio0", "gpio1";
2889                                 function = "qup13";
2890                                 drive-strength = <2>;
2891                                 bias-pull-up;
2892                         };
2893
2894                         qup_i2c14_default: qup-i2c14-default-state {
2895                                 pins = "gpio56", "gpio57";
2896                                 function = "qup14";
2897                                 drive-strength = <2>;
2898                                 bias-disable;
2899                         };
2900
2901                         qup_i2c15_default: qup-i2c15-default-state {
2902                                 pins = "gpio60", "gpio61";
2903                                 function = "qup15";
2904                                 drive-strength = <2>;
2905                                 bias-disable;
2906                         };
2907
2908                         qup_i2c16_default: qup-i2c16-default-state {
2909                                 pins = "gpio64", "gpio65";
2910                                 function = "qup16";
2911                                 drive-strength = <2>;
2912                                 bias-disable;
2913                         };
2914
2915                         qup_i2c17_default: qup-i2c17-default-state {
2916                                 pins = "gpio72", "gpio73";
2917                                 function = "qup17";
2918                                 drive-strength = <2>;
2919                                 bias-disable;
2920                         };
2921
2922                         qup_i2c19_default: qup-i2c19-default-state {
2923                                 pins = "gpio76", "gpio77";
2924                                 function = "qup19";
2925                                 drive-strength = <2>;
2926                                 bias-disable;
2927                         };
2928                 };
2929
2930                 apps_smmu: iommu@15000000 {
2931                         compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
2932                         reg = <0 0x15000000 0 0x100000>;
2933                         #iommu-cells = <2>;
2934                         #global-interrupts = <2>;
2935                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
2936                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2937                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2938                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2939                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2940                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2941                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2942                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2943                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2944                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2945                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2946                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2947                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2948                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2949                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2950                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2951                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2952                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2953                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2954                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2955                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2956                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2957                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2958                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2959                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2960                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2961                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2962                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2963                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2964                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2965                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2966                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2967                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2968                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2969                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2970                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2971                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2972                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2973                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2974                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2975                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2976                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2977                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2978                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2979                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2980                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2981                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2982                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2983                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2984                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2985                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2986                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2987                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2988                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2989                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2990                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2991                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2992                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2993                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2994                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2995                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2996                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2997                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2998                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2999                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3000                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3001                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3002                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3003                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3004                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3005                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3006                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3007                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3008                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3009                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3010                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3011                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3012                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3013                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3014                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3015                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3016                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3017                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3018                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3019                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3020                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3021                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3022                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3023                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3024                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3025                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3026                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3027                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3028                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3029                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3030                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3031                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3032                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3033                 };
3034
3035                 adsp: remoteproc@17300000 {
3036                         compatible = "qcom,sm8350-adsp-pas";
3037                         reg = <0 0x17300000 0 0x100>;
3038
3039                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3040                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3041                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3042                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3043                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3044                         interrupt-names = "wdog", "fatal", "ready",
3045                                           "handover", "stop-ack";
3046
3047                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3048                         clock-names = "xo";
3049
3050                         power-domains = <&rpmhpd SM8350_LCX>,
3051                                         <&rpmhpd SM8350_LMX>;
3052                         power-domain-names = "lcx", "lmx";
3053
3054                         memory-region = <&pil_adsp_mem>;
3055
3056                         qcom,qmp = <&aoss_qmp>;
3057
3058                         qcom,smem-states = <&smp2p_adsp_out 0>;
3059                         qcom,smem-state-names = "stop";
3060
3061                         status = "disabled";
3062
3063                         glink-edge {
3064                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3065                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3066                                                              IRQ_TYPE_EDGE_RISING>;
3067                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
3068                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3069
3070                                 label = "lpass";
3071                                 qcom,remote-pid = <2>;
3072
3073                                 fastrpc {
3074                                         compatible = "qcom,fastrpc";
3075                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3076                                         label = "adsp";
3077                                         qcom,non-secure-domain;
3078                                         #address-cells = <1>;
3079                                         #size-cells = <0>;
3080
3081                                         compute-cb@3 {
3082                                                 compatible = "qcom,fastrpc-compute-cb";
3083                                                 reg = <3>;
3084                                                 iommus = <&apps_smmu 0x1803 0x0>;
3085                                         };
3086
3087                                         compute-cb@4 {
3088                                                 compatible = "qcom,fastrpc-compute-cb";
3089                                                 reg = <4>;
3090                                                 iommus = <&apps_smmu 0x1804 0x0>;
3091                                         };
3092
3093                                         compute-cb@5 {
3094                                                 compatible = "qcom,fastrpc-compute-cb";
3095                                                 reg = <5>;
3096                                                 iommus = <&apps_smmu 0x1805 0x0>;
3097                                         };
3098                                 };
3099                         };
3100                 };
3101
3102                 intc: interrupt-controller@17a00000 {
3103                         compatible = "arm,gic-v3";
3104                         #interrupt-cells = <3>;
3105                         interrupt-controller;
3106                         #redistributor-regions = <1>;
3107                         redistributor-stride = <0 0x20000>;
3108                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
3109                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
3110                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3111                 };
3112
3113                 timer@17c20000 {
3114                         compatible = "arm,armv7-timer-mem";
3115                         #address-cells = <1>;
3116                         #size-cells = <1>;
3117                         ranges = <0 0 0 0x20000000>;
3118                         reg = <0x0 0x17c20000 0x0 0x1000>;
3119                         clock-frequency = <19200000>;
3120
3121                         frame@17c21000 {
3122                                 frame-number = <0>;
3123                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3124                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3125                                 reg = <0x17c21000 0x1000>,
3126                                       <0x17c22000 0x1000>;
3127                         };
3128
3129                         frame@17c23000 {
3130                                 frame-number = <1>;
3131                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3132                                 reg = <0x17c23000 0x1000>;
3133                                 status = "disabled";
3134                         };
3135
3136                         frame@17c25000 {
3137                                 frame-number = <2>;
3138                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3139                                 reg = <0x17c25000 0x1000>;
3140                                 status = "disabled";
3141                         };
3142
3143                         frame@17c27000 {
3144                                 frame-number = <3>;
3145                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3146                                 reg = <0x17c27000 0x1000>;
3147                                 status = "disabled";
3148                         };
3149
3150                         frame@17c29000 {
3151                                 frame-number = <4>;
3152                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3153                                 reg = <0x17c29000 0x1000>;
3154                                 status = "disabled";
3155                         };
3156
3157                         frame@17c2b000 {
3158                                 frame-number = <5>;
3159                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3160                                 reg = <0x17c2b000 0x1000>;
3161                                 status = "disabled";
3162                         };
3163
3164                         frame@17c2d000 {
3165                                 frame-number = <6>;
3166                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3167                                 reg = <0x17c2d000 0x1000>;
3168                                 status = "disabled";
3169                         };
3170                 };
3171
3172                 apps_rsc: rsc@18200000 {
3173                         label = "apps_rsc";
3174                         compatible = "qcom,rpmh-rsc";
3175                         reg = <0x0 0x18200000 0x0 0x10000>,
3176                                 <0x0 0x18210000 0x0 0x10000>,
3177                                 <0x0 0x18220000 0x0 0x10000>;
3178                         reg-names = "drv-0", "drv-1", "drv-2";
3179                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3180                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3181                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3182                         qcom,tcs-offset = <0xd00>;
3183                         qcom,drv-id = <2>;
3184                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
3185                                           <WAKE_TCS    3>, <CONTROL_TCS 0>;
3186                         power-domains = <&CLUSTER_PD>;
3187
3188                         rpmhcc: clock-controller {
3189                                 compatible = "qcom,sm8350-rpmh-clk";
3190                                 #clock-cells = <1>;
3191                                 clock-names = "xo";
3192                                 clocks = <&xo_board>;
3193                         };
3194
3195                         rpmhpd: power-controller {
3196                                 compatible = "qcom,sm8350-rpmhpd";
3197                                 #power-domain-cells = <1>;
3198                                 operating-points-v2 = <&rpmhpd_opp_table>;
3199
3200                                 rpmhpd_opp_table: opp-table {
3201                                         compatible = "operating-points-v2";
3202
3203                                         rpmhpd_opp_ret: opp1 {
3204                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3205                                         };
3206
3207                                         rpmhpd_opp_min_svs: opp2 {
3208                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3209                                         };
3210
3211                                         rpmhpd_opp_low_svs: opp3 {
3212                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3213                                         };
3214
3215                                         rpmhpd_opp_svs: opp4 {
3216                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3217                                         };
3218
3219                                         rpmhpd_opp_svs_l1: opp5 {
3220                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3221                                         };
3222
3223                                         rpmhpd_opp_nom: opp6 {
3224                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3225                                         };
3226
3227                                         rpmhpd_opp_nom_l1: opp7 {
3228                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3229                                         };
3230
3231                                         rpmhpd_opp_nom_l2: opp8 {
3232                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3233                                         };
3234
3235                                         rpmhpd_opp_turbo: opp9 {
3236                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3237                                         };
3238
3239                                         rpmhpd_opp_turbo_l1: opp10 {
3240                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3241                                         };
3242                                 };
3243                         };
3244
3245                         apps_bcm_voter: bcm-voter {
3246                                 compatible = "qcom,bcm-voter";
3247                         };
3248                 };
3249
3250                 cpufreq_hw: cpufreq@18591000 {
3251                         compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3252                         reg = <0 0x18591000 0 0x1000>,
3253                               <0 0x18592000 0 0x1000>,
3254                               <0 0x18593000 0 0x1000>;
3255                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3256
3257                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3258                         clock-names = "xo", "alternate";
3259
3260                         #freq-domain-cells = <1>;
3261                         #clock-cells = <1>;
3262                 };
3263
3264                 cdsp: remoteproc@98900000 {
3265                         compatible = "qcom,sm8350-cdsp-pas";
3266                         reg = <0 0x98900000 0 0x1400000>;
3267
3268                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3269                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3270                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3271                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3272                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3273                         interrupt-names = "wdog", "fatal", "ready",
3274                                           "handover", "stop-ack";
3275
3276                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3277                         clock-names = "xo";
3278
3279                         power-domains = <&rpmhpd SM8350_CX>,
3280                                         <&rpmhpd SM8350_MXC>;
3281                         power-domain-names = "cx", "mxc";
3282
3283                         interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3284
3285                         memory-region = <&pil_cdsp_mem>;
3286
3287                         qcom,qmp = <&aoss_qmp>;
3288
3289                         qcom,smem-states = <&smp2p_cdsp_out 0>;
3290                         qcom,smem-state-names = "stop";
3291
3292                         status = "disabled";
3293
3294                         glink-edge {
3295                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3296                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3297                                                              IRQ_TYPE_EDGE_RISING>;
3298                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
3299                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3300
3301                                 label = "cdsp";
3302                                 qcom,remote-pid = <5>;
3303
3304                                 fastrpc {
3305                                         compatible = "qcom,fastrpc";
3306                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3307                                         label = "cdsp";
3308                                         qcom,non-secure-domain;
3309                                         #address-cells = <1>;
3310                                         #size-cells = <0>;
3311
3312                                         compute-cb@1 {
3313                                                 compatible = "qcom,fastrpc-compute-cb";
3314                                                 reg = <1>;
3315                                                 iommus = <&apps_smmu 0x2161 0x0400>,
3316                                                          <&apps_smmu 0x1181 0x0420>;
3317                                         };
3318
3319                                         compute-cb@2 {
3320                                                 compatible = "qcom,fastrpc-compute-cb";
3321                                                 reg = <2>;
3322                                                 iommus = <&apps_smmu 0x2162 0x0400>,
3323                                                          <&apps_smmu 0x1182 0x0420>;
3324                                         };
3325
3326                                         compute-cb@3 {
3327                                                 compatible = "qcom,fastrpc-compute-cb";
3328                                                 reg = <3>;
3329                                                 iommus = <&apps_smmu 0x2163 0x0400>,
3330                                                          <&apps_smmu 0x1183 0x0420>;
3331                                         };
3332
3333                                         compute-cb@4 {
3334                                                 compatible = "qcom,fastrpc-compute-cb";
3335                                                 reg = <4>;
3336                                                 iommus = <&apps_smmu 0x2164 0x0400>,
3337                                                          <&apps_smmu 0x1184 0x0420>;
3338                                         };
3339
3340                                         compute-cb@5 {
3341                                                 compatible = "qcom,fastrpc-compute-cb";
3342                                                 reg = <5>;
3343                                                 iommus = <&apps_smmu 0x2165 0x0400>,
3344                                                          <&apps_smmu 0x1185 0x0420>;
3345                                         };
3346
3347                                         compute-cb@6 {
3348                                                 compatible = "qcom,fastrpc-compute-cb";
3349                                                 reg = <6>;
3350                                                 iommus = <&apps_smmu 0x2166 0x0400>,
3351                                                          <&apps_smmu 0x1186 0x0420>;
3352                                         };
3353
3354                                         compute-cb@7 {
3355                                                 compatible = "qcom,fastrpc-compute-cb";
3356                                                 reg = <7>;
3357                                                 iommus = <&apps_smmu 0x2167 0x0400>,
3358                                                          <&apps_smmu 0x1187 0x0420>;
3359                                         };
3360
3361                                         compute-cb@8 {
3362                                                 compatible = "qcom,fastrpc-compute-cb";
3363                                                 reg = <8>;
3364                                                 iommus = <&apps_smmu 0x2168 0x0400>,
3365                                                          <&apps_smmu 0x1188 0x0420>;
3366                                         };
3367
3368                                         /* note: secure cb9 in downstream */
3369                                 };
3370                         };
3371                 };
3372         };
3373
3374         thermal_zones: thermal-zones {
3375                 cpu0-thermal {
3376                         polling-delay-passive = <250>;
3377                         polling-delay = <1000>;
3378
3379                         thermal-sensors = <&tsens0 1>;
3380
3381                         trips {
3382                                 cpu0_alert0: trip-point0 {
3383                                         temperature = <90000>;
3384                                         hysteresis = <2000>;
3385                                         type = "passive";
3386                                 };
3387
3388                                 cpu0_alert1: trip-point1 {
3389                                         temperature = <95000>;
3390                                         hysteresis = <2000>;
3391                                         type = "passive";
3392                                 };
3393
3394                                 cpu0_crit: cpu-crit {
3395                                         temperature = <110000>;
3396                                         hysteresis = <1000>;
3397                                         type = "critical";
3398                                 };
3399                         };
3400
3401                         cooling-maps {
3402                                 map0 {
3403                                         trip = <&cpu0_alert0>;
3404                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3405                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3406                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3407                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3408                                 };
3409                                 map1 {
3410                                         trip = <&cpu0_alert1>;
3411                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3412                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3413                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3414                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3415                                 };
3416                         };
3417                 };
3418
3419                 cpu1-thermal {
3420                         polling-delay-passive = <250>;
3421                         polling-delay = <1000>;
3422
3423                         thermal-sensors = <&tsens0 2>;
3424
3425                         trips {
3426                                 cpu1_alert0: trip-point0 {
3427                                         temperature = <90000>;
3428                                         hysteresis = <2000>;
3429                                         type = "passive";
3430                                 };
3431
3432                                 cpu1_alert1: trip-point1 {
3433                                         temperature = <95000>;
3434                                         hysteresis = <2000>;
3435                                         type = "passive";
3436                                 };
3437
3438                                 cpu1_crit: cpu-crit {
3439                                         temperature = <110000>;
3440                                         hysteresis = <1000>;
3441                                         type = "critical";
3442                                 };
3443                         };
3444
3445                         cooling-maps {
3446                                 map0 {
3447                                         trip = <&cpu1_alert0>;
3448                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3449                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3450                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3451                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3452                                 };
3453                                 map1 {
3454                                         trip = <&cpu1_alert1>;
3455                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3456                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3457                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3458                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3459                                 };
3460                         };
3461                 };
3462
3463                 cpu2-thermal {
3464                         polling-delay-passive = <250>;
3465                         polling-delay = <1000>;
3466
3467                         thermal-sensors = <&tsens0 3>;
3468
3469                         trips {
3470                                 cpu2_alert0: trip-point0 {
3471                                         temperature = <90000>;
3472                                         hysteresis = <2000>;
3473                                         type = "passive";
3474                                 };
3475
3476                                 cpu2_alert1: trip-point1 {
3477                                         temperature = <95000>;
3478                                         hysteresis = <2000>;
3479                                         type = "passive";
3480                                 };
3481
3482                                 cpu2_crit: cpu-crit {
3483                                         temperature = <110000>;
3484                                         hysteresis = <1000>;
3485                                         type = "critical";
3486                                 };
3487                         };
3488
3489                         cooling-maps {
3490                                 map0 {
3491                                         trip = <&cpu2_alert0>;
3492                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3493                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3494                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3495                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3496                                 };
3497                                 map1 {
3498                                         trip = <&cpu2_alert1>;
3499                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3500                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3501                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3502                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3503                                 };
3504                         };
3505                 };
3506
3507                 cpu3-thermal {
3508                         polling-delay-passive = <250>;
3509                         polling-delay = <1000>;
3510
3511                         thermal-sensors = <&tsens0 4>;
3512
3513                         trips {
3514                                 cpu3_alert0: trip-point0 {
3515                                         temperature = <90000>;
3516                                         hysteresis = <2000>;
3517                                         type = "passive";
3518                                 };
3519
3520                                 cpu3_alert1: trip-point1 {
3521                                         temperature = <95000>;
3522                                         hysteresis = <2000>;
3523                                         type = "passive";
3524                                 };
3525
3526                                 cpu3_crit: cpu-crit {
3527                                         temperature = <110000>;
3528                                         hysteresis = <1000>;
3529                                         type = "critical";
3530                                 };
3531                         };
3532
3533                         cooling-maps {
3534                                 map0 {
3535                                         trip = <&cpu3_alert0>;
3536                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3537                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3538                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3539                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3540                                 };
3541                                 map1 {
3542                                         trip = <&cpu3_alert1>;
3543                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3544                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3545                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3546                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3547                                 };
3548                         };
3549                 };
3550
3551                 cpu4-top-thermal {
3552                         polling-delay-passive = <250>;
3553                         polling-delay = <1000>;
3554
3555                         thermal-sensors = <&tsens0 7>;
3556
3557                         trips {
3558                                 cpu4_top_alert0: trip-point0 {
3559                                         temperature = <90000>;
3560                                         hysteresis = <2000>;
3561                                         type = "passive";
3562                                 };
3563
3564                                 cpu4_top_alert1: trip-point1 {
3565                                         temperature = <95000>;
3566                                         hysteresis = <2000>;
3567                                         type = "passive";
3568                                 };
3569
3570                                 cpu4_top_crit: cpu-crit {
3571                                         temperature = <110000>;
3572                                         hysteresis = <1000>;
3573                                         type = "critical";
3574                                 };
3575                         };
3576
3577                         cooling-maps {
3578                                 map0 {
3579                                         trip = <&cpu4_top_alert0>;
3580                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3581                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3582                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3583                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3584                                 };
3585                                 map1 {
3586                                         trip = <&cpu4_top_alert1>;
3587                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3588                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3589                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3590                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3591                                 };
3592                         };
3593                 };
3594
3595                 cpu5-top-thermal {
3596                         polling-delay-passive = <250>;
3597                         polling-delay = <1000>;
3598
3599                         thermal-sensors = <&tsens0 8>;
3600
3601                         trips {
3602                                 cpu5_top_alert0: trip-point0 {
3603                                         temperature = <90000>;
3604                                         hysteresis = <2000>;
3605                                         type = "passive";
3606                                 };
3607
3608                                 cpu5_top_alert1: trip-point1 {
3609                                         temperature = <95000>;
3610                                         hysteresis = <2000>;
3611                                         type = "passive";
3612                                 };
3613
3614                                 cpu5_top_crit: cpu-crit {
3615                                         temperature = <110000>;
3616                                         hysteresis = <1000>;
3617                                         type = "critical";
3618                                 };
3619                         };
3620
3621                         cooling-maps {
3622                                 map0 {
3623                                         trip = <&cpu5_top_alert0>;
3624                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3625                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3626                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3627                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3628                                 };
3629                                 map1 {
3630                                         trip = <&cpu5_top_alert1>;
3631                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3632                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3633                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3634                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3635                                 };
3636                         };
3637                 };
3638
3639                 cpu6-top-thermal {
3640                         polling-delay-passive = <250>;
3641                         polling-delay = <1000>;
3642
3643                         thermal-sensors = <&tsens0 9>;
3644
3645                         trips {
3646                                 cpu6_top_alert0: trip-point0 {
3647                                         temperature = <90000>;
3648                                         hysteresis = <2000>;
3649                                         type = "passive";
3650                                 };
3651
3652                                 cpu6_top_alert1: trip-point1 {
3653                                         temperature = <95000>;
3654                                         hysteresis = <2000>;
3655                                         type = "passive";
3656                                 };
3657
3658                                 cpu6_top_crit: cpu-crit {
3659                                         temperature = <110000>;
3660                                         hysteresis = <1000>;
3661                                         type = "critical";
3662                                 };
3663                         };
3664
3665                         cooling-maps {
3666                                 map0 {
3667                                         trip = <&cpu6_top_alert0>;
3668                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3669                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3670                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3671                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3672                                 };
3673                                 map1 {
3674                                         trip = <&cpu6_top_alert1>;
3675                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3676                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3677                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3678                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3679                                 };
3680                         };
3681                 };
3682
3683                 cpu7-top-thermal {
3684                         polling-delay-passive = <250>;
3685                         polling-delay = <1000>;
3686
3687                         thermal-sensors = <&tsens0 10>;
3688
3689                         trips {
3690                                 cpu7_top_alert0: trip-point0 {
3691                                         temperature = <90000>;
3692                                         hysteresis = <2000>;
3693                                         type = "passive";
3694                                 };
3695
3696                                 cpu7_top_alert1: trip-point1 {
3697                                         temperature = <95000>;
3698                                         hysteresis = <2000>;
3699                                         type = "passive";
3700                                 };
3701
3702                                 cpu7_top_crit: cpu-crit {
3703                                         temperature = <110000>;
3704                                         hysteresis = <1000>;
3705                                         type = "critical";
3706                                 };
3707                         };
3708
3709                         cooling-maps {
3710                                 map0 {
3711                                         trip = <&cpu7_top_alert0>;
3712                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3713                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3714                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3715                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3716                                 };
3717                                 map1 {
3718                                         trip = <&cpu7_top_alert1>;
3719                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3720                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3721                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3722                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3723                                 };
3724                         };
3725                 };
3726
3727                 cpu4-bottom-thermal {
3728                         polling-delay-passive = <250>;
3729                         polling-delay = <1000>;
3730
3731                         thermal-sensors = <&tsens0 11>;
3732
3733                         trips {
3734                                 cpu4_bottom_alert0: trip-point0 {
3735                                         temperature = <90000>;
3736                                         hysteresis = <2000>;
3737                                         type = "passive";
3738                                 };
3739
3740                                 cpu4_bottom_alert1: trip-point1 {
3741                                         temperature = <95000>;
3742                                         hysteresis = <2000>;
3743                                         type = "passive";
3744                                 };
3745
3746                                 cpu4_bottom_crit: cpu-crit {
3747                                         temperature = <110000>;
3748                                         hysteresis = <1000>;
3749                                         type = "critical";
3750                                 };
3751                         };
3752
3753                         cooling-maps {
3754                                 map0 {
3755                                         trip = <&cpu4_bottom_alert0>;
3756                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3757                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3758                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3759                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3760                                 };
3761                                 map1 {
3762                                         trip = <&cpu4_bottom_alert1>;
3763                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3764                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3765                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3766                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3767                                 };
3768                         };
3769                 };
3770
3771                 cpu5-bottom-thermal {
3772                         polling-delay-passive = <250>;
3773                         polling-delay = <1000>;
3774
3775                         thermal-sensors = <&tsens0 12>;
3776
3777                         trips {
3778                                 cpu5_bottom_alert0: trip-point0 {
3779                                         temperature = <90000>;
3780                                         hysteresis = <2000>;
3781                                         type = "passive";
3782                                 };
3783
3784                                 cpu5_bottom_alert1: trip-point1 {
3785                                         temperature = <95000>;
3786                                         hysteresis = <2000>;
3787                                         type = "passive";
3788                                 };
3789
3790                                 cpu5_bottom_crit: cpu-crit {
3791                                         temperature = <110000>;
3792                                         hysteresis = <1000>;
3793                                         type = "critical";
3794                                 };
3795                         };
3796
3797                         cooling-maps {
3798                                 map0 {
3799                                         trip = <&cpu5_bottom_alert0>;
3800                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3801                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3802                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3803                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3804                                 };
3805                                 map1 {
3806                                         trip = <&cpu5_bottom_alert1>;
3807                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3808                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3809                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3810                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3811                                 };
3812                         };
3813                 };
3814
3815                 cpu6-bottom-thermal {
3816                         polling-delay-passive = <250>;
3817                         polling-delay = <1000>;
3818
3819                         thermal-sensors = <&tsens0 13>;
3820
3821                         trips {
3822                                 cpu6_bottom_alert0: trip-point0 {
3823                                         temperature = <90000>;
3824                                         hysteresis = <2000>;
3825                                         type = "passive";
3826                                 };
3827
3828                                 cpu6_bottom_alert1: trip-point1 {
3829                                         temperature = <95000>;
3830                                         hysteresis = <2000>;
3831                                         type = "passive";
3832                                 };
3833
3834                                 cpu6_bottom_crit: cpu-crit {
3835                                         temperature = <110000>;
3836                                         hysteresis = <1000>;
3837                                         type = "critical";
3838                                 };
3839                         };
3840
3841                         cooling-maps {
3842                                 map0 {
3843                                         trip = <&cpu6_bottom_alert0>;
3844                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3845                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3846                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3847                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3848                                 };
3849                                 map1 {
3850                                         trip = <&cpu6_bottom_alert1>;
3851                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3852                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3853                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3854                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3855                                 };
3856                         };
3857                 };
3858
3859                 cpu7-bottom-thermal {
3860                         polling-delay-passive = <250>;
3861                         polling-delay = <1000>;
3862
3863                         thermal-sensors = <&tsens0 14>;
3864
3865                         trips {
3866                                 cpu7_bottom_alert0: trip-point0 {
3867                                         temperature = <90000>;
3868                                         hysteresis = <2000>;
3869                                         type = "passive";
3870                                 };
3871
3872                                 cpu7_bottom_alert1: trip-point1 {
3873                                         temperature = <95000>;
3874                                         hysteresis = <2000>;
3875                                         type = "passive";
3876                                 };
3877
3878                                 cpu7_bottom_crit: cpu-crit {
3879                                         temperature = <110000>;
3880                                         hysteresis = <1000>;
3881                                         type = "critical";
3882                                 };
3883                         };
3884
3885                         cooling-maps {
3886                                 map0 {
3887                                         trip = <&cpu7_bottom_alert0>;
3888                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3889                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3890                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3891                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3892                                 };
3893                                 map1 {
3894                                         trip = <&cpu7_bottom_alert1>;
3895                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3896                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3897                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3898                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3899                                 };
3900                         };
3901                 };
3902
3903                 aoss0-thermal {
3904                         polling-delay-passive = <250>;
3905                         polling-delay = <1000>;
3906
3907                         thermal-sensors = <&tsens0 0>;
3908
3909                         trips {
3910                                 aoss0_alert0: trip-point0 {
3911                                         temperature = <90000>;
3912                                         hysteresis = <2000>;
3913                                         type = "hot";
3914                                 };
3915                         };
3916                 };
3917
3918                 cluster0-thermal {
3919                         polling-delay-passive = <250>;
3920                         polling-delay = <1000>;
3921
3922                         thermal-sensors = <&tsens0 5>;
3923
3924                         trips {
3925                                 cluster0_alert0: trip-point0 {
3926                                         temperature = <90000>;
3927                                         hysteresis = <2000>;
3928                                         type = "hot";
3929                                 };
3930                                 cluster0_crit: cluster0_crit {
3931                                         temperature = <110000>;
3932                                         hysteresis = <2000>;
3933                                         type = "critical";
3934                                 };
3935                         };
3936                 };
3937
3938                 cluster1-thermal {
3939                         polling-delay-passive = <250>;
3940                         polling-delay = <1000>;
3941
3942                         thermal-sensors = <&tsens0 6>;
3943
3944                         trips {
3945                                 cluster1_alert0: trip-point0 {
3946                                         temperature = <90000>;
3947                                         hysteresis = <2000>;
3948                                         type = "hot";
3949                                 };
3950                                 cluster1_crit: cluster1_crit {
3951                                         temperature = <110000>;
3952                                         hysteresis = <2000>;
3953                                         type = "critical";
3954                                 };
3955                         };
3956                 };
3957
3958                 aoss1-thermal {
3959                         polling-delay-passive = <250>;
3960                         polling-delay = <1000>;
3961
3962                         thermal-sensors = <&tsens1 0>;
3963
3964                         trips {
3965                                 aoss1_alert0: trip-point0 {
3966                                         temperature = <90000>;
3967                                         hysteresis = <2000>;
3968                                         type = "hot";
3969                                 };
3970                         };
3971                 };
3972
3973                 gpu-top-thermal {
3974                         polling-delay-passive = <250>;
3975                         polling-delay = <1000>;
3976
3977                         thermal-sensors = <&tsens1 1>;
3978
3979                         trips {
3980                                 gpu1_alert0: trip-point0 {
3981                                         temperature = <90000>;
3982                                         hysteresis = <1000>;
3983                                         type = "hot";
3984                                 };
3985                         };
3986                 };
3987
3988                 gpu-bottom-thermal {
3989                         polling-delay-passive = <250>;
3990                         polling-delay = <1000>;
3991
3992                         thermal-sensors = <&tsens1 2>;
3993
3994                         trips {
3995                                 gpu2_alert0: trip-point0 {
3996                                         temperature = <90000>;
3997                                         hysteresis = <1000>;
3998                                         type = "hot";
3999                                 };
4000                         };
4001                 };
4002
4003                 nspss1-thermal {
4004                         polling-delay-passive = <250>;
4005                         polling-delay = <1000>;
4006
4007                         thermal-sensors = <&tsens1 3>;
4008
4009                         trips {
4010                                 nspss1_alert0: trip-point0 {
4011                                         temperature = <90000>;
4012                                         hysteresis = <1000>;
4013                                         type = "hot";
4014                                 };
4015                         };
4016                 };
4017
4018                 nspss2-thermal {
4019                         polling-delay-passive = <250>;
4020                         polling-delay = <1000>;
4021
4022                         thermal-sensors = <&tsens1 4>;
4023
4024                         trips {
4025                                 nspss2_alert0: trip-point0 {
4026                                         temperature = <90000>;
4027                                         hysteresis = <1000>;
4028                                         type = "hot";
4029                                 };
4030                         };
4031                 };
4032
4033                 nspss3-thermal {
4034                         polling-delay-passive = <250>;
4035                         polling-delay = <1000>;
4036
4037                         thermal-sensors = <&tsens1 5>;
4038
4039                         trips {
4040                                 nspss3_alert0: trip-point0 {
4041                                         temperature = <90000>;
4042                                         hysteresis = <1000>;
4043                                         type = "hot";
4044                                 };
4045                         };
4046                 };
4047
4048                 video-thermal {
4049                         polling-delay-passive = <250>;
4050                         polling-delay = <1000>;
4051
4052                         thermal-sensors = <&tsens1 6>;
4053
4054                         trips {
4055                                 video_alert0: trip-point0 {
4056                                         temperature = <90000>;
4057                                         hysteresis = <2000>;
4058                                         type = "hot";
4059                                 };
4060                         };
4061                 };
4062
4063                 mem-thermal {
4064                         polling-delay-passive = <250>;
4065                         polling-delay = <1000>;
4066
4067                         thermal-sensors = <&tsens1 7>;
4068
4069                         trips {
4070                                 mem_alert0: trip-point0 {
4071                                         temperature = <90000>;
4072                                         hysteresis = <2000>;
4073                                         type = "hot";
4074                                 };
4075                         };
4076                 };
4077
4078                 modem1-top-thermal {
4079                         polling-delay-passive = <250>;
4080                         polling-delay = <1000>;
4081
4082                         thermal-sensors = <&tsens1 8>;
4083
4084                         trips {
4085                                 modem1_alert0: trip-point0 {
4086                                         temperature = <90000>;
4087                                         hysteresis = <2000>;
4088                                         type = "hot";
4089                                 };
4090                         };
4091                 };
4092
4093                 modem2-top-thermal {
4094                         polling-delay-passive = <250>;
4095                         polling-delay = <1000>;
4096
4097                         thermal-sensors = <&tsens1 9>;
4098
4099                         trips {
4100                                 modem2_alert0: trip-point0 {
4101                                         temperature = <90000>;
4102                                         hysteresis = <2000>;
4103                                         type = "hot";
4104                                 };
4105                         };
4106                 };
4107
4108                 modem3-top-thermal {
4109                         polling-delay-passive = <250>;
4110                         polling-delay = <1000>;
4111
4112                         thermal-sensors = <&tsens1 10>;
4113
4114                         trips {
4115                                 modem3_alert0: trip-point0 {
4116                                         temperature = <90000>;
4117                                         hysteresis = <2000>;
4118                                         type = "hot";
4119                                 };
4120                         };
4121                 };
4122
4123                 modem4-top-thermal {
4124                         polling-delay-passive = <250>;
4125                         polling-delay = <1000>;
4126
4127                         thermal-sensors = <&tsens1 11>;
4128
4129                         trips {
4130                                 modem4_alert0: trip-point0 {
4131                                         temperature = <90000>;
4132                                         hysteresis = <2000>;
4133                                         type = "hot";
4134                                 };
4135                         };
4136                 };
4137
4138                 camera-top-thermal {
4139                         polling-delay-passive = <250>;
4140                         polling-delay = <1000>;
4141
4142                         thermal-sensors = <&tsens1 12>;
4143
4144                         trips {
4145                                 camera1_alert0: trip-point0 {
4146                                         temperature = <90000>;
4147                                         hysteresis = <2000>;
4148                                         type = "hot";
4149                                 };
4150                         };
4151                 };
4152
4153                 cam-bottom-thermal {
4154                         polling-delay-passive = <250>;
4155                         polling-delay = <1000>;
4156
4157                         thermal-sensors = <&tsens1 13>;
4158
4159                         trips {
4160                                 camera2_alert0: trip-point0 {
4161                                         temperature = <90000>;
4162                                         hysteresis = <2000>;
4163                                         type = "hot";
4164                                 };
4165                         };
4166                 };
4167         };
4168
4169         timer {
4170                 compatible = "arm,armv8-timer";
4171                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4172                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4173                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4174                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
4175         };
4176 };