arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/dma/qcom-gpi.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  14 #include <dt-bindings/interconnect/qcom,sm8250.h>
  15 #include <dt-bindings/mailbox/qcom-ipcc.h>
  16 #include <dt-bindings/power/qcom-rpmpd.h>
  17 #include <dt-bindings/soc/qcom,apr.h>
  18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  19 #include <dt-bindings/sound/qcom,q6afe.h>
  20 #include <dt-bindings/thermal/thermal.h>
  21 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
  22 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
  23
  24 / {
  25         interrupt-parent = <&intc>;
  26
  27         #address-cells = <2>;
  28         #size-cells = <2>;
  29
  30         aliases {
  31                 i2c0 = &i2c0;
  32                 i2c1 = &i2c1;
  33                 i2c2 = &i2c2;
  34                 i2c3 = &i2c3;
  35                 i2c4 = &i2c4;
  36                 i2c5 = &i2c5;
  37                 i2c6 = &i2c6;
  38                 i2c7 = &i2c7;
  39                 i2c8 = &i2c8;
  40                 i2c9 = &i2c9;
  41                 i2c10 = &i2c10;
  42                 i2c11 = &i2c11;
  43                 i2c12 = &i2c12;
  44                 i2c13 = &i2c13;
  45                 i2c14 = &i2c14;
  46                 i2c15 = &i2c15;
  47                 i2c16 = &i2c16;
  48                 i2c17 = &i2c17;
  49                 i2c18 = &i2c18;
  50                 i2c19 = &i2c19;
  51                 spi0 = &spi0;
  52                 spi1 = &spi1;
  53                 spi2 = &spi2;
  54                 spi3 = &spi3;
  55                 spi4 = &spi4;
  56                 spi5 = &spi5;
  57                 spi6 = &spi6;
  58                 spi7 = &spi7;
  59                 spi8 = &spi8;
  60                 spi9 = &spi9;
  61                 spi10 = &spi10;
  62                 spi11 = &spi11;
  63                 spi12 = &spi12;
  64                 spi13 = &spi13;
  65                 spi14 = &spi14;
  66                 spi15 = &spi15;
  67                 spi16 = &spi16;
  68                 spi17 = &spi17;
  69                 spi18 = &spi18;
  70                 spi19 = &spi19;
  71         };
  72
  73         chosen { };
  74
  75         clocks {
  76                 xo_board: xo-board {
  77                         compatible = "fixed-clock";
  78                         #clock-cells = <0>;
  79                         clock-frequency = <38400000>;
  80                         clock-output-names = "xo_board";
  81                 };
  82
  83                 sleep_clk: sleep-clk {
  84                         compatible = "fixed-clock";
  85                         clock-frequency = <32768>;
  86                         #clock-cells = <0>;
  87                 };
  88         };
  89
  90         cpus {
  91                 #address-cells = <2>;
  92                 #size-cells = <0>;
  93
  94                 CPU0: cpu@0 {
  95                         device_type = "cpu";
  96                         compatible = "qcom,kryo485";
  97                         reg = <0x0 0x0>;
  98                         enable-method = "psci";
  99                         capacity-dmips-mhz = <448>;
 100                         dynamic-power-coefficient = <205>;
 101                         next-level-cache = <&L2_0>;
 102                         power-domains = <&CPU_PD0>;
 103                         power-domain-names = "psci";
 104                         qcom,freq-domain = <&cpufreq_hw 0>;
 105                         operating-points-v2 = <&cpu0_opp_table>;
 106                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 107                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 108                         #cooling-cells = <2>;
 109                         L2_0: l2-cache {
 110                                 compatible = "cache";
 111                                 next-level-cache = <&L3_0>;
 112                                 L3_0: l3-cache {
 113                                         compatible = "cache";
 114                                 };
 115                         };
 116                 };
 117
 118                 CPU1: cpu@100 {
 119                         device_type = "cpu";
 120                         compatible = "qcom,kryo485";
 121                         reg = <0x0 0x100>;
 122                         enable-method = "psci";
 123                         capacity-dmips-mhz = <448>;
 124                         dynamic-power-coefficient = <205>;
 125                         next-level-cache = <&L2_100>;
 126                         power-domains = <&CPU_PD1>;
 127                         power-domain-names = "psci";
 128                         qcom,freq-domain = <&cpufreq_hw 0>;
 129                         operating-points-v2 = <&cpu0_opp_table>;
 130                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 131                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 132                         #cooling-cells = <2>;
 133                         L2_100: l2-cache {
 134                                 compatible = "cache";
 135                                 next-level-cache = <&L3_0>;
 136                         };
 137                 };
 138
 139                 CPU2: cpu@200 {
 140                         device_type = "cpu";
 141                         compatible = "qcom,kryo485";
 142                         reg = <0x0 0x200>;
 143                         enable-method = "psci";
 144                         capacity-dmips-mhz = <448>;
 145                         dynamic-power-coefficient = <205>;
 146                         next-level-cache = <&L2_200>;
 147                         power-domains = <&CPU_PD2>;
 148                         power-domain-names = "psci";
 149                         qcom,freq-domain = <&cpufreq_hw 0>;
 150                         operating-points-v2 = <&cpu0_opp_table>;
 151                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 152                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 153                         #cooling-cells = <2>;
 154                         L2_200: l2-cache {
 155                                 compatible = "cache";
 156                                 next-level-cache = <&L3_0>;
 157                         };
 158                 };
 159
 160                 CPU3: cpu@300 {
 161                         device_type = "cpu";
 162                         compatible = "qcom,kryo485";
 163                         reg = <0x0 0x300>;
 164                         enable-method = "psci";
 165                         capacity-dmips-mhz = <448>;
 166                         dynamic-power-coefficient = <205>;
 167                         next-level-cache = <&L2_300>;
 168                         power-domains = <&CPU_PD3>;
 169                         power-domain-names = "psci";
 170                         qcom,freq-domain = <&cpufreq_hw 0>;
 171                         operating-points-v2 = <&cpu0_opp_table>;
 172                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 173                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 174                         #cooling-cells = <2>;
 175                         L2_300: l2-cache {
 176                                 compatible = "cache";
 177                                 next-level-cache = <&L3_0>;
 178                         };
 179                 };
 180
 181                 CPU4: cpu@400 {
 182                         device_type = "cpu";
 183                         compatible = "qcom,kryo485";
 184                         reg = <0x0 0x400>;
 185                         enable-method = "psci";
 186                         capacity-dmips-mhz = <1024>;
 187                         dynamic-power-coefficient = <379>;
 188                         next-level-cache = <&L2_400>;
 189                         power-domains = <&CPU_PD4>;
 190                         power-domain-names = "psci";
 191                         qcom,freq-domain = <&cpufreq_hw 1>;
 192                         operating-points-v2 = <&cpu4_opp_table>;
 193                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 194                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 195                         #cooling-cells = <2>;
 196                         L2_400: l2-cache {
 197                                 compatible = "cache";
 198                                 next-level-cache = <&L3_0>;
 199                         };
 200                 };
 201
 202                 CPU5: cpu@500 {
 203                         device_type = "cpu";
 204                         compatible = "qcom,kryo485";
 205                         reg = <0x0 0x500>;
 206                         enable-method = "psci";
 207                         capacity-dmips-mhz = <1024>;
 208                         dynamic-power-coefficient = <379>;
 209                         next-level-cache = <&L2_500>;
 210                         power-domains = <&CPU_PD5>;
 211                         power-domain-names = "psci";
 212                         qcom,freq-domain = <&cpufreq_hw 1>;
 213                         operating-points-v2 = <&cpu4_opp_table>;
 214                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 215                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 216                         #cooling-cells = <2>;
 217                         L2_500: l2-cache {
 218                                 compatible = "cache";
 219                                 next-level-cache = <&L3_0>;
 220                         };
 221
 222                 };
 223
 224                 CPU6: cpu@600 {
 225                         device_type = "cpu";
 226                         compatible = "qcom,kryo485";
 227                         reg = <0x0 0x600>;
 228                         enable-method = "psci";
 229                         capacity-dmips-mhz = <1024>;
 230                         dynamic-power-coefficient = <379>;
 231                         next-level-cache = <&L2_600>;
 232                         power-domains = <&CPU_PD6>;
 233                         power-domain-names = "psci";
 234                         qcom,freq-domain = <&cpufreq_hw 1>;
 235                         operating-points-v2 = <&cpu4_opp_table>;
 236                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 237                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 238                         #cooling-cells = <2>;
 239                         L2_600: l2-cache {
 240                                 compatible = "cache";
 241                                 next-level-cache = <&L3_0>;
 242                         };
 243                 };
 244
 245                 CPU7: cpu@700 {
 246                         device_type = "cpu";
 247                         compatible = "qcom,kryo485";
 248                         reg = <0x0 0x700>;
 249                         enable-method = "psci";
 250                         capacity-dmips-mhz = <1024>;
 251                         dynamic-power-coefficient = <444>;
 252                         next-level-cache = <&L2_700>;
 253                         power-domains = <&CPU_PD7>;
 254                         power-domain-names = "psci";
 255                         qcom,freq-domain = <&cpufreq_hw 2>;
 256                         operating-points-v2 = <&cpu7_opp_table>;
 257                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 258                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 259                         #cooling-cells = <2>;
 260                         L2_700: l2-cache {
 261                                 compatible = "cache";
 262                                 next-level-cache = <&L3_0>;
 263                         };
 264                 };
 265
 266                 cpu-map {
 267                         cluster0 {
 268                                 core0 {
 269                                         cpu = <&CPU0>;
 270                                 };
 271
 272                                 core1 {
 273                                         cpu = <&CPU1>;
 274                                 };
 275
 276                                 core2 {
 277                                         cpu = <&CPU2>;
 278                                 };
 279
 280                                 core3 {
 281                                         cpu = <&CPU3>;
 282                                 };
 283
 284                                 core4 {
 285                                         cpu = <&CPU4>;
 286                                 };
 287
 288                                 core5 {
 289                                         cpu = <&CPU5>;
 290                                 };
 291
 292                                 core6 {
 293                                         cpu = <&CPU6>;
 294                                 };
 295
 296                                 core7 {
 297                                         cpu = <&CPU7>;
 298                                 };
 299                         };
 300                 };
 301
 302                 idle-states {
 303                         entry-method = "psci";
 304
 305                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 306                                 compatible = "arm,idle-state";
 307                                 idle-state-name = "silver-rail-power-collapse";
 308                                 arm,psci-suspend-param = <0x40000004>;
 309                                 entry-latency-us = <360>;
 310                                 exit-latency-us = <531>;
 311                                 min-residency-us = <3934>;
 312                                 local-timer-stop;
 313                         };
 314
 315                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 316                                 compatible = "arm,idle-state";
 317                                 idle-state-name = "gold-rail-power-collapse";
 318                                 arm,psci-suspend-param = <0x40000004>;
 319                                 entry-latency-us = <702>;
 320                                 exit-latency-us = <1061>;
 321                                 min-residency-us = <4488>;
 322                                 local-timer-stop;
 323                         };
 324                 };
 325
 326                 domain-idle-states {
 327                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 328                                 compatible = "domain-idle-state";
 329                                 idle-state-name = "cluster-llcc-off";
 330                                 arm,psci-suspend-param = <0x4100c244>;
 331                                 entry-latency-us = <3264>;
 332                                 exit-latency-us = <6562>;
 333                                 min-residency-us = <9987>;
 334                                 local-timer-stop;
 335                         };
 336                 };
 337         };
 338
 339         cpu0_opp_table: cpu0_opp_table {
 340                 compatible = "operating-points-v2";
 341                 opp-shared;
 342
 343                 cpu0_opp1: opp-300000000 {
 344                         opp-hz = /bits/ 64 <300000000>;
 345                         opp-peak-kBps = <800000 9600000>;
 346                 };
 347
 348                 cpu0_opp2: opp-403200000 {
 349                         opp-hz = /bits/ 64 <403200000>;
 350                         opp-peak-kBps = <800000 9600000>;
 351                 };
 352
 353                 cpu0_opp3: opp-518400000 {
 354                         opp-hz = /bits/ 64 <518400000>;
 355                         opp-peak-kBps = <800000 16588800>;
 356                 };
 357
 358                 cpu0_opp4: opp-614400000 {
 359                         opp-hz = /bits/ 64 <614400000>;
 360                         opp-peak-kBps = <800000 16588800>;
 361                 };
 362
 363                 cpu0_opp5: opp-691200000 {
 364                         opp-hz = /bits/ 64 <691200000>;
 365                         opp-peak-kBps = <800000 19660800>;
 366                 };
 367
 368                 cpu0_opp6: opp-787200000 {
 369                         opp-hz = /bits/ 64 <787200000>;
 370                         opp-peak-kBps = <1804000 19660800>;
 371                 };
 372
 373                 cpu0_opp7: opp-883200000 {
 374                         opp-hz = /bits/ 64 <883200000>;
 375                         opp-peak-kBps = <1804000 23347200>;
 376                 };
 377
 378                 cpu0_opp8: opp-979200000 {
 379                         opp-hz = /bits/ 64 <979200000>;
 380                         opp-peak-kBps = <1804000 26419200>;
 381                 };
 382
 383                 cpu0_opp9: opp-1075200000 {
 384                         opp-hz = /bits/ 64 <1075200000>;
 385                         opp-peak-kBps = <1804000 29491200>;
 386                 };
 387
 388                 cpu0_opp10: opp-1171200000 {
 389                         opp-hz = /bits/ 64 <1171200000>;
 390                         opp-peak-kBps = <1804000 32563200>;
 391                 };
 392
 393                 cpu0_opp11: opp-1248000000 {
 394                         opp-hz = /bits/ 64 <1248000000>;
 395                         opp-peak-kBps = <1804000 36249600>;
 396                 };
 397
 398                 cpu0_opp12: opp-1344000000 {
 399                         opp-hz = /bits/ 64 <1344000000>;
 400                         opp-peak-kBps = <2188000 36249600>;
 401                 };
 402
 403                 cpu0_opp13: opp-1420800000 {
 404                         opp-hz = /bits/ 64 <1420800000>;
 405                         opp-peak-kBps = <2188000 39321600>;
 406                 };
 407
 408                 cpu0_opp14: opp-1516800000 {
 409                         opp-hz = /bits/ 64 <1516800000>;
 410                         opp-peak-kBps = <3072000 42393600>;
 411                 };
 412
 413                 cpu0_opp15: opp-1612800000 {
 414                         opp-hz = /bits/ 64 <1612800000>;
 415                         opp-peak-kBps = <3072000 42393600>;
 416                 };
 417
 418                 cpu0_opp16: opp-1708800000 {
 419                         opp-hz = /bits/ 64 <1708800000>;
 420                         opp-peak-kBps = <4068000 42393600>;
 421                 };
 422
 423                 cpu0_opp17: opp-1804800000 {
 424                         opp-hz = /bits/ 64 <1804800000>;
 425                         opp-peak-kBps = <4068000 42393600>;
 426                 };
 427         };
 428
 429         cpu4_opp_table: cpu4_opp_table {
 430                 compatible = "operating-points-v2";
 431                 opp-shared;
 432
 433                 cpu4_opp1: opp-710400000 {
 434                         opp-hz = /bits/ 64 <710400000>;
 435                         opp-peak-kBps = <1804000 19660800>;
 436                 };
 437
 438                 cpu4_opp2: opp-825600000 {
 439                         opp-hz = /bits/ 64 <825600000>;
 440                         opp-peak-kBps = <2188000 23347200>;
 441                 };
 442
 443                 cpu4_opp3: opp-940800000 {
 444                         opp-hz = /bits/ 64 <940800000>;
 445                         opp-peak-kBps = <2188000 26419200>;
 446                 };
 447
 448                 cpu4_opp4: opp-1056000000 {
 449                         opp-hz = /bits/ 64 <1056000000>;
 450                         opp-peak-kBps = <3072000 26419200>;
 451                 };
 452
 453                 cpu4_opp5: opp-1171200000 {
 454                         opp-hz = /bits/ 64 <1171200000>;
 455                         opp-peak-kBps = <3072000 29491200>;
 456                 };
 457
 458                 cpu4_opp6: opp-1286400000 {
 459                         opp-hz = /bits/ 64 <1286400000>;
 460                         opp-peak-kBps = <4068000 29491200>;
 461                 };
 462
 463                 cpu4_opp7: opp-1382400000 {
 464                         opp-hz = /bits/ 64 <1382400000>;
 465                         opp-peak-kBps = <4068000 32563200>;
 466                 };
 467
 468                 cpu4_opp8: opp-1478400000 {
 469                         opp-hz = /bits/ 64 <1478400000>;
 470                         opp-peak-kBps = <4068000 32563200>;
 471                 };
 472
 473                 cpu4_opp9: opp-1574400000 {
 474                         opp-hz = /bits/ 64 <1574400000>;
 475                         opp-peak-kBps = <5412000 39321600>;
 476                 };
 477
 478                 cpu4_opp10: opp-1670400000 {
 479                         opp-hz = /bits/ 64 <1670400000>;
 480                         opp-peak-kBps = <5412000 42393600>;
 481                 };
 482
 483                 cpu4_opp11: opp-1766400000 {
 484                         opp-hz = /bits/ 64 <1766400000>;
 485                         opp-peak-kBps = <5412000 45465600>;
 486                 };
 487
 488                 cpu4_opp12: opp-1862400000 {
 489                         opp-hz = /bits/ 64 <1862400000>;
 490                         opp-peak-kBps = <6220000 45465600>;
 491                 };
 492
 493                 cpu4_opp13: opp-1958400000 {
 494                         opp-hz = /bits/ 64 <1958400000>;
 495                         opp-peak-kBps = <6220000 48537600>;
 496                 };
 497
 498                 cpu4_opp14: opp-2054400000 {
 499                         opp-hz = /bits/ 64 <2054400000>;
 500                         opp-peak-kBps = <7216000 48537600>;
 501                 };
 502
 503                 cpu4_opp15: opp-2150400000 {
 504                         opp-hz = /bits/ 64 <2150400000>;
 505                         opp-peak-kBps = <7216000 51609600>;
 506                 };
 507
 508                 cpu4_opp16: opp-2246400000 {
 509                         opp-hz = /bits/ 64 <2246400000>;
 510                         opp-peak-kBps = <7216000 51609600>;
 511                 };
 512
 513                 cpu4_opp17: opp-2342400000 {
 514                         opp-hz = /bits/ 64 <2342400000>;
 515                         opp-peak-kBps = <8368000 51609600>;
 516                 };
 517
 518                 cpu4_opp18: opp-2419200000 {
 519                         opp-hz = /bits/ 64 <2419200000>;
 520                         opp-peak-kBps = <8368000 51609600>;
 521                 };
 522         };
 523
 524         cpu7_opp_table: cpu7_opp_table {
 525                 compatible = "operating-points-v2";
 526                 opp-shared;
 527
 528                 cpu7_opp1: opp-844800000 {
 529                         opp-hz = /bits/ 64 <844800000>;
 530                         opp-peak-kBps = <2188000 19660800>;
 531                 };
 532
 533                 cpu7_opp2: opp-960000000 {
 534                         opp-hz = /bits/ 64 <960000000>;
 535                         opp-peak-kBps = <2188000 26419200>;
 536                 };
 537
 538                 cpu7_opp3: opp-1075200000 {
 539                         opp-hz = /bits/ 64 <1075200000>;
 540                         opp-peak-kBps = <3072000 26419200>;
 541                 };
 542
 543                 cpu7_opp4: opp-1190400000 {
 544                         opp-hz = /bits/ 64 <1190400000>;
 545                         opp-peak-kBps = <3072000 29491200>;
 546                 };
 547
 548                 cpu7_opp5: opp-1305600000 {
 549                         opp-hz = /bits/ 64 <1305600000>;
 550                         opp-peak-kBps = <4068000 32563200>;
 551                 };
 552
 553                 cpu7_opp6: opp-1401600000 {
 554                         opp-hz = /bits/ 64 <1401600000>;
 555                         opp-peak-kBps = <4068000 32563200>;
 556                 };
 557
 558                 cpu7_opp7: opp-1516800000 {
 559                         opp-hz = /bits/ 64 <1516800000>;
 560                         opp-peak-kBps = <4068000 36249600>;
 561                 };
 562
 563                 cpu7_opp8: opp-1632000000 {
 564                         opp-hz = /bits/ 64 <1632000000>;
 565                         opp-peak-kBps = <5412000 39321600>;
 566                 };
 567
 568                 cpu7_opp9: opp-1747200000 {
 569                         opp-hz = /bits/ 64 <1708800000>;
 570                         opp-peak-kBps = <5412000 42393600>;
 571                 };
 572
 573                 cpu7_opp10: opp-1862400000 {
 574                         opp-hz = /bits/ 64 <1862400000>;
 575                         opp-peak-kBps = <6220000 45465600>;
 576                 };
 577
 578                 cpu7_opp11: opp-1977600000 {
 579                         opp-hz = /bits/ 64 <1977600000>;
 580                         opp-peak-kBps = <6220000 48537600>;
 581                 };
 582
 583                 cpu7_opp12: opp-2073600000 {
 584                         opp-hz = /bits/ 64 <2073600000>;
 585                         opp-peak-kBps = <7216000 48537600>;
 586                 };
 587
 588                 cpu7_opp13: opp-2169600000 {
 589                         opp-hz = /bits/ 64 <2169600000>;
 590                         opp-peak-kBps = <7216000 51609600>;
 591                 };
 592
 593                 cpu7_opp14: opp-2265600000 {
 594                         opp-hz = /bits/ 64 <2265600000>;
 595                         opp-peak-kBps = <7216000 51609600>;
 596                 };
 597
 598                 cpu7_opp15: opp-2361600000 {
 599                         opp-hz = /bits/ 64 <2361600000>;
 600                         opp-peak-kBps = <8368000 51609600>;
 601                 };
 602
 603                 cpu7_opp16: opp-2457600000 {
 604                         opp-hz = /bits/ 64 <2457600000>;
 605                         opp-peak-kBps = <8368000 51609600>;
 606                 };
 607
 608                 cpu7_opp17: opp-2553600000 {
 609                         opp-hz = /bits/ 64 <2553600000>;
 610                         opp-peak-kBps = <8368000 51609600>;
 611                 };
 612
 613                 cpu7_opp18: opp-2649600000 {
 614                         opp-hz = /bits/ 64 <2649600000>;
 615                         opp-peak-kBps = <8368000 51609600>;
 616                 };
 617
 618                 cpu7_opp19: opp-2745600000 {
 619                         opp-hz = /bits/ 64 <2745600000>;
 620                         opp-peak-kBps = <8368000 51609600>;
 621                 };
 622
 623                 cpu7_opp20: opp-2841600000 {
 624                         opp-hz = /bits/ 64 <2841600000>;
 625                         opp-peak-kBps = <8368000 51609600>;
 626                 };
 627         };
 628
 629         firmware {
 630                 scm: scm {
 631                         compatible = "qcom,scm";
 632                         #reset-cells = <1>;
 633                 };
 634         };
 635
 636         memory@80000000 {
 637                 device_type = "memory";
 638                 /* We expect the bootloader to fill in the size */
 639                 reg = <0x0 0x80000000 0x0 0x0>;
 640         };
 641
 642         pmu {
 643                 compatible = "arm,armv8-pmuv3";
 644                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 645         };
 646
 647         psci {
 648                 compatible = "arm,psci-1.0";
 649                 method = "smc";
 650
 651                 CPU_PD0: cpu0 {
 652                         #power-domain-cells = <0>;
 653                         power-domains = <&CLUSTER_PD>;
 654                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 655                 };
 656
 657                 CPU_PD1: cpu1 {
 658                         #power-domain-cells = <0>;
 659                         power-domains = <&CLUSTER_PD>;
 660                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 661                 };
 662
 663                 CPU_PD2: cpu2 {
 664                         #power-domain-cells = <0>;
 665                         power-domains = <&CLUSTER_PD>;
 666                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 667                 };
 668
 669                 CPU_PD3: cpu3 {
 670                         #power-domain-cells = <0>;
 671                         power-domains = <&CLUSTER_PD>;
 672                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 673                 };
 674
 675                 CPU_PD4: cpu4 {
 676                         #power-domain-cells = <0>;
 677                         power-domains = <&CLUSTER_PD>;
 678                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 679                 };
 680
 681                 CPU_PD5: cpu5 {
 682                         #power-domain-cells = <0>;
 683                         power-domains = <&CLUSTER_PD>;
 684                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 685                 };
 686
 687                 CPU_PD6: cpu6 {
 688                         #power-domain-cells = <0>;
 689                         power-domains = <&CLUSTER_PD>;
 690                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 691                 };
 692
 693                 CPU_PD7: cpu7 {
 694                         #power-domain-cells = <0>;
 695                         power-domains = <&CLUSTER_PD>;
 696                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 697                 };
 698
 699                 CLUSTER_PD: cpu-cluster0 {
 700                         #power-domain-cells = <0>;
 701                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 702                 };
 703         };
 704
 705         reserved-memory {
 706                 #address-cells = <2>;
 707                 #size-cells = <2>;
 708                 ranges;
 709
 710                 hyp_mem: memory@80000000 {
 711                         reg = <0x0 0x80000000 0x0 0x600000>;
 712                         no-map;
 713                 };
 714
 715                 xbl_aop_mem: memory@80700000 {
 716                         reg = <0x0 0x80700000 0x0 0x160000>;
 717                         no-map;
 718                 };
 719
 720                 cmd_db: memory@80860000 {
 721                         compatible = "qcom,cmd-db";
 722                         reg = <0x0 0x80860000 0x0 0x20000>;
 723                         no-map;
 724                 };
 725
 726                 smem_mem: memory@80900000 {
 727                         reg = <0x0 0x80900000 0x0 0x200000>;
 728                         no-map;
 729                 };
 730
 731                 removed_mem: memory@80b00000 {
 732                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 733                         no-map;
 734                 };
 735
 736                 camera_mem: memory@86200000 {
 737                         reg = <0x0 0x86200000 0x0 0x500000>;
 738                         no-map;
 739                 };
 740
 741                 wlan_mem: memory@86700000 {
 742                         reg = <0x0 0x86700000 0x0 0x100000>;
 743                         no-map;
 744                 };
 745
 746                 ipa_fw_mem: memory@86800000 {
 747                         reg = <0x0 0x86800000 0x0 0x10000>;
 748                         no-map;
 749                 };
 750
 751                 ipa_gsi_mem: memory@86810000 {
 752                         reg = <0x0 0x86810000 0x0 0xa000>;
 753                         no-map;
 754                 };
 755
 756                 gpu_mem: memory@8681a000 {
 757                         reg = <0x0 0x8681a000 0x0 0x2000>;
 758                         no-map;
 759                 };
 760
 761                 npu_mem: memory@86900000 {
 762                         reg = <0x0 0x86900000 0x0 0x500000>;
 763                         no-map;
 764                 };
 765
 766                 video_mem: memory@86e00000 {
 767                         reg = <0x0 0x86e00000 0x0 0x500000>;
 768                         no-map;
 769                 };
 770
 771                 cvp_mem: memory@87300000 {
 772                         reg = <0x0 0x87300000 0x0 0x500000>;
 773                         no-map;
 774                 };
 775
 776                 cdsp_mem: memory@87800000 {
 777                         reg = <0x0 0x87800000 0x0 0x1400000>;
 778                         no-map;
 779                 };
 780
 781                 slpi_mem: memory@88c00000 {
 782                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 783                         no-map;
 784                 };
 785
 786                 adsp_mem: memory@8a100000 {
 787                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 788                         no-map;
 789                 };
 790
 791                 spss_mem: memory@8be00000 {
 792                         reg = <0x0 0x8be00000 0x0 0x100000>;
 793                         no-map;
 794                 };
 795
 796                 cdsp_secure_heap: memory@8bf00000 {
 797                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 798                         no-map;
 799                 };
 800         };
 801
 802         smem {
 803                 compatible = "qcom,smem";
 804                 memory-region = <&smem_mem>;
 805                 hwlocks = <&tcsr_mutex 3>;
 806         };
 807
 808         smp2p-adsp {
 809                 compatible = "qcom,smp2p";
 810                 qcom,smem = <443>, <429>;
 811                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 812                                              IPCC_MPROC_SIGNAL_SMP2P
 813                                              IRQ_TYPE_EDGE_RISING>;
 814                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 815                                 IPCC_MPROC_SIGNAL_SMP2P>;
 816
 817                 qcom,local-pid = <0>;
 818                 qcom,remote-pid = <2>;
 819
 820                 smp2p_adsp_out: master-kernel {
 821                         qcom,entry-name = "master-kernel";
 822                         #qcom,smem-state-cells = <1>;
 823                 };
 824
 825                 smp2p_adsp_in: slave-kernel {
 826                         qcom,entry-name = "slave-kernel";
 827                         interrupt-controller;
 828                         #interrupt-cells = <2>;
 829                 };
 830         };
 831
 832         smp2p-cdsp {
 833                 compatible = "qcom,smp2p";
 834                 qcom,smem = <94>, <432>;
 835                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 836                                              IPCC_MPROC_SIGNAL_SMP2P
 837                                              IRQ_TYPE_EDGE_RISING>;
 838                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 839                                 IPCC_MPROC_SIGNAL_SMP2P>;
 840
 841                 qcom,local-pid = <0>;
 842                 qcom,remote-pid = <5>;
 843
 844                 smp2p_cdsp_out: master-kernel {
 845                         qcom,entry-name = "master-kernel";
 846                         #qcom,smem-state-cells = <1>;
 847                 };
 848
 849                 smp2p_cdsp_in: slave-kernel {
 850                         qcom,entry-name = "slave-kernel";
 851                         interrupt-controller;
 852                         #interrupt-cells = <2>;
 853                 };
 854         };
 855
 856         smp2p-slpi {
 857                 compatible = "qcom,smp2p";
 858                 qcom,smem = <481>, <430>;
 859                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 860                                              IPCC_MPROC_SIGNAL_SMP2P
 861                                              IRQ_TYPE_EDGE_RISING>;
 862                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 863                                 IPCC_MPROC_SIGNAL_SMP2P>;
 864
 865                 qcom,local-pid = <0>;
 866                 qcom,remote-pid = <3>;
 867
 868                 smp2p_slpi_out: master-kernel {
 869                         qcom,entry-name = "master-kernel";
 870                         #qcom,smem-state-cells = <1>;
 871                 };
 872
 873                 smp2p_slpi_in: slave-kernel {
 874                         qcom,entry-name = "slave-kernel";
 875                         interrupt-controller;
 876                         #interrupt-cells = <2>;
 877                 };
 878         };
 879
 880         soc: soc@0 {
 881                 #address-cells = <2>;
 882                 #size-cells = <2>;
 883                 ranges = <0 0 0 0 0x10 0>;
 884                 dma-ranges = <0 0 0 0 0x10 0>;
 885                 compatible = "simple-bus";
 886
 887                 gcc: clock-controller@100000 {
 888                         compatible = "qcom,gcc-sm8250";
 889                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 890                         #clock-cells = <1>;
 891                         #reset-cells = <1>;
 892                         #power-domain-cells = <1>;
 893                         clock-names = "bi_tcxo",
 894                                       "bi_tcxo_ao",
 895                                       "sleep_clk";
 896                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 897                                  <&rpmhcc RPMH_CXO_CLK_A>,
 898                                  <&sleep_clk>;
 899                 };
 900
 901                 ipcc: mailbox@408000 {
 902                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 903                         reg = <0 0x00408000 0 0x1000>;
 904                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 905                         interrupt-controller;
 906                         #interrupt-cells = <3>;
 907                         #mbox-cells = <2>;
 908                 };
 909
 910                 rng: rng@793000 {
 911                         compatible = "qcom,prng-ee";
 912                         reg = <0 0x00793000 0 0x1000>;
 913                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 914                         clock-names = "core";
 915                 };
 916
 917                 qup_opp_table: qup-opp-table {
 918                         compatible = "operating-points-v2";
 919
 920                         opp-50000000 {
 921                                 opp-hz = /bits/ 64 <50000000>;
 922                                 required-opps = <&rpmhpd_opp_min_svs>;
 923                         };
 924
 925                         opp-75000000 {
 926                                 opp-hz = /bits/ 64 <75000000>;
 927                                 required-opps = <&rpmhpd_opp_low_svs>;
 928                         };
 929
 930                         opp-120000000 {
 931                                 opp-hz = /bits/ 64 <120000000>;
 932                                 required-opps = <&rpmhpd_opp_svs>;
 933                         };
 934                 };
 935
 936                 gpi_dma2: dma-controller@800000 {
 937                         compatible = "qcom,sm8250-gpi-dma";
 938                         reg = <0 0x00800000 0 0x70000>;
 939                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 940                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 941                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 942                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 943                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 944                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 945                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 946                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 947                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 948                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
 949                         dma-channels = <10>;
 950                         dma-channel-mask = <0x3f>;
 951                         iommus = <&apps_smmu 0x76 0x0>;
 952                         #dma-cells = <3>;
 953                         status = "disabled";
 954                 };
 955
 956                 qupv3_id_2: geniqup@8c0000 {
 957                         compatible = "qcom,geni-se-qup";
 958                         reg = <0x0 0x008c0000 0x0 0x6000>;
 959                         clock-names = "m-ahb", "s-ahb";
 960                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 961                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 962                         #address-cells = <2>;
 963                         #size-cells = <2>;
 964                         iommus = <&apps_smmu 0x63 0x0>;
 965                         ranges;
 966                         status = "disabled";
 967
 968                         i2c14: i2c@880000 {
 969                                 compatible = "qcom,geni-i2c";
 970                                 reg = <0 0x00880000 0 0x4000>;
 971                                 clock-names = "se";
 972                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 973                                 pinctrl-names = "default";
 974                                 pinctrl-0 = <&qup_i2c14_default>;
 975                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 976                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 977                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 978                                 dma-names = "tx", "rx";
 979                                 #address-cells = <1>;
 980                                 #size-cells = <0>;
 981                                 status = "disabled";
 982                         };
 983
 984                         spi14: spi@880000 {
 985                                 compatible = "qcom,geni-spi";
 986                                 reg = <0 0x00880000 0 0x4000>;
 987                                 clock-names = "se";
 988                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 989                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 990                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 991                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 992                                 dma-names = "tx", "rx";
 993                                 power-domains = <&rpmhpd SM8250_CX>;
 994                                 operating-points-v2 = <&qup_opp_table>;
 995                                 #address-cells = <1>;
 996                                 #size-cells = <0>;
 997                                 status = "disabled";
 998                         };
 999
1000                         i2c15: i2c@884000 {
1001                                 compatible = "qcom,geni-i2c";
1002                                 reg = <0 0x00884000 0 0x4000>;
1003                                 clock-names = "se";
1004                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1005                                 pinctrl-names = "default";
1006                                 pinctrl-0 = <&qup_i2c15_default>;
1007                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1008                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1009                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1010                                 dma-names = "tx", "rx";
1011                                 #address-cells = <1>;
1012                                 #size-cells = <0>;
1013                                 status = "disabled";
1014                         };
1015
1016                         spi15: spi@884000 {
1017                                 compatible = "qcom,geni-spi";
1018                                 reg = <0 0x00884000 0 0x4000>;
1019                                 clock-names = "se";
1020                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1021                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1022                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1023                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1024                                 dma-names = "tx", "rx";
1025                                 power-domains = <&rpmhpd SM8250_CX>;
1026                                 operating-points-v2 = <&qup_opp_table>;
1027                                 #address-cells = <1>;
1028                                 #size-cells = <0>;
1029                                 status = "disabled";
1030                         };
1031
1032                         i2c16: i2c@888000 {
1033                                 compatible = "qcom,geni-i2c";
1034                                 reg = <0 0x00888000 0 0x4000>;
1035                                 clock-names = "se";
1036                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1037                                 pinctrl-names = "default";
1038                                 pinctrl-0 = <&qup_i2c16_default>;
1039                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1040                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1041                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1042                                 dma-names = "tx", "rx";
1043                                 #address-cells = <1>;
1044                                 #size-cells = <0>;
1045                                 status = "disabled";
1046                         };
1047
1048                         spi16: spi@888000 {
1049                                 compatible = "qcom,geni-spi";
1050                                 reg = <0 0x00888000 0 0x4000>;
1051                                 clock-names = "se";
1052                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1053                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1054                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1055                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1056                                 dma-names = "tx", "rx";
1057                                 power-domains = <&rpmhpd SM8250_CX>;
1058                                 operating-points-v2 = <&qup_opp_table>;
1059                                 #address-cells = <1>;
1060                                 #size-cells = <0>;
1061                                 status = "disabled";
1062                         };
1063
1064                         i2c17: i2c@88c000 {
1065                                 compatible = "qcom,geni-i2c";
1066                                 reg = <0 0x0088c000 0 0x4000>;
1067                                 clock-names = "se";
1068                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1069                                 pinctrl-names = "default";
1070                                 pinctrl-0 = <&qup_i2c17_default>;
1071                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1072                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1073                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1074                                 dma-names = "tx", "rx";
1075                                 #address-cells = <1>;
1076                                 #size-cells = <0>;
1077                                 status = "disabled";
1078                         };
1079
1080                         spi17: spi@88c000 {
1081                                 compatible = "qcom,geni-spi";
1082                                 reg = <0 0x0088c000 0 0x4000>;
1083                                 clock-names = "se";
1084                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1085                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1086                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1087                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1088                                 dma-names = "tx", "rx";
1089                                 power-domains = <&rpmhpd SM8250_CX>;
1090                                 operating-points-v2 = <&qup_opp_table>;
1091                                 #address-cells = <1>;
1092                                 #size-cells = <0>;
1093                                 status = "disabled";
1094                         };
1095
1096                         uart17: serial@88c000 {
1097                                 compatible = "qcom,geni-uart";
1098                                 reg = <0 0x0088c000 0 0x4000>;
1099                                 clock-names = "se";
1100                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1101                                 pinctrl-names = "default";
1102                                 pinctrl-0 = <&qup_uart17_default>;
1103                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1104                                 power-domains = <&rpmhpd SM8250_CX>;
1105                                 operating-points-v2 = <&qup_opp_table>;
1106                                 status = "disabled";
1107                         };
1108
1109                         i2c18: i2c@890000 {
1110                                 compatible = "qcom,geni-i2c";
1111                                 reg = <0 0x00890000 0 0x4000>;
1112                                 clock-names = "se";
1113                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1114                                 pinctrl-names = "default";
1115                                 pinctrl-0 = <&qup_i2c18_default>;
1116                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1117                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1118                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1119                                 dma-names = "tx", "rx";
1120                                 #address-cells = <1>;
1121                                 #size-cells = <0>;
1122                                 status = "disabled";
1123                         };
1124
1125                         spi18: spi@890000 {
1126                                 compatible = "qcom,geni-spi";
1127                                 reg = <0 0x00890000 0 0x4000>;
1128                                 clock-names = "se";
1129                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1130                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1131                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1132                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1133                                 dma-names = "tx", "rx";
1134                                 power-domains = <&rpmhpd SM8250_CX>;
1135                                 operating-points-v2 = <&qup_opp_table>;
1136                                 #address-cells = <1>;
1137                                 #size-cells = <0>;
1138                                 status = "disabled";
1139                         };
1140
1141                         uart18: serial@890000 {
1142                                 compatible = "qcom,geni-uart";
1143                                 reg = <0 0x00890000 0 0x4000>;
1144                                 clock-names = "se";
1145                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1146                                 pinctrl-names = "default";
1147                                 pinctrl-0 = <&qup_uart18_default>;
1148                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1149                                 power-domains = <&rpmhpd SM8250_CX>;
1150                                 operating-points-v2 = <&qup_opp_table>;
1151                                 status = "disabled";
1152                         };
1153
1154                         i2c19: i2c@894000 {
1155                                 compatible = "qcom,geni-i2c";
1156                                 reg = <0 0x00894000 0 0x4000>;
1157                                 clock-names = "se";
1158                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1159                                 pinctrl-names = "default";
1160                                 pinctrl-0 = <&qup_i2c19_default>;
1161                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1162                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1163                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1164                                 dma-names = "tx", "rx";
1165                                 #address-cells = <1>;
1166                                 #size-cells = <0>;
1167                                 status = "disabled";
1168                         };
1169
1170                         spi19: spi@894000 {
1171                                 compatible = "qcom,geni-spi";
1172                                 reg = <0 0x00894000 0 0x4000>;
1173                                 clock-names = "se";
1174                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1175                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1176                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1177                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1178                                 dma-names = "tx", "rx";
1179                                 power-domains = <&rpmhpd SM8250_CX>;
1180                                 operating-points-v2 = <&qup_opp_table>;
1181                                 #address-cells = <1>;
1182                                 #size-cells = <0>;
1183                                 status = "disabled";
1184                         };
1185                 };
1186
1187                 gpi_dma0: dma-controller@900000 {
1188                         compatible = "qcom,sm8250-gpi-dma";
1189                         reg = <0 0x00900000 0 0x70000>;
1190                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1191                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1192                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1193                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1194                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1195                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1196                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1197                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1198                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1199                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1200                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1201                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1202                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1203                         dma-channels = <15>;
1204                         dma-channel-mask = <0x7ff>;
1205                         iommus = <&apps_smmu 0x5b6 0x0>;
1206                         #dma-cells = <3>;
1207                         status = "disabled";
1208                 };
1209
1210                 qupv3_id_0: geniqup@9c0000 {
1211                         compatible = "qcom,geni-se-qup";
1212                         reg = <0x0 0x009c0000 0x0 0x6000>;
1213                         clock-names = "m-ahb", "s-ahb";
1214                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1215                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1216                         #address-cells = <2>;
1217                         #size-cells = <2>;
1218                         iommus = <&apps_smmu 0x5a3 0x0>;
1219                         ranges;
1220                         status = "disabled";
1221
1222                         i2c0: i2c@980000 {
1223                                 compatible = "qcom,geni-i2c";
1224                                 reg = <0 0x00980000 0 0x4000>;
1225                                 clock-names = "se";
1226                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1227                                 pinctrl-names = "default";
1228                                 pinctrl-0 = <&qup_i2c0_default>;
1229                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1230                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1231                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1232                                 dma-names = "tx", "rx";
1233                                 #address-cells = <1>;
1234                                 #size-cells = <0>;
1235                                 status = "disabled";
1236                         };
1237
1238                         spi0: spi@980000 {
1239                                 compatible = "qcom,geni-spi";
1240                                 reg = <0 0x00980000 0 0x4000>;
1241                                 clock-names = "se";
1242                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1243                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1244                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1245                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1246                                 dma-names = "tx", "rx";
1247                                 power-domains = <&rpmhpd SM8250_CX>;
1248                                 operating-points-v2 = <&qup_opp_table>;
1249                                 #address-cells = <1>;
1250                                 #size-cells = <0>;
1251                                 status = "disabled";
1252                         };
1253
1254                         i2c1: i2c@984000 {
1255                                 compatible = "qcom,geni-i2c";
1256                                 reg = <0 0x00984000 0 0x4000>;
1257                                 clock-names = "se";
1258                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1259                                 pinctrl-names = "default";
1260                                 pinctrl-0 = <&qup_i2c1_default>;
1261                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1262                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1263                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1264                                 dma-names = "tx", "rx";
1265                                 #address-cells = <1>;
1266                                 #size-cells = <0>;
1267                                 status = "disabled";
1268                         };
1269
1270                         spi1: spi@984000 {
1271                                 compatible = "qcom,geni-spi";
1272                                 reg = <0 0x00984000 0 0x4000>;
1273                                 clock-names = "se";
1274                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1275                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1276                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1277                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1278                                 dma-names = "tx", "rx";
1279                                 power-domains = <&rpmhpd SM8250_CX>;
1280                                 operating-points-v2 = <&qup_opp_table>;
1281                                 #address-cells = <1>;
1282                                 #size-cells = <0>;
1283                                 status = "disabled";
1284                         };
1285
1286                         i2c2: i2c@988000 {
1287                                 compatible = "qcom,geni-i2c";
1288                                 reg = <0 0x00988000 0 0x4000>;
1289                                 clock-names = "se";
1290                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1291                                 pinctrl-names = "default";
1292                                 pinctrl-0 = <&qup_i2c2_default>;
1293                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1294                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1295                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1296                                 dma-names = "tx", "rx";
1297                                 #address-cells = <1>;
1298                                 #size-cells = <0>;
1299                                 status = "disabled";
1300                         };
1301
1302                         spi2: spi@988000 {
1303                                 compatible = "qcom,geni-spi";
1304                                 reg = <0 0x00988000 0 0x4000>;
1305                                 clock-names = "se";
1306                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1307                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1308                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1309                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1310                                 dma-names = "tx", "rx";
1311                                 power-domains = <&rpmhpd SM8250_CX>;
1312                                 operating-points-v2 = <&qup_opp_table>;
1313                                 #address-cells = <1>;
1314                                 #size-cells = <0>;
1315                                 status = "disabled";
1316                         };
1317
1318                         uart2: serial@988000 {
1319                                 compatible = "qcom,geni-debug-uart";
1320                                 reg = <0 0x00988000 0 0x4000>;
1321                                 clock-names = "se";
1322                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1323                                 pinctrl-names = "default";
1324                                 pinctrl-0 = <&qup_uart2_default>;
1325                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1326                                 power-domains = <&rpmhpd SM8250_CX>;
1327                                 operating-points-v2 = <&qup_opp_table>;
1328                                 status = "disabled";
1329                         };
1330
1331                         i2c3: i2c@98c000 {
1332                                 compatible = "qcom,geni-i2c";
1333                                 reg = <0 0x0098c000 0 0x4000>;
1334                                 clock-names = "se";
1335                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1336                                 pinctrl-names = "default";
1337                                 pinctrl-0 = <&qup_i2c3_default>;
1338                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1339                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1340                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1341                                 dma-names = "tx", "rx";
1342                                 #address-cells = <1>;
1343                                 #size-cells = <0>;
1344                                 status = "disabled";
1345                         };
1346
1347                         spi3: spi@98c000 {
1348                                 compatible = "qcom,geni-spi";
1349                                 reg = <0 0x0098c000 0 0x4000>;
1350                                 clock-names = "se";
1351                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1352                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1353                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1354                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1355                                 dma-names = "tx", "rx";
1356                                 power-domains = <&rpmhpd SM8250_CX>;
1357                                 operating-points-v2 = <&qup_opp_table>;
1358                                 #address-cells = <1>;
1359                                 #size-cells = <0>;
1360                                 status = "disabled";
1361                         };
1362
1363                         i2c4: i2c@990000 {
1364                                 compatible = "qcom,geni-i2c";
1365                                 reg = <0 0x00990000 0 0x4000>;
1366                                 clock-names = "se";
1367                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1368                                 pinctrl-names = "default";
1369                                 pinctrl-0 = <&qup_i2c4_default>;
1370                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1371                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1372                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1373                                 dma-names = "tx", "rx";
1374                                 #address-cells = <1>;
1375                                 #size-cells = <0>;
1376                                 status = "disabled";
1377                         };
1378
1379                         spi4: spi@990000 {
1380                                 compatible = "qcom,geni-spi";
1381                                 reg = <0 0x00990000 0 0x4000>;
1382                                 clock-names = "se";
1383                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1384                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1385                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1386                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1387                                 dma-names = "tx", "rx";
1388                                 power-domains = <&rpmhpd SM8250_CX>;
1389                                 operating-points-v2 = <&qup_opp_table>;
1390                                 #address-cells = <1>;
1391                                 #size-cells = <0>;
1392                                 status = "disabled";
1393                         };
1394
1395                         i2c5: i2c@994000 {
1396                                 compatible = "qcom,geni-i2c";
1397                                 reg = <0 0x00994000 0 0x4000>;
1398                                 clock-names = "se";
1399                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1400                                 pinctrl-names = "default";
1401                                 pinctrl-0 = <&qup_i2c5_default>;
1402                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1403                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1404                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1405                                 dma-names = "tx", "rx";
1406                                 #address-cells = <1>;
1407                                 #size-cells = <0>;
1408                                 status = "disabled";
1409                         };
1410
1411                         spi5: spi@994000 {
1412                                 compatible = "qcom,geni-spi";
1413                                 reg = <0 0x00994000 0 0x4000>;
1414                                 clock-names = "se";
1415                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1416                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1417                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1418                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1419                                 dma-names = "tx", "rx";
1420                                 power-domains = <&rpmhpd SM8250_CX>;
1421                                 operating-points-v2 = <&qup_opp_table>;
1422                                 #address-cells = <1>;
1423                                 #size-cells = <0>;
1424                                 status = "disabled";
1425                         };
1426
1427                         i2c6: i2c@998000 {
1428                                 compatible = "qcom,geni-i2c";
1429                                 reg = <0 0x00998000 0 0x4000>;
1430                                 clock-names = "se";
1431                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1432                                 pinctrl-names = "default";
1433                                 pinctrl-0 = <&qup_i2c6_default>;
1434                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1435                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1436                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1437                                 dma-names = "tx", "rx";
1438                                 #address-cells = <1>;
1439                                 #size-cells = <0>;
1440                                 status = "disabled";
1441                         };
1442
1443                         spi6: spi@998000 {
1444                                 compatible = "qcom,geni-spi";
1445                                 reg = <0 0x00998000 0 0x4000>;
1446                                 clock-names = "se";
1447                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1448                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1449                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1450                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1451                                 dma-names = "tx", "rx";
1452                                 power-domains = <&rpmhpd SM8250_CX>;
1453                                 operating-points-v2 = <&qup_opp_table>;
1454                                 #address-cells = <1>;
1455                                 #size-cells = <0>;
1456                                 status = "disabled";
1457                         };
1458
1459                         uart6: serial@998000 {
1460                                 compatible = "qcom,geni-uart";
1461                                 reg = <0 0x00998000 0 0x4000>;
1462                                 clock-names = "se";
1463                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1464                                 pinctrl-names = "default";
1465                                 pinctrl-0 = <&qup_uart6_default>;
1466                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1467                                 power-domains = <&rpmhpd SM8250_CX>;
1468                                 operating-points-v2 = <&qup_opp_table>;
1469                                 status = "disabled";
1470                         };
1471
1472                         i2c7: i2c@99c000 {
1473                                 compatible = "qcom,geni-i2c";
1474                                 reg = <0 0x0099c000 0 0x4000>;
1475                                 clock-names = "se";
1476                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1477                                 pinctrl-names = "default";
1478                                 pinctrl-0 = <&qup_i2c7_default>;
1479                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1480                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1481                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1482                                 dma-names = "tx", "rx";
1483                                 #address-cells = <1>;
1484                                 #size-cells = <0>;
1485                                 status = "disabled";
1486                         };
1487
1488                         spi7: spi@99c000 {
1489                                 compatible = "qcom,geni-spi";
1490                                 reg = <0 0x0099c000 0 0x4000>;
1491                                 clock-names = "se";
1492                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1493                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1494                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1495                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1496                                 dma-names = "tx", "rx";
1497                                 power-domains = <&rpmhpd SM8250_CX>;
1498                                 operating-points-v2 = <&qup_opp_table>;
1499                                 #address-cells = <1>;
1500                                 #size-cells = <0>;
1501                                 status = "disabled";
1502                         };
1503                 };
1504
1505                 gpi_dma1: dma-controller@a00000 {
1506                         compatible = "qcom,sm8250-gpi-dma";
1507                         reg = <0 0x00a00000 0 0x70000>;
1508                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1509                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1510                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1511                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1512                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1513                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1514                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1515                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1516                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1517                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1518                         dma-channels = <10>;
1519                         dma-channel-mask = <0x3f>;
1520                         iommus = <&apps_smmu 0x56 0x0>;
1521                         #dma-cells = <3>;
1522                         status = "disabled";
1523                 };
1524
1525                 qupv3_id_1: geniqup@ac0000 {
1526                         compatible = "qcom,geni-se-qup";
1527                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1528                         clock-names = "m-ahb", "s-ahb";
1529                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1530                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1531                         #address-cells = <2>;
1532                         #size-cells = <2>;
1533                         iommus = <&apps_smmu 0x43 0x0>;
1534                         ranges;
1535                         status = "disabled";
1536
1537                         i2c8: i2c@a80000 {
1538                                 compatible = "qcom,geni-i2c";
1539                                 reg = <0 0x00a80000 0 0x4000>;
1540                                 clock-names = "se";
1541                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1542                                 pinctrl-names = "default";
1543                                 pinctrl-0 = <&qup_i2c8_default>;
1544                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1545                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1546                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1547                                 dma-names = "tx", "rx";
1548                                 #address-cells = <1>;
1549                                 #size-cells = <0>;
1550                                 status = "disabled";
1551                         };
1552
1553                         spi8: spi@a80000 {
1554                                 compatible = "qcom,geni-spi";
1555                                 reg = <0 0x00a80000 0 0x4000>;
1556                                 clock-names = "se";
1557                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1558                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1559                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1560                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1561                                 dma-names = "tx", "rx";
1562                                 power-domains = <&rpmhpd SM8250_CX>;
1563                                 operating-points-v2 = <&qup_opp_table>;
1564                                 #address-cells = <1>;
1565                                 #size-cells = <0>;
1566                                 status = "disabled";
1567                         };
1568
1569                         i2c9: i2c@a84000 {
1570                                 compatible = "qcom,geni-i2c";
1571                                 reg = <0 0x00a84000 0 0x4000>;
1572                                 clock-names = "se";
1573                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1574                                 pinctrl-names = "default";
1575                                 pinctrl-0 = <&qup_i2c9_default>;
1576                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1577                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1578                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1579                                 dma-names = "tx", "rx";
1580                                 #address-cells = <1>;
1581                                 #size-cells = <0>;
1582                                 status = "disabled";
1583                         };
1584
1585                         spi9: spi@a84000 {
1586                                 compatible = "qcom,geni-spi";
1587                                 reg = <0 0x00a84000 0 0x4000>;
1588                                 clock-names = "se";
1589                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1590                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1591                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1592                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1593                                 dma-names = "tx", "rx";
1594                                 power-domains = <&rpmhpd SM8250_CX>;
1595                                 operating-points-v2 = <&qup_opp_table>;
1596                                 #address-cells = <1>;
1597                                 #size-cells = <0>;
1598                                 status = "disabled";
1599                         };
1600
1601                         i2c10: i2c@a88000 {
1602                                 compatible = "qcom,geni-i2c";
1603                                 reg = <0 0x00a88000 0 0x4000>;
1604                                 clock-names = "se";
1605                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1606                                 pinctrl-names = "default";
1607                                 pinctrl-0 = <&qup_i2c10_default>;
1608                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1609                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1610                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1611                                 dma-names = "tx", "rx";
1612                                 #address-cells = <1>;
1613                                 #size-cells = <0>;
1614                                 status = "disabled";
1615                         };
1616
1617                         spi10: spi@a88000 {
1618                                 compatible = "qcom,geni-spi";
1619                                 reg = <0 0x00a88000 0 0x4000>;
1620                                 clock-names = "se";
1621                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1622                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1623                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1624                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1625                                 dma-names = "tx", "rx";
1626                                 power-domains = <&rpmhpd SM8250_CX>;
1627                                 operating-points-v2 = <&qup_opp_table>;
1628                                 #address-cells = <1>;
1629                                 #size-cells = <0>;
1630                                 status = "disabled";
1631                         };
1632
1633                         i2c11: i2c@a8c000 {
1634                                 compatible = "qcom,geni-i2c";
1635                                 reg = <0 0x00a8c000 0 0x4000>;
1636                                 clock-names = "se";
1637                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1638                                 pinctrl-names = "default";
1639                                 pinctrl-0 = <&qup_i2c11_default>;
1640                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1641                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1642                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1643                                 dma-names = "tx", "rx";
1644                                 #address-cells = <1>;
1645                                 #size-cells = <0>;
1646                                 status = "disabled";
1647                         };
1648
1649                         spi11: spi@a8c000 {
1650                                 compatible = "qcom,geni-spi";
1651                                 reg = <0 0x00a8c000 0 0x4000>;
1652                                 clock-names = "se";
1653                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1654                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1655                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1656                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1657                                 dma-names = "tx", "rx";
1658                                 power-domains = <&rpmhpd SM8250_CX>;
1659                                 operating-points-v2 = <&qup_opp_table>;
1660                                 #address-cells = <1>;
1661                                 #size-cells = <0>;
1662                                 status = "disabled";
1663                         };
1664
1665                         i2c12: i2c@a90000 {
1666                                 compatible = "qcom,geni-i2c";
1667                                 reg = <0 0x00a90000 0 0x4000>;
1668                                 clock-names = "se";
1669                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1670                                 pinctrl-names = "default";
1671                                 pinctrl-0 = <&qup_i2c12_default>;
1672                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1673                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1674                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1675                                 dma-names = "tx", "rx";
1676                                 #address-cells = <1>;
1677                                 #size-cells = <0>;
1678                                 status = "disabled";
1679                         };
1680
1681                         spi12: spi@a90000 {
1682                                 compatible = "qcom,geni-spi";
1683                                 reg = <0 0x00a90000 0 0x4000>;
1684                                 clock-names = "se";
1685                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1686                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1687                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1688                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1689                                 dma-names = "tx", "rx";
1690                                 power-domains = <&rpmhpd SM8250_CX>;
1691                                 operating-points-v2 = <&qup_opp_table>;
1692                                 #address-cells = <1>;
1693                                 #size-cells = <0>;
1694                                 status = "disabled";
1695                         };
1696
1697                         uart12: serial@a90000 {
1698                                 compatible = "qcom,geni-debug-uart";
1699                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1700                                 clock-names = "se";
1701                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1702                                 pinctrl-names = "default";
1703                                 pinctrl-0 = <&qup_uart12_default>;
1704                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1705                                 power-domains = <&rpmhpd SM8250_CX>;
1706                                 operating-points-v2 = <&qup_opp_table>;
1707                                 status = "disabled";
1708                         };
1709
1710                         i2c13: i2c@a94000 {
1711                                 compatible = "qcom,geni-i2c";
1712                                 reg = <0 0x00a94000 0 0x4000>;
1713                                 clock-names = "se";
1714                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1715                                 pinctrl-names = "default";
1716                                 pinctrl-0 = <&qup_i2c13_default>;
1717                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1718                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1719                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1720                                 dma-names = "tx", "rx";
1721                                 #address-cells = <1>;
1722                                 #size-cells = <0>;
1723                                 status = "disabled";
1724                         };
1725
1726                         spi13: spi@a94000 {
1727                                 compatible = "qcom,geni-spi";
1728                                 reg = <0 0x00a94000 0 0x4000>;
1729                                 clock-names = "se";
1730                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1731                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1732                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1733                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1734                                 dma-names = "tx", "rx";
1735                                 power-domains = <&rpmhpd SM8250_CX>;
1736                                 operating-points-v2 = <&qup_opp_table>;
1737                                 #address-cells = <1>;
1738                                 #size-cells = <0>;
1739                                 status = "disabled";
1740                         };
1741                 };
1742
1743                 config_noc: interconnect@1500000 {
1744                         compatible = "qcom,sm8250-config-noc";
1745                         reg = <0 0x01500000 0 0xa580>;
1746                         #interconnect-cells = <1>;
1747                         qcom,bcm-voters = <&apps_bcm_voter>;
1748                 };
1749
1750                 system_noc: interconnect@1620000 {
1751                         compatible = "qcom,sm8250-system-noc";
1752                         reg = <0 0x01620000 0 0x1c200>;
1753                         #interconnect-cells = <1>;
1754                         qcom,bcm-voters = <&apps_bcm_voter>;
1755                 };
1756
1757                 mc_virt: interconnect@163d000 {
1758                         compatible = "qcom,sm8250-mc-virt";
1759                         reg = <0 0x0163d000 0 0x1000>;
1760                         #interconnect-cells = <1>;
1761                         qcom,bcm-voters = <&apps_bcm_voter>;
1762                 };
1763
1764                 aggre1_noc: interconnect@16e0000 {
1765                         compatible = "qcom,sm8250-aggre1-noc";
1766                         reg = <0 0x016e0000 0 0x1f180>;
1767                         #interconnect-cells = <1>;
1768                         qcom,bcm-voters = <&apps_bcm_voter>;
1769                 };
1770
1771                 aggre2_noc: interconnect@1700000 {
1772                         compatible = "qcom,sm8250-aggre2-noc";
1773                         reg = <0 0x01700000 0 0x33000>;
1774                         #interconnect-cells = <1>;
1775                         qcom,bcm-voters = <&apps_bcm_voter>;
1776                 };
1777
1778                 compute_noc: interconnect@1733000 {
1779                         compatible = "qcom,sm8250-compute-noc";
1780                         reg = <0 0x01733000 0 0xa180>;
1781                         #interconnect-cells = <1>;
1782                         qcom,bcm-voters = <&apps_bcm_voter>;
1783                 };
1784
1785                 mmss_noc: interconnect@1740000 {
1786                         compatible = "qcom,sm8250-mmss-noc";
1787                         reg = <0 0x01740000 0 0x1f080>;
1788                         #interconnect-cells = <1>;
1789                         qcom,bcm-voters = <&apps_bcm_voter>;
1790                 };
1791
1792                 pcie0: pci@1c00000 {
1793                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1794                         reg = <0 0x01c00000 0 0x3000>,
1795                               <0 0x60000000 0 0xf1d>,
1796                               <0 0x60000f20 0 0xa8>,
1797                               <0 0x60001000 0 0x1000>,
1798                               <0 0x60100000 0 0x100000>;
1799                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1800                         device_type = "pci";
1801                         linux,pci-domain = <0>;
1802                         bus-range = <0x00 0xff>;
1803                         num-lanes = <1>;
1804
1805                         #address-cells = <3>;
1806                         #size-cells = <2>;
1807
1808                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1809                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1810
1811                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1812                         interrupt-names = "msi";
1813                         #interrupt-cells = <1>;
1814                         interrupt-map-mask = <0 0 0 0x7>;
1815                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1816                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1817                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1818                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1819
1820                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1821                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1822                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1823                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1824                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1825                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1826                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1827                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1828                         clock-names = "pipe",
1829                                       "aux",
1830                                       "cfg",
1831                                       "bus_master",
1832                                       "bus_slave",
1833                                       "slave_q2a",
1834                                       "tbu",
1835                                       "ddrss_sf_tbu";
1836
1837                         iommus = <&apps_smmu 0x1c00 0x7f>;
1838                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1839                                     <0x100 &apps_smmu 0x1c01 0x1>;
1840
1841                         resets = <&gcc GCC_PCIE_0_BCR>;
1842                         reset-names = "pci";
1843
1844                         power-domains = <&gcc PCIE_0_GDSC>;
1845
1846                         phys = <&pcie0_lane>;
1847                         phy-names = "pciephy";
1848
1849                         perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
1850                         wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1851
1852                         pinctrl-names = "default";
1853                         pinctrl-0 = <&pcie0_default_state>;
1854
1855                         status = "disabled";
1856                 };
1857
1858                 pcie0_phy: phy@1c06000 {
1859                         compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1860                         reg = <0 0x01c06000 0 0x1c0>;
1861                         #address-cells = <2>;
1862                         #size-cells = <2>;
1863                         ranges;
1864                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1865                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1866                                  <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1867                                  <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1868                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1869
1870                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1871                         reset-names = "phy";
1872
1873                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1874                         assigned-clock-rates = <100000000>;
1875
1876                         status = "disabled";
1877
1878                         pcie0_lane: phy@1c06200 {
1879                                 reg = <0 0x1c06200 0 0x170>, /* tx */
1880                                       <0 0x1c06400 0 0x200>, /* rx */
1881                                       <0 0x1c06800 0 0x1f0>, /* pcs */
1882                                       <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1883                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1884                                 clock-names = "pipe0";
1885
1886                                 #phy-cells = <0>;
1887                                 clock-output-names = "pcie_0_pipe_clk";
1888                         };
1889                 };
1890
1891                 pcie1: pci@1c08000 {
1892                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1893                         reg = <0 0x01c08000 0 0x3000>,
1894                               <0 0x40000000 0 0xf1d>,
1895                               <0 0x40000f20 0 0xa8>,
1896                               <0 0x40001000 0 0x1000>,
1897                               <0 0x40100000 0 0x100000>;
1898                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1899                         device_type = "pci";
1900                         linux,pci-domain = <1>;
1901                         bus-range = <0x00 0xff>;
1902                         num-lanes = <2>;
1903
1904                         #address-cells = <3>;
1905                         #size-cells = <2>;
1906
1907                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1908                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1909
1910                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1911                         interrupt-names = "msi";
1912                         #interrupt-cells = <1>;
1913                         interrupt-map-mask = <0 0 0 0x7>;
1914                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1915                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1916                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1917                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1918
1919                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1920                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1921                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1922                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1923                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1924                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1925                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1926                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1927                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1928                         clock-names = "pipe",
1929                                       "aux",
1930                                       "cfg",
1931                                       "bus_master",
1932                                       "bus_slave",
1933                                       "slave_q2a",
1934                                       "ref",
1935                                       "tbu",
1936                                       "ddrss_sf_tbu";
1937
1938                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1939                         assigned-clock-rates = <19200000>;
1940
1941                         iommus = <&apps_smmu 0x1c80 0x7f>;
1942                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1943                                     <0x100 &apps_smmu 0x1c81 0x1>;
1944
1945                         resets = <&gcc GCC_PCIE_1_BCR>;
1946                         reset-names = "pci";
1947
1948                         power-domains = <&gcc PCIE_1_GDSC>;
1949
1950                         phys = <&pcie1_lane>;
1951                         phy-names = "pciephy";
1952
1953                         perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
1954                         wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
1955
1956                         pinctrl-names = "default";
1957                         pinctrl-0 = <&pcie1_default_state>;
1958
1959                         status = "disabled";
1960                 };
1961
1962                 pcie1_phy: phy@1c0e000 {
1963                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1964                         reg = <0 0x01c0e000 0 0x1c0>;
1965                         #address-cells = <2>;
1966                         #size-cells = <2>;
1967                         ranges;
1968                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1969                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1970                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1971                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1972                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1973
1974                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1975                         reset-names = "phy";
1976
1977                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1978                         assigned-clock-rates = <100000000>;
1979
1980                         status = "disabled";
1981
1982                         pcie1_lane: phy@1c0e200 {
1983                                 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1984                                       <0 0x1c0e400 0 0x200>, /* rx0 */
1985                                       <0 0x1c0ea00 0 0x1f0>, /* pcs */
1986                                       <0 0x1c0e600 0 0x170>, /* tx1 */
1987                                       <0 0x1c0e800 0 0x200>, /* rx1 */
1988                                       <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1989                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1990                                 clock-names = "pipe0";
1991
1992                                 #phy-cells = <0>;
1993                                 clock-output-names = "pcie_1_pipe_clk";
1994                         };
1995                 };
1996
1997                 pcie2: pci@1c10000 {
1998                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1999                         reg = <0 0x01c10000 0 0x3000>,
2000                               <0 0x64000000 0 0xf1d>,
2001                               <0 0x64000f20 0 0xa8>,
2002                               <0 0x64001000 0 0x1000>,
2003                               <0 0x64100000 0 0x100000>;
2004                         reg-names = "parf", "dbi", "elbi", "atu", "config";
2005                         device_type = "pci";
2006                         linux,pci-domain = <2>;
2007                         bus-range = <0x00 0xff>;
2008                         num-lanes = <2>;
2009
2010                         #address-cells = <3>;
2011                         #size-cells = <2>;
2012
2013                         ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2014                                  <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2015
2016                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2017                         interrupt-names = "msi";
2018                         #interrupt-cells = <1>;
2019                         interrupt-map-mask = <0 0 0 0x7>;
2020                         interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2021                                         <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2022                                         <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2023                                         <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2024
2025                         clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2026                                  <&gcc GCC_PCIE_2_AUX_CLK>,
2027                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2028                                  <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2029                                  <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2030                                  <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2031                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2032                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2033                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2034                         clock-names = "pipe",
2035                                       "aux",
2036                                       "cfg",
2037                                       "bus_master",
2038                                       "bus_slave",
2039                                       "slave_q2a",
2040                                       "ref",
2041                                       "tbu",
2042                                       "ddrss_sf_tbu";
2043
2044                         assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2045                         assigned-clock-rates = <19200000>;
2046
2047                         iommus = <&apps_smmu 0x1d00 0x7f>;
2048                         iommu-map = <0x0   &apps_smmu 0x1d00 0x1>,
2049                                     <0x100 &apps_smmu 0x1d01 0x1>;
2050
2051                         resets = <&gcc GCC_PCIE_2_BCR>;
2052                         reset-names = "pci";
2053
2054                         power-domains = <&gcc PCIE_2_GDSC>;
2055
2056                         phys = <&pcie2_lane>;
2057                         phy-names = "pciephy";
2058
2059                         perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2060                         wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2061
2062                         pinctrl-names = "default";
2063                         pinctrl-0 = <&pcie2_default_state>;
2064
2065                         status = "disabled";
2066                 };
2067
2068                 pcie2_phy: phy@1c16000 {
2069                         compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2070                         reg = <0 0x1c16000 0 0x1c0>;
2071                         #address-cells = <2>;
2072                         #size-cells = <2>;
2073                         ranges;
2074                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2075                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2076                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2077                                  <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2078                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2079
2080                         resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2081                         reset-names = "phy";
2082
2083                         assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2084                         assigned-clock-rates = <100000000>;
2085
2086                         status = "disabled";
2087
2088                         pcie2_lane: phy@1c16200 {
2089                                 reg = <0 0x1c16200 0 0x170>, /* tx0 */
2090                                       <0 0x1c16400 0 0x200>, /* rx0 */
2091                                       <0 0x1c16a00 0 0x1f0>, /* pcs */
2092                                       <0 0x1c16600 0 0x170>, /* tx1 */
2093                                       <0 0x1c16800 0 0x200>, /* rx1 */
2094                                       <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2095                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
2096                                 clock-names = "pipe0";
2097
2098                                 #phy-cells = <0>;
2099                                 clock-output-names = "pcie_2_pipe_clk";
2100                         };
2101                 };
2102
2103                 ufs_mem_hc: ufshc@1d84000 {
2104                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2105                                      "jedec,ufs-2.0";
2106                         reg = <0 0x01d84000 0 0x3000>;
2107                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2108                         phys = <&ufs_mem_phy_lanes>;
2109                         phy-names = "ufsphy";
2110                         lanes-per-direction = <2>;
2111                         #reset-cells = <1>;
2112                         resets = <&gcc GCC_UFS_PHY_BCR>;
2113                         reset-names = "rst";
2114
2115                         power-domains = <&gcc UFS_PHY_GDSC>;
2116
2117                         iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2118
2119                         clock-names =
2120                                 "core_clk",
2121                                 "bus_aggr_clk",
2122                                 "iface_clk",
2123                                 "core_clk_unipro",
2124                                 "ref_clk",
2125                                 "tx_lane0_sync_clk",
2126                                 "rx_lane0_sync_clk",
2127                                 "rx_lane1_sync_clk";
2128                         clocks =
2129                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2130                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2131                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2132                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2133                                 <&rpmhcc RPMH_CXO_CLK>,
2134                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2135                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2136                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2137                         freq-table-hz =
2138                                 <37500000 300000000>,
2139                                 <0 0>,
2140                                 <0 0>,
2141                                 <37500000 300000000>,
2142                                 <0 0>,
2143                                 <0 0>,
2144                                 <0 0>,
2145                                 <0 0>;
2146
2147                         status = "disabled";
2148                 };
2149
2150                 ufs_mem_phy: phy@1d87000 {
2151                         compatible = "qcom,sm8250-qmp-ufs-phy";
2152                         reg = <0 0x01d87000 0 0x1c0>;
2153                         #address-cells = <2>;
2154                         #size-cells = <2>;
2155                         ranges;
2156                         clock-names = "ref",
2157                                       "ref_aux";
2158                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2159                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2160
2161                         resets = <&ufs_mem_hc 0>;
2162                         reset-names = "ufsphy";
2163                         status = "disabled";
2164
2165                         ufs_mem_phy_lanes: phy@1d87400 {
2166                                 reg = <0 0x01d87400 0 0x108>,
2167                                       <0 0x01d87600 0 0x1e0>,
2168                                       <0 0x01d87c00 0 0x1dc>,
2169                                       <0 0x01d87800 0 0x108>,
2170                                       <0 0x01d87a00 0 0x1e0>;
2171                                 #phy-cells = <0>;
2172                         };
2173                 };
2174
2175                 ipa_virt: interconnect@1e00000 {
2176                         compatible = "qcom,sm8250-ipa-virt";
2177                         reg = <0 0x01e00000 0 0x1000>;
2178                         #interconnect-cells = <1>;
2179                         qcom,bcm-voters = <&apps_bcm_voter>;
2180                 };
2181
2182                 tcsr_mutex: hwlock@1f40000 {
2183                         compatible = "qcom,tcsr-mutex";
2184                         reg = <0x0 0x01f40000 0x0 0x40000>;
2185                         #hwlock-cells = <1>;
2186                 };
2187
2188                 wsamacro: codec@3240000 {
2189                         compatible = "qcom,sm8250-lpass-wsa-macro";
2190                         reg = <0 0x03240000 0 0x1000>;
2191                         clocks = <&audiocc 1>,
2192                                  <&audiocc 0>,
2193                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2194                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2195                                  <&aoncc 0>,
2196                                  <&vamacro>;
2197
2198                         clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2199
2200                         #clock-cells = <0>;
2201                         clock-frequency = <9600000>;
2202                         clock-output-names = "mclk";
2203                         #sound-dai-cells = <1>;
2204
2205                         pinctrl-names = "default";
2206                         pinctrl-0 = <&wsa_swr_active>;
2207                 };
2208
2209                 swr0: soundwire-controller@3250000 {
2210                         reg = <0 0x03250000 0 0x2000>;
2211                         compatible = "qcom,soundwire-v1.5.1";
2212                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2213                         clocks = <&wsamacro>;
2214                         clock-names = "iface";
2215
2216                         qcom,din-ports = <2>;
2217                         qcom,dout-ports = <6>;
2218
2219                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2220                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2221                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2222                         qcom,ports-block-pack-mode =    /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2223
2224                         #sound-dai-cells = <1>;
2225                         #address-cells = <2>;
2226                         #size-cells = <0>;
2227                 };
2228
2229                 audiocc: clock-controller@3300000 {
2230                         compatible = "qcom,sm8250-lpass-audiocc";
2231                         reg = <0 0x03300000 0 0x30000>;
2232                         #clock-cells = <1>;
2233                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2234                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2235                                 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2236                         clock-names = "core", "audio", "bus";
2237                 };
2238
2239                 vamacro: codec@3370000 {
2240                         compatible = "qcom,sm8250-lpass-va-macro";
2241                         reg = <0 0x03370000 0 0x1000>;
2242                         clocks = <&aoncc 0>,
2243                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2244                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2245
2246                         clock-names = "mclk", "macro", "dcodec";
2247
2248                         #clock-cells = <0>;
2249                         clock-frequency = <9600000>;
2250                         clock-output-names = "fsgen";
2251                         #sound-dai-cells = <1>;
2252                 };
2253
2254                 rxmacro: rxmacro@3200000 {
2255                         pinctrl-names = "default";
2256                         pinctrl-0 = <&rx_swr_active>;
2257                         compatible = "qcom,sm8250-lpass-rx-macro";
2258                         reg = <0 0x3200000 0 0x1000>;
2259                         status = "disabled";
2260
2261                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2262                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2263                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2264                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2265                                 <&vamacro>;
2266
2267                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2268
2269                         #clock-cells = <0>;
2270                         clock-frequency = <9600000>;
2271                         clock-output-names = "mclk";
2272                         #sound-dai-cells = <1>;
2273                 };
2274
2275                 swr1: soundwire-controller@3210000 {
2276                         reg = <0 0x3210000 0 0x2000>;
2277                         compatible = "qcom,soundwire-v1.5.1";
2278                         status = "disabled";
2279                         interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2280                         clocks = <&rxmacro>;
2281                         clock-names = "iface";
2282                         label = "RX";
2283                         qcom,din-ports = <0>;
2284                         qcom,dout-ports = <5>;
2285
2286                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
2287                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2288                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2289                         qcom,ports-hstart =             /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
2290                         qcom,ports-hstop =              /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
2291                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
2292                         qcom,ports-block-pack-mode =    /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
2293                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2294                         qcom,ports-block-group-count =  /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
2295
2296                         #sound-dai-cells = <1>;
2297                         #address-cells = <2>;
2298                         #size-cells = <0>;
2299                 };
2300
2301                 txmacro: txmacro@3220000 {
2302                         pinctrl-names = "default";
2303                         pinctrl-0 = <&tx_swr_active>;
2304                         compatible = "qcom,sm8250-lpass-tx-macro";
2305                         reg = <0 0x3220000 0 0x1000>;
2306                         status = "disabled";
2307
2308                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2309                                  <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2310                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2311                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2312                                  <&vamacro>;
2313
2314                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2315
2316                         #clock-cells = <0>;
2317                         clock-frequency = <9600000>;
2318                         clock-output-names = "mclk";
2319                         #address-cells = <2>;
2320                         #size-cells = <2>;
2321                         #sound-dai-cells = <1>;
2322                 };
2323
2324                 /* tx macro */
2325                 swr2: soundwire-controller@3230000 {
2326                         reg = <0 0x3230000 0 0x2000>;
2327                         compatible = "qcom,soundwire-v1.5.1";
2328                         interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2329                         interrupt-names = "core";
2330                         status = "disabled";
2331
2332                         clocks = <&txmacro>;
2333                         clock-names = "iface";
2334                         label = "TX";
2335
2336                         qcom,din-ports = <5>;
2337                         qcom,dout-ports = <0>;
2338                         qcom,ports-sinterval-low =      /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
2339                         qcom,ports-offset1 =            /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
2340                         qcom,ports-offset2 =            /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
2341                         qcom,ports-block-pack-mode =    /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2342                         qcom,ports-hstart =             /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2343                         qcom,ports-hstop =              /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2344                         qcom,ports-word-length =        /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2345                         qcom,ports-block-group-count =  /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2346                         qcom,ports-lane-control =       /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
2347                         qcom,port-offset = <1>;
2348                         #sound-dai-cells = <1>;
2349                         #address-cells = <2>;
2350                         #size-cells = <0>;
2351                 };
2352
2353                 aoncc: clock-controller@3380000 {
2354                         compatible = "qcom,sm8250-lpass-aoncc";
2355                         reg = <0 0x03380000 0 0x40000>;
2356                         #clock-cells = <1>;
2357                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2358                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2359                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2360                         clock-names = "core", "audio", "bus";
2361                 };
2362
2363                 lpass_tlmm: pinctrl@33c0000{
2364                         compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2365                         reg = <0 0x033c0000 0x0 0x20000>,
2366                               <0 0x03550000 0x0 0x10000>;
2367                         gpio-controller;
2368                         #gpio-cells = <2>;
2369                         gpio-ranges = <&lpass_tlmm 0 0 14>;
2370
2371                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2372                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2373                         clock-names = "core", "audio";
2374
2375                         wsa_swr_active: wsa-swr-active-pins {
2376                                 clk {
2377                                         pins = "gpio10";
2378                                         function = "wsa_swr_clk";
2379                                         drive-strength = <2>;
2380                                         slew-rate = <1>;
2381                                         bias-disable;
2382                                 };
2383
2384                                 data {
2385                                         pins = "gpio11";
2386                                         function = "wsa_swr_data";
2387                                         drive-strength = <2>;
2388                                         slew-rate = <1>;
2389                                         bias-bus-hold;
2390
2391                                 };
2392                         };
2393
2394                         wsa_swr_sleep: wsa-swr-sleep-pins {
2395                                 clk {
2396                                         pins = "gpio10";
2397                                         function = "wsa_swr_clk";
2398                                         drive-strength = <2>;
2399                                         input-enable;
2400                                         bias-pull-down;
2401                                 };
2402
2403                                 data {
2404                                         pins = "gpio11";
2405                                         function = "wsa_swr_data";
2406                                         drive-strength = <2>;
2407                                         input-enable;
2408                                         bias-pull-down;
2409
2410                                 };
2411                         };
2412
2413                         dmic01_active: dmic01-active-pins {
2414                                 clk {
2415                                         pins = "gpio6";
2416                                         function = "dmic1_clk";
2417                                         drive-strength = <8>;
2418                                         output-high;
2419                                 };
2420                                 data {
2421                                         pins = "gpio7";
2422                                         function = "dmic1_data";
2423                                         drive-strength = <8>;
2424                                         input-enable;
2425                                 };
2426                         };
2427
2428                         dmic01_sleep: dmic01-sleep-pins {
2429                                 clk {
2430                                         pins = "gpio6";
2431                                         function = "dmic1_clk";
2432                                         drive-strength = <2>;
2433                                         bias-disable;
2434                                         output-low;
2435                                 };
2436
2437                                 data {
2438                                         pins = "gpio7";
2439                                         function = "dmic1_data";
2440                                         drive-strength = <2>;
2441                                         pull-down;
2442                                         input-enable;
2443                                 };
2444                         };
2445
2446                         rx_swr_active: rx_swr-active-pins {
2447                                 clk {
2448                                         pins = "gpio3";
2449                                         function = "swr_rx_clk";
2450                                         drive-strength = <2>;
2451                                         slew-rate = <1>;
2452                                         bias-disable;
2453                                 };
2454
2455                                 data {
2456                                         pins = "gpio4", "gpio5";
2457                                         function = "swr_rx_data";
2458                                         drive-strength = <2>;
2459                                         slew-rate = <1>;
2460                                         bias-bus-hold;
2461                                 };
2462                         };
2463
2464                         tx_swr_active: tx_swr-active-pins {
2465                                 clk {
2466                                         pins = "gpio0";
2467                                         function = "swr_tx_clk";
2468                                         drive-strength = <2>;
2469                                         slew-rate = <1>;
2470                                         bias-disable;
2471                                 };
2472
2473                                 data {
2474                                         pins = "gpio1", "gpio2";
2475                                         function = "swr_tx_data";
2476                                         drive-strength = <2>;
2477                                         slew-rate = <1>;
2478                                         bias-bus-hold;
2479                                 };
2480                         };
2481
2482                         tx_swr_sleep: tx_swr-sleep-pins {
2483                                 clk {
2484                                         pins = "gpio0";
2485                                         function = "swr_tx_clk";
2486                                         drive-strength = <2>;
2487                                         input-enable;
2488                                         bias-pull-down;
2489                                 };
2490
2491                                 data1 {
2492                                         pins = "gpio1";
2493                                         function = "swr_tx_data";
2494                                         drive-strength = <2>;
2495                                         input-enable;
2496                                         bias-bus-hold;
2497                                 };
2498
2499                                 data2 {
2500                                         pins = "gpio2";
2501                                         function = "swr_tx_data";
2502                                         drive-strength = <2>;
2503                                         input-enable;
2504                                         bias-pull-down;
2505                                 };
2506                         };
2507                 };
2508
2509                 gpu: gpu@3d00000 {
2510                         compatible = "qcom,adreno-650.2",
2511                                      "qcom,adreno";
2512
2513                         reg = <0 0x03d00000 0 0x40000>;
2514                         reg-names = "kgsl_3d0_reg_memory";
2515
2516                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2517
2518                         iommus = <&adreno_smmu 0 0x401>;
2519
2520                         operating-points-v2 = <&gpu_opp_table>;
2521
2522                         qcom,gmu = <&gmu>;
2523
2524                         status = "disabled";
2525
2526                         zap-shader {
2527                                 memory-region = <&gpu_mem>;
2528                         };
2529
2530                         /* note: downstream checks gpu binning for 670 Mhz */
2531                         gpu_opp_table: opp-table {
2532                                 compatible = "operating-points-v2";
2533
2534                                 opp-670000000 {
2535                                         opp-hz = /bits/ 64 <670000000>;
2536                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2537                                 };
2538
2539                                 opp-587000000 {
2540                                         opp-hz = /bits/ 64 <587000000>;
2541                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2542                                 };
2543
2544                                 opp-525000000 {
2545                                         opp-hz = /bits/ 64 <525000000>;
2546                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2547                                 };
2548
2549                                 opp-490000000 {
2550                                         opp-hz = /bits/ 64 <490000000>;
2551                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2552                                 };
2553
2554                                 opp-441600000 {
2555                                         opp-hz = /bits/ 64 <441600000>;
2556                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2557                                 };
2558
2559                                 opp-400000000 {
2560                                         opp-hz = /bits/ 64 <400000000>;
2561                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2562                                 };
2563
2564                                 opp-305000000 {
2565                                         opp-hz = /bits/ 64 <305000000>;
2566                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2567                                 };
2568                         };
2569                 };
2570
2571                 gmu: gmu@3d6a000 {
2572                         compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2573
2574                         reg = <0 0x03d6a000 0 0x30000>,
2575                               <0 0x3de0000 0 0x10000>,
2576                               <0 0xb290000 0 0x10000>,
2577                               <0 0xb490000 0 0x10000>;
2578                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2579
2580                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2581                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2582                         interrupt-names = "hfi", "gmu";
2583
2584                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2585                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2586                                  <&gpucc GPU_CC_CXO_CLK>,
2587                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2588                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2589                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2590
2591                         power-domains = <&gpucc GPU_CX_GDSC>,
2592                                         <&gpucc GPU_GX_GDSC>;
2593                         power-domain-names = "cx", "gx";
2594
2595                         iommus = <&adreno_smmu 5 0x400>;
2596
2597                         operating-points-v2 = <&gmu_opp_table>;
2598
2599                         status = "disabled";
2600
2601                         gmu_opp_table: opp-table {
2602                                 compatible = "operating-points-v2";
2603
2604                                 opp-200000000 {
2605                                         opp-hz = /bits/ 64 <200000000>;
2606                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2607                                 };
2608                         };
2609                 };
2610
2611                 gpucc: clock-controller@3d90000 {
2612                         compatible = "qcom,sm8250-gpucc";
2613                         reg = <0 0x03d90000 0 0x9000>;
2614                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2615                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2616                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2617                         clock-names = "bi_tcxo",
2618                                       "gcc_gpu_gpll0_clk_src",
2619                                       "gcc_gpu_gpll0_div_clk_src";
2620                         #clock-cells = <1>;
2621                         #reset-cells = <1>;
2622                         #power-domain-cells = <1>;
2623                 };
2624
2625                 adreno_smmu: iommu@3da0000 {
2626                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
2627                         reg = <0 0x03da0000 0 0x10000>;
2628                         #iommu-cells = <2>;
2629                         #global-interrupts = <2>;
2630                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2631                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2632                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2633                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2634                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2635                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2636                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2637                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2638                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2639                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
2640                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2641                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2642                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2643                         clock-names = "ahb", "bus", "iface";
2644
2645                         power-domains = <&gpucc GPU_CX_GDSC>;
2646                 };
2647
2648                 slpi: remoteproc@5c00000 {
2649                         compatible = "qcom,sm8250-slpi-pas";
2650                         reg = <0 0x05c00000 0 0x4000>;
2651
2652                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2653                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2654                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2655                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2656                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2657                         interrupt-names = "wdog", "fatal", "ready",
2658                                           "handover", "stop-ack";
2659
2660                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2661                         clock-names = "xo";
2662
2663                         power-domains = <&rpmhpd SM8250_LCX>,
2664                                         <&rpmhpd SM8250_LMX>;
2665                         power-domain-names = "lcx", "lmx";
2666
2667                         memory-region = <&slpi_mem>;
2668
2669                         qcom,qmp = <&aoss_qmp>;
2670
2671                         qcom,smem-states = <&smp2p_slpi_out 0>;
2672                         qcom,smem-state-names = "stop";
2673
2674                         status = "disabled";
2675
2676                         glink-edge {
2677                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2678                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2679                                                              IRQ_TYPE_EDGE_RISING>;
2680                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2681                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2682
2683                                 label = "slpi";
2684                                 qcom,remote-pid = <3>;
2685
2686                                 fastrpc {
2687                                         compatible = "qcom,fastrpc";
2688                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2689                                         label = "sdsp";
2690                                         qcom,non-secure-domain;
2691                                         #address-cells = <1>;
2692                                         #size-cells = <0>;
2693
2694                                         compute-cb@1 {
2695                                                 compatible = "qcom,fastrpc-compute-cb";
2696                                                 reg = <1>;
2697                                                 iommus = <&apps_smmu 0x0541 0x0>;
2698                                         };
2699
2700                                         compute-cb@2 {
2701                                                 compatible = "qcom,fastrpc-compute-cb";
2702                                                 reg = <2>;
2703                                                 iommus = <&apps_smmu 0x0542 0x0>;
2704                                         };
2705
2706                                         compute-cb@3 {
2707                                                 compatible = "qcom,fastrpc-compute-cb";
2708                                                 reg = <3>;
2709                                                 iommus = <&apps_smmu 0x0543 0x0>;
2710                                                 /* note: shared-cb = <4> in downstream */
2711                                         };
2712                                 };
2713                         };
2714                 };
2715
2716                 cdsp: remoteproc@8300000 {
2717                         compatible = "qcom,sm8250-cdsp-pas";
2718                         reg = <0 0x08300000 0 0x10000>;
2719
2720                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2721                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2722                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2723                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2724                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2725                         interrupt-names = "wdog", "fatal", "ready",
2726                                           "handover", "stop-ack";
2727
2728                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2729                         clock-names = "xo";
2730
2731                         power-domains = <&rpmhpd SM8250_CX>;
2732
2733                         memory-region = <&cdsp_mem>;
2734
2735                         qcom,qmp = <&aoss_qmp>;
2736
2737                         qcom,smem-states = <&smp2p_cdsp_out 0>;
2738                         qcom,smem-state-names = "stop";
2739
2740                         status = "disabled";
2741
2742                         glink-edge {
2743                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2744                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2745                                                              IRQ_TYPE_EDGE_RISING>;
2746                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2747                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2748
2749                                 label = "cdsp";
2750                                 qcom,remote-pid = <5>;
2751
2752                                 fastrpc {
2753                                         compatible = "qcom,fastrpc";
2754                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2755                                         label = "cdsp";
2756                                         qcom,non-secure-domain;
2757                                         #address-cells = <1>;
2758                                         #size-cells = <0>;
2759
2760                                         compute-cb@1 {
2761                                                 compatible = "qcom,fastrpc-compute-cb";
2762                                                 reg = <1>;
2763                                                 iommus = <&apps_smmu 0x1001 0x0460>;
2764                                         };
2765
2766                                         compute-cb@2 {
2767                                                 compatible = "qcom,fastrpc-compute-cb";
2768                                                 reg = <2>;
2769                                                 iommus = <&apps_smmu 0x1002 0x0460>;
2770                                         };
2771
2772                                         compute-cb@3 {
2773                                                 compatible = "qcom,fastrpc-compute-cb";
2774                                                 reg = <3>;
2775                                                 iommus = <&apps_smmu 0x1003 0x0460>;
2776                                         };
2777
2778                                         compute-cb@4 {
2779                                                 compatible = "qcom,fastrpc-compute-cb";
2780                                                 reg = <4>;
2781                                                 iommus = <&apps_smmu 0x1004 0x0460>;
2782                                         };
2783
2784                                         compute-cb@5 {
2785                                                 compatible = "qcom,fastrpc-compute-cb";
2786                                                 reg = <5>;
2787                                                 iommus = <&apps_smmu 0x1005 0x0460>;
2788                                         };
2789
2790                                         compute-cb@6 {
2791                                                 compatible = "qcom,fastrpc-compute-cb";
2792                                                 reg = <6>;
2793                                                 iommus = <&apps_smmu 0x1006 0x0460>;
2794                                         };
2795
2796                                         compute-cb@7 {
2797                                                 compatible = "qcom,fastrpc-compute-cb";
2798                                                 reg = <7>;
2799                                                 iommus = <&apps_smmu 0x1007 0x0460>;
2800                                         };
2801
2802                                         compute-cb@8 {
2803                                                 compatible = "qcom,fastrpc-compute-cb";
2804                                                 reg = <8>;
2805                                                 iommus = <&apps_smmu 0x1008 0x0460>;
2806                                         };
2807
2808                                         /* note: secure cb9 in downstream */
2809                                 };
2810                         };
2811                 };
2812
2813                 sound: sound {
2814                 };
2815
2816                 usb_1_hsphy: phy@88e3000 {
2817                         compatible = "qcom,sm8250-usb-hs-phy",
2818                                      "qcom,usb-snps-hs-7nm-phy";
2819                         reg = <0 0x088e3000 0 0x400>;
2820                         status = "disabled";
2821                         #phy-cells = <0>;
2822
2823                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2824                         clock-names = "ref";
2825
2826                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2827                 };
2828
2829                 usb_2_hsphy: phy@88e4000 {
2830                         compatible = "qcom,sm8250-usb-hs-phy",
2831                                      "qcom,usb-snps-hs-7nm-phy";
2832                         reg = <0 0x088e4000 0 0x400>;
2833                         status = "disabled";
2834                         #phy-cells = <0>;
2835
2836                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2837                         clock-names = "ref";
2838
2839                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2840                 };
2841
2842                 usb_1_qmpphy: phy@88e9000 {
2843                         compatible = "qcom,sm8250-qmp-usb3-dp-phy";
2844                         reg = <0 0x088e9000 0 0x200>,
2845                               <0 0x088e8000 0 0x40>,
2846                               <0 0x088ea000 0 0x200>;
2847                         status = "disabled";
2848                         #address-cells = <2>;
2849                         #size-cells = <2>;
2850                         ranges;
2851
2852                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2853                                  <&rpmhcc RPMH_CXO_CLK>,
2854                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2855                         clock-names = "aux", "ref_clk_src", "com_aux";
2856
2857                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2858                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2859                         reset-names = "phy", "common";
2860
2861                         usb_1_ssphy: usb3-phy@88e9200 {
2862                                 reg = <0 0x088e9200 0 0x200>,
2863                                       <0 0x088e9400 0 0x200>,
2864                                       <0 0x088e9c00 0 0x400>,
2865                                       <0 0x088e9600 0 0x200>,
2866                                       <0 0x088e9800 0 0x200>,
2867                                       <0 0x088e9a00 0 0x100>;
2868                                 #clock-cells = <0>;
2869                                 #phy-cells = <0>;
2870                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2871                                 clock-names = "pipe0";
2872                                 clock-output-names = "usb3_phy_pipe_clk_src";
2873                         };
2874
2875                         dp_phy: dp-phy@88ea200 {
2876                                 reg = <0 0x088ea200 0 0x200>,
2877                                       <0 0x088ea400 0 0x200>,
2878                                       <0 0x088eac00 0 0x400>,
2879                                       <0 0x088ea600 0 0x200>,
2880                                       <0 0x088ea800 0 0x200>,
2881                                       <0 0x088eaa00 0 0x100>;
2882                                 #phy-cells = <0>;
2883                                 #clock-cells = <1>;
2884                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2885                                 clock-names = "pipe0";
2886                                 clock-output-names = "usb3_phy_pipe_clk_src";
2887                         };
2888                 };
2889
2890                 usb_2_qmpphy: phy@88eb000 {
2891                         compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2892                         reg = <0 0x088eb000 0 0x200>;
2893                         status = "disabled";
2894                         #address-cells = <2>;
2895                         #size-cells = <2>;
2896                         ranges;
2897
2898                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2899                                  <&rpmhcc RPMH_CXO_CLK>,
2900                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
2901                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2902                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2903
2904                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2905                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2906                         reset-names = "phy", "common";
2907
2908                         usb_2_ssphy: phy@88eb200 {
2909                                 reg = <0 0x088eb200 0 0x200>,
2910                                       <0 0x088eb400 0 0x200>,
2911                                       <0 0x088eb800 0 0x800>;
2912                                 #clock-cells = <0>;
2913                                 #phy-cells = <0>;
2914                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2915                                 clock-names = "pipe0";
2916                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2917                         };
2918                 };
2919
2920                 sdhc_2: sdhci@8804000 {
2921                         compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2922                         reg = <0 0x08804000 0 0x1000>;
2923
2924                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2925                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2926                         interrupt-names = "hc_irq", "pwr_irq";
2927
2928                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2929                                  <&gcc GCC_SDCC2_APPS_CLK>,
2930                                  <&rpmhcc RPMH_CXO_CLK>;
2931                         clock-names = "iface", "core", "xo";
2932                         iommus = <&apps_smmu 0x4a0 0x0>;
2933                         qcom,dll-config = <0x0007642c>;
2934                         qcom,ddr-config = <0x80040868>;
2935                         power-domains = <&rpmhpd SM8250_CX>;
2936                         operating-points-v2 = <&sdhc2_opp_table>;
2937
2938                         status = "disabled";
2939
2940                         sdhc2_opp_table: sdhc2-opp-table {
2941                                 compatible = "operating-points-v2";
2942
2943                                 opp-19200000 {
2944                                         opp-hz = /bits/ 64 <19200000>;
2945                                         required-opps = <&rpmhpd_opp_min_svs>;
2946                                 };
2947
2948                                 opp-50000000 {
2949                                         opp-hz = /bits/ 64 <50000000>;
2950                                         required-opps = <&rpmhpd_opp_low_svs>;
2951                                 };
2952
2953                                 opp-100000000 {
2954                                         opp-hz = /bits/ 64 <100000000>;
2955                                         required-opps = <&rpmhpd_opp_svs>;
2956                                 };
2957
2958                                 opp-202000000 {
2959                                         opp-hz = /bits/ 64 <202000000>;
2960                                         required-opps = <&rpmhpd_opp_svs_l1>;
2961                                 };
2962                         };
2963                 };
2964
2965                 dc_noc: interconnect@90c0000 {
2966                         compatible = "qcom,sm8250-dc-noc";
2967                         reg = <0 0x090c0000 0 0x4200>;
2968                         #interconnect-cells = <1>;
2969                         qcom,bcm-voters = <&apps_bcm_voter>;
2970                 };
2971
2972                 gem_noc: interconnect@9100000 {
2973                         compatible = "qcom,sm8250-gem-noc";
2974                         reg = <0 0x09100000 0 0xb4000>;
2975                         #interconnect-cells = <1>;
2976                         qcom,bcm-voters = <&apps_bcm_voter>;
2977                 };
2978
2979                 npu_noc: interconnect@9990000 {
2980                         compatible = "qcom,sm8250-npu-noc";
2981                         reg = <0 0x09990000 0 0x1600>;
2982                         #interconnect-cells = <1>;
2983                         qcom,bcm-voters = <&apps_bcm_voter>;
2984                 };
2985
2986                 usb_1: usb@a6f8800 {
2987                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2988                         reg = <0 0x0a6f8800 0 0x400>;
2989                         status = "disabled";
2990                         #address-cells = <2>;
2991                         #size-cells = <2>;
2992                         ranges;
2993                         dma-ranges;
2994
2995                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2996                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2997                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2998                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2999                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3000                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
3001                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3002                                       "sleep", "xo";
3003
3004                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3005                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3006                         assigned-clock-rates = <19200000>, <200000000>;
3007
3008                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3009                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3010                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3011                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
3012                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
3013                                           "dm_hs_phy_irq", "ss_phy_irq";
3014
3015                         power-domains = <&gcc USB30_PRIM_GDSC>;
3016
3017                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3018
3019                         usb_1_dwc3: usb@a600000 {
3020                                 compatible = "snps,dwc3";
3021                                 reg = <0 0x0a600000 0 0xcd00>;
3022                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3023                                 iommus = <&apps_smmu 0x0 0x0>;
3024                                 snps,dis_u2_susphy_quirk;
3025                                 snps,dis_enblslpm_quirk;
3026                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3027                                 phy-names = "usb2-phy", "usb3-phy";
3028                         };
3029                 };
3030
3031                 system-cache-controller@9200000 {
3032                         compatible = "qcom,sm8250-llcc";
3033                         reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
3034                         reg-names = "llcc_base", "llcc_broadcast_base";
3035                 };
3036
3037                 usb_2: usb@a8f8800 {
3038                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3039                         reg = <0 0x0a8f8800 0 0x400>;
3040                         status = "disabled";
3041                         #address-cells = <2>;
3042                         #size-cells = <2>;
3043                         ranges;
3044                         dma-ranges;
3045
3046                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3047                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3048                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3049                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3050                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3051                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
3052                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3053                                       "sleep", "xo";
3054
3055                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3056                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3057                         assigned-clock-rates = <19200000>, <200000000>;
3058
3059                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3060                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3061                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3062                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
3063                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
3064                                           "dm_hs_phy_irq", "ss_phy_irq";
3065
3066                         power-domains = <&gcc USB30_SEC_GDSC>;
3067
3068                         resets = <&gcc GCC_USB30_SEC_BCR>;
3069
3070                         usb_2_dwc3: usb@a800000 {
3071                                 compatible = "snps,dwc3";
3072                                 reg = <0 0x0a800000 0 0xcd00>;
3073                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3074                                 iommus = <&apps_smmu 0x20 0>;
3075                                 snps,dis_u2_susphy_quirk;
3076                                 snps,dis_enblslpm_quirk;
3077                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3078                                 phy-names = "usb2-phy", "usb3-phy";
3079                         };
3080                 };
3081
3082                 venus: video-codec@aa00000 {
3083                         compatible = "qcom,sm8250-venus";
3084                         reg = <0 0x0aa00000 0 0x100000>;
3085                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3086                         power-domains = <&videocc MVS0C_GDSC>,
3087                                         <&videocc MVS0_GDSC>,
3088                                         <&rpmhpd SM8250_MX>;
3089                         power-domain-names = "venus", "vcodec0", "mx";
3090                         operating-points-v2 = <&venus_opp_table>;
3091
3092                         clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
3093                                  <&videocc VIDEO_CC_MVS0C_CLK>,
3094                                  <&videocc VIDEO_CC_MVS0_CLK>;
3095                         clock-names = "iface", "core", "vcodec0_core";
3096
3097                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
3098                                         <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
3099                         interconnect-names = "cpu-cfg", "video-mem";
3100
3101                         iommus = <&apps_smmu 0x2100 0x0400>;
3102                         memory-region = <&video_mem>;
3103
3104                         resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
3105                                  <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
3106                         reset-names = "bus", "core";
3107
3108                         status = "disabled";
3109
3110                         video-decoder {
3111                                 compatible = "venus-decoder";
3112                         };
3113
3114                         video-encoder {
3115                                 compatible = "venus-encoder";
3116                         };
3117
3118                         venus_opp_table: venus-opp-table {
3119                                 compatible = "operating-points-v2";
3120
3121                                 opp-720000000 {
3122                                         opp-hz = /bits/ 64 <720000000>;
3123                                         required-opps = <&rpmhpd_opp_low_svs>;
3124                                 };
3125
3126                                 opp-1014000000 {
3127                                         opp-hz = /bits/ 64 <1014000000>;
3128                                         required-opps = <&rpmhpd_opp_svs>;
3129                                 };
3130
3131                                 opp-1098000000 {
3132                                         opp-hz = /bits/ 64 <1098000000>;
3133                                         required-opps = <&rpmhpd_opp_svs_l1>;
3134                                 };
3135
3136                                 opp-1332000000 {
3137                                         opp-hz = /bits/ 64 <1332000000>;
3138                                         required-opps = <&rpmhpd_opp_nom>;
3139                                 };
3140                         };
3141                 };
3142
3143                 videocc: clock-controller@abf0000 {
3144                         compatible = "qcom,sm8250-videocc";
3145                         reg = <0 0x0abf0000 0 0x10000>;
3146                         clocks = <&gcc GCC_VIDEO_AHB_CLK>,
3147                                  <&rpmhcc RPMH_CXO_CLK>,
3148                                  <&rpmhcc RPMH_CXO_CLK_A>;
3149                         power-domains = <&rpmhpd SM8250_MMCX>;
3150                         required-opps = <&rpmhpd_opp_low_svs>;
3151                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
3152                         #clock-cells = <1>;
3153                         #reset-cells = <1>;
3154                         #power-domain-cells = <1>;
3155                 };
3156
3157                 cci0: cci@ac4f000 {
3158                         compatible = "qcom,sm8250-cci";
3159                         #address-cells = <1>;
3160                         #size-cells = <0>;
3161
3162                         reg = <0 0x0ac4f000 0 0x1000>;
3163                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3164                         power-domains = <&camcc TITAN_TOP_GDSC>;
3165
3166                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3167                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3168                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3169                                  <&camcc CAM_CC_CCI_0_CLK>,
3170                                  <&camcc CAM_CC_CCI_0_CLK_SRC>;
3171                         clock-names = "camnoc_axi",
3172                                       "slow_ahb_src",
3173                                       "cpas_ahb",
3174                                       "cci",
3175                                       "cci_src";
3176
3177                         pinctrl-0 = <&cci0_default>;
3178                         pinctrl-1 = <&cci0_sleep>;
3179                         pinctrl-names = "default", "sleep";
3180
3181                         status = "disabled";
3182
3183                         cci0_i2c0: i2c-bus@0 {
3184                                 reg = <0>;
3185                                 clock-frequency = <1000000>;
3186                                 #address-cells = <1>;
3187                                 #size-cells = <0>;
3188                         };
3189
3190                         cci0_i2c1: i2c-bus@1 {
3191                                 reg = <1>;
3192                                 clock-frequency = <1000000>;
3193                                 #address-cells = <1>;
3194                                 #size-cells = <0>;
3195                         };
3196                 };
3197
3198                 cci1: cci@ac50000 {
3199                         compatible = "qcom,sm8250-cci";
3200                         #address-cells = <1>;
3201                         #size-cells = <0>;
3202
3203                         reg = <0 0x0ac50000 0 0x1000>;
3204                         interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
3205                         power-domains = <&camcc TITAN_TOP_GDSC>;
3206
3207                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3208                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3209                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3210                                  <&camcc CAM_CC_CCI_1_CLK>,
3211                                  <&camcc CAM_CC_CCI_1_CLK_SRC>;
3212                         clock-names = "camnoc_axi",
3213                                       "slow_ahb_src",
3214                                       "cpas_ahb",
3215                                       "cci",
3216                                       "cci_src";
3217
3218                         pinctrl-0 = <&cci1_default>;
3219                         pinctrl-1 = <&cci1_sleep>;
3220                         pinctrl-names = "default", "sleep";
3221
3222                         status = "disabled";
3223
3224                         cci1_i2c0: i2c-bus@0 {
3225                                 reg = <0>;
3226                                 clock-frequency = <1000000>;
3227                                 #address-cells = <1>;
3228                                 #size-cells = <0>;
3229                         };
3230
3231                         cci1_i2c1: i2c-bus@1 {
3232                                 reg = <1>;
3233                                 clock-frequency = <1000000>;
3234                                 #address-cells = <1>;
3235                                 #size-cells = <0>;
3236                         };
3237                 };
3238
3239                 camss: camss@ac6a000 {
3240                         compatible = "qcom,sm8250-camss";
3241                         status = "disabled";
3242
3243                         reg = <0 0xac6a000 0 0x2000>,
3244                               <0 0xac6c000 0 0x2000>,
3245                               <0 0xac6e000 0 0x1000>,
3246                               <0 0xac70000 0 0x1000>,
3247                               <0 0xac72000 0 0x1000>,
3248                               <0 0xac74000 0 0x1000>,
3249                               <0 0xacb4000 0 0xd000>,
3250                               <0 0xacc3000 0 0xd000>,
3251                               <0 0xacd9000 0 0x2200>,
3252                               <0 0xacdb200 0 0x2200>;
3253                         reg-names = "csiphy0",
3254                                     "csiphy1",
3255                                     "csiphy2",
3256                                     "csiphy3",
3257                                     "csiphy4",
3258                                     "csiphy5",
3259                                     "vfe0",
3260                                     "vfe1",
3261                                     "vfe_lite0",
3262                                     "vfe_lite1";
3263
3264                         interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3265                                      <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3266                                      <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3267                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3268                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
3269                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
3270                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3271                                      <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3272                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3273                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
3274                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3275                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3276                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
3277                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
3278                         interrupt-names = "csiphy0",
3279                                           "csiphy1",
3280                                           "csiphy2",
3281                                           "csiphy3",
3282                                           "csiphy4",
3283                                           "csiphy5",
3284                                           "csid0",
3285                                           "csid1",
3286                                           "csid2",
3287                                           "csid3",
3288                                           "vfe0",
3289                                           "vfe1",
3290                                           "vfe_lite0",
3291                                           "vfe_lite1";
3292
3293                         power-domains = <&camcc IFE_0_GDSC>,
3294                                         <&camcc IFE_1_GDSC>,
3295                                         <&camcc TITAN_TOP_GDSC>;
3296
3297                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3298                                  <&gcc GCC_CAMERA_HF_AXI_CLK>,
3299                                  <&gcc GCC_CAMERA_SF_AXI_CLK>,
3300                                  <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3301                                  <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
3302                                  <&camcc CAM_CC_CORE_AHB_CLK>,
3303                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3304                                  <&camcc CAM_CC_CSIPHY0_CLK>,
3305                                  <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
3306                                  <&camcc CAM_CC_CSIPHY1_CLK>,
3307                                  <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
3308                                  <&camcc CAM_CC_CSIPHY2_CLK>,
3309                                  <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
3310                                  <&camcc CAM_CC_CSIPHY3_CLK>,
3311                                  <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
3312                                  <&camcc CAM_CC_CSIPHY4_CLK>,
3313                                  <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
3314                                  <&camcc CAM_CC_CSIPHY5_CLK>,
3315                                  <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
3316                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3317                                  <&camcc CAM_CC_IFE_0_AHB_CLK>,
3318                                  <&camcc CAM_CC_IFE_0_AXI_CLK>,
3319                                  <&camcc CAM_CC_IFE_0_CLK>,
3320                                  <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
3321                                  <&camcc CAM_CC_IFE_0_CSID_CLK>,
3322                                  <&camcc CAM_CC_IFE_0_AREG_CLK>,
3323                                  <&camcc CAM_CC_IFE_1_AHB_CLK>,
3324                                  <&camcc CAM_CC_IFE_1_AXI_CLK>,
3325                                  <&camcc CAM_CC_IFE_1_CLK>,
3326                                  <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
3327                                  <&camcc CAM_CC_IFE_1_CSID_CLK>,
3328                                  <&camcc CAM_CC_IFE_1_AREG_CLK>,
3329                                  <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
3330                                  <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
3331                                  <&camcc CAM_CC_IFE_LITE_CLK>,
3332                                  <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
3333                                  <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
3334
3335                         clock-names = "cam_ahb_clk",
3336                                       "cam_hf_axi",
3337                                       "cam_sf_axi",
3338                                       "camnoc_axi",
3339                                       "camnoc_axi_src",
3340                                       "core_ahb",
3341                                       "cpas_ahb",
3342                                       "csiphy0",
3343                                       "csiphy0_timer",
3344                                       "csiphy1",
3345                                       "csiphy1_timer",
3346                                       "csiphy2",
3347                                       "csiphy2_timer",
3348                                       "csiphy3",
3349                                       "csiphy3_timer",
3350                                       "csiphy4",
3351                                       "csiphy4_timer",
3352                                       "csiphy5",
3353                                       "csiphy5_timer",
3354                                       "slow_ahb_src",
3355                                       "vfe0_ahb",
3356                                       "vfe0_axi",
3357                                       "vfe0",
3358                                       "vfe0_cphy_rx",
3359                                       "vfe0_csid",
3360                                       "vfe0_areg",
3361                                       "vfe1_ahb",
3362                                       "vfe1_axi",
3363                                       "vfe1",
3364                                       "vfe1_cphy_rx",
3365                                       "vfe1_csid",
3366                                       "vfe1_areg",
3367                                       "vfe_lite_ahb",
3368                                       "vfe_lite_axi",
3369                                       "vfe_lite",
3370                                       "vfe_lite_cphy_rx",
3371                                       "vfe_lite_csid";
3372
3373                         iommus = <&apps_smmu 0x800 0x400>,
3374                                  <&apps_smmu 0x801 0x400>,
3375                                  <&apps_smmu 0x840 0x400>,
3376                                  <&apps_smmu 0x841 0x400>,
3377                                  <&apps_smmu 0xc00 0x400>,
3378                                  <&apps_smmu 0xc01 0x400>,
3379                                  <&apps_smmu 0xc40 0x400>,
3380                                  <&apps_smmu 0xc41 0x400>;
3381
3382                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
3383                                         <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
3384                                         <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
3385                                         <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
3386                         interconnect-names = "cam_ahb",
3387                                              "cam_hf_0_mnoc",
3388                                              "cam_sf_0_mnoc",
3389                                              "cam_sf_icp_mnoc";
3390                 };
3391
3392                 camcc: clock-controller@ad00000 {
3393                         compatible = "qcom,sm8250-camcc";
3394                         reg = <0 0x0ad00000 0 0x10000>;
3395                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3396                                  <&rpmhcc RPMH_CXO_CLK>,
3397                                  <&rpmhcc RPMH_CXO_CLK_A>,
3398                                  <&sleep_clk>;
3399                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3400                         power-domains = <&rpmhpd SM8250_MMCX>;
3401                         required-opps = <&rpmhpd_opp_low_svs>;
3402                         #clock-cells = <1>;
3403                         #reset-cells = <1>;
3404                         #power-domain-cells = <1>;
3405                 };
3406
3407                 mdss: mdss@ae00000 {
3408                         compatible = "qcom,sm8250-mdss";
3409                         reg = <0 0x0ae00000 0 0x1000>;
3410                         reg-names = "mdss";
3411
3412                         interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
3413                                         <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
3414                         interconnect-names = "mdp0-mem", "mdp1-mem";
3415
3416                         power-domains = <&dispcc MDSS_GDSC>;
3417
3418                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3419                                  <&gcc GCC_DISP_HF_AXI_CLK>,
3420                                  <&gcc GCC_DISP_SF_AXI_CLK>,
3421                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
3422                         clock-names = "iface", "bus", "nrt_bus", "core";
3423
3424                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
3425                         assigned-clock-rates = <460000000>;
3426
3427                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3428                         interrupt-controller;
3429                         #interrupt-cells = <1>;
3430
3431                         iommus = <&apps_smmu 0x820 0x402>;
3432
3433                         status = "disabled";
3434
3435                         #address-cells = <2>;
3436                         #size-cells = <2>;
3437                         ranges;
3438
3439                         mdss_mdp: mdp@ae01000 {
3440                                 compatible = "qcom,sm8250-dpu";
3441                                 reg = <0 0x0ae01000 0 0x8f000>,
3442                                       <0 0x0aeb0000 0 0x2008>;
3443                                 reg-names = "mdp", "vbif";
3444
3445                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3446                                          <&gcc GCC_DISP_HF_AXI_CLK>,
3447                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3448                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3449                                 clock-names = "iface", "bus", "core", "vsync";
3450
3451                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
3452                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3453                                 assigned-clock-rates = <460000000>,
3454                                                        <19200000>;
3455
3456                                 operating-points-v2 = <&mdp_opp_table>;
3457                                 power-domains = <&rpmhpd SM8250_MMCX>;
3458
3459                                 interrupt-parent = <&mdss>;
3460                                 interrupts = <0>;
3461
3462                                 ports {
3463                                         #address-cells = <1>;
3464                                         #size-cells = <0>;
3465
3466                                         port@0 {
3467                                                 reg = <0>;
3468                                                 dpu_intf1_out: endpoint {
3469                                                         remote-endpoint = <&dsi0_in>;
3470                                                 };
3471                                         };
3472
3473                                         port@1 {
3474                                                 reg = <1>;
3475                                                 dpu_intf2_out: endpoint {
3476                                                         remote-endpoint = <&dsi1_in>;
3477                                                 };
3478                                         };
3479                                 };
3480
3481                                 mdp_opp_table: mdp-opp-table {
3482                                         compatible = "operating-points-v2";
3483
3484                                         opp-200000000 {
3485                                                 opp-hz = /bits/ 64 <200000000>;
3486                                                 required-opps = <&rpmhpd_opp_low_svs>;
3487                                         };
3488
3489                                         opp-300000000 {
3490                                                 opp-hz = /bits/ 64 <300000000>;
3491                                                 required-opps = <&rpmhpd_opp_svs>;
3492                                         };
3493
3494                                         opp-345000000 {
3495                                                 opp-hz = /bits/ 64 <345000000>;
3496                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3497                                         };
3498
3499                                         opp-460000000 {
3500                                                 opp-hz = /bits/ 64 <460000000>;
3501                                                 required-opps = <&rpmhpd_opp_nom>;
3502                                         };
3503                                 };
3504                         };
3505
3506                         dsi0: dsi@ae94000 {
3507                                 compatible = "qcom,mdss-dsi-ctrl";
3508                                 reg = <0 0x0ae94000 0 0x400>;
3509                                 reg-names = "dsi_ctrl";
3510
3511                                 interrupt-parent = <&mdss>;
3512                                 interrupts = <4>;
3513
3514                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3515                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3516                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3517                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3518                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3519                                         <&gcc GCC_DISP_HF_AXI_CLK>;
3520                                 clock-names = "byte",
3521                                               "byte_intf",
3522                                               "pixel",
3523                                               "core",
3524                                               "iface",
3525                                               "bus";
3526
3527                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3528                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
3529
3530                                 operating-points-v2 = <&dsi_opp_table>;
3531                                 power-domains = <&rpmhpd SM8250_MMCX>;
3532
3533                                 phys = <&dsi0_phy>;
3534                                 phy-names = "dsi";
3535
3536                                 status = "disabled";
3537
3538                                 #address-cells = <1>;
3539                                 #size-cells = <0>;
3540
3541                                 ports {
3542                                         #address-cells = <1>;
3543                                         #size-cells = <0>;
3544
3545                                         port@0 {
3546                                                 reg = <0>;
3547                                                 dsi0_in: endpoint {
3548                                                         remote-endpoint = <&dpu_intf1_out>;
3549                                                 };
3550                                         };
3551
3552                                         port@1 {
3553                                                 reg = <1>;
3554                                                 dsi0_out: endpoint {
3555                                                 };
3556                                         };
3557                                 };
3558                         };
3559
3560                         dsi0_phy: dsi-phy@ae94400 {
3561                                 compatible = "qcom,dsi-phy-7nm";
3562                                 reg = <0 0x0ae94400 0 0x200>,
3563                                       <0 0x0ae94600 0 0x280>,
3564                                       <0 0x0ae94900 0 0x260>;
3565                                 reg-names = "dsi_phy",
3566                                             "dsi_phy_lane",
3567                                             "dsi_pll";
3568
3569                                 #clock-cells = <1>;
3570                                 #phy-cells = <0>;
3571
3572                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3573                                          <&rpmhcc RPMH_CXO_CLK>;
3574                                 clock-names = "iface", "ref";
3575
3576                                 status = "disabled";
3577                         };
3578
3579                         dsi1: dsi@ae96000 {
3580                                 compatible = "qcom,mdss-dsi-ctrl";
3581                                 reg = <0 0x0ae96000 0 0x400>;
3582                                 reg-names = "dsi_ctrl";
3583
3584                                 interrupt-parent = <&mdss>;
3585                                 interrupts = <5>;
3586
3587                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3588                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3589                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3590                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3591                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3592                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3593                                 clock-names = "byte",
3594                                               "byte_intf",
3595                                               "pixel",
3596                                               "core",
3597                                               "iface",
3598                                               "bus";
3599
3600                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3601                                 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
3602
3603                                 operating-points-v2 = <&dsi_opp_table>;
3604                                 power-domains = <&rpmhpd SM8250_MMCX>;
3605
3606                                 phys = <&dsi1_phy>;
3607                                 phy-names = "dsi";
3608
3609                                 status = "disabled";
3610
3611                                 #address-cells = <1>;
3612                                 #size-cells = <0>;
3613
3614                                 ports {
3615                                         #address-cells = <1>;
3616                                         #size-cells = <0>;
3617
3618                                         port@0 {
3619                                                 reg = <0>;
3620                                                 dsi1_in: endpoint {
3621                                                         remote-endpoint = <&dpu_intf2_out>;
3622                                                 };
3623                                         };
3624
3625                                         port@1 {
3626                                                 reg = <1>;
3627                                                 dsi1_out: endpoint {
3628                                                 };
3629                                         };
3630                                 };
3631                         };
3632
3633                         dsi1_phy: dsi-phy@ae96400 {
3634                                 compatible = "qcom,dsi-phy-7nm";
3635                                 reg = <0 0x0ae96400 0 0x200>,
3636                                       <0 0x0ae96600 0 0x280>,
3637                                       <0 0x0ae96900 0 0x260>;
3638                                 reg-names = "dsi_phy",
3639                                             "dsi_phy_lane",
3640                                             "dsi_pll";
3641
3642                                 #clock-cells = <1>;
3643                                 #phy-cells = <0>;
3644
3645                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3646                                          <&rpmhcc RPMH_CXO_CLK>;
3647                                 clock-names = "iface", "ref";
3648
3649                                 status = "disabled";
3650
3651                                 dsi_opp_table: dsi-opp-table {
3652                                         compatible = "operating-points-v2";
3653
3654                                         opp-187500000 {
3655                                                 opp-hz = /bits/ 64 <187500000>;
3656                                                 required-opps = <&rpmhpd_opp_low_svs>;
3657                                         };
3658
3659                                         opp-300000000 {
3660                                                 opp-hz = /bits/ 64 <300000000>;
3661                                                 required-opps = <&rpmhpd_opp_svs>;
3662                                         };
3663
3664                                         opp-358000000 {
3665                                                 opp-hz = /bits/ 64 <358000000>;
3666                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3667                                         };
3668                                 };
3669                         };
3670                 };
3671
3672                 dispcc: clock-controller@af00000 {
3673                         compatible = "qcom,sm8250-dispcc";
3674                         reg = <0 0x0af00000 0 0x10000>;
3675                         power-domains = <&rpmhpd SM8250_MMCX>;
3676                         required-opps = <&rpmhpd_opp_low_svs>;
3677                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3678                                  <&dsi0_phy 0>,
3679                                  <&dsi0_phy 1>,
3680                                  <&dsi1_phy 0>,
3681                                  <&dsi1_phy 1>,
3682                                  <&dp_phy 0>,
3683                                  <&dp_phy 1>;
3684                         clock-names = "bi_tcxo",
3685                                       "dsi0_phy_pll_out_byteclk",
3686                                       "dsi0_phy_pll_out_dsiclk",
3687                                       "dsi1_phy_pll_out_byteclk",
3688                                       "dsi1_phy_pll_out_dsiclk",
3689                                       "dp_phy_pll_link_clk",
3690                                       "dp_phy_pll_vco_div_clk";
3691                         #clock-cells = <1>;
3692                         #reset-cells = <1>;
3693                         #power-domain-cells = <1>;
3694                 };
3695
3696                 pdc: interrupt-controller@b220000 {
3697                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
3698                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
3699                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3700                                           <125 63 1>, <126 716 12>;
3701                         #interrupt-cells = <2>;
3702                         interrupt-parent = <&intc>;
3703                         interrupt-controller;
3704                 };
3705
3706                 tsens0: thermal-sensor@c263000 {
3707                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
3708                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3709                               <0 0x0c222000 0 0x1ff>; /* SROT */
3710                         #qcom,sensors = <16>;
3711                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3712                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3713                         interrupt-names = "uplow", "critical";
3714                         #thermal-sensor-cells = <1>;
3715                 };
3716
3717                 tsens1: thermal-sensor@c265000 {
3718                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
3719                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3720                               <0 0x0c223000 0 0x1ff>; /* SROT */
3721                         #qcom,sensors = <9>;
3722                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3723                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3724                         interrupt-names = "uplow", "critical";
3725                         #thermal-sensor-cells = <1>;
3726                 };
3727
3728                 aoss_qmp: power-controller@c300000 {
3729                         compatible = "qcom,sm8250-aoss-qmp";
3730                         reg = <0 0x0c300000 0 0x400>;
3731                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
3732                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
3733                                                      IRQ_TYPE_EDGE_RISING>;
3734                         mboxes = <&ipcc IPCC_CLIENT_AOP
3735                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
3736
3737                         #clock-cells = <0>;
3738                 };
3739
3740                 sram@c3f0000 {
3741                         compatible = "qcom,rpmh-stats";
3742                         reg = <0 0x0c3f0000 0 0x400>;
3743                 };
3744
3745                 spmi_bus: spmi@c440000 {
3746                         compatible = "qcom,spmi-pmic-arb";
3747                         reg = <0x0 0x0c440000 0x0 0x0001100>,
3748                               <0x0 0x0c600000 0x0 0x2000000>,
3749                               <0x0 0x0e600000 0x0 0x0100000>,
3750                               <0x0 0x0e700000 0x0 0x00a0000>,
3751                               <0x0 0x0c40a000 0x0 0x0026000>;
3752                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3753                         interrupt-names = "periph_irq";
3754                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3755                         qcom,ee = <0>;
3756                         qcom,channel = <0>;
3757                         #address-cells = <2>;
3758                         #size-cells = <0>;
3759                         interrupt-controller;
3760                         #interrupt-cells = <4>;
3761                 };
3762
3763                 tlmm: pinctrl@f100000 {
3764                         compatible = "qcom,sm8250-pinctrl";
3765                         reg = <0 0x0f100000 0 0x300000>,
3766                               <0 0x0f500000 0 0x300000>,
3767                               <0 0x0f900000 0 0x300000>;
3768                         reg-names = "west", "south", "north";
3769                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3770                         gpio-controller;
3771                         #gpio-cells = <2>;
3772                         interrupt-controller;
3773                         #interrupt-cells = <2>;
3774                         gpio-ranges = <&tlmm 0 0 181>;
3775                         wakeup-parent = <&pdc>;
3776
3777                         cci0_default: cci0-default {
3778                                 cci0_i2c0_default: cci0-i2c0-default {
3779                                         /* SDA, SCL */
3780                                         pins = "gpio101", "gpio102";
3781                                         function = "cci_i2c";
3782
3783                                         bias-pull-up;
3784                                         drive-strength = <2>; /* 2 mA */
3785                                 };
3786
3787                                 cci0_i2c1_default: cci0-i2c1-default {
3788                                         /* SDA, SCL */
3789                                         pins = "gpio103", "gpio104";
3790                                         function = "cci_i2c";
3791
3792                                         bias-pull-up;
3793                                         drive-strength = <2>; /* 2 mA */
3794                                 };
3795                         };
3796
3797                         cci0_sleep: cci0-sleep {
3798                                 cci0_i2c0_sleep: cci0-i2c0-sleep {
3799                                         /* SDA, SCL */
3800                                         pins = "gpio101", "gpio102";
3801                                         function = "cci_i2c";
3802
3803                                         drive-strength = <2>; /* 2 mA */
3804                                         bias-pull-down;
3805                                 };
3806
3807                                 cci0_i2c1_sleep: cci0-i2c1-sleep {
3808                                         /* SDA, SCL */
3809                                         pins = "gpio103", "gpio104";
3810                                         function = "cci_i2c";
3811
3812                                         drive-strength = <2>; /* 2 mA */
3813                                         bias-pull-down;
3814                                 };
3815                         };
3816
3817                         cci1_default: cci1-default {
3818                                 cci1_i2c0_default: cci1-i2c0-default {
3819                                         /* SDA, SCL */
3820                                         pins = "gpio105","gpio106";
3821                                         function = "cci_i2c";
3822
3823                                         bias-pull-up;
3824                                         drive-strength = <2>; /* 2 mA */
3825                                 };
3826
3827                                 cci1_i2c1_default: cci1-i2c1-default {
3828                                         /* SDA, SCL */
3829                                         pins = "gpio107","gpio108";
3830                                         function = "cci_i2c";
3831
3832                                         bias-pull-up;
3833                                         drive-strength = <2>; /* 2 mA */
3834                                 };
3835                         };
3836
3837                         cci1_sleep: cci1-sleep {
3838                                 cci1_i2c0_sleep: cci1-i2c0-sleep {
3839                                         /* SDA, SCL */
3840                                         pins = "gpio105","gpio106";
3841                                         function = "cci_i2c";
3842
3843                                         bias-pull-down;
3844                                         drive-strength = <2>; /* 2 mA */
3845                                 };
3846
3847                                 cci1_i2c1_sleep: cci1-i2c1-sleep {
3848                                         /* SDA, SCL */
3849                                         pins = "gpio107","gpio108";
3850                                         function = "cci_i2c";
3851
3852                                         bias-pull-down;
3853                                         drive-strength = <2>; /* 2 mA */
3854                                 };
3855                         };
3856
3857                         pri_mi2s_active: pri-mi2s-active {
3858                                 sclk {
3859                                         pins = "gpio138";
3860                                         function = "mi2s0_sck";
3861                                         drive-strength = <8>;
3862                                         bias-disable;
3863                                 };
3864
3865                                 ws {
3866                                         pins = "gpio141";
3867                                         function = "mi2s0_ws";
3868                                         drive-strength = <8>;
3869                                         output-high;
3870                                 };
3871
3872                                 data0 {
3873                                         pins = "gpio139";
3874                                         function = "mi2s0_data0";
3875                                         drive-strength = <8>;
3876                                         bias-disable;
3877                                         output-high;
3878                                 };
3879
3880                                 data1 {
3881                                         pins = "gpio140";
3882                                         function = "mi2s0_data1";
3883                                         drive-strength = <8>;
3884                                         output-high;
3885                                 };
3886                         };
3887
3888                         qup_i2c0_default: qup-i2c0-default {
3889                                 mux {
3890                                         pins = "gpio28", "gpio29";
3891                                         function = "qup0";
3892                                 };
3893
3894                                 config {
3895                                         pins = "gpio28", "gpio29";
3896                                         drive-strength = <2>;
3897                                         bias-disable;
3898                                 };
3899                         };
3900
3901                         qup_i2c1_default: qup-i2c1-default {
3902                                 pinmux {
3903                                         pins = "gpio4", "gpio5";
3904                                         function = "qup1";
3905                                 };
3906
3907                                 config {
3908                                         pins = "gpio4", "gpio5";
3909                                         drive-strength = <2>;
3910                                         bias-disable;
3911                                 };
3912                         };
3913
3914                         qup_i2c2_default: qup-i2c2-default {
3915                                 mux {
3916                                         pins = "gpio115", "gpio116";
3917                                         function = "qup2";
3918                                 };
3919
3920                                 config {
3921                                         pins = "gpio115", "gpio116";
3922                                         drive-strength = <2>;
3923                                         bias-disable;
3924                                 };
3925                         };
3926
3927                         qup_i2c3_default: qup-i2c3-default {
3928                                 mux {
3929                                         pins = "gpio119", "gpio120";
3930                                         function = "qup3";
3931                                 };
3932
3933                                 config {
3934                                         pins = "gpio119", "gpio120";
3935                                         drive-strength = <2>;
3936                                         bias-disable;
3937                                 };
3938                         };
3939
3940                         qup_i2c4_default: qup-i2c4-default {
3941                                 mux {
3942                                         pins = "gpio8", "gpio9";
3943                                         function = "qup4";
3944                                 };
3945
3946                                 config {
3947                                         pins = "gpio8", "gpio9";
3948                                         drive-strength = <2>;
3949                                         bias-disable;
3950                                 };
3951                         };
3952
3953                         qup_i2c5_default: qup-i2c5-default {
3954                                 mux {
3955                                         pins = "gpio12", "gpio13";
3956                                         function = "qup5";
3957                                 };
3958
3959                                 config {
3960                                         pins = "gpio12", "gpio13";
3961                                         drive-strength = <2>;
3962                                         bias-disable;
3963                                 };
3964                         };
3965
3966                         qup_i2c6_default: qup-i2c6-default {
3967                                 mux {
3968                                         pins = "gpio16", "gpio17";
3969                                         function = "qup6";
3970                                 };
3971
3972                                 config {
3973                                         pins = "gpio16", "gpio17";
3974                                         drive-strength = <2>;
3975                                         bias-disable;
3976                                 };
3977                         };
3978
3979                         qup_i2c7_default: qup-i2c7-default {
3980                                 mux {
3981                                         pins = "gpio20", "gpio21";
3982                                         function = "qup7";
3983                                 };
3984
3985                                 config {
3986                                         pins = "gpio20", "gpio21";
3987                                         drive-strength = <2>;
3988                                         bias-disable;
3989                                 };
3990                         };
3991
3992                         qup_i2c8_default: qup-i2c8-default {
3993                                 mux {
3994                                         pins = "gpio24", "gpio25";
3995                                         function = "qup8";
3996                                 };
3997
3998                                 config {
3999                                         pins = "gpio24", "gpio25";
4000                                         drive-strength = <2>;
4001                                         bias-disable;
4002                                 };
4003                         };
4004
4005                         qup_i2c9_default: qup-i2c9-default {
4006                                 mux {
4007                                         pins = "gpio125", "gpio126";
4008                                         function = "qup9";
4009                                 };
4010
4011                                 config {
4012                                         pins = "gpio125", "gpio126";
4013                                         drive-strength = <2>;
4014                                         bias-disable;
4015                                 };
4016                         };
4017
4018                         qup_i2c10_default: qup-i2c10-default {
4019                                 mux {
4020                                         pins = "gpio129", "gpio130";
4021                                         function = "qup10";
4022                                 };
4023
4024                                 config {
4025                                         pins = "gpio129", "gpio130";
4026                                         drive-strength = <2>;
4027                                         bias-disable;
4028                                 };
4029                         };
4030
4031                         qup_i2c11_default: qup-i2c11-default {
4032                                 mux {
4033                                         pins = "gpio60", "gpio61";
4034                                         function = "qup11";
4035                                 };
4036
4037                                 config {
4038                                         pins = "gpio60", "gpio61";
4039                                         drive-strength = <2>;
4040                                         bias-disable;
4041                                 };
4042                         };
4043
4044                         qup_i2c12_default: qup-i2c12-default {
4045                                 mux {
4046                                         pins = "gpio32", "gpio33";
4047                                         function = "qup12";
4048                                 };
4049
4050                                 config {
4051                                         pins = "gpio32", "gpio33";
4052                                         drive-strength = <2>;
4053                                         bias-disable;
4054                                 };
4055                         };
4056
4057                         qup_i2c13_default: qup-i2c13-default {
4058                                 mux {
4059                                         pins = "gpio36", "gpio37";
4060                                         function = "qup13";
4061                                 };
4062
4063                                 config {
4064                                         pins = "gpio36", "gpio37";
4065                                         drive-strength = <2>;
4066                                         bias-disable;
4067                                 };
4068                         };
4069
4070                         qup_i2c14_default: qup-i2c14-default {
4071                                 mux {
4072                                         pins = "gpio40", "gpio41";
4073                                         function = "qup14";
4074                                 };
4075
4076                                 config {
4077                                         pins = "gpio40", "gpio41";
4078                                         drive-strength = <2>;
4079                                         bias-disable;
4080                                 };
4081                         };
4082
4083                         qup_i2c15_default: qup-i2c15-default {
4084                                 mux {
4085                                         pins = "gpio44", "gpio45";
4086                                         function = "qup15";
4087                                 };
4088
4089                                 config {
4090                                         pins = "gpio44", "gpio45";
4091                                         drive-strength = <2>;
4092                                         bias-disable;
4093                                 };
4094                         };
4095
4096                         qup_i2c16_default: qup-i2c16-default {
4097                                 mux {
4098                                         pins = "gpio48", "gpio49";
4099                                         function = "qup16";
4100                                 };
4101
4102                                 config {
4103                                         pins = "gpio48", "gpio49";
4104                                         drive-strength = <2>;
4105                                         bias-disable;
4106                                 };
4107                         };
4108
4109                         qup_i2c17_default: qup-i2c17-default {
4110                                 mux {
4111                                         pins = "gpio52", "gpio53";
4112                                         function = "qup17";
4113                                 };
4114
4115                                 config {
4116                                         pins = "gpio52", "gpio53";
4117                                         drive-strength = <2>;
4118                                         bias-disable;
4119                                 };
4120                         };
4121
4122                         qup_i2c18_default: qup-i2c18-default {
4123                                 mux {
4124                                         pins = "gpio56", "gpio57";
4125                                         function = "qup18";
4126                                 };
4127
4128                                 config {
4129                                         pins = "gpio56", "gpio57";
4130                                         drive-strength = <2>;
4131                                         bias-disable;
4132                                 };
4133                         };
4134
4135                         qup_i2c19_default: qup-i2c19-default {
4136                                 mux {
4137                                         pins = "gpio0", "gpio1";
4138                                         function = "qup19";
4139                                 };
4140
4141                                 config {
4142                                         pins = "gpio0", "gpio1";
4143                                         drive-strength = <2>;
4144                                         bias-disable;
4145                                 };
4146                         };
4147
4148                         qup_spi0_cs: qup-spi0-cs {
4149                                 pins = "gpio31";
4150                                 function = "qup0";
4151                         };
4152
4153                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
4154                                 pins = "gpio31";
4155                                 function = "gpio";
4156                         };
4157
4158                         qup_spi0_data_clk: qup-spi0-data-clk {
4159                                 pins = "gpio28", "gpio29",
4160                                        "gpio30";
4161                                 function = "qup0";
4162                         };
4163
4164                         qup_spi1_cs: qup-spi1-cs {
4165                                 pins = "gpio7";
4166                                 function = "qup1";
4167                         };
4168
4169                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
4170                                 pins = "gpio7";
4171                                 function = "gpio";
4172                         };
4173
4174                         qup_spi1_data_clk: qup-spi1-data-clk {
4175                                 pins = "gpio4", "gpio5",
4176                                        "gpio6";
4177                                 function = "qup1";
4178                         };
4179
4180                         qup_spi2_cs: qup-spi2-cs {
4181                                 pins = "gpio118";
4182                                 function = "qup2";
4183                         };
4184
4185                         qup_spi2_cs_gpio: qup-spi2-cs-gpio {
4186                                 pins = "gpio118";
4187                                 function = "gpio";
4188                         };
4189
4190                         qup_spi2_data_clk: qup-spi2-data-clk {
4191                                 pins = "gpio115", "gpio116",
4192                                        "gpio117";
4193                                 function = "qup2";
4194                         };
4195
4196                         qup_spi3_cs: qup-spi3-cs {
4197                                 pins = "gpio122";
4198                                 function = "qup3";
4199                         };
4200
4201                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
4202                                 pins = "gpio122";
4203                                 function = "gpio";
4204                         };
4205
4206                         qup_spi3_data_clk: qup-spi3-data-clk {
4207                                 pins = "gpio119", "gpio120",
4208                                        "gpio121";
4209                                 function = "qup3";
4210                         };
4211
4212                         qup_spi4_cs: qup-spi4-cs {
4213                                 pins = "gpio11";
4214                                 function = "qup4";
4215                         };
4216
4217                         qup_spi4_cs_gpio: qup-spi4-cs-gpio {
4218                                 pins = "gpio11";
4219                                 function = "gpio";
4220                         };
4221
4222                         qup_spi4_data_clk: qup-spi4-data-clk {
4223                                 pins = "gpio8", "gpio9",
4224                                        "gpio10";
4225                                 function = "qup4";
4226                         };
4227
4228                         qup_spi5_cs: qup-spi5-cs {
4229                                 pins = "gpio15";
4230                                 function = "qup5";
4231                         };
4232
4233                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
4234                                 pins = "gpio15";
4235                                 function = "gpio";
4236                         };
4237
4238                         qup_spi5_data_clk: qup-spi5-data-clk {
4239                                 pins = "gpio12", "gpio13",
4240                                        "gpio14";
4241                                 function = "qup5";
4242                         };
4243
4244                         qup_spi6_cs: qup-spi6-cs {
4245                                 pins = "gpio19";
4246                                 function = "qup6";
4247                         };
4248
4249                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
4250                                 pins = "gpio19";
4251                                 function = "gpio";
4252                         };
4253
4254                         qup_spi6_data_clk: qup-spi6-data-clk {
4255                                 pins = "gpio16", "gpio17",
4256                                        "gpio18";
4257                                 function = "qup6";
4258                         };
4259
4260                         qup_spi7_cs: qup-spi7-cs {
4261                                 pins = "gpio23";
4262                                 function = "qup7";
4263                         };
4264
4265                         qup_spi7_cs_gpio: qup-spi7-cs-gpio {
4266                                 pins = "gpio23";
4267                                 function = "gpio";
4268                         };
4269
4270                         qup_spi7_data_clk: qup-spi7-data-clk {
4271                                 pins = "gpio20", "gpio21",
4272                                        "gpio22";
4273                                 function = "qup7";
4274                         };
4275
4276                         qup_spi8_cs: qup-spi8-cs {
4277                                 pins = "gpio27";
4278                                 function = "qup8";
4279                         };
4280
4281                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
4282                                 pins = "gpio27";
4283                                 function = "gpio";
4284                         };
4285
4286                         qup_spi8_data_clk: qup-spi8-data-clk {
4287                                 pins = "gpio24", "gpio25",
4288                                        "gpio26";
4289                                 function = "qup8";
4290                         };
4291
4292                         qup_spi9_cs: qup-spi9-cs {
4293                                 pins = "gpio128";
4294                                 function = "qup9";
4295                         };
4296
4297                         qup_spi9_cs_gpio: qup-spi9-cs-gpio {
4298                                 pins = "gpio128";
4299                                 function = "gpio";
4300                         };
4301
4302                         qup_spi9_data_clk: qup-spi9-data-clk {
4303                                 pins = "gpio125", "gpio126",
4304                                        "gpio127";
4305                                 function = "qup9";
4306                         };
4307
4308                         qup_spi10_cs: qup-spi10-cs {
4309                                 pins = "gpio132";
4310                                 function = "qup10";
4311                         };
4312
4313                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
4314                                 pins = "gpio132";
4315                                 function = "gpio";
4316                         };
4317
4318                         qup_spi10_data_clk: qup-spi10-data-clk {
4319                                 pins = "gpio129", "gpio130",
4320                                        "gpio131";
4321                                 function = "qup10";
4322                         };
4323
4324                         qup_spi11_cs: qup-spi11-cs {
4325                                 pins = "gpio63";
4326                                 function = "qup11";
4327                         };
4328
4329                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
4330                                 pins = "gpio63";
4331                                 function = "gpio";
4332                         };
4333
4334                         qup_spi11_data_clk: qup-spi11-data-clk {
4335                                 pins = "gpio60", "gpio61",
4336                                        "gpio62";
4337                                 function = "qup11";
4338                         };
4339
4340                         qup_spi12_cs: qup-spi12-cs {
4341                                 pins = "gpio35";
4342                                 function = "qup12";
4343                         };
4344
4345                         qup_spi12_cs_gpio: qup-spi12-cs-gpio {
4346                                 pins = "gpio35";
4347                                 function = "gpio";
4348                         };
4349
4350                         qup_spi12_data_clk: qup-spi12-data-clk {
4351                                 pins = "gpio32", "gpio33",
4352                                        "gpio34";
4353                                 function = "qup12";
4354                         };
4355
4356                         qup_spi13_cs: qup-spi13-cs {
4357                                 pins = "gpio39";
4358                                 function = "qup13";
4359                         };
4360
4361                         qup_spi13_cs_gpio: qup-spi13-cs-gpio {
4362                                 pins = "gpio39";
4363                                 function = "gpio";
4364                         };
4365
4366                         qup_spi13_data_clk: qup-spi13-data-clk {
4367                                 pins = "gpio36", "gpio37",
4368                                        "gpio38";
4369                                 function = "qup13";
4370                         };
4371
4372                         qup_spi14_cs: qup-spi14-cs {
4373                                 pins = "gpio43";
4374                                 function = "qup14";
4375                         };
4376
4377                         qup_spi14_cs_gpio: qup-spi14-cs-gpio {
4378                                 pins = "gpio43";
4379                                 function = "gpio";
4380                         };
4381
4382                         qup_spi14_data_clk: qup-spi14-data-clk {
4383                                 pins = "gpio40", "gpio41",
4384                                        "gpio42";
4385                                 function = "qup14";
4386                         };
4387
4388                         qup_spi15_cs: qup-spi15-cs {
4389                                 pins = "gpio47";
4390                                 function = "qup15";
4391                         };
4392
4393                         qup_spi15_cs_gpio: qup-spi15-cs-gpio {
4394                                 pins = "gpio47";
4395                                 function = "gpio";
4396                         };
4397
4398                         qup_spi15_data_clk: qup-spi15-data-clk {
4399                                 pins = "gpio44", "gpio45",
4400                                        "gpio46";
4401                                 function = "qup15";
4402                         };
4403
4404                         qup_spi16_cs: qup-spi16-cs {
4405                                 pins = "gpio51";
4406                                 function = "qup16";
4407                         };
4408
4409                         qup_spi16_cs_gpio: qup-spi16-cs-gpio {
4410                                 pins = "gpio51";
4411                                 function = "gpio";
4412                         };
4413
4414                         qup_spi16_data_clk: qup-spi16-data-clk {
4415                                 pins = "gpio48", "gpio49",
4416                                        "gpio50";
4417                                 function = "qup16";
4418                         };
4419
4420                         qup_spi17_cs: qup-spi17-cs {
4421                                 pins = "gpio55";
4422                                 function = "qup17";
4423                         };
4424
4425                         qup_spi17_cs_gpio: qup-spi17-cs-gpio {
4426                                 pins = "gpio55";
4427                                 function = "gpio";
4428                         };
4429
4430                         qup_spi17_data_clk: qup-spi17-data-clk {
4431                                 pins = "gpio52", "gpio53",
4432                                        "gpio54";
4433                                 function = "qup17";
4434                         };
4435
4436                         qup_spi18_cs: qup-spi18-cs {
4437                                 pins = "gpio59";
4438                                 function = "qup18";
4439                         };
4440
4441                         qup_spi18_cs_gpio: qup-spi18-cs-gpio {
4442                                 pins = "gpio59";
4443                                 function = "gpio";
4444                         };
4445
4446                         qup_spi18_data_clk: qup-spi18-data-clk {
4447                                 pins = "gpio56", "gpio57",
4448                                        "gpio58";
4449                                 function = "qup18";
4450                         };
4451
4452                         qup_spi19_cs: qup-spi19-cs {
4453                                 pins = "gpio3";
4454                                 function = "qup19";
4455                         };
4456
4457                         qup_spi19_cs_gpio: qup-spi19-cs-gpio {
4458                                 pins = "gpio3";
4459                                 function = "gpio";
4460                         };
4461
4462                         qup_spi19_data_clk: qup-spi19-data-clk {
4463                                 pins = "gpio0", "gpio1",
4464                                        "gpio2";
4465                                 function = "qup19";
4466                         };
4467
4468                         qup_uart2_default: qup-uart2-default {
4469                                 mux {
4470                                         pins = "gpio117", "gpio118";
4471                                         function = "qup2";
4472                                 };
4473                         };
4474
4475                         qup_uart6_default: qup-uart6-default {
4476                                 mux {
4477                                         pins = "gpio16", "gpio17",
4478                                                 "gpio18", "gpio19";
4479                                         function = "qup6";
4480                                 };
4481                         };
4482
4483                         qup_uart12_default: qup-uart12-default {
4484                                 mux {
4485                                         pins = "gpio34", "gpio35";
4486                                         function = "qup12";
4487                                 };
4488                         };
4489
4490                         qup_uart17_default: qup-uart17-default {
4491                                 mux {
4492                                         pins = "gpio52", "gpio53",
4493                                                 "gpio54", "gpio55";
4494                                         function = "qup17";
4495                                 };
4496                         };
4497
4498                         qup_uart18_default: qup-uart18-default {
4499                                 mux {
4500                                         pins = "gpio58", "gpio59";
4501                                         function = "qup18";
4502                                 };
4503                         };
4504
4505                         tert_mi2s_active: tert-mi2s-active {
4506                                 sck {
4507                                         pins = "gpio133";
4508                                         function = "mi2s2_sck";
4509                                         drive-strength = <8>;
4510                                         bias-disable;
4511                                 };
4512
4513                                 data0 {
4514                                         pins = "gpio134";
4515                                         function = "mi2s2_data0";
4516                                         drive-strength = <8>;
4517                                         bias-disable;
4518                                         output-high;
4519                                 };
4520
4521                                 ws {
4522                                         pins = "gpio135";
4523                                         function = "mi2s2_ws";
4524                                         drive-strength = <8>;
4525                                         output-high;
4526                                 };
4527                         };
4528
4529                         sdc2_sleep_state: sdc2-sleep {
4530                                 clk {
4531                                         pins = "sdc2_clk";
4532                                         drive-strength = <2>;
4533                                         bias-disable;
4534                                 };
4535
4536                                 cmd {
4537                                         pins = "sdc2_cmd";
4538                                         drive-strength = <2>;
4539                                         bias-pull-up;
4540                                 };
4541
4542                                 data {
4543                                         pins = "sdc2_data";
4544                                         drive-strength = <2>;
4545                                         bias-pull-up;
4546                                 };
4547                         };
4548
4549                         pcie0_default_state: pcie0-default {
4550                                 perst {
4551                                         pins = "gpio79";
4552                                         function = "gpio";
4553                                         drive-strength = <2>;
4554                                         bias-pull-down;
4555                                 };
4556
4557                                 clkreq {
4558                                         pins = "gpio80";
4559                                         function = "pci_e0";
4560                                         drive-strength = <2>;
4561                                         bias-pull-up;
4562                                 };
4563
4564                                 wake {
4565                                         pins = "gpio81";
4566                                         function = "gpio";
4567                                         drive-strength = <2>;
4568                                         bias-pull-up;
4569                                 };
4570                         };
4571
4572                         pcie1_default_state: pcie1-default {
4573                                 perst {
4574                                         pins = "gpio82";
4575                                         function = "gpio";
4576                                         drive-strength = <2>;
4577                                         bias-pull-down;
4578                                 };
4579
4580                                 clkreq {
4581                                         pins = "gpio83";
4582                                         function = "pci_e1";
4583                                         drive-strength = <2>;
4584                                         bias-pull-up;
4585                                 };
4586
4587                                 wake {
4588                                         pins = "gpio84";
4589                                         function = "gpio";
4590                                         drive-strength = <2>;
4591                                         bias-pull-up;
4592                                 };
4593                         };
4594
4595                         pcie2_default_state: pcie2-default {
4596                                 perst {
4597                                         pins = "gpio85";
4598                                         function = "gpio";
4599                                         drive-strength = <2>;
4600                                         bias-pull-down;
4601                                 };
4602
4603                                 clkreq {
4604                                         pins = "gpio86";
4605                                         function = "pci_e2";
4606                                         drive-strength = <2>;
4607                                         bias-pull-up;
4608                                 };
4609
4610                                 wake {
4611                                         pins = "gpio87";
4612                                         function = "gpio";
4613                                         drive-strength = <2>;
4614                                         bias-pull-up;
4615                                 };
4616                         };
4617                 };
4618
4619                 apps_smmu: iommu@15000000 {
4620                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
4621                         reg = <0 0x15000000 0 0x100000>;
4622                         #iommu-cells = <2>;
4623                         #global-interrupts = <2>;
4624                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4625                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4626                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4627                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4628                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4629                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4630                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4631                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4632                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4633                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4634                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4635                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4636                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4637                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4638                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4639                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4640                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4641                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4642                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4643                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4644                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4645                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4646                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4647                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4648                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4649                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4650                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4651                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4652                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4653                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4654                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4655                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4656                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4657                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4658                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4659                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4660                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4661                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4662                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4663                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4664                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4665                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4666                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4667                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4668                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4669                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4670                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4671                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4672                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4673                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4674                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4675                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4676                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4677                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4678                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4679                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4680                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4681                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4682                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4683                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4684                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4685                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4686                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4687                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4688                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4689                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4690                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4691                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4692                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4693                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4694                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4695                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4696                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4697                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4698                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4699                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4700                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4701                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4702                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4703                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4704                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4705                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4706                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4707                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4708                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4709                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4710                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4711                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4712                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4713                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4714                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4715                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4716                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4717                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4718                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4719                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4720                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
4721                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
4722                 };
4723
4724                 adsp: remoteproc@17300000 {
4725                         compatible = "qcom,sm8250-adsp-pas";
4726                         reg = <0 0x17300000 0 0x100>;
4727
4728                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
4729                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4730                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
4731                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
4732                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
4733                         interrupt-names = "wdog", "fatal", "ready",
4734                                           "handover", "stop-ack";
4735
4736                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4737                         clock-names = "xo";
4738
4739                         power-domains = <&rpmhpd SM8250_LCX>,
4740                                         <&rpmhpd SM8250_LMX>;
4741                         power-domain-names = "lcx", "lmx";
4742
4743                         memory-region = <&adsp_mem>;
4744
4745                         qcom,qmp = <&aoss_qmp>;
4746
4747                         qcom,smem-states = <&smp2p_adsp_out 0>;
4748                         qcom,smem-state-names = "stop";
4749
4750                         status = "disabled";
4751
4752                         glink-edge {
4753                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4754                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4755                                                              IRQ_TYPE_EDGE_RISING>;
4756                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
4757                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4758
4759                                 label = "lpass";
4760                                 qcom,remote-pid = <2>;
4761
4762                                 apr {
4763                                         compatible = "qcom,apr-v2";
4764                                         qcom,glink-channels = "apr_audio_svc";
4765                                         qcom,domain = <APR_DOMAIN_ADSP>;
4766                                         #address-cells = <1>;
4767                                         #size-cells = <0>;
4768
4769                                         apr-service@3 {
4770                                                 reg = <APR_SVC_ADSP_CORE>;
4771                                                 compatible = "qcom,q6core";
4772                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4773                                         };
4774
4775                                         q6afe: apr-service@4 {
4776                                                 compatible = "qcom,q6afe";
4777                                                 reg = <APR_SVC_AFE>;
4778                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4779                                                 q6afedai: dais {
4780                                                         compatible = "qcom,q6afe-dais";
4781                                                         #address-cells = <1>;
4782                                                         #size-cells = <0>;
4783                                                         #sound-dai-cells = <1>;
4784                                                 };
4785
4786                                                 q6afecc: cc {
4787                                                         compatible = "qcom,q6afe-clocks";
4788                                                         #clock-cells = <2>;
4789                                                 };
4790                                         };
4791
4792                                         q6asm: apr-service@7 {
4793                                                 compatible = "qcom,q6asm";
4794                                                 reg = <APR_SVC_ASM>;
4795                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4796                                                 q6asmdai: dais {
4797                                                         compatible = "qcom,q6asm-dais";
4798                                                         #address-cells = <1>;
4799                                                         #size-cells = <0>;
4800                                                         #sound-dai-cells = <1>;
4801                                                         iommus = <&apps_smmu 0x1801 0x0>;
4802                                                 };
4803                                         };
4804
4805                                         q6adm: apr-service@8 {
4806                                                 compatible = "qcom,q6adm";
4807                                                 reg = <APR_SVC_ADM>;
4808                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4809                                                 q6routing: routing {
4810                                                         compatible = "qcom,q6adm-routing";
4811                                                         #sound-dai-cells = <0>;
4812                                                 };
4813                                         };
4814                                 };
4815
4816                                 fastrpc {
4817                                         compatible = "qcom,fastrpc";
4818                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4819                                         label = "adsp";
4820                                         qcom,non-secure-domain;
4821                                         #address-cells = <1>;
4822                                         #size-cells = <0>;
4823
4824                                         compute-cb@3 {
4825                                                 compatible = "qcom,fastrpc-compute-cb";
4826                                                 reg = <3>;
4827                                                 iommus = <&apps_smmu 0x1803 0x0>;
4828                                         };
4829
4830                                         compute-cb@4 {
4831                                                 compatible = "qcom,fastrpc-compute-cb";
4832                                                 reg = <4>;
4833                                                 iommus = <&apps_smmu 0x1804 0x0>;
4834                                         };
4835
4836                                         compute-cb@5 {
4837                                                 compatible = "qcom,fastrpc-compute-cb";
4838                                                 reg = <5>;
4839                                                 iommus = <&apps_smmu 0x1805 0x0>;
4840                                         };
4841                                 };
4842                         };
4843                 };
4844
4845                 intc: interrupt-controller@17a00000 {
4846                         compatible = "arm,gic-v3";
4847                         #interrupt-cells = <3>;
4848                         interrupt-controller;
4849                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
4850                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
4851                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4852                 };
4853
4854                 watchdog@17c10000 {
4855                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
4856                         reg = <0 0x17c10000 0 0x1000>;
4857                         clocks = <&sleep_clk>;
4858                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4859                 };
4860
4861                 timer@17c20000 {
4862                         #address-cells = <2>;
4863                         #size-cells = <2>;
4864                         ranges;
4865                         compatible = "arm,armv7-timer-mem";
4866                         reg = <0x0 0x17c20000 0x0 0x1000>;
4867                         clock-frequency = <19200000>;
4868
4869                         frame@17c21000 {
4870                                 frame-number = <0>;
4871                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4872                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4873                                 reg = <0x0 0x17c21000 0x0 0x1000>,
4874                                       <0x0 0x17c22000 0x0 0x1000>;
4875                         };
4876
4877                         frame@17c23000 {
4878                                 frame-number = <1>;
4879                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4880                                 reg = <0x0 0x17c23000 0x0 0x1000>;
4881                                 status = "disabled";
4882                         };
4883
4884                         frame@17c25000 {
4885                                 frame-number = <2>;
4886                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4887                                 reg = <0x0 0x17c25000 0x0 0x1000>;
4888                                 status = "disabled";
4889                         };
4890
4891                         frame@17c27000 {
4892                                 frame-number = <3>;
4893                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4894                                 reg = <0x0 0x17c27000 0x0 0x1000>;
4895                                 status = "disabled";
4896                         };
4897
4898                         frame@17c29000 {
4899                                 frame-number = <4>;
4900                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4901                                 reg = <0x0 0x17c29000 0x0 0x1000>;
4902                                 status = "disabled";
4903                         };
4904
4905                         frame@17c2b000 {
4906                                 frame-number = <5>;
4907                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4908                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
4909                                 status = "disabled";
4910                         };
4911
4912                         frame@17c2d000 {
4913                                 frame-number = <6>;
4914                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4915                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
4916                                 status = "disabled";
4917                         };
4918                 };
4919
4920                 apps_rsc: rsc@18200000 {
4921                         label = "apps_rsc";
4922                         compatible = "qcom,rpmh-rsc";
4923                         reg = <0x0 0x18200000 0x0 0x10000>,
4924                                 <0x0 0x18210000 0x0 0x10000>,
4925                                 <0x0 0x18220000 0x0 0x10000>;
4926                         reg-names = "drv-0", "drv-1", "drv-2";
4927                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4928                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4929                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4930                         qcom,tcs-offset = <0xd00>;
4931                         qcom,drv-id = <2>;
4932                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
4933                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
4934
4935                         rpmhcc: clock-controller {
4936                                 compatible = "qcom,sm8250-rpmh-clk";
4937                                 #clock-cells = <1>;
4938                                 clock-names = "xo";
4939                                 clocks = <&xo_board>;
4940                         };
4941
4942                         rpmhpd: power-controller {
4943                                 compatible = "qcom,sm8250-rpmhpd";
4944                                 #power-domain-cells = <1>;
4945                                 operating-points-v2 = <&rpmhpd_opp_table>;
4946
4947                                 rpmhpd_opp_table: opp-table {
4948                                         compatible = "operating-points-v2";
4949
4950                                         rpmhpd_opp_ret: opp1 {
4951                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4952                                         };
4953
4954                                         rpmhpd_opp_min_svs: opp2 {
4955                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4956                                         };
4957
4958                                         rpmhpd_opp_low_svs: opp3 {
4959                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4960                                         };
4961
4962                                         rpmhpd_opp_svs: opp4 {
4963                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4964                                         };
4965
4966                                         rpmhpd_opp_svs_l1: opp5 {
4967                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4968                                         };
4969
4970                                         rpmhpd_opp_nom: opp6 {
4971                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4972                                         };
4973
4974                                         rpmhpd_opp_nom_l1: opp7 {
4975                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4976                                         };
4977
4978                                         rpmhpd_opp_nom_l2: opp8 {
4979                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4980                                         };
4981
4982                                         rpmhpd_opp_turbo: opp9 {
4983                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4984                                         };
4985
4986                                         rpmhpd_opp_turbo_l1: opp10 {
4987                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4988                                         };
4989                                 };
4990                         };
4991
4992                         apps_bcm_voter: bcm-voter {
4993                                 compatible = "qcom,bcm-voter";
4994                         };
4995                 };
4996
4997                 epss_l3: interconnect@18590000 {
4998                         compatible = "qcom,sm8250-epss-l3";
4999                         reg = <0 0x18590000 0 0x1000>;
5000
5001                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5002                         clock-names = "xo", "alternate";
5003
5004                         #interconnect-cells = <1>;
5005                 };
5006
5007                 cpufreq_hw: cpufreq@18591000 {
5008                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
5009                         reg = <0 0x18591000 0 0x1000>,
5010                               <0 0x18592000 0 0x1000>,
5011                               <0 0x18593000 0 0x1000>;
5012                         reg-names = "freq-domain0", "freq-domain1",
5013                                     "freq-domain2";
5014
5015                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5016                         clock-names = "xo", "alternate";
5017                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
5018                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5019                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5020                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5021                         #freq-domain-cells = <1>;
5022                 };
5023         };
5024
5025         timer {
5026                 compatible = "arm,armv8-timer";
5027                 interrupts = <GIC_PPI 13
5028                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5029                              <GIC_PPI 14
5030                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5031                              <GIC_PPI 11
5032                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5033                              <GIC_PPI 10
5034                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5035         };
5036
5037         thermal-zones {
5038                 cpu0-thermal {
5039                         polling-delay-passive = <250>;
5040                         polling-delay = <1000>;
5041
5042                         thermal-sensors = <&tsens0 1>;
5043
5044                         trips {
5045                                 cpu0_alert0: trip-point0 {
5046                                         temperature = <90000>;
5047                                         hysteresis = <2000>;
5048                                         type = "passive";
5049                                 };
5050
5051                                 cpu0_alert1: trip-point1 {
5052                                         temperature = <95000>;
5053                                         hysteresis = <2000>;
5054                                         type = "passive";
5055                                 };
5056
5057                                 cpu0_crit: cpu_crit {
5058                                         temperature = <110000>;
5059                                         hysteresis = <1000>;
5060                                         type = "critical";
5061                                 };
5062                         };
5063
5064                         cooling-maps {
5065                                 map0 {
5066                                         trip = <&cpu0_alert0>;
5067                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071                                 };
5072                                 map1 {
5073                                         trip = <&cpu0_alert1>;
5074                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078                                 };
5079                         };
5080                 };
5081
5082                 cpu1-thermal {
5083                         polling-delay-passive = <250>;
5084                         polling-delay = <1000>;
5085
5086                         thermal-sensors = <&tsens0 2>;
5087
5088                         trips {
5089                                 cpu1_alert0: trip-point0 {
5090                                         temperature = <90000>;
5091                                         hysteresis = <2000>;
5092                                         type = "passive";
5093                                 };
5094
5095                                 cpu1_alert1: trip-point1 {
5096                                         temperature = <95000>;
5097                                         hysteresis = <2000>;
5098                                         type = "passive";
5099                                 };
5100
5101                                 cpu1_crit: cpu_crit {
5102                                         temperature = <110000>;
5103                                         hysteresis = <1000>;
5104                                         type = "critical";
5105                                 };
5106                         };
5107
5108                         cooling-maps {
5109                                 map0 {
5110                                         trip = <&cpu1_alert0>;
5111                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5114                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5115                                 };
5116                                 map1 {
5117                                         trip = <&cpu1_alert1>;
5118                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5121                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5122                                 };
5123                         };
5124                 };
5125
5126                 cpu2-thermal {
5127                         polling-delay-passive = <250>;
5128                         polling-delay = <1000>;
5129
5130                         thermal-sensors = <&tsens0 3>;
5131
5132                         trips {
5133                                 cpu2_alert0: trip-point0 {
5134                                         temperature = <90000>;
5135                                         hysteresis = <2000>;
5136                                         type = "passive";
5137                                 };
5138
5139                                 cpu2_alert1: trip-point1 {
5140                                         temperature = <95000>;
5141                                         hysteresis = <2000>;
5142                                         type = "passive";
5143                                 };
5144
5145                                 cpu2_crit: cpu_crit {
5146                                         temperature = <110000>;
5147                                         hysteresis = <1000>;
5148                                         type = "critical";
5149                                 };
5150                         };
5151
5152                         cooling-maps {
5153                                 map0 {
5154                                         trip = <&cpu2_alert0>;
5155                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5156                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5157                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5158                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5159                                 };
5160                                 map1 {
5161                                         trip = <&cpu2_alert1>;
5162                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5163                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5164                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5165                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5166                                 };
5167                         };
5168                 };
5169
5170                 cpu3-thermal {
5171                         polling-delay-passive = <250>;
5172                         polling-delay = <1000>;
5173
5174                         thermal-sensors = <&tsens0 4>;
5175
5176                         trips {
5177                                 cpu3_alert0: trip-point0 {
5178                                         temperature = <90000>;
5179                                         hysteresis = <2000>;
5180                                         type = "passive";
5181                                 };
5182
5183                                 cpu3_alert1: trip-point1 {
5184                                         temperature = <95000>;
5185                                         hysteresis = <2000>;
5186                                         type = "passive";
5187                                 };
5188
5189                                 cpu3_crit: cpu_crit {
5190                                         temperature = <110000>;
5191                                         hysteresis = <1000>;
5192                                         type = "critical";
5193                                 };
5194                         };
5195
5196                         cooling-maps {
5197                                 map0 {
5198                                         trip = <&cpu3_alert0>;
5199                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5200                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5201                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5202                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5203                                 };
5204                                 map1 {
5205                                         trip = <&cpu3_alert1>;
5206                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5207                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5208                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5209                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5210                                 };
5211                         };
5212                 };
5213
5214                 cpu4-top-thermal {
5215                         polling-delay-passive = <250>;
5216                         polling-delay = <1000>;
5217
5218                         thermal-sensors = <&tsens0 7>;
5219
5220                         trips {
5221                                 cpu4_top_alert0: trip-point0 {
5222                                         temperature = <90000>;
5223                                         hysteresis = <2000>;
5224                                         type = "passive";
5225                                 };
5226
5227                                 cpu4_top_alert1: trip-point1 {
5228                                         temperature = <95000>;
5229                                         hysteresis = <2000>;
5230                                         type = "passive";
5231                                 };
5232
5233                                 cpu4_top_crit: cpu_crit {
5234                                         temperature = <110000>;
5235                                         hysteresis = <1000>;
5236                                         type = "critical";
5237                                 };
5238                         };
5239
5240                         cooling-maps {
5241                                 map0 {
5242                                         trip = <&cpu4_top_alert0>;
5243                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5244                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5245                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5246                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5247                                 };
5248                                 map1 {
5249                                         trip = <&cpu4_top_alert1>;
5250                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5251                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5252                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5253                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5254                                 };
5255                         };
5256                 };
5257
5258                 cpu5-top-thermal {
5259                         polling-delay-passive = <250>;
5260                         polling-delay = <1000>;
5261
5262                         thermal-sensors = <&tsens0 8>;
5263
5264                         trips {
5265                                 cpu5_top_alert0: trip-point0 {
5266                                         temperature = <90000>;
5267                                         hysteresis = <2000>;
5268                                         type = "passive";
5269                                 };
5270
5271                                 cpu5_top_alert1: trip-point1 {
5272                                         temperature = <95000>;
5273                                         hysteresis = <2000>;
5274                                         type = "passive";
5275                                 };
5276
5277                                 cpu5_top_crit: cpu_crit {
5278                                         temperature = <110000>;
5279                                         hysteresis = <1000>;
5280                                         type = "critical";
5281                                 };
5282                         };
5283
5284                         cooling-maps {
5285                                 map0 {
5286                                         trip = <&cpu5_top_alert0>;
5287                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5288                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5289                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5290                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5291                                 };
5292                                 map1 {
5293                                         trip = <&cpu5_top_alert1>;
5294                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5295                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5296                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5297                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5298                                 };
5299                         };
5300                 };
5301
5302                 cpu6-top-thermal {
5303                         polling-delay-passive = <250>;
5304                         polling-delay = <1000>;
5305
5306                         thermal-sensors = <&tsens0 9>;
5307
5308                         trips {
5309                                 cpu6_top_alert0: trip-point0 {
5310                                         temperature = <90000>;
5311                                         hysteresis = <2000>;
5312                                         type = "passive";
5313                                 };
5314
5315                                 cpu6_top_alert1: trip-point1 {
5316                                         temperature = <95000>;
5317                                         hysteresis = <2000>;
5318                                         type = "passive";
5319                                 };
5320
5321                                 cpu6_top_crit: cpu_crit {
5322                                         temperature = <110000>;
5323                                         hysteresis = <1000>;
5324                                         type = "critical";
5325                                 };
5326                         };
5327
5328                         cooling-maps {
5329                                 map0 {
5330                                         trip = <&cpu6_top_alert0>;
5331                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5332                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5333                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5334                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5335                                 };
5336                                 map1 {
5337                                         trip = <&cpu6_top_alert1>;
5338                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5339                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5340                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5341                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5342                                 };
5343                         };
5344                 };
5345
5346                 cpu7-top-thermal {
5347                         polling-delay-passive = <250>;
5348                         polling-delay = <1000>;
5349
5350                         thermal-sensors = <&tsens0 10>;
5351
5352                         trips {
5353                                 cpu7_top_alert0: trip-point0 {
5354                                         temperature = <90000>;
5355                                         hysteresis = <2000>;
5356                                         type = "passive";
5357                                 };
5358
5359                                 cpu7_top_alert1: trip-point1 {
5360                                         temperature = <95000>;
5361                                         hysteresis = <2000>;
5362                                         type = "passive";
5363                                 };
5364
5365                                 cpu7_top_crit: cpu_crit {
5366                                         temperature = <110000>;
5367                                         hysteresis = <1000>;
5368                                         type = "critical";
5369                                 };
5370                         };
5371
5372                         cooling-maps {
5373                                 map0 {
5374                                         trip = <&cpu7_top_alert0>;
5375                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5376                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5377                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5378                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5379                                 };
5380                                 map1 {
5381                                         trip = <&cpu7_top_alert1>;
5382                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5383                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5384                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5385                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5386                                 };
5387                         };
5388                 };
5389
5390                 cpu4-bottom-thermal {
5391                         polling-delay-passive = <250>;
5392                         polling-delay = <1000>;
5393
5394                         thermal-sensors = <&tsens0 11>;
5395
5396                         trips {
5397                                 cpu4_bottom_alert0: trip-point0 {
5398                                         temperature = <90000>;
5399                                         hysteresis = <2000>;
5400                                         type = "passive";
5401                                 };
5402
5403                                 cpu4_bottom_alert1: trip-point1 {
5404                                         temperature = <95000>;
5405                                         hysteresis = <2000>;
5406                                         type = "passive";
5407                                 };
5408
5409                                 cpu4_bottom_crit: cpu_crit {
5410                                         temperature = <110000>;
5411                                         hysteresis = <1000>;
5412                                         type = "critical";
5413                                 };
5414                         };
5415
5416                         cooling-maps {
5417                                 map0 {
5418                                         trip = <&cpu4_bottom_alert0>;
5419                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5420                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5421                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5422                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5423                                 };
5424                                 map1 {
5425                                         trip = <&cpu4_bottom_alert1>;
5426                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5427                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5428                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5429                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5430                                 };
5431                         };
5432                 };
5433
5434                 cpu5-bottom-thermal {
5435                         polling-delay-passive = <250>;
5436                         polling-delay = <1000>;
5437
5438                         thermal-sensors = <&tsens0 12>;
5439
5440                         trips {
5441                                 cpu5_bottom_alert0: trip-point0 {
5442                                         temperature = <90000>;
5443                                         hysteresis = <2000>;
5444                                         type = "passive";
5445                                 };
5446
5447                                 cpu5_bottom_alert1: trip-point1 {
5448                                         temperature = <95000>;
5449                                         hysteresis = <2000>;
5450                                         type = "passive";
5451                                 };
5452
5453                                 cpu5_bottom_crit: cpu_crit {
5454                                         temperature = <110000>;
5455                                         hysteresis = <1000>;
5456                                         type = "critical";
5457                                 };
5458                         };
5459
5460                         cooling-maps {
5461                                 map0 {
5462                                         trip = <&cpu5_bottom_alert0>;
5463                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5464                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5465                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5466                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5467                                 };
5468                                 map1 {
5469                                         trip = <&cpu5_bottom_alert1>;
5470                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5471                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5472                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5473                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5474                                 };
5475                         };
5476                 };
5477
5478                 cpu6-bottom-thermal {
5479                         polling-delay-passive = <250>;
5480                         polling-delay = <1000>;
5481
5482                         thermal-sensors = <&tsens0 13>;
5483
5484                         trips {
5485                                 cpu6_bottom_alert0: trip-point0 {
5486                                         temperature = <90000>;
5487                                         hysteresis = <2000>;
5488                                         type = "passive";
5489                                 };
5490
5491                                 cpu6_bottom_alert1: trip-point1 {
5492                                         temperature = <95000>;
5493                                         hysteresis = <2000>;
5494                                         type = "passive";
5495                                 };
5496
5497                                 cpu6_bottom_crit: cpu_crit {
5498                                         temperature = <110000>;
5499                                         hysteresis = <1000>;
5500                                         type = "critical";
5501                                 };
5502                         };
5503
5504                         cooling-maps {
5505                                 map0 {
5506                                         trip = <&cpu6_bottom_alert0>;
5507                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5508                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5509                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5510                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5511                                 };
5512                                 map1 {
5513                                         trip = <&cpu6_bottom_alert1>;
5514                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5515                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5516                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5517                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5518                                 };
5519                         };
5520                 };
5521
5522                 cpu7-bottom-thermal {
5523                         polling-delay-passive = <250>;
5524                         polling-delay = <1000>;
5525
5526                         thermal-sensors = <&tsens0 14>;
5527
5528                         trips {
5529                                 cpu7_bottom_alert0: trip-point0 {
5530                                         temperature = <90000>;
5531                                         hysteresis = <2000>;
5532                                         type = "passive";
5533                                 };
5534
5535                                 cpu7_bottom_alert1: trip-point1 {
5536                                         temperature = <95000>;
5537                                         hysteresis = <2000>;
5538                                         type = "passive";
5539                                 };
5540
5541                                 cpu7_bottom_crit: cpu_crit {
5542                                         temperature = <110000>;
5543                                         hysteresis = <1000>;
5544                                         type = "critical";
5545                                 };
5546                         };
5547
5548                         cooling-maps {
5549                                 map0 {
5550                                         trip = <&cpu7_bottom_alert0>;
5551                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5552                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5553                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5554                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5555                                 };
5556                                 map1 {
5557                                         trip = <&cpu7_bottom_alert1>;
5558                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5559                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5560                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5561                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5562                                 };
5563                         };
5564                 };
5565
5566                 aoss0-thermal {
5567                         polling-delay-passive = <250>;
5568                         polling-delay = <1000>;
5569
5570                         thermal-sensors = <&tsens0 0>;
5571
5572                         trips {
5573                                 aoss0_alert0: trip-point0 {
5574                                         temperature = <90000>;
5575                                         hysteresis = <2000>;
5576                                         type = "hot";
5577                                 };
5578                         };
5579                 };
5580
5581                 cluster0-thermal {
5582                         polling-delay-passive = <250>;
5583                         polling-delay = <1000>;
5584
5585                         thermal-sensors = <&tsens0 5>;
5586
5587                         trips {
5588                                 cluster0_alert0: trip-point0 {
5589                                         temperature = <90000>;
5590                                         hysteresis = <2000>;
5591                                         type = "hot";
5592                                 };
5593                                 cluster0_crit: cluster0_crit {
5594                                         temperature = <110000>;
5595                                         hysteresis = <2000>;
5596                                         type = "critical";
5597                                 };
5598                         };
5599                 };
5600
5601                 cluster1-thermal {
5602                         polling-delay-passive = <250>;
5603                         polling-delay = <1000>;
5604
5605                         thermal-sensors = <&tsens0 6>;
5606
5607                         trips {
5608                                 cluster1_alert0: trip-point0 {
5609                                         temperature = <90000>;
5610                                         hysteresis = <2000>;
5611                                         type = "hot";
5612                                 };
5613                                 cluster1_crit: cluster1_crit {
5614                                         temperature = <110000>;
5615                                         hysteresis = <2000>;
5616                                         type = "critical";
5617                                 };
5618                         };
5619                 };
5620
5621                 gpu-top-thermal {
5622                         polling-delay-passive = <250>;
5623                         polling-delay = <1000>;
5624
5625                         thermal-sensors = <&tsens0 15>;
5626
5627                         trips {
5628                                 gpu1_alert0: trip-point0 {
5629                                         temperature = <90000>;
5630                                         hysteresis = <2000>;
5631                                         type = "hot";
5632                                 };
5633                         };
5634                 };
5635
5636                 aoss1-thermal {
5637                         polling-delay-passive = <250>;
5638                         polling-delay = <1000>;
5639
5640                         thermal-sensors = <&tsens1 0>;
5641
5642                         trips {
5643                                 aoss1_alert0: trip-point0 {
5644                                         temperature = <90000>;
5645                                         hysteresis = <2000>;
5646                                         type = "hot";
5647                                 };
5648                         };
5649                 };
5650
5651                 wlan-thermal {
5652                         polling-delay-passive = <250>;
5653                         polling-delay = <1000>;
5654
5655                         thermal-sensors = <&tsens1 1>;
5656
5657                         trips {
5658                                 wlan_alert0: trip-point0 {
5659                                         temperature = <90000>;
5660                                         hysteresis = <2000>;
5661                                         type = "hot";
5662                                 };
5663                         };
5664                 };
5665
5666                 video-thermal {
5667                         polling-delay-passive = <250>;
5668                         polling-delay = <1000>;
5669
5670                         thermal-sensors = <&tsens1 2>;
5671
5672                         trips {
5673                                 video_alert0: trip-point0 {
5674                                         temperature = <90000>;
5675                                         hysteresis = <2000>;
5676                                         type = "hot";
5677                                 };
5678                         };
5679                 };
5680
5681                 mem-thermal {
5682                         polling-delay-passive = <250>;
5683                         polling-delay = <1000>;
5684
5685                         thermal-sensors = <&tsens1 3>;
5686
5687                         trips {
5688                                 mem_alert0: trip-point0 {
5689                                         temperature = <90000>;
5690                                         hysteresis = <2000>;
5691                                         type = "hot";
5692                                 };
5693                         };
5694                 };
5695
5696                 q6-hvx-thermal {
5697                         polling-delay-passive = <250>;
5698                         polling-delay = <1000>;
5699
5700                         thermal-sensors = <&tsens1 4>;
5701
5702                         trips {
5703                                 q6_hvx_alert0: trip-point0 {
5704                                         temperature = <90000>;
5705                                         hysteresis = <2000>;
5706                                         type = "hot";
5707                                 };
5708                         };
5709                 };
5710
5711                 camera-thermal {
5712                         polling-delay-passive = <250>;
5713                         polling-delay = <1000>;
5714
5715                         thermal-sensors = <&tsens1 5>;
5716
5717                         trips {
5718                                 camera_alert0: trip-point0 {
5719                                         temperature = <90000>;
5720                                         hysteresis = <2000>;
5721                                         type = "hot";
5722                                 };
5723                         };
5724                 };
5725
5726                 compute-thermal {
5727                         polling-delay-passive = <250>;
5728                         polling-delay = <1000>;
5729
5730                         thermal-sensors = <&tsens1 6>;
5731
5732                         trips {
5733                                 compute_alert0: trip-point0 {
5734                                         temperature = <90000>;
5735                                         hysteresis = <2000>;
5736                                         type = "hot";
5737                                 };
5738                         };
5739                 };
5740
5741                 npu-thermal {
5742                         polling-delay-passive = <250>;
5743                         polling-delay = <1000>;
5744
5745                         thermal-sensors = <&tsens1 7>;
5746
5747                         trips {
5748                                 npu_alert0: trip-point0 {
5749                                         temperature = <90000>;
5750                                         hysteresis = <2000>;
5751                                         type = "hot";
5752                                 };
5753                         };
5754                 };
5755
5756                 gpu-bottom-thermal {
5757                         polling-delay-passive = <250>;
5758                         polling-delay = <1000>;
5759
5760                         thermal-sensors = <&tsens1 8>;
5761
5762                         trips {
5763                                 gpu2_alert0: trip-point0 {
5764                                         temperature = <90000>;
5765                                         hysteresis = <2000>;
5766                                         type = "hot";
5767                                 };
5768                         };
5769                 };
5770         };
5771 };