arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/dma/qcom-gpi.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  14 #include <dt-bindings/interconnect/qcom,sm8250.h>
  15 #include <dt-bindings/mailbox/qcom-ipcc.h>
  16 #include <dt-bindings/power/qcom-rpmpd.h>
  17 #include <dt-bindings/soc/qcom,apr.h>
  18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  19 #include <dt-bindings/sound/qcom,q6afe.h>
  20 #include <dt-bindings/thermal/thermal.h>
  21 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
  22 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
  23
  24 / {
  25         interrupt-parent = <&intc>;
  26
  27         #address-cells = <2>;
  28         #size-cells = <2>;
  29
  30         aliases {
  31                 i2c0 = &i2c0;
  32                 i2c1 = &i2c1;
  33                 i2c2 = &i2c2;
  34                 i2c3 = &i2c3;
  35                 i2c4 = &i2c4;
  36                 i2c5 = &i2c5;
  37                 i2c6 = &i2c6;
  38                 i2c7 = &i2c7;
  39                 i2c8 = &i2c8;
  40                 i2c9 = &i2c9;
  41                 i2c10 = &i2c10;
  42                 i2c11 = &i2c11;
  43                 i2c12 = &i2c12;
  44                 i2c13 = &i2c13;
  45                 i2c14 = &i2c14;
  46                 i2c15 = &i2c15;
  47                 i2c16 = &i2c16;
  48                 i2c17 = &i2c17;
  49                 i2c18 = &i2c18;
  50                 i2c19 = &i2c19;
  51                 spi0 = &spi0;
  52                 spi1 = &spi1;
  53                 spi2 = &spi2;
  54                 spi3 = &spi3;
  55                 spi4 = &spi4;
  56                 spi5 = &spi5;
  57                 spi6 = &spi6;
  58                 spi7 = &spi7;
  59                 spi8 = &spi8;
  60                 spi9 = &spi9;
  61                 spi10 = &spi10;
  62                 spi11 = &spi11;
  63                 spi12 = &spi12;
  64                 spi13 = &spi13;
  65                 spi14 = &spi14;
  66                 spi15 = &spi15;
  67                 spi16 = &spi16;
  68                 spi17 = &spi17;
  69                 spi18 = &spi18;
  70                 spi19 = &spi19;
  71         };
  72
  73         chosen { };
  74
  75         clocks {
  76                 xo_board: xo-board {
  77                         compatible = "fixed-clock";
  78                         #clock-cells = <0>;
  79                         clock-frequency = <38400000>;
  80                         clock-output-names = "xo_board";
  81                 };
  82
  83                 sleep_clk: sleep-clk {
  84                         compatible = "fixed-clock";
  85                         clock-frequency = <32768>;
  86                         #clock-cells = <0>;
  87                 };
  88         };
  89
  90         cpus {
  91                 #address-cells = <2>;
  92                 #size-cells = <0>;
  93
  94                 CPU0: cpu@0 {
  95                         device_type = "cpu";
  96                         compatible = "qcom,kryo485";
  97                         reg = <0x0 0x0>;
  98                         enable-method = "psci";
  99                         capacity-dmips-mhz = <448>;
 100                         dynamic-power-coefficient = <205>;
 101                         next-level-cache = <&L2_0>;
 102                         power-domains = <&CPU_PD0>;
 103                         power-domain-names = "psci";
 104                         qcom,freq-domain = <&cpufreq_hw 0>;
 105                         operating-points-v2 = <&cpu0_opp_table>;
 106                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 107                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 108                         #cooling-cells = <2>;
 109                         L2_0: l2-cache {
 110                                 compatible = "cache";
 111                                 next-level-cache = <&L3_0>;
 112                                 L3_0: l3-cache {
 113                                         compatible = "cache";
 114                                 };
 115                         };
 116                 };
 117
 118                 CPU1: cpu@100 {
 119                         device_type = "cpu";
 120                         compatible = "qcom,kryo485";
 121                         reg = <0x0 0x100>;
 122                         enable-method = "psci";
 123                         capacity-dmips-mhz = <448>;
 124                         dynamic-power-coefficient = <205>;
 125                         next-level-cache = <&L2_100>;
 126                         power-domains = <&CPU_PD1>;
 127                         power-domain-names = "psci";
 128                         qcom,freq-domain = <&cpufreq_hw 0>;
 129                         operating-points-v2 = <&cpu0_opp_table>;
 130                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 131                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 132                         #cooling-cells = <2>;
 133                         L2_100: l2-cache {
 134                                 compatible = "cache";
 135                                 next-level-cache = <&L3_0>;
 136                         };
 137                 };
 138
 139                 CPU2: cpu@200 {
 140                         device_type = "cpu";
 141                         compatible = "qcom,kryo485";
 142                         reg = <0x0 0x200>;
 143                         enable-method = "psci";
 144                         capacity-dmips-mhz = <448>;
 145                         dynamic-power-coefficient = <205>;
 146                         next-level-cache = <&L2_200>;
 147                         power-domains = <&CPU_PD2>;
 148                         power-domain-names = "psci";
 149                         qcom,freq-domain = <&cpufreq_hw 0>;
 150                         operating-points-v2 = <&cpu0_opp_table>;
 151                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 152                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 153                         #cooling-cells = <2>;
 154                         L2_200: l2-cache {
 155                                 compatible = "cache";
 156                                 next-level-cache = <&L3_0>;
 157                         };
 158                 };
 159
 160                 CPU3: cpu@300 {
 161                         device_type = "cpu";
 162                         compatible = "qcom,kryo485";
 163                         reg = <0x0 0x300>;
 164                         enable-method = "psci";
 165                         capacity-dmips-mhz = <448>;
 166                         dynamic-power-coefficient = <205>;
 167                         next-level-cache = <&L2_300>;
 168                         power-domains = <&CPU_PD3>;
 169                         power-domain-names = "psci";
 170                         qcom,freq-domain = <&cpufreq_hw 0>;
 171                         operating-points-v2 = <&cpu0_opp_table>;
 172                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 173                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 174                         #cooling-cells = <2>;
 175                         L2_300: l2-cache {
 176                                 compatible = "cache";
 177                                 next-level-cache = <&L3_0>;
 178                         };
 179                 };
 180
 181                 CPU4: cpu@400 {
 182                         device_type = "cpu";
 183                         compatible = "qcom,kryo485";
 184                         reg = <0x0 0x400>;
 185                         enable-method = "psci";
 186                         capacity-dmips-mhz = <1024>;
 187                         dynamic-power-coefficient = <379>;
 188                         next-level-cache = <&L2_400>;
 189                         power-domains = <&CPU_PD4>;
 190                         power-domain-names = "psci";
 191                         qcom,freq-domain = <&cpufreq_hw 1>;
 192                         operating-points-v2 = <&cpu4_opp_table>;
 193                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 194                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 195                         #cooling-cells = <2>;
 196                         L2_400: l2-cache {
 197                                 compatible = "cache";
 198                                 next-level-cache = <&L3_0>;
 199                         };
 200                 };
 201
 202                 CPU5: cpu@500 {
 203                         device_type = "cpu";
 204                         compatible = "qcom,kryo485";
 205                         reg = <0x0 0x500>;
 206                         enable-method = "psci";
 207                         capacity-dmips-mhz = <1024>;
 208                         dynamic-power-coefficient = <379>;
 209                         next-level-cache = <&L2_500>;
 210                         power-domains = <&CPU_PD5>;
 211                         power-domain-names = "psci";
 212                         qcom,freq-domain = <&cpufreq_hw 1>;
 213                         operating-points-v2 = <&cpu4_opp_table>;
 214                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 215                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 216                         #cooling-cells = <2>;
 217                         L2_500: l2-cache {
 218                                 compatible = "cache";
 219                                 next-level-cache = <&L3_0>;
 220                         };
 221
 222                 };
 223
 224                 CPU6: cpu@600 {
 225                         device_type = "cpu";
 226                         compatible = "qcom,kryo485";
 227                         reg = <0x0 0x600>;
 228                         enable-method = "psci";
 229                         capacity-dmips-mhz = <1024>;
 230                         dynamic-power-coefficient = <379>;
 231                         next-level-cache = <&L2_600>;
 232                         power-domains = <&CPU_PD6>;
 233                         power-domain-names = "psci";
 234                         qcom,freq-domain = <&cpufreq_hw 1>;
 235                         operating-points-v2 = <&cpu4_opp_table>;
 236                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 237                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 238                         #cooling-cells = <2>;
 239                         L2_600: l2-cache {
 240                                 compatible = "cache";
 241                                 next-level-cache = <&L3_0>;
 242                         };
 243                 };
 244
 245                 CPU7: cpu@700 {
 246                         device_type = "cpu";
 247                         compatible = "qcom,kryo485";
 248                         reg = <0x0 0x700>;
 249                         enable-method = "psci";
 250                         capacity-dmips-mhz = <1024>;
 251                         dynamic-power-coefficient = <444>;
 252                         next-level-cache = <&L2_700>;
 253                         power-domains = <&CPU_PD7>;
 254                         power-domain-names = "psci";
 255                         qcom,freq-domain = <&cpufreq_hw 2>;
 256                         operating-points-v2 = <&cpu7_opp_table>;
 257                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 258                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 259                         #cooling-cells = <2>;
 260                         L2_700: l2-cache {
 261                                 compatible = "cache";
 262                                 next-level-cache = <&L3_0>;
 263                         };
 264                 };
 265
 266                 cpu-map {
 267                         cluster0 {
 268                                 core0 {
 269                                         cpu = <&CPU0>;
 270                                 };
 271
 272                                 core1 {
 273                                         cpu = <&CPU1>;
 274                                 };
 275
 276                                 core2 {
 277                                         cpu = <&CPU2>;
 278                                 };
 279
 280                                 core3 {
 281                                         cpu = <&CPU3>;
 282                                 };
 283
 284                                 core4 {
 285                                         cpu = <&CPU4>;
 286                                 };
 287
 288                                 core5 {
 289                                         cpu = <&CPU5>;
 290                                 };
 291
 292                                 core6 {
 293                                         cpu = <&CPU6>;
 294                                 };
 295
 296                                 core7 {
 297                                         cpu = <&CPU7>;
 298                                 };
 299                         };
 300                 };
 301
 302                 idle-states {
 303                         entry-method = "psci";
 304
 305                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 306                                 compatible = "arm,idle-state";
 307                                 idle-state-name = "silver-rail-power-collapse";
 308                                 arm,psci-suspend-param = <0x40000004>;
 309                                 entry-latency-us = <360>;
 310                                 exit-latency-us = <531>;
 311                                 min-residency-us = <3934>;
 312                                 local-timer-stop;
 313                         };
 314
 315                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 316                                 compatible = "arm,idle-state";
 317                                 idle-state-name = "gold-rail-power-collapse";
 318                                 arm,psci-suspend-param = <0x40000004>;
 319                                 entry-latency-us = <702>;
 320                                 exit-latency-us = <1061>;
 321                                 min-residency-us = <4488>;
 322                                 local-timer-stop;
 323                         };
 324                 };
 325
 326                 domain-idle-states {
 327                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 328                                 compatible = "domain-idle-state";
 329                                 idle-state-name = "cluster-llcc-off";
 330                                 arm,psci-suspend-param = <0x4100c244>;
 331                                 entry-latency-us = <3264>;
 332                                 exit-latency-us = <6562>;
 333                                 min-residency-us = <9987>;
 334                                 local-timer-stop;
 335                         };
 336                 };
 337         };
 338
 339         cpu0_opp_table: cpu0_opp_table {
 340                 compatible = "operating-points-v2";
 341                 opp-shared;
 342
 343                 cpu0_opp1: opp-300000000 {
 344                         opp-hz = /bits/ 64 <300000000>;
 345                         opp-peak-kBps = <800000 9600000>;
 346                 };
 347
 348                 cpu0_opp2: opp-403200000 {
 349                         opp-hz = /bits/ 64 <403200000>;
 350                         opp-peak-kBps = <800000 9600000>;
 351                 };
 352
 353                 cpu0_opp3: opp-518400000 {
 354                         opp-hz = /bits/ 64 <518400000>;
 355                         opp-peak-kBps = <800000 16588800>;
 356                 };
 357
 358                 cpu0_opp4: opp-614400000 {
 359                         opp-hz = /bits/ 64 <614400000>;
 360                         opp-peak-kBps = <800000 16588800>;
 361                 };
 362
 363                 cpu0_opp5: opp-691200000 {
 364                         opp-hz = /bits/ 64 <691200000>;
 365                         opp-peak-kBps = <800000 19660800>;
 366                 };
 367
 368                 cpu0_opp6: opp-787200000 {
 369                         opp-hz = /bits/ 64 <787200000>;
 370                         opp-peak-kBps = <1804000 19660800>;
 371                 };
 372
 373                 cpu0_opp7: opp-883200000 {
 374                         opp-hz = /bits/ 64 <883200000>;
 375                         opp-peak-kBps = <1804000 23347200>;
 376                 };
 377
 378                 cpu0_opp8: opp-979200000 {
 379                         opp-hz = /bits/ 64 <979200000>;
 380                         opp-peak-kBps = <1804000 26419200>;
 381                 };
 382
 383                 cpu0_opp9: opp-1075200000 {
 384                         opp-hz = /bits/ 64 <1075200000>;
 385                         opp-peak-kBps = <1804000 29491200>;
 386                 };
 387
 388                 cpu0_opp10: opp-1171200000 {
 389                         opp-hz = /bits/ 64 <1171200000>;
 390                         opp-peak-kBps = <1804000 32563200>;
 391                 };
 392
 393                 cpu0_opp11: opp-1248000000 {
 394                         opp-hz = /bits/ 64 <1248000000>;
 395                         opp-peak-kBps = <1804000 36249600>;
 396                 };
 397
 398                 cpu0_opp12: opp-1344000000 {
 399                         opp-hz = /bits/ 64 <1344000000>;
 400                         opp-peak-kBps = <2188000 36249600>;
 401                 };
 402
 403                 cpu0_opp13: opp-1420800000 {
 404                         opp-hz = /bits/ 64 <1420800000>;
 405                         opp-peak-kBps = <2188000 39321600>;
 406                 };
 407
 408                 cpu0_opp14: opp-1516800000 {
 409                         opp-hz = /bits/ 64 <1516800000>;
 410                         opp-peak-kBps = <3072000 42393600>;
 411                 };
 412
 413                 cpu0_opp15: opp-1612800000 {
 414                         opp-hz = /bits/ 64 <1612800000>;
 415                         opp-peak-kBps = <3072000 42393600>;
 416                 };
 417
 418                 cpu0_opp16: opp-1708800000 {
 419                         opp-hz = /bits/ 64 <1708800000>;
 420                         opp-peak-kBps = <4068000 42393600>;
 421                 };
 422
 423                 cpu0_opp17: opp-1804800000 {
 424                         opp-hz = /bits/ 64 <1804800000>;
 425                         opp-peak-kBps = <4068000 42393600>;
 426                 };
 427         };
 428
 429         cpu4_opp_table: cpu4_opp_table {
 430                 compatible = "operating-points-v2";
 431                 opp-shared;
 432
 433                 cpu4_opp1: opp-710400000 {
 434                         opp-hz = /bits/ 64 <710400000>;
 435                         opp-peak-kBps = <1804000 19660800>;
 436                 };
 437
 438                 cpu4_opp2: opp-825600000 {
 439                         opp-hz = /bits/ 64 <825600000>;
 440                         opp-peak-kBps = <2188000 23347200>;
 441                 };
 442
 443                 cpu4_opp3: opp-940800000 {
 444                         opp-hz = /bits/ 64 <940800000>;
 445                         opp-peak-kBps = <2188000 26419200>;
 446                 };
 447
 448                 cpu4_opp4: opp-1056000000 {
 449                         opp-hz = /bits/ 64 <1056000000>;
 450                         opp-peak-kBps = <3072000 26419200>;
 451                 };
 452
 453                 cpu4_opp5: opp-1171200000 {
 454                         opp-hz = /bits/ 64 <1171200000>;
 455                         opp-peak-kBps = <3072000 29491200>;
 456                 };
 457
 458                 cpu4_opp6: opp-1286400000 {
 459                         opp-hz = /bits/ 64 <1286400000>;
 460                         opp-peak-kBps = <4068000 29491200>;
 461                 };
 462
 463                 cpu4_opp7: opp-1382400000 {
 464                         opp-hz = /bits/ 64 <1382400000>;
 465                         opp-peak-kBps = <4068000 32563200>;
 466                 };
 467
 468                 cpu4_opp8: opp-1478400000 {
 469                         opp-hz = /bits/ 64 <1478400000>;
 470                         opp-peak-kBps = <4068000 32563200>;
 471                 };
 472
 473                 cpu4_opp9: opp-1574400000 {
 474                         opp-hz = /bits/ 64 <1574400000>;
 475                         opp-peak-kBps = <5412000 39321600>;
 476                 };
 477
 478                 cpu4_opp10: opp-1670400000 {
 479                         opp-hz = /bits/ 64 <1670400000>;
 480                         opp-peak-kBps = <5412000 42393600>;
 481                 };
 482
 483                 cpu4_opp11: opp-1766400000 {
 484                         opp-hz = /bits/ 64 <1766400000>;
 485                         opp-peak-kBps = <5412000 45465600>;
 486                 };
 487
 488                 cpu4_opp12: opp-1862400000 {
 489                         opp-hz = /bits/ 64 <1862400000>;
 490                         opp-peak-kBps = <6220000 45465600>;
 491                 };
 492
 493                 cpu4_opp13: opp-1958400000 {
 494                         opp-hz = /bits/ 64 <1958400000>;
 495                         opp-peak-kBps = <6220000 48537600>;
 496                 };
 497
 498                 cpu4_opp14: opp-2054400000 {
 499                         opp-hz = /bits/ 64 <2054400000>;
 500                         opp-peak-kBps = <7216000 48537600>;
 501                 };
 502
 503                 cpu4_opp15: opp-2150400000 {
 504                         opp-hz = /bits/ 64 <2150400000>;
 505                         opp-peak-kBps = <7216000 51609600>;
 506                 };
 507
 508                 cpu4_opp16: opp-2246400000 {
 509                         opp-hz = /bits/ 64 <2246400000>;
 510                         opp-peak-kBps = <7216000 51609600>;
 511                 };
 512
 513                 cpu4_opp17: opp-2342400000 {
 514                         opp-hz = /bits/ 64 <2342400000>;
 515                         opp-peak-kBps = <8368000 51609600>;
 516                 };
 517
 518                 cpu4_opp18: opp-2419200000 {
 519                         opp-hz = /bits/ 64 <2419200000>;
 520                         opp-peak-kBps = <8368000 51609600>;
 521                 };
 522         };
 523
 524         cpu7_opp_table: cpu7_opp_table {
 525                 compatible = "operating-points-v2";
 526                 opp-shared;
 527
 528                 cpu7_opp1: opp-844800000 {
 529                         opp-hz = /bits/ 64 <844800000>;
 530                         opp-peak-kBps = <2188000 19660800>;
 531                 };
 532
 533                 cpu7_opp2: opp-960000000 {
 534                         opp-hz = /bits/ 64 <960000000>;
 535                         opp-peak-kBps = <2188000 26419200>;
 536                 };
 537
 538                 cpu7_opp3: opp-1075200000 {
 539                         opp-hz = /bits/ 64 <1075200000>;
 540                         opp-peak-kBps = <3072000 26419200>;
 541                 };
 542
 543                 cpu7_opp4: opp-1190400000 {
 544                         opp-hz = /bits/ 64 <1190400000>;
 545                         opp-peak-kBps = <3072000 29491200>;
 546                 };
 547
 548                 cpu7_opp5: opp-1305600000 {
 549                         opp-hz = /bits/ 64 <1305600000>;
 550                         opp-peak-kBps = <4068000 32563200>;
 551                 };
 552
 553                 cpu7_opp6: opp-1401600000 {
 554                         opp-hz = /bits/ 64 <1401600000>;
 555                         opp-peak-kBps = <4068000 32563200>;
 556                 };
 557
 558                 cpu7_opp7: opp-1516800000 {
 559                         opp-hz = /bits/ 64 <1516800000>;
 560                         opp-peak-kBps = <4068000 36249600>;
 561                 };
 562
 563                 cpu7_opp8: opp-1632000000 {
 564                         opp-hz = /bits/ 64 <1632000000>;
 565                         opp-peak-kBps = <5412000 39321600>;
 566                 };
 567
 568                 cpu7_opp9: opp-1747200000 {
 569                         opp-hz = /bits/ 64 <1708800000>;
 570                         opp-peak-kBps = <5412000 42393600>;
 571                 };
 572
 573                 cpu7_opp10: opp-1862400000 {
 574                         opp-hz = /bits/ 64 <1862400000>;
 575                         opp-peak-kBps = <6220000 45465600>;
 576                 };
 577
 578                 cpu7_opp11: opp-1977600000 {
 579                         opp-hz = /bits/ 64 <1977600000>;
 580                         opp-peak-kBps = <6220000 48537600>;
 581                 };
 582
 583                 cpu7_opp12: opp-2073600000 {
 584                         opp-hz = /bits/ 64 <2073600000>;
 585                         opp-peak-kBps = <7216000 48537600>;
 586                 };
 587
 588                 cpu7_opp13: opp-2169600000 {
 589                         opp-hz = /bits/ 64 <2169600000>;
 590                         opp-peak-kBps = <7216000 51609600>;
 591                 };
 592
 593                 cpu7_opp14: opp-2265600000 {
 594                         opp-hz = /bits/ 64 <2265600000>;
 595                         opp-peak-kBps = <7216000 51609600>;
 596                 };
 597
 598                 cpu7_opp15: opp-2361600000 {
 599                         opp-hz = /bits/ 64 <2361600000>;
 600                         opp-peak-kBps = <8368000 51609600>;
 601                 };
 602
 603                 cpu7_opp16: opp-2457600000 {
 604                         opp-hz = /bits/ 64 <2457600000>;
 605                         opp-peak-kBps = <8368000 51609600>;
 606                 };
 607
 608                 cpu7_opp17: opp-2553600000 {
 609                         opp-hz = /bits/ 64 <2553600000>;
 610                         opp-peak-kBps = <8368000 51609600>;
 611                 };
 612
 613                 cpu7_opp18: opp-2649600000 {
 614                         opp-hz = /bits/ 64 <2649600000>;
 615                         opp-peak-kBps = <8368000 51609600>;
 616                 };
 617
 618                 cpu7_opp19: opp-2745600000 {
 619                         opp-hz = /bits/ 64 <2745600000>;
 620                         opp-peak-kBps = <8368000 51609600>;
 621                 };
 622
 623                 cpu7_opp20: opp-2841600000 {
 624                         opp-hz = /bits/ 64 <2841600000>;
 625                         opp-peak-kBps = <8368000 51609600>;
 626                 };
 627         };
 628
 629         firmware {
 630                 scm: scm {
 631                         compatible = "qcom,scm";
 632                         #reset-cells = <1>;
 633                 };
 634         };
 635
 636         memory@80000000 {
 637                 device_type = "memory";
 638                 /* We expect the bootloader to fill in the size */
 639                 reg = <0x0 0x80000000 0x0 0x0>;
 640         };
 641
 642         pmu {
 643                 compatible = "arm,armv8-pmuv3";
 644                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 645         };
 646
 647         psci {
 648                 compatible = "arm,psci-1.0";
 649                 method = "smc";
 650
 651                 CPU_PD0: cpu0 {
 652                         #power-domain-cells = <0>;
 653                         power-domains = <&CLUSTER_PD>;
 654                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 655                 };
 656
 657                 CPU_PD1: cpu1 {
 658                         #power-domain-cells = <0>;
 659                         power-domains = <&CLUSTER_PD>;
 660                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 661                 };
 662
 663                 CPU_PD2: cpu2 {
 664                         #power-domain-cells = <0>;
 665                         power-domains = <&CLUSTER_PD>;
 666                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 667                 };
 668
 669                 CPU_PD3: cpu3 {
 670                         #power-domain-cells = <0>;
 671                         power-domains = <&CLUSTER_PD>;
 672                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 673                 };
 674
 675                 CPU_PD4: cpu4 {
 676                         #power-domain-cells = <0>;
 677                         power-domains = <&CLUSTER_PD>;
 678                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 679                 };
 680
 681                 CPU_PD5: cpu5 {
 682                         #power-domain-cells = <0>;
 683                         power-domains = <&CLUSTER_PD>;
 684                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 685                 };
 686
 687                 CPU_PD6: cpu6 {
 688                         #power-domain-cells = <0>;
 689                         power-domains = <&CLUSTER_PD>;
 690                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 691                 };
 692
 693                 CPU_PD7: cpu7 {
 694                         #power-domain-cells = <0>;
 695                         power-domains = <&CLUSTER_PD>;
 696                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 697                 };
 698
 699                 CLUSTER_PD: cpu-cluster0 {
 700                         #power-domain-cells = <0>;
 701                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 702                 };
 703         };
 704
 705         reserved-memory {
 706                 #address-cells = <2>;
 707                 #size-cells = <2>;
 708                 ranges;
 709
 710                 hyp_mem: memory@80000000 {
 711                         reg = <0x0 0x80000000 0x0 0x600000>;
 712                         no-map;
 713                 };
 714
 715                 xbl_aop_mem: memory@80700000 {
 716                         reg = <0x0 0x80700000 0x0 0x160000>;
 717                         no-map;
 718                 };
 719
 720                 cmd_db: memory@80860000 {
 721                         compatible = "qcom,cmd-db";
 722                         reg = <0x0 0x80860000 0x0 0x20000>;
 723                         no-map;
 724                 };
 725
 726                 smem_mem: memory@80900000 {
 727                         reg = <0x0 0x80900000 0x0 0x200000>;
 728                         no-map;
 729                 };
 730
 731                 removed_mem: memory@80b00000 {
 732                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 733                         no-map;
 734                 };
 735
 736                 camera_mem: memory@86200000 {
 737                         reg = <0x0 0x86200000 0x0 0x500000>;
 738                         no-map;
 739                 };
 740
 741                 wlan_mem: memory@86700000 {
 742                         reg = <0x0 0x86700000 0x0 0x100000>;
 743                         no-map;
 744                 };
 745
 746                 ipa_fw_mem: memory@86800000 {
 747                         reg = <0x0 0x86800000 0x0 0x10000>;
 748                         no-map;
 749                 };
 750
 751                 ipa_gsi_mem: memory@86810000 {
 752                         reg = <0x0 0x86810000 0x0 0xa000>;
 753                         no-map;
 754                 };
 755
 756                 gpu_mem: memory@8681a000 {
 757                         reg = <0x0 0x8681a000 0x0 0x2000>;
 758                         no-map;
 759                 };
 760
 761                 npu_mem: memory@86900000 {
 762                         reg = <0x0 0x86900000 0x0 0x500000>;
 763                         no-map;
 764                 };
 765
 766                 video_mem: memory@86e00000 {
 767                         reg = <0x0 0x86e00000 0x0 0x500000>;
 768                         no-map;
 769                 };
 770
 771                 cvp_mem: memory@87300000 {
 772                         reg = <0x0 0x87300000 0x0 0x500000>;
 773                         no-map;
 774                 };
 775
 776                 cdsp_mem: memory@87800000 {
 777                         reg = <0x0 0x87800000 0x0 0x1400000>;
 778                         no-map;
 779                 };
 780
 781                 slpi_mem: memory@88c00000 {
 782                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 783                         no-map;
 784                 };
 785
 786                 adsp_mem: memory@8a100000 {
 787                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 788                         no-map;
 789                 };
 790
 791                 spss_mem: memory@8be00000 {
 792                         reg = <0x0 0x8be00000 0x0 0x100000>;
 793                         no-map;
 794                 };
 795
 796                 cdsp_secure_heap: memory@8bf00000 {
 797                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 798                         no-map;
 799                 };
 800         };
 801
 802         smem {
 803                 compatible = "qcom,smem";
 804                 memory-region = <&smem_mem>;
 805                 hwlocks = <&tcsr_mutex 3>;
 806         };
 807
 808         smp2p-adsp {
 809                 compatible = "qcom,smp2p";
 810                 qcom,smem = <443>, <429>;
 811                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 812                                              IPCC_MPROC_SIGNAL_SMP2P
 813                                              IRQ_TYPE_EDGE_RISING>;
 814                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 815                                 IPCC_MPROC_SIGNAL_SMP2P>;
 816
 817                 qcom,local-pid = <0>;
 818                 qcom,remote-pid = <2>;
 819
 820                 smp2p_adsp_out: master-kernel {
 821                         qcom,entry-name = "master-kernel";
 822                         #qcom,smem-state-cells = <1>;
 823                 };
 824
 825                 smp2p_adsp_in: slave-kernel {
 826                         qcom,entry-name = "slave-kernel";
 827                         interrupt-controller;
 828                         #interrupt-cells = <2>;
 829                 };
 830         };
 831
 832         smp2p-cdsp {
 833                 compatible = "qcom,smp2p";
 834                 qcom,smem = <94>, <432>;
 835                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 836                                              IPCC_MPROC_SIGNAL_SMP2P
 837                                              IRQ_TYPE_EDGE_RISING>;
 838                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 839                                 IPCC_MPROC_SIGNAL_SMP2P>;
 840
 841                 qcom,local-pid = <0>;
 842                 qcom,remote-pid = <5>;
 843
 844                 smp2p_cdsp_out: master-kernel {
 845                         qcom,entry-name = "master-kernel";
 846                         #qcom,smem-state-cells = <1>;
 847                 };
 848
 849                 smp2p_cdsp_in: slave-kernel {
 850                         qcom,entry-name = "slave-kernel";
 851                         interrupt-controller;
 852                         #interrupt-cells = <2>;
 853                 };
 854         };
 855
 856         smp2p-slpi {
 857                 compatible = "qcom,smp2p";
 858                 qcom,smem = <481>, <430>;
 859                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 860                                              IPCC_MPROC_SIGNAL_SMP2P
 861                                              IRQ_TYPE_EDGE_RISING>;
 862                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 863                                 IPCC_MPROC_SIGNAL_SMP2P>;
 864
 865                 qcom,local-pid = <0>;
 866                 qcom,remote-pid = <3>;
 867
 868                 smp2p_slpi_out: master-kernel {
 869                         qcom,entry-name = "master-kernel";
 870                         #qcom,smem-state-cells = <1>;
 871                 };
 872
 873                 smp2p_slpi_in: slave-kernel {
 874                         qcom,entry-name = "slave-kernel";
 875                         interrupt-controller;
 876                         #interrupt-cells = <2>;
 877                 };
 878         };
 879
 880         soc: soc@0 {
 881                 #address-cells = <2>;
 882                 #size-cells = <2>;
 883                 ranges = <0 0 0 0 0x10 0>;
 884                 dma-ranges = <0 0 0 0 0x10 0>;
 885                 compatible = "simple-bus";
 886
 887                 gcc: clock-controller@100000 {
 888                         compatible = "qcom,gcc-sm8250";
 889                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 890                         #clock-cells = <1>;
 891                         #reset-cells = <1>;
 892                         #power-domain-cells = <1>;
 893                         clock-names = "bi_tcxo",
 894                                       "bi_tcxo_ao",
 895                                       "sleep_clk";
 896                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 897                                  <&rpmhcc RPMH_CXO_CLK_A>,
 898                                  <&sleep_clk>;
 899                 };
 900
 901                 ipcc: mailbox@408000 {
 902                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 903                         reg = <0 0x00408000 0 0x1000>;
 904                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 905                         interrupt-controller;
 906                         #interrupt-cells = <3>;
 907                         #mbox-cells = <2>;
 908                 };
 909
 910                 rng: rng@793000 {
 911                         compatible = "qcom,prng-ee";
 912                         reg = <0 0x00793000 0 0x1000>;
 913                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 914                         clock-names = "core";
 915                 };
 916
 917                 qup_opp_table: qup-opp-table {
 918                         compatible = "operating-points-v2";
 919
 920                         opp-50000000 {
 921                                 opp-hz = /bits/ 64 <50000000>;
 922                                 required-opps = <&rpmhpd_opp_min_svs>;
 923                         };
 924
 925                         opp-75000000 {
 926                                 opp-hz = /bits/ 64 <75000000>;
 927                                 required-opps = <&rpmhpd_opp_low_svs>;
 928                         };
 929
 930                         opp-120000000 {
 931                                 opp-hz = /bits/ 64 <120000000>;
 932                                 required-opps = <&rpmhpd_opp_svs>;
 933                         };
 934                 };
 935
 936                 gpi_dma2: dma-controller@800000 {
 937                         compatible = "qcom,sm8250-gpi-dma";
 938                         reg = <0 0x00800000 0 0x70000>;
 939                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 940                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 941                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 942                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 943                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 944                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 945                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 946                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 947                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 948                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
 949                         dma-channels = <10>;
 950                         dma-channel-mask = <0x3f>;
 951                         iommus = <&apps_smmu 0x76 0x0>;
 952                         #dma-cells = <3>;
 953                         status = "disabled";
 954                 };
 955
 956                 qupv3_id_2: geniqup@8c0000 {
 957                         compatible = "qcom,geni-se-qup";
 958                         reg = <0x0 0x008c0000 0x0 0x6000>;
 959                         clock-names = "m-ahb", "s-ahb";
 960                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 961                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 962                         #address-cells = <2>;
 963                         #size-cells = <2>;
 964                         iommus = <&apps_smmu 0x63 0x0>;
 965                         ranges;
 966                         status = "disabled";
 967
 968                         i2c14: i2c@880000 {
 969                                 compatible = "qcom,geni-i2c";
 970                                 reg = <0 0x00880000 0 0x4000>;
 971                                 clock-names = "se";
 972                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 973                                 pinctrl-names = "default";
 974                                 pinctrl-0 = <&qup_i2c14_default>;
 975                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 976                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 977                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 978                                 dma-names = "tx", "rx";
 979                                 #address-cells = <1>;
 980                                 #size-cells = <0>;
 981                                 status = "disabled";
 982                         };
 983
 984                         spi14: spi@880000 {
 985                                 compatible = "qcom,geni-spi";
 986                                 reg = <0 0x00880000 0 0x4000>;
 987                                 clock-names = "se";
 988                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 989                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 990                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 991                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 992                                 dma-names = "tx", "rx";
 993                                 power-domains = <&rpmhpd SM8250_CX>;
 994                                 operating-points-v2 = <&qup_opp_table>;
 995                                 #address-cells = <1>;
 996                                 #size-cells = <0>;
 997                                 status = "disabled";
 998                         };
 999
1000                         i2c15: i2c@884000 {
1001                                 compatible = "qcom,geni-i2c";
1002                                 reg = <0 0x00884000 0 0x4000>;
1003                                 clock-names = "se";
1004                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1005                                 pinctrl-names = "default";
1006                                 pinctrl-0 = <&qup_i2c15_default>;
1007                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1008                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1009                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1010                                 dma-names = "tx", "rx";
1011                                 #address-cells = <1>;
1012                                 #size-cells = <0>;
1013                                 status = "disabled";
1014                         };
1015
1016                         spi15: spi@884000 {
1017                                 compatible = "qcom,geni-spi";
1018                                 reg = <0 0x00884000 0 0x4000>;
1019                                 clock-names = "se";
1020                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1021                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1022                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1023                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1024                                 dma-names = "tx", "rx";
1025                                 power-domains = <&rpmhpd SM8250_CX>;
1026                                 operating-points-v2 = <&qup_opp_table>;
1027                                 #address-cells = <1>;
1028                                 #size-cells = <0>;
1029                                 status = "disabled";
1030                         };
1031
1032                         i2c16: i2c@888000 {
1033                                 compatible = "qcom,geni-i2c";
1034                                 reg = <0 0x00888000 0 0x4000>;
1035                                 clock-names = "se";
1036                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1037                                 pinctrl-names = "default";
1038                                 pinctrl-0 = <&qup_i2c16_default>;
1039                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1040                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1041                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1042                                 dma-names = "tx", "rx";
1043                                 #address-cells = <1>;
1044                                 #size-cells = <0>;
1045                                 status = "disabled";
1046                         };
1047
1048                         spi16: spi@888000 {
1049                                 compatible = "qcom,geni-spi";
1050                                 reg = <0 0x00888000 0 0x4000>;
1051                                 clock-names = "se";
1052                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1053                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1054                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1055                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1056                                 dma-names = "tx", "rx";
1057                                 power-domains = <&rpmhpd SM8250_CX>;
1058                                 operating-points-v2 = <&qup_opp_table>;
1059                                 #address-cells = <1>;
1060                                 #size-cells = <0>;
1061                                 status = "disabled";
1062                         };
1063
1064                         i2c17: i2c@88c000 {
1065                                 compatible = "qcom,geni-i2c";
1066                                 reg = <0 0x0088c000 0 0x4000>;
1067                                 clock-names = "se";
1068                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1069                                 pinctrl-names = "default";
1070                                 pinctrl-0 = <&qup_i2c17_default>;
1071                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1072                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1073                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1074                                 dma-names = "tx", "rx";
1075                                 #address-cells = <1>;
1076                                 #size-cells = <0>;
1077                                 status = "disabled";
1078                         };
1079
1080                         spi17: spi@88c000 {
1081                                 compatible = "qcom,geni-spi";
1082                                 reg = <0 0x0088c000 0 0x4000>;
1083                                 clock-names = "se";
1084                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1085                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1086                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1087                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1088                                 dma-names = "tx", "rx";
1089                                 power-domains = <&rpmhpd SM8250_CX>;
1090                                 operating-points-v2 = <&qup_opp_table>;
1091                                 #address-cells = <1>;
1092                                 #size-cells = <0>;
1093                                 status = "disabled";
1094                         };
1095
1096                         uart17: serial@88c000 {
1097                                 compatible = "qcom,geni-uart";
1098                                 reg = <0 0x0088c000 0 0x4000>;
1099                                 clock-names = "se";
1100                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1101                                 pinctrl-names = "default";
1102                                 pinctrl-0 = <&qup_uart17_default>;
1103                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1104                                 power-domains = <&rpmhpd SM8250_CX>;
1105                                 operating-points-v2 = <&qup_opp_table>;
1106                                 status = "disabled";
1107                         };
1108
1109                         i2c18: i2c@890000 {
1110                                 compatible = "qcom,geni-i2c";
1111                                 reg = <0 0x00890000 0 0x4000>;
1112                                 clock-names = "se";
1113                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1114                                 pinctrl-names = "default";
1115                                 pinctrl-0 = <&qup_i2c18_default>;
1116                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1117                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1118                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1119                                 dma-names = "tx", "rx";
1120                                 #address-cells = <1>;
1121                                 #size-cells = <0>;
1122                                 status = "disabled";
1123                         };
1124
1125                         spi18: spi@890000 {
1126                                 compatible = "qcom,geni-spi";
1127                                 reg = <0 0x00890000 0 0x4000>;
1128                                 clock-names = "se";
1129                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1130                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1131                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1132                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1133                                 dma-names = "tx", "rx";
1134                                 power-domains = <&rpmhpd SM8250_CX>;
1135                                 operating-points-v2 = <&qup_opp_table>;
1136                                 #address-cells = <1>;
1137                                 #size-cells = <0>;
1138                                 status = "disabled";
1139                         };
1140
1141                         uart18: serial@890000 {
1142                                 compatible = "qcom,geni-uart";
1143                                 reg = <0 0x00890000 0 0x4000>;
1144                                 clock-names = "se";
1145                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1146                                 pinctrl-names = "default";
1147                                 pinctrl-0 = <&qup_uart18_default>;
1148                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1149                                 power-domains = <&rpmhpd SM8250_CX>;
1150                                 operating-points-v2 = <&qup_opp_table>;
1151                                 status = "disabled";
1152                         };
1153
1154                         i2c19: i2c@894000 {
1155                                 compatible = "qcom,geni-i2c";
1156                                 reg = <0 0x00894000 0 0x4000>;
1157                                 clock-names = "se";
1158                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1159                                 pinctrl-names = "default";
1160                                 pinctrl-0 = <&qup_i2c19_default>;
1161                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1162                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1163                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1164                                 dma-names = "tx", "rx";
1165                                 #address-cells = <1>;
1166                                 #size-cells = <0>;
1167                                 status = "disabled";
1168                         };
1169
1170                         spi19: spi@894000 {
1171                                 compatible = "qcom,geni-spi";
1172                                 reg = <0 0x00894000 0 0x4000>;
1173                                 clock-names = "se";
1174                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1175                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1176                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1177                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1178                                 dma-names = "tx", "rx";
1179                                 power-domains = <&rpmhpd SM8250_CX>;
1180                                 operating-points-v2 = <&qup_opp_table>;
1181                                 #address-cells = <1>;
1182                                 #size-cells = <0>;
1183                                 status = "disabled";
1184                         };
1185                 };
1186
1187                 gpi_dma0: dma-controller@900000 {
1188                         compatible = "qcom,sm8250-gpi-dma";
1189                         reg = <0 0x00900000 0 0x70000>;
1190                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1191                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1192                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1193                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1194                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1195                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1196                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1197                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1198                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1199                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1200                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1201                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1202                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1203                         dma-channels = <15>;
1204                         dma-channel-mask = <0x7ff>;
1205                         iommus = <&apps_smmu 0x5b6 0x0>;
1206                         #dma-cells = <3>;
1207                         status = "disabled";
1208                 };
1209
1210                 qupv3_id_0: geniqup@9c0000 {
1211                         compatible = "qcom,geni-se-qup";
1212                         reg = <0x0 0x009c0000 0x0 0x6000>;
1213                         clock-names = "m-ahb", "s-ahb";
1214                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1215                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1216                         #address-cells = <2>;
1217                         #size-cells = <2>;
1218                         iommus = <&apps_smmu 0x5a3 0x0>;
1219                         ranges;
1220                         status = "disabled";
1221
1222                         i2c0: i2c@980000 {
1223                                 compatible = "qcom,geni-i2c";
1224                                 reg = <0 0x00980000 0 0x4000>;
1225                                 clock-names = "se";
1226                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1227                                 pinctrl-names = "default";
1228                                 pinctrl-0 = <&qup_i2c0_default>;
1229                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1230                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1231                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1232                                 dma-names = "tx", "rx";
1233                                 #address-cells = <1>;
1234                                 #size-cells = <0>;
1235                                 status = "disabled";
1236                         };
1237
1238                         spi0: spi@980000 {
1239                                 compatible = "qcom,geni-spi";
1240                                 reg = <0 0x00980000 0 0x4000>;
1241                                 clock-names = "se";
1242                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1243                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1244                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1245                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1246                                 dma-names = "tx", "rx";
1247                                 power-domains = <&rpmhpd SM8250_CX>;
1248                                 operating-points-v2 = <&qup_opp_table>;
1249                                 #address-cells = <1>;
1250                                 #size-cells = <0>;
1251                                 status = "disabled";
1252                         };
1253
1254                         i2c1: i2c@984000 {
1255                                 compatible = "qcom,geni-i2c";
1256                                 reg = <0 0x00984000 0 0x4000>;
1257                                 clock-names = "se";
1258                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1259                                 pinctrl-names = "default";
1260                                 pinctrl-0 = <&qup_i2c1_default>;
1261                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1262                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1263                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1264                                 dma-names = "tx", "rx";
1265                                 #address-cells = <1>;
1266                                 #size-cells = <0>;
1267                                 status = "disabled";
1268                         };
1269
1270                         spi1: spi@984000 {
1271                                 compatible = "qcom,geni-spi";
1272                                 reg = <0 0x00984000 0 0x4000>;
1273                                 clock-names = "se";
1274                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1275                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1276                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1277                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1278                                 dma-names = "tx", "rx";
1279                                 power-domains = <&rpmhpd SM8250_CX>;
1280                                 operating-points-v2 = <&qup_opp_table>;
1281                                 #address-cells = <1>;
1282                                 #size-cells = <0>;
1283                                 status = "disabled";
1284                         };
1285
1286                         i2c2: i2c@988000 {
1287                                 compatible = "qcom,geni-i2c";
1288                                 reg = <0 0x00988000 0 0x4000>;
1289                                 clock-names = "se";
1290                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1291                                 pinctrl-names = "default";
1292                                 pinctrl-0 = <&qup_i2c2_default>;
1293                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1294                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1295                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1296                                 dma-names = "tx", "rx";
1297                                 #address-cells = <1>;
1298                                 #size-cells = <0>;
1299                                 status = "disabled";
1300                         };
1301
1302                         spi2: spi@988000 {
1303                                 compatible = "qcom,geni-spi";
1304                                 reg = <0 0x00988000 0 0x4000>;
1305                                 clock-names = "se";
1306                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1307                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1308                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1309                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1310                                 dma-names = "tx", "rx";
1311                                 power-domains = <&rpmhpd SM8250_CX>;
1312                                 operating-points-v2 = <&qup_opp_table>;
1313                                 #address-cells = <1>;
1314                                 #size-cells = <0>;
1315                                 status = "disabled";
1316                         };
1317
1318                         uart2: serial@988000 {
1319                                 compatible = "qcom,geni-debug-uart";
1320                                 reg = <0 0x00988000 0 0x4000>;
1321                                 clock-names = "se";
1322                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1323                                 pinctrl-names = "default";
1324                                 pinctrl-0 = <&qup_uart2_default>;
1325                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1326                                 power-domains = <&rpmhpd SM8250_CX>;
1327                                 operating-points-v2 = <&qup_opp_table>;
1328                                 status = "disabled";
1329                         };
1330
1331                         i2c3: i2c@98c000 {
1332                                 compatible = "qcom,geni-i2c";
1333                                 reg = <0 0x0098c000 0 0x4000>;
1334                                 clock-names = "se";
1335                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1336                                 pinctrl-names = "default";
1337                                 pinctrl-0 = <&qup_i2c3_default>;
1338                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1339                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1340                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1341                                 dma-names = "tx", "rx";
1342                                 #address-cells = <1>;
1343                                 #size-cells = <0>;
1344                                 status = "disabled";
1345                         };
1346
1347                         spi3: spi@98c000 {
1348                                 compatible = "qcom,geni-spi";
1349                                 reg = <0 0x0098c000 0 0x4000>;
1350                                 clock-names = "se";
1351                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1352                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1353                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1354                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1355                                 dma-names = "tx", "rx";
1356                                 power-domains = <&rpmhpd SM8250_CX>;
1357                                 operating-points-v2 = <&qup_opp_table>;
1358                                 #address-cells = <1>;
1359                                 #size-cells = <0>;
1360                                 status = "disabled";
1361                         };
1362
1363                         i2c4: i2c@990000 {
1364                                 compatible = "qcom,geni-i2c";
1365                                 reg = <0 0x00990000 0 0x4000>;
1366                                 clock-names = "se";
1367                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1368                                 pinctrl-names = "default";
1369                                 pinctrl-0 = <&qup_i2c4_default>;
1370                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1371                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1372                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1373                                 dma-names = "tx", "rx";
1374                                 #address-cells = <1>;
1375                                 #size-cells = <0>;
1376                                 status = "disabled";
1377                         };
1378
1379                         spi4: spi@990000 {
1380                                 compatible = "qcom,geni-spi";
1381                                 reg = <0 0x00990000 0 0x4000>;
1382                                 clock-names = "se";
1383                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1384                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1385                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1386                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1387                                 dma-names = "tx", "rx";
1388                                 power-domains = <&rpmhpd SM8250_CX>;
1389                                 operating-points-v2 = <&qup_opp_table>;
1390                                 #address-cells = <1>;
1391                                 #size-cells = <0>;
1392                                 status = "disabled";
1393                         };
1394
1395                         i2c5: i2c@994000 {
1396                                 compatible = "qcom,geni-i2c";
1397                                 reg = <0 0x00994000 0 0x4000>;
1398                                 clock-names = "se";
1399                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1400                                 pinctrl-names = "default";
1401                                 pinctrl-0 = <&qup_i2c5_default>;
1402                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1403                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1404                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1405                                 dma-names = "tx", "rx";
1406                                 #address-cells = <1>;
1407                                 #size-cells = <0>;
1408                                 status = "disabled";
1409                         };
1410
1411                         spi5: spi@994000 {
1412                                 compatible = "qcom,geni-spi";
1413                                 reg = <0 0x00994000 0 0x4000>;
1414                                 clock-names = "se";
1415                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1416                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1417                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1418                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1419                                 dma-names = "tx", "rx";
1420                                 power-domains = <&rpmhpd SM8250_CX>;
1421                                 operating-points-v2 = <&qup_opp_table>;
1422                                 #address-cells = <1>;
1423                                 #size-cells = <0>;
1424                                 status = "disabled";
1425                         };
1426
1427                         i2c6: i2c@998000 {
1428                                 compatible = "qcom,geni-i2c";
1429                                 reg = <0 0x00998000 0 0x4000>;
1430                                 clock-names = "se";
1431                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1432                                 pinctrl-names = "default";
1433                                 pinctrl-0 = <&qup_i2c6_default>;
1434                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1435                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1436                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1437                                 dma-names = "tx", "rx";
1438                                 #address-cells = <1>;
1439                                 #size-cells = <0>;
1440                                 status = "disabled";
1441                         };
1442
1443                         spi6: spi@998000 {
1444                                 compatible = "qcom,geni-spi";
1445                                 reg = <0 0x00998000 0 0x4000>;
1446                                 clock-names = "se";
1447                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1448                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1449                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1450                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1451                                 dma-names = "tx", "rx";
1452                                 power-domains = <&rpmhpd SM8250_CX>;
1453                                 operating-points-v2 = <&qup_opp_table>;
1454                                 #address-cells = <1>;
1455                                 #size-cells = <0>;
1456                                 status = "disabled";
1457                         };
1458
1459                         uart6: serial@998000 {
1460                                 compatible = "qcom,geni-uart";
1461                                 reg = <0 0x00998000 0 0x4000>;
1462                                 clock-names = "se";
1463                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1464                                 pinctrl-names = "default";
1465                                 pinctrl-0 = <&qup_uart6_default>;
1466                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1467                                 power-domains = <&rpmhpd SM8250_CX>;
1468                                 operating-points-v2 = <&qup_opp_table>;
1469                                 status = "disabled";
1470                         };
1471
1472                         i2c7: i2c@99c000 {
1473                                 compatible = "qcom,geni-i2c";
1474                                 reg = <0 0x0099c000 0 0x4000>;
1475                                 clock-names = "se";
1476                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1477                                 pinctrl-names = "default";
1478                                 pinctrl-0 = <&qup_i2c7_default>;
1479                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1480                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1481                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1482                                 dma-names = "tx", "rx";
1483                                 #address-cells = <1>;
1484                                 #size-cells = <0>;
1485                                 status = "disabled";
1486                         };
1487
1488                         spi7: spi@99c000 {
1489                                 compatible = "qcom,geni-spi";
1490                                 reg = <0 0x0099c000 0 0x4000>;
1491                                 clock-names = "se";
1492                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1493                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1494                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1495                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1496                                 dma-names = "tx", "rx";
1497                                 power-domains = <&rpmhpd SM8250_CX>;
1498                                 operating-points-v2 = <&qup_opp_table>;
1499                                 #address-cells = <1>;
1500                                 #size-cells = <0>;
1501                                 status = "disabled";
1502                         };
1503                 };
1504
1505                 gpi_dma1: dma-controller@a00000 {
1506                         compatible = "qcom,sm8250-gpi-dma";
1507                         reg = <0 0x00a00000 0 0x70000>;
1508                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1509                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1510                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1511                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1512                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1513                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1514                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1515                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1516                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1517                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1518                         dma-channels = <10>;
1519                         dma-channel-mask = <0x3f>;
1520                         iommus = <&apps_smmu 0x56 0x0>;
1521                         #dma-cells = <3>;
1522                         status = "disabled";
1523                 };
1524
1525                 qupv3_id_1: geniqup@ac0000 {
1526                         compatible = "qcom,geni-se-qup";
1527                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1528                         clock-names = "m-ahb", "s-ahb";
1529                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1530                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1531                         #address-cells = <2>;
1532                         #size-cells = <2>;
1533                         iommus = <&apps_smmu 0x43 0x0>;
1534                         ranges;
1535                         status = "disabled";
1536
1537                         i2c8: i2c@a80000 {
1538                                 compatible = "qcom,geni-i2c";
1539                                 reg = <0 0x00a80000 0 0x4000>;
1540                                 clock-names = "se";
1541                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1542                                 pinctrl-names = "default";
1543                                 pinctrl-0 = <&qup_i2c8_default>;
1544                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1545                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1546                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1547                                 dma-names = "tx", "rx";
1548                                 #address-cells = <1>;
1549                                 #size-cells = <0>;
1550                                 status = "disabled";
1551                         };
1552
1553                         spi8: spi@a80000 {
1554                                 compatible = "qcom,geni-spi";
1555                                 reg = <0 0x00a80000 0 0x4000>;
1556                                 clock-names = "se";
1557                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1558                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1559                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1560                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1561                                 dma-names = "tx", "rx";
1562                                 power-domains = <&rpmhpd SM8250_CX>;
1563                                 operating-points-v2 = <&qup_opp_table>;
1564                                 #address-cells = <1>;
1565                                 #size-cells = <0>;
1566                                 status = "disabled";
1567                         };
1568
1569                         i2c9: i2c@a84000 {
1570                                 compatible = "qcom,geni-i2c";
1571                                 reg = <0 0x00a84000 0 0x4000>;
1572                                 clock-names = "se";
1573                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1574                                 pinctrl-names = "default";
1575                                 pinctrl-0 = <&qup_i2c9_default>;
1576                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1577                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1578                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1579                                 dma-names = "tx", "rx";
1580                                 #address-cells = <1>;
1581                                 #size-cells = <0>;
1582                                 status = "disabled";
1583                         };
1584
1585                         spi9: spi@a84000 {
1586                                 compatible = "qcom,geni-spi";
1587                                 reg = <0 0x00a84000 0 0x4000>;
1588                                 clock-names = "se";
1589                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1590                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1591                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1592                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1593                                 dma-names = "tx", "rx";
1594                                 power-domains = <&rpmhpd SM8250_CX>;
1595                                 operating-points-v2 = <&qup_opp_table>;
1596                                 #address-cells = <1>;
1597                                 #size-cells = <0>;
1598                                 status = "disabled";
1599                         };
1600
1601                         i2c10: i2c@a88000 {
1602                                 compatible = "qcom,geni-i2c";
1603                                 reg = <0 0x00a88000 0 0x4000>;
1604                                 clock-names = "se";
1605                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1606                                 pinctrl-names = "default";
1607                                 pinctrl-0 = <&qup_i2c10_default>;
1608                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1609                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1610                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1611                                 dma-names = "tx", "rx";
1612                                 #address-cells = <1>;
1613                                 #size-cells = <0>;
1614                                 status = "disabled";
1615                         };
1616
1617                         spi10: spi@a88000 {
1618                                 compatible = "qcom,geni-spi";
1619                                 reg = <0 0x00a88000 0 0x4000>;
1620                                 clock-names = "se";
1621                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1622                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1623                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1624                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1625                                 dma-names = "tx", "rx";
1626                                 power-domains = <&rpmhpd SM8250_CX>;
1627                                 operating-points-v2 = <&qup_opp_table>;
1628                                 #address-cells = <1>;
1629                                 #size-cells = <0>;
1630                                 status = "disabled";
1631                         };
1632
1633                         i2c11: i2c@a8c000 {
1634                                 compatible = "qcom,geni-i2c";
1635                                 reg = <0 0x00a8c000 0 0x4000>;
1636                                 clock-names = "se";
1637                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1638                                 pinctrl-names = "default";
1639                                 pinctrl-0 = <&qup_i2c11_default>;
1640                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1641                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1642                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1643                                 dma-names = "tx", "rx";
1644                                 #address-cells = <1>;
1645                                 #size-cells = <0>;
1646                                 status = "disabled";
1647                         };
1648
1649                         spi11: spi@a8c000 {
1650                                 compatible = "qcom,geni-spi";
1651                                 reg = <0 0x00a8c000 0 0x4000>;
1652                                 clock-names = "se";
1653                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1654                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1655                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1656                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1657                                 dma-names = "tx", "rx";
1658                                 power-domains = <&rpmhpd SM8250_CX>;
1659                                 operating-points-v2 = <&qup_opp_table>;
1660                                 #address-cells = <1>;
1661                                 #size-cells = <0>;
1662                                 status = "disabled";
1663                         };
1664
1665                         i2c12: i2c@a90000 {
1666                                 compatible = "qcom,geni-i2c";
1667                                 reg = <0 0x00a90000 0 0x4000>;
1668                                 clock-names = "se";
1669                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1670                                 pinctrl-names = "default";
1671                                 pinctrl-0 = <&qup_i2c12_default>;
1672                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1673                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1674                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1675                                 dma-names = "tx", "rx";
1676                                 #address-cells = <1>;
1677                                 #size-cells = <0>;
1678                                 status = "disabled";
1679                         };
1680
1681                         spi12: spi@a90000 {
1682                                 compatible = "qcom,geni-spi";
1683                                 reg = <0 0x00a90000 0 0x4000>;
1684                                 clock-names = "se";
1685                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1686                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1687                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1688                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1689                                 dma-names = "tx", "rx";
1690                                 power-domains = <&rpmhpd SM8250_CX>;
1691                                 operating-points-v2 = <&qup_opp_table>;
1692                                 #address-cells = <1>;
1693                                 #size-cells = <0>;
1694                                 status = "disabled";
1695                         };
1696
1697                         uart12: serial@a90000 {
1698                                 compatible = "qcom,geni-debug-uart";
1699                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1700                                 clock-names = "se";
1701                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1702                                 pinctrl-names = "default";
1703                                 pinctrl-0 = <&qup_uart12_default>;
1704                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1705                                 power-domains = <&rpmhpd SM8250_CX>;
1706                                 operating-points-v2 = <&qup_opp_table>;
1707                                 status = "disabled";
1708                         };
1709
1710                         i2c13: i2c@a94000 {
1711                                 compatible = "qcom,geni-i2c";
1712                                 reg = <0 0x00a94000 0 0x4000>;
1713                                 clock-names = "se";
1714                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1715                                 pinctrl-names = "default";
1716                                 pinctrl-0 = <&qup_i2c13_default>;
1717                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1718                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1719                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1720                                 dma-names = "tx", "rx";
1721                                 #address-cells = <1>;
1722                                 #size-cells = <0>;
1723                                 status = "disabled";
1724                         };
1725
1726                         spi13: spi@a94000 {
1727                                 compatible = "qcom,geni-spi";
1728                                 reg = <0 0x00a94000 0 0x4000>;
1729                                 clock-names = "se";
1730                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1731                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1732                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1733                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1734                                 dma-names = "tx", "rx";
1735                                 power-domains = <&rpmhpd SM8250_CX>;
1736                                 operating-points-v2 = <&qup_opp_table>;
1737                                 #address-cells = <1>;
1738                                 #size-cells = <0>;
1739                                 status = "disabled";
1740                         };
1741                 };
1742
1743                 config_noc: interconnect@1500000 {
1744                         compatible = "qcom,sm8250-config-noc";
1745                         reg = <0 0x01500000 0 0xa580>;
1746                         #interconnect-cells = <1>;
1747                         qcom,bcm-voters = <&apps_bcm_voter>;
1748                 };
1749
1750                 system_noc: interconnect@1620000 {
1751                         compatible = "qcom,sm8250-system-noc";
1752                         reg = <0 0x01620000 0 0x1c200>;
1753                         #interconnect-cells = <1>;
1754                         qcom,bcm-voters = <&apps_bcm_voter>;
1755                 };
1756
1757                 mc_virt: interconnect@163d000 {
1758                         compatible = "qcom,sm8250-mc-virt";
1759                         reg = <0 0x0163d000 0 0x1000>;
1760                         #interconnect-cells = <1>;
1761                         qcom,bcm-voters = <&apps_bcm_voter>;
1762                 };
1763
1764                 aggre1_noc: interconnect@16e0000 {
1765                         compatible = "qcom,sm8250-aggre1-noc";
1766                         reg = <0 0x016e0000 0 0x1f180>;
1767                         #interconnect-cells = <1>;
1768                         qcom,bcm-voters = <&apps_bcm_voter>;
1769                 };
1770
1771                 aggre2_noc: interconnect@1700000 {
1772                         compatible = "qcom,sm8250-aggre2-noc";
1773                         reg = <0 0x01700000 0 0x33000>;
1774                         #interconnect-cells = <1>;
1775                         qcom,bcm-voters = <&apps_bcm_voter>;
1776                 };
1777
1778                 compute_noc: interconnect@1733000 {
1779                         compatible = "qcom,sm8250-compute-noc";
1780                         reg = <0 0x01733000 0 0xa180>;
1781                         #interconnect-cells = <1>;
1782                         qcom,bcm-voters = <&apps_bcm_voter>;
1783                 };
1784
1785                 mmss_noc: interconnect@1740000 {
1786                         compatible = "qcom,sm8250-mmss-noc";
1787                         reg = <0 0x01740000 0 0x1f080>;
1788                         #interconnect-cells = <1>;
1789                         qcom,bcm-voters = <&apps_bcm_voter>;
1790                 };
1791
1792                 pcie0: pci@1c00000 {
1793                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1794                         reg = <0 0x01c00000 0 0x3000>,
1795                               <0 0x60000000 0 0xf1d>,
1796                               <0 0x60000f20 0 0xa8>,
1797                               <0 0x60001000 0 0x1000>,
1798                               <0 0x60100000 0 0x100000>;
1799                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1800                         device_type = "pci";
1801                         linux,pci-domain = <0>;
1802                         bus-range = <0x00 0xff>;
1803                         num-lanes = <1>;
1804
1805                         #address-cells = <3>;
1806                         #size-cells = <2>;
1807
1808                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1809                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1810
1811                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1812                         interrupt-names = "msi";
1813                         #interrupt-cells = <1>;
1814                         interrupt-map-mask = <0 0 0 0x7>;
1815                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1816                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1817                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1818                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1819
1820                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1821                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1822                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1823                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1824                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1825                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1826                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1827                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1828                         clock-names = "pipe",
1829                                       "aux",
1830                                       "cfg",
1831                                       "bus_master",
1832                                       "bus_slave",
1833                                       "slave_q2a",
1834                                       "tbu",
1835                                       "ddrss_sf_tbu";
1836
1837                         iommus = <&apps_smmu 0x1c00 0x7f>;
1838                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1839                                     <0x100 &apps_smmu 0x1c01 0x1>;
1840
1841                         resets = <&gcc GCC_PCIE_0_BCR>;
1842                         reset-names = "pci";
1843
1844                         power-domains = <&gcc PCIE_0_GDSC>;
1845
1846                         phys = <&pcie0_lane>;
1847                         phy-names = "pciephy";
1848
1849                         perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
1850                         wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1851
1852                         pinctrl-names = "default";
1853                         pinctrl-0 = <&pcie0_default_state>;
1854
1855                         status = "disabled";
1856                 };
1857
1858                 pcie0_phy: phy@1c06000 {
1859                         compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1860                         reg = <0 0x01c06000 0 0x1c0>;
1861                         #address-cells = <2>;
1862                         #size-cells = <2>;
1863                         ranges;
1864                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1865                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1866                                  <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1867                                  <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1868                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1869
1870                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1871                         reset-names = "phy";
1872
1873                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1874                         assigned-clock-rates = <100000000>;
1875
1876                         status = "disabled";
1877
1878                         pcie0_lane: phy@1c06200 {
1879                                 reg = <0 0x1c06200 0 0x170>, /* tx */
1880                                       <0 0x1c06400 0 0x200>, /* rx */
1881                                       <0 0x1c06800 0 0x1f0>, /* pcs */
1882                                       <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1883                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1884                                 clock-names = "pipe0";
1885
1886                                 #phy-cells = <0>;
1887                                 clock-output-names = "pcie_0_pipe_clk";
1888                         };
1889                 };
1890
1891                 pcie1: pci@1c08000 {
1892                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1893                         reg = <0 0x01c08000 0 0x3000>,
1894                               <0 0x40000000 0 0xf1d>,
1895                               <0 0x40000f20 0 0xa8>,
1896                               <0 0x40001000 0 0x1000>,
1897                               <0 0x40100000 0 0x100000>;
1898                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1899                         device_type = "pci";
1900                         linux,pci-domain = <1>;
1901                         bus-range = <0x00 0xff>;
1902                         num-lanes = <2>;
1903
1904                         #address-cells = <3>;
1905                         #size-cells = <2>;
1906
1907                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1908                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1909
1910                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1911                         interrupt-names = "msi";
1912                         #interrupt-cells = <1>;
1913                         interrupt-map-mask = <0 0 0 0x7>;
1914                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1915                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1916                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1917                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1918
1919                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1920                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1921                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1922                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1923                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1924                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1925                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1926                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1927                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1928                         clock-names = "pipe",
1929                                       "aux",
1930                                       "cfg",
1931                                       "bus_master",
1932                                       "bus_slave",
1933                                       "slave_q2a",
1934                                       "ref",
1935                                       "tbu",
1936                                       "ddrss_sf_tbu";
1937
1938                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1939                         assigned-clock-rates = <19200000>;
1940
1941                         iommus = <&apps_smmu 0x1c80 0x7f>;
1942                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1943                                     <0x100 &apps_smmu 0x1c81 0x1>;
1944
1945                         resets = <&gcc GCC_PCIE_1_BCR>;
1946                         reset-names = "pci";
1947
1948                         power-domains = <&gcc PCIE_1_GDSC>;
1949
1950                         phys = <&pcie1_lane>;
1951                         phy-names = "pciephy";
1952
1953                         perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
1954                         wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
1955
1956                         pinctrl-names = "default";
1957                         pinctrl-0 = <&pcie1_default_state>;
1958
1959                         status = "disabled";
1960                 };
1961
1962                 pcie1_phy: phy@1c0e000 {
1963                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1964                         reg = <0 0x01c0e000 0 0x1c0>;
1965                         #address-cells = <2>;
1966                         #size-cells = <2>;
1967                         ranges;
1968                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1969                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1970                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1971                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1972                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1973
1974                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1975                         reset-names = "phy";
1976
1977                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1978                         assigned-clock-rates = <100000000>;
1979
1980                         status = "disabled";
1981
1982                         pcie1_lane: phy@1c0e200 {
1983                                 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1984                                       <0 0x1c0e400 0 0x200>, /* rx0 */
1985                                       <0 0x1c0ea00 0 0x1f0>, /* pcs */
1986                                       <0 0x1c0e600 0 0x170>, /* tx1 */
1987                                       <0 0x1c0e800 0 0x200>, /* rx1 */
1988                                       <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1989                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1990                                 clock-names = "pipe0";
1991
1992                                 #phy-cells = <0>;
1993                                 clock-output-names = "pcie_1_pipe_clk";
1994                         };
1995                 };
1996
1997                 pcie2: pci@1c10000 {
1998                         compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1999                         reg = <0 0x01c10000 0 0x3000>,
2000                               <0 0x64000000 0 0xf1d>,
2001                               <0 0x64000f20 0 0xa8>,
2002                               <0 0x64001000 0 0x1000>,
2003                               <0 0x64100000 0 0x100000>;
2004                         reg-names = "parf", "dbi", "elbi", "atu", "config";
2005                         device_type = "pci";
2006                         linux,pci-domain = <2>;
2007                         bus-range = <0x00 0xff>;
2008                         num-lanes = <2>;
2009
2010                         #address-cells = <3>;
2011                         #size-cells = <2>;
2012
2013                         ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2014                                  <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2015
2016                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2017                         interrupt-names = "msi";
2018                         #interrupt-cells = <1>;
2019                         interrupt-map-mask = <0 0 0 0x7>;
2020                         interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2021                                         <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2022                                         <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2023                                         <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2024
2025                         clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2026                                  <&gcc GCC_PCIE_2_AUX_CLK>,
2027                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2028                                  <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2029                                  <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2030                                  <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2031                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2032                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2033                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2034                         clock-names = "pipe",
2035                                       "aux",
2036                                       "cfg",
2037                                       "bus_master",
2038                                       "bus_slave",
2039                                       "slave_q2a",
2040                                       "ref",
2041                                       "tbu",
2042                                       "ddrss_sf_tbu";
2043
2044                         assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2045                         assigned-clock-rates = <19200000>;
2046
2047                         iommus = <&apps_smmu 0x1d00 0x7f>;
2048                         iommu-map = <0x0   &apps_smmu 0x1d00 0x1>,
2049                                     <0x100 &apps_smmu 0x1d01 0x1>;
2050
2051                         resets = <&gcc GCC_PCIE_2_BCR>;
2052                         reset-names = "pci";
2053
2054                         power-domains = <&gcc PCIE_2_GDSC>;
2055
2056                         phys = <&pcie2_lane>;
2057                         phy-names = "pciephy";
2058
2059                         perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2060                         wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2061
2062                         pinctrl-names = "default";
2063                         pinctrl-0 = <&pcie2_default_state>;
2064
2065                         status = "disabled";
2066                 };
2067
2068                 pcie2_phy: phy@1c16000 {
2069                         compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2070                         reg = <0 0x1c16000 0 0x1c0>;
2071                         #address-cells = <2>;
2072                         #size-cells = <2>;
2073                         ranges;
2074                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2075                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2076                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2077                                  <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2078                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2079
2080                         resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2081                         reset-names = "phy";
2082
2083                         assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2084                         assigned-clock-rates = <100000000>;
2085
2086                         status = "disabled";
2087
2088                         pcie2_lane: phy@1c16200 {
2089                                 reg = <0 0x1c16200 0 0x170>, /* tx0 */
2090                                       <0 0x1c16400 0 0x200>, /* rx0 */
2091                                       <0 0x1c16a00 0 0x1f0>, /* pcs */
2092                                       <0 0x1c16600 0 0x170>, /* tx1 */
2093                                       <0 0x1c16800 0 0x200>, /* rx1 */
2094                                       <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2095                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
2096                                 clock-names = "pipe0";
2097
2098                                 #phy-cells = <0>;
2099                                 clock-output-names = "pcie_2_pipe_clk";
2100                         };
2101                 };
2102
2103                 ufs_mem_hc: ufshc@1d84000 {
2104                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2105                                      "jedec,ufs-2.0";
2106                         reg = <0 0x01d84000 0 0x3000>;
2107                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2108                         phys = <&ufs_mem_phy_lanes>;
2109                         phy-names = "ufsphy";
2110                         lanes-per-direction = <2>;
2111                         #reset-cells = <1>;
2112                         resets = <&gcc GCC_UFS_PHY_BCR>;
2113                         reset-names = "rst";
2114
2115                         power-domains = <&gcc UFS_PHY_GDSC>;
2116
2117                         iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2118
2119                         clock-names =
2120                                 "core_clk",
2121                                 "bus_aggr_clk",
2122                                 "iface_clk",
2123                                 "core_clk_unipro",
2124                                 "ref_clk",
2125                                 "tx_lane0_sync_clk",
2126                                 "rx_lane0_sync_clk",
2127                                 "rx_lane1_sync_clk";
2128                         clocks =
2129                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2130                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2131                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2132                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2133                                 <&rpmhcc RPMH_CXO_CLK>,
2134                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2135                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2136                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2137                         freq-table-hz =
2138                                 <37500000 300000000>,
2139                                 <0 0>,
2140                                 <0 0>,
2141                                 <37500000 300000000>,
2142                                 <0 0>,
2143                                 <0 0>,
2144                                 <0 0>,
2145                                 <0 0>;
2146
2147                         status = "disabled";
2148                 };
2149
2150                 ufs_mem_phy: phy@1d87000 {
2151                         compatible = "qcom,sm8250-qmp-ufs-phy";
2152                         reg = <0 0x01d87000 0 0x1c0>;
2153                         #address-cells = <2>;
2154                         #size-cells = <2>;
2155                         ranges;
2156                         clock-names = "ref",
2157                                       "ref_aux";
2158                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2159                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2160
2161                         resets = <&ufs_mem_hc 0>;
2162                         reset-names = "ufsphy";
2163                         status = "disabled";
2164
2165                         ufs_mem_phy_lanes: phy@1d87400 {
2166                                 reg = <0 0x01d87400 0 0x108>,
2167                                       <0 0x01d87600 0 0x1e0>,
2168                                       <0 0x01d87c00 0 0x1dc>,
2169                                       <0 0x01d87800 0 0x108>,
2170                                       <0 0x01d87a00 0 0x1e0>;
2171                                 #phy-cells = <0>;
2172                         };
2173                 };
2174
2175                 ipa_virt: interconnect@1e00000 {
2176                         compatible = "qcom,sm8250-ipa-virt";
2177                         reg = <0 0x01e00000 0 0x1000>;
2178                         #interconnect-cells = <1>;
2179                         qcom,bcm-voters = <&apps_bcm_voter>;
2180                 };
2181
2182                 tcsr_mutex: hwlock@1f40000 {
2183                         compatible = "qcom,tcsr-mutex";
2184                         reg = <0x0 0x01f40000 0x0 0x40000>;
2185                         #hwlock-cells = <1>;
2186                 };
2187
2188                 wsamacro: codec@3240000 {
2189                         compatible = "qcom,sm8250-lpass-wsa-macro";
2190                         reg = <0 0x03240000 0 0x1000>;
2191                         clocks = <&audiocc 1>,
2192                                  <&audiocc 0>,
2193                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2194                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2195                                  <&aoncc 0>,
2196                                  <&vamacro>;
2197
2198                         clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2199
2200                         #clock-cells = <0>;
2201                         clock-frequency = <9600000>;
2202                         clock-output-names = "mclk";
2203                         #sound-dai-cells = <1>;
2204
2205                         pinctrl-names = "default";
2206                         pinctrl-0 = <&wsa_swr_active>;
2207                 };
2208
2209                 swr0: soundwire-controller@3250000 {
2210                         reg = <0 0x03250000 0 0x2000>;
2211                         compatible = "qcom,soundwire-v1.5.1";
2212                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2213                         clocks = <&wsamacro>;
2214                         clock-names = "iface";
2215
2216                         qcom,din-ports = <2>;
2217                         qcom,dout-ports = <6>;
2218
2219                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2220                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2221                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2222                         qcom,ports-block-pack-mode =    /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2223
2224                         #sound-dai-cells = <1>;
2225                         #address-cells = <2>;
2226                         #size-cells = <0>;
2227                 };
2228
2229                 audiocc: clock-controller@3300000 {
2230                         compatible = "qcom,sm8250-lpass-audiocc";
2231                         reg = <0 0x03300000 0 0x30000>;
2232                         #clock-cells = <1>;
2233                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2234                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2235                                 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2236                         clock-names = "core", "audio", "bus";
2237                 };
2238
2239                 vamacro: codec@3370000 {
2240                         compatible = "qcom,sm8250-lpass-va-macro";
2241                         reg = <0 0x03370000 0 0x1000>;
2242                         clocks = <&aoncc 0>,
2243                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2244                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2245
2246                         clock-names = "mclk", "macro", "dcodec";
2247
2248                         #clock-cells = <0>;
2249                         clock-frequency = <9600000>;
2250                         clock-output-names = "fsgen";
2251                         #sound-dai-cells = <1>;
2252                 };
2253
2254                 rxmacro: rxmacro@3200000 {
2255                         pinctrl-names = "default";
2256                         pinctrl-0 = <&rx_swr_active>;
2257                         compatible = "qcom,sm8250-lpass-rx-macro";
2258                         reg = <0 0x3200000 0 0x1000>;
2259                         status = "disabled";
2260
2261                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2262                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2263                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2264                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2265                                 <&vamacro>;
2266
2267                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2268
2269                         #clock-cells = <0>;
2270                         clock-frequency = <9600000>;
2271                         clock-output-names = "mclk";
2272                         #sound-dai-cells = <1>;
2273                 };
2274
2275                 swr1: soundwire-controller@3210000 {
2276                         reg = <0 0x3210000 0 0x2000>;
2277                         compatible = "qcom,soundwire-v1.5.1";
2278                         status = "disabled";
2279                         interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2280                         clocks = <&rxmacro>;
2281                         clock-names = "iface";
2282                         label = "RX";
2283                         qcom,din-ports = <0>;
2284                         qcom,dout-ports = <5>;
2285
2286                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
2287                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2288                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2289                         qcom,ports-hstart =             /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
2290                         qcom,ports-hstop =              /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
2291                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
2292                         qcom,ports-block-pack-mode =    /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
2293                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2294                         qcom,ports-block-group-count =  /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
2295
2296                         #sound-dai-cells = <1>;
2297                         #address-cells = <2>;
2298                         #size-cells = <0>;
2299                 };
2300
2301                 txmacro: txmacro@3220000 {
2302                         pinctrl-names = "default";
2303                         pinctrl-0 = <&tx_swr_active>;
2304                         compatible = "qcom,sm8250-lpass-tx-macro";
2305                         reg = <0 0x3220000 0 0x1000>;
2306                         status = "disabled";
2307
2308                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2309                                  <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2310                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2311                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2312                                  <&vamacro>;
2313
2314                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2315
2316                         #clock-cells = <0>;
2317                         clock-frequency = <9600000>;
2318                         clock-output-names = "mclk";
2319                         #address-cells = <2>;
2320                         #size-cells = <2>;
2321                         #sound-dai-cells = <1>;
2322                 };
2323
2324                 /* tx macro */
2325                 swr2: soundwire-controller@3230000 {
2326                         reg = <0 0x3230000 0 0x2000>;
2327                         compatible = "qcom,soundwire-v1.5.1";
2328                         interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2329                         interrupt-names = "core";
2330                         status = "disabled";
2331
2332                         clocks = <&txmacro>;
2333                         clock-names = "iface";
2334                         label = "TX";
2335
2336                         qcom,din-ports = <5>;
2337                         qcom,dout-ports = <0>;
2338                         qcom,ports-sinterval-low =      /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
2339                         qcom,ports-offset1 =            /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
2340                         qcom,ports-offset2 =            /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
2341                         qcom,ports-block-pack-mode =    /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2342                         qcom,ports-hstart =             /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2343                         qcom,ports-hstop =              /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2344                         qcom,ports-word-length =        /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2345                         qcom,ports-block-group-count =  /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2346                         qcom,ports-lane-control =       /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
2347                         qcom,port-offset = <1>;
2348                         #sound-dai-cells = <1>;
2349                         #address-cells = <2>;
2350                         #size-cells = <0>;
2351                 };
2352
2353                 aoncc: clock-controller@3380000 {
2354                         compatible = "qcom,sm8250-lpass-aoncc";
2355                         reg = <0 0x03380000 0 0x40000>;
2356                         #clock-cells = <1>;
2357                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2358                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2359                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2360                         clock-names = "core", "audio", "bus";
2361                 };
2362
2363                 lpass_tlmm: pinctrl@33c0000{
2364                         compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2365                         reg = <0 0x033c0000 0x0 0x20000>,
2366                               <0 0x03550000 0x0 0x10000>;
2367                         gpio-controller;
2368                         #gpio-cells = <2>;
2369                         gpio-ranges = <&lpass_tlmm 0 0 14>;
2370
2371                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2372                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2373                         clock-names = "core", "audio";
2374
2375                         wsa_swr_active: wsa-swr-active-pins {
2376                                 clk {
2377                                         pins = "gpio10";
2378                                         function = "wsa_swr_clk";
2379                                         drive-strength = <2>;
2380                                         slew-rate = <1>;
2381                                         bias-disable;
2382                                 };
2383
2384                                 data {
2385                                         pins = "gpio11";
2386                                         function = "wsa_swr_data";
2387                                         drive-strength = <2>;
2388                                         slew-rate = <1>;
2389                                         bias-bus-hold;
2390
2391                                 };
2392                         };
2393
2394                         wsa_swr_sleep: wsa-swr-sleep-pins {
2395                                 clk {
2396                                         pins = "gpio10";
2397                                         function = "wsa_swr_clk";
2398                                         drive-strength = <2>;
2399                                         input-enable;
2400                                         bias-pull-down;
2401                                 };
2402
2403                                 data {
2404                                         pins = "gpio11";
2405                                         function = "wsa_swr_data";
2406                                         drive-strength = <2>;
2407                                         input-enable;
2408                                         bias-pull-down;
2409
2410                                 };
2411                         };
2412
2413                         dmic01_active: dmic01-active-pins {
2414                                 clk {
2415                                         pins = "gpio6";
2416                                         function = "dmic1_clk";
2417                                         drive-strength = <8>;
2418                                         output-high;
2419                                 };
2420                                 data {
2421                                         pins = "gpio7";
2422                                         function = "dmic1_data";
2423                                         drive-strength = <8>;
2424                                         input-enable;
2425                                 };
2426                         };
2427
2428                         dmic01_sleep: dmic01-sleep-pins {
2429                                 clk {
2430                                         pins = "gpio6";
2431                                         function = "dmic1_clk";
2432                                         drive-strength = <2>;
2433                                         bias-disable;
2434                                         output-low;
2435                                 };
2436
2437                                 data {
2438                                         pins = "gpio7";
2439                                         function = "dmic1_data";
2440                                         drive-strength = <2>;
2441                                         pull-down;
2442                                         input-enable;
2443                                 };
2444                         };
2445
2446                         rx_swr_active: rx_swr-active-pins {
2447                                 clk {
2448                                         pins = "gpio3";
2449                                         function = "swr_rx_clk";
2450                                         drive-strength = <2>;
2451                                         slew-rate = <1>;
2452                                         bias-disable;
2453                                 };
2454
2455                                 data {
2456                                         pins = "gpio4", "gpio5";
2457                                         function = "swr_rx_data";
2458                                         drive-strength = <2>;
2459                                         slew-rate = <1>;
2460                                         bias-bus-hold;
2461                                 };
2462                         };
2463
2464                         tx_swr_active: tx_swr-active-pins {
2465                                 clk {
2466                                         pins = "gpio0";
2467                                         function = "swr_tx_clk";
2468                                         drive-strength = <2>;
2469                                         slew-rate = <1>;
2470                                         bias-disable;
2471                                 };
2472
2473                                 data {
2474                                         pins = "gpio1", "gpio2";
2475                                         function = "swr_tx_data";
2476                                         drive-strength = <2>;
2477                                         slew-rate = <1>;
2478                                         bias-bus-hold;
2479                                 };
2480                         };
2481
2482                         tx_swr_sleep: tx_swr-sleep-pins {
2483                                 clk {
2484                                         pins = "gpio0";
2485                                         function = "swr_tx_clk";
2486                                         drive-strength = <2>;
2487                                         input-enable;
2488                                         bias-pull-down;
2489                                 };
2490
2491                                 data1 {
2492                                         pins = "gpio1";
2493                                         function = "swr_tx_data";
2494                                         drive-strength = <2>;
2495                                         input-enable;
2496                                         bias-bus-hold;
2497                                 };
2498
2499                                 data2 {
2500                                         pins = "gpio2";
2501                                         function = "swr_tx_data";
2502                                         drive-strength = <2>;
2503                                         input-enable;
2504                                         bias-pull-down;
2505                                 };
2506                         };
2507                 };
2508
2509                 gpu: gpu@3d00000 {
2510                         compatible = "qcom,adreno-650.2",
2511                                      "qcom,adreno";
2512
2513                         reg = <0 0x03d00000 0 0x40000>;
2514                         reg-names = "kgsl_3d0_reg_memory";
2515
2516                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2517
2518                         iommus = <&adreno_smmu 0 0x401>;
2519
2520                         operating-points-v2 = <&gpu_opp_table>;
2521
2522                         qcom,gmu = <&gmu>;
2523
2524                         status = "disabled";
2525
2526                         zap-shader {
2527                                 memory-region = <&gpu_mem>;
2528                         };
2529
2530                         /* note: downstream checks gpu binning for 670 Mhz */
2531                         gpu_opp_table: opp-table {
2532                                 compatible = "operating-points-v2";
2533
2534                                 opp-670000000 {
2535                                         opp-hz = /bits/ 64 <670000000>;
2536                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2537                                 };
2538
2539                                 opp-587000000 {
2540                                         opp-hz = /bits/ 64 <587000000>;
2541                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2542                                 };
2543
2544                                 opp-525000000 {
2545                                         opp-hz = /bits/ 64 <525000000>;
2546                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2547                                 };
2548
2549                                 opp-490000000 {
2550                                         opp-hz = /bits/ 64 <490000000>;
2551                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2552                                 };
2553
2554                                 opp-441600000 {
2555                                         opp-hz = /bits/ 64 <441600000>;
2556                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2557                                 };
2558
2559                                 opp-400000000 {
2560                                         opp-hz = /bits/ 64 <400000000>;
2561                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2562                                 };
2563
2564                                 opp-305000000 {
2565                                         opp-hz = /bits/ 64 <305000000>;
2566                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2567                                 };
2568                         };
2569                 };
2570
2571                 gmu: gmu@3d6a000 {
2572                         compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2573
2574                         reg = <0 0x03d6a000 0 0x30000>,
2575                               <0 0x3de0000 0 0x10000>,
2576                               <0 0xb290000 0 0x10000>,
2577                               <0 0xb490000 0 0x10000>;
2578                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2579
2580                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2581                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2582                         interrupt-names = "hfi", "gmu";
2583
2584                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2585                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2586                                  <&gpucc GPU_CC_CXO_CLK>,
2587                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2588                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2589                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2590
2591                         power-domains = <&gpucc GPU_CX_GDSC>,
2592                                         <&gpucc GPU_GX_GDSC>;
2593                         power-domain-names = "cx", "gx";
2594
2595                         iommus = <&adreno_smmu 5 0x400>;
2596
2597                         operating-points-v2 = <&gmu_opp_table>;
2598
2599                         status = "disabled";
2600
2601                         gmu_opp_table: opp-table {
2602                                 compatible = "operating-points-v2";
2603
2604                                 opp-200000000 {
2605                                         opp-hz = /bits/ 64 <200000000>;
2606                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2607                                 };
2608                         };
2609                 };
2610
2611                 gpucc: clock-controller@3d90000 {
2612                         compatible = "qcom,sm8250-gpucc";
2613                         reg = <0 0x03d90000 0 0x9000>;
2614                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2615                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2616                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2617                         clock-names = "bi_tcxo",
2618                                       "gcc_gpu_gpll0_clk_src",
2619                                       "gcc_gpu_gpll0_div_clk_src";
2620                         #clock-cells = <1>;
2621                         #reset-cells = <1>;
2622                         #power-domain-cells = <1>;
2623                 };
2624
2625                 adreno_smmu: iommu@3da0000 {
2626                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
2627                         reg = <0 0x03da0000 0 0x10000>;
2628                         #iommu-cells = <2>;
2629                         #global-interrupts = <2>;
2630                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2631                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2632                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2633                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2634                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2635                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2636                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2637                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2638                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2639                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
2640                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2641                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2642                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2643                         clock-names = "ahb", "bus", "iface";
2644
2645                         power-domains = <&gpucc GPU_CX_GDSC>;
2646                 };
2647
2648                 slpi: remoteproc@5c00000 {
2649                         compatible = "qcom,sm8250-slpi-pas";
2650                         reg = <0 0x05c00000 0 0x4000>;
2651
2652                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2653                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2654                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2655                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2656                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2657                         interrupt-names = "wdog", "fatal", "ready",
2658                                           "handover", "stop-ack";
2659
2660                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2661                         clock-names = "xo";
2662
2663                         power-domains = <&rpmhpd SM8250_LCX>,
2664                                         <&rpmhpd SM8250_LMX>;
2665                         power-domain-names = "lcx", "lmx";
2666
2667                         memory-region = <&slpi_mem>;
2668
2669                         qcom,qmp = <&aoss_qmp>;
2670
2671                         qcom,smem-states = <&smp2p_slpi_out 0>;
2672                         qcom,smem-state-names = "stop";
2673
2674                         status = "disabled";
2675
2676                         glink-edge {
2677                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2678                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2679                                                              IRQ_TYPE_EDGE_RISING>;
2680                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2681                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2682
2683                                 label = "slpi";
2684                                 qcom,remote-pid = <3>;
2685
2686                                 fastrpc {
2687                                         compatible = "qcom,fastrpc";
2688                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2689                                         label = "sdsp";
2690                                         qcom,non-secure-domain;
2691                                         #address-cells = <1>;
2692                                         #size-cells = <0>;
2693
2694                                         compute-cb@1 {
2695                                                 compatible = "qcom,fastrpc-compute-cb";
2696                                                 reg = <1>;
2697                                                 iommus = <&apps_smmu 0x0541 0x0>;
2698                                         };
2699
2700                                         compute-cb@2 {
2701                                                 compatible = "qcom,fastrpc-compute-cb";
2702                                                 reg = <2>;
2703                                                 iommus = <&apps_smmu 0x0542 0x0>;
2704                                         };
2705
2706                                         compute-cb@3 {
2707                                                 compatible = "qcom,fastrpc-compute-cb";
2708                                                 reg = <3>;
2709                                                 iommus = <&apps_smmu 0x0543 0x0>;
2710                                                 /* note: shared-cb = <4> in downstream */
2711                                         };
2712                                 };
2713                         };
2714                 };
2715
2716                 cdsp: remoteproc@8300000 {
2717                         compatible = "qcom,sm8250-cdsp-pas";
2718                         reg = <0 0x08300000 0 0x10000>;
2719
2720                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2721                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2722                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2723                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2724                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2725                         interrupt-names = "wdog", "fatal", "ready",
2726                                           "handover", "stop-ack";
2727
2728                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2729                         clock-names = "xo";
2730
2731                         power-domains = <&rpmhpd SM8250_CX>;
2732
2733                         memory-region = <&cdsp_mem>;
2734
2735                         qcom,qmp = <&aoss_qmp>;
2736
2737                         qcom,smem-states = <&smp2p_cdsp_out 0>;
2738                         qcom,smem-state-names = "stop";
2739
2740                         status = "disabled";
2741
2742                         glink-edge {
2743                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2744                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2745                                                              IRQ_TYPE_EDGE_RISING>;
2746                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2747                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2748
2749                                 label = "cdsp";
2750                                 qcom,remote-pid = <5>;
2751
2752                                 fastrpc {
2753                                         compatible = "qcom,fastrpc";
2754                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2755                                         label = "cdsp";
2756                                         qcom,non-secure-domain;
2757                                         #address-cells = <1>;
2758                                         #size-cells = <0>;
2759
2760                                         compute-cb@1 {
2761                                                 compatible = "qcom,fastrpc-compute-cb";
2762                                                 reg = <1>;
2763                                                 iommus = <&apps_smmu 0x1001 0x0460>;
2764                                         };
2765
2766                                         compute-cb@2 {
2767                                                 compatible = "qcom,fastrpc-compute-cb";
2768                                                 reg = <2>;
2769                                                 iommus = <&apps_smmu 0x1002 0x0460>;
2770                                         };
2771
2772                                         compute-cb@3 {
2773                                                 compatible = "qcom,fastrpc-compute-cb";
2774                                                 reg = <3>;
2775                                                 iommus = <&apps_smmu 0x1003 0x0460>;
2776                                         };
2777
2778                                         compute-cb@4 {
2779                                                 compatible = "qcom,fastrpc-compute-cb";
2780                                                 reg = <4>;
2781                                                 iommus = <&apps_smmu 0x1004 0x0460>;
2782                                         };
2783
2784                                         compute-cb@5 {
2785                                                 compatible = "qcom,fastrpc-compute-cb";
2786                                                 reg = <5>;
2787                                                 iommus = <&apps_smmu 0x1005 0x0460>;
2788                                         };
2789
2790                                         compute-cb@6 {
2791                                                 compatible = "qcom,fastrpc-compute-cb";
2792                                                 reg = <6>;
2793                                                 iommus = <&apps_smmu 0x1006 0x0460>;
2794                                         };
2795
2796                                         compute-cb@7 {
2797                                                 compatible = "qcom,fastrpc-compute-cb";
2798                                                 reg = <7>;
2799                                                 iommus = <&apps_smmu 0x1007 0x0460>;
2800                                         };
2801
2802                                         compute-cb@8 {
2803                                                 compatible = "qcom,fastrpc-compute-cb";
2804                                                 reg = <8>;
2805                                                 iommus = <&apps_smmu 0x1008 0x0460>;
2806                                         };
2807
2808                                         /* note: secure cb9 in downstream */
2809                                 };
2810                         };
2811                 };
2812
2813                 sound: sound {
2814                 };
2815
2816                 usb_1_hsphy: phy@88e3000 {
2817                         compatible = "qcom,sm8250-usb-hs-phy",
2818                                      "qcom,usb-snps-hs-7nm-phy";
2819                         reg = <0 0x088e3000 0 0x400>;
2820                         status = "disabled";
2821                         #phy-cells = <0>;
2822
2823                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2824                         clock-names = "ref";
2825
2826                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2827                 };
2828
2829                 usb_2_hsphy: phy@88e4000 {
2830                         compatible = "qcom,sm8250-usb-hs-phy",
2831                                      "qcom,usb-snps-hs-7nm-phy";
2832                         reg = <0 0x088e4000 0 0x400>;
2833                         status = "disabled";
2834                         #phy-cells = <0>;
2835
2836                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2837                         clock-names = "ref";
2838
2839                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2840                 };
2841
2842                 usb_1_qmpphy: phy@88e9000 {
2843                         compatible = "qcom,sm8250-qmp-usb3-dp-phy";
2844                         reg = <0 0x088e9000 0 0x200>,
2845                               <0 0x088e8000 0 0x40>,
2846                               <0 0x088ea000 0 0x200>;
2847                         status = "disabled";
2848                         #address-cells = <2>;
2849                         #size-cells = <2>;
2850                         ranges;
2851
2852                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2853                                  <&rpmhcc RPMH_CXO_CLK>,
2854                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2855                         clock-names = "aux", "ref_clk_src", "com_aux";
2856
2857                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2858                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2859                         reset-names = "phy", "common";
2860
2861                         usb_1_ssphy: usb3-phy@88e9200 {
2862                                 reg = <0 0x088e9200 0 0x200>,
2863                                       <0 0x088e9400 0 0x200>,
2864                                       <0 0x088e9c00 0 0x400>,
2865                                       <0 0x088e9600 0 0x200>,
2866                                       <0 0x088e9800 0 0x200>,
2867                                       <0 0x088e9a00 0 0x100>;
2868                                 #clock-cells = <0>;
2869                                 #phy-cells = <0>;
2870                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2871                                 clock-names = "pipe0";
2872                                 clock-output-names = "usb3_phy_pipe_clk_src";
2873                         };
2874
2875                         dp_phy: dp-phy@88ea200 {
2876                                 reg = <0 0x088ea200 0 0x200>,
2877                                       <0 0x088ea400 0 0x200>,
2878                                       <0 0x088eac00 0 0x400>,
2879                                       <0 0x088ea600 0 0x200>,
2880                                       <0 0x088ea800 0 0x200>,
2881                                       <0 0x088eaa00 0 0x100>;
2882                                 #phy-cells = <0>;
2883                                 #clock-cells = <1>;
2884                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2885                                 clock-names = "pipe0";
2886                                 clock-output-names = "usb3_phy_pipe_clk_src";
2887                         };
2888                 };
2889
2890                 usb_2_qmpphy: phy@88eb000 {
2891                         compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2892                         reg = <0 0x088eb000 0 0x200>;
2893                         status = "disabled";
2894                         #address-cells = <2>;
2895                         #size-cells = <2>;
2896                         ranges;
2897
2898                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2899                                  <&rpmhcc RPMH_CXO_CLK>,
2900                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
2901                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2902                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2903
2904                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2905                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2906                         reset-names = "phy", "common";
2907
2908                         usb_2_ssphy: phy@88eb200 {
2909                                 reg = <0 0x088eb200 0 0x200>,
2910                                       <0 0x088eb400 0 0x200>,
2911                                       <0 0x088eb800 0 0x800>;
2912                                 #clock-cells = <0>;
2913                                 #phy-cells = <0>;
2914                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2915                                 clock-names = "pipe0";
2916                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2917                         };
2918                 };
2919
2920                 sdhc_2: sdhci@8804000 {
2921                         compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2922                         reg = <0 0x08804000 0 0x1000>;
2923
2924                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2925                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2926                         interrupt-names = "hc_irq", "pwr_irq";
2927
2928                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2929                                  <&gcc GCC_SDCC2_APPS_CLK>,
2930                                  <&rpmhcc RPMH_CXO_CLK>;
2931                         clock-names = "iface", "core", "xo";
2932                         iommus = <&apps_smmu 0x4a0 0x0>;
2933                         qcom,dll-config = <0x0007642c>;
2934                         qcom,ddr-config = <0x80040868>;
2935                         power-domains = <&rpmhpd SM8250_CX>;
2936                         operating-points-v2 = <&sdhc2_opp_table>;
2937
2938                         status = "disabled";
2939
2940                         sdhc2_opp_table: sdhc2-opp-table {
2941                                 compatible = "operating-points-v2";
2942
2943                                 opp-19200000 {
2944                                         opp-hz = /bits/ 64 <19200000>;
2945                                         required-opps = <&rpmhpd_opp_min_svs>;
2946                                 };
2947
2948                                 opp-50000000 {
2949                                         opp-hz = /bits/ 64 <50000000>;
2950                                         required-opps = <&rpmhpd_opp_low_svs>;
2951                                 };
2952
2953                                 opp-100000000 {
2954                                         opp-hz = /bits/ 64 <100000000>;
2955                                         required-opps = <&rpmhpd_opp_svs>;
2956                                 };
2957
2958                                 opp-202000000 {
2959                                         opp-hz = /bits/ 64 <202000000>;
2960                                         required-opps = <&rpmhpd_opp_svs_l1>;
2961                                 };
2962                         };
2963                 };
2964
2965                 dc_noc: interconnect@90c0000 {
2966                         compatible = "qcom,sm8250-dc-noc";
2967                         reg = <0 0x090c0000 0 0x4200>;
2968                         #interconnect-cells = <1>;
2969                         qcom,bcm-voters = <&apps_bcm_voter>;
2970                 };
2971
2972                 gem_noc: interconnect@9100000 {
2973                         compatible = "qcom,sm8250-gem-noc";
2974                         reg = <0 0x09100000 0 0xb4000>;
2975                         #interconnect-cells = <1>;
2976                         qcom,bcm-voters = <&apps_bcm_voter>;
2977                 };
2978
2979                 npu_noc: interconnect@9990000 {
2980                         compatible = "qcom,sm8250-npu-noc";
2981                         reg = <0 0x09990000 0 0x1600>;
2982                         #interconnect-cells = <1>;
2983                         qcom,bcm-voters = <&apps_bcm_voter>;
2984                 };
2985
2986                 usb_1: usb@a6f8800 {
2987                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2988                         reg = <0 0x0a6f8800 0 0x400>;
2989                         status = "disabled";
2990                         #address-cells = <2>;
2991                         #size-cells = <2>;
2992                         ranges;
2993                         dma-ranges;
2994
2995                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2996                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2997                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2998                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2999                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3000                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
3001                         clock-names = "cfg_noc",
3002                                       "core",
3003                                       "iface",
3004                                       "sleep",
3005                                       "mock_utmi",
3006                                       "xo";
3007
3008                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3009                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3010                         assigned-clock-rates = <19200000>, <200000000>;
3011
3012                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3013                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3014                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3015                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
3016                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
3017                                           "dm_hs_phy_irq", "ss_phy_irq";
3018
3019                         power-domains = <&gcc USB30_PRIM_GDSC>;
3020
3021                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3022
3023                         usb_1_dwc3: usb@a600000 {
3024                                 compatible = "snps,dwc3";
3025                                 reg = <0 0x0a600000 0 0xcd00>;
3026                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3027                                 iommus = <&apps_smmu 0x0 0x0>;
3028                                 snps,dis_u2_susphy_quirk;
3029                                 snps,dis_enblslpm_quirk;
3030                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3031                                 phy-names = "usb2-phy", "usb3-phy";
3032                         };
3033                 };
3034
3035                 system-cache-controller@9200000 {
3036                         compatible = "qcom,sm8250-llcc";
3037                         reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
3038                         reg-names = "llcc_base", "llcc_broadcast_base";
3039                 };
3040
3041                 usb_2: usb@a8f8800 {
3042                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3043                         reg = <0 0x0a8f8800 0 0x400>;
3044                         status = "disabled";
3045                         #address-cells = <2>;
3046                         #size-cells = <2>;
3047                         ranges;
3048                         dma-ranges;
3049
3050                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3051                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3052                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3053                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3054                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3055                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
3056                         clock-names = "cfg_noc",
3057                                       "core",
3058                                       "iface",
3059                                       "sleep",
3060                                       "mock_utmi",
3061                                       "xo";
3062
3063                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3064                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3065                         assigned-clock-rates = <19200000>, <200000000>;
3066
3067                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3068                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3069                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3070                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
3071                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
3072                                           "dm_hs_phy_irq", "ss_phy_irq";
3073
3074                         power-domains = <&gcc USB30_SEC_GDSC>;
3075
3076                         resets = <&gcc GCC_USB30_SEC_BCR>;
3077
3078                         usb_2_dwc3: usb@a800000 {
3079                                 compatible = "snps,dwc3";
3080                                 reg = <0 0x0a800000 0 0xcd00>;
3081                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3082                                 iommus = <&apps_smmu 0x20 0>;
3083                                 snps,dis_u2_susphy_quirk;
3084                                 snps,dis_enblslpm_quirk;
3085                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3086                                 phy-names = "usb2-phy", "usb3-phy";
3087                         };
3088                 };
3089
3090                 venus: video-codec@aa00000 {
3091                         compatible = "qcom,sm8250-venus";
3092                         reg = <0 0x0aa00000 0 0x100000>;
3093                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3094                         power-domains = <&videocc MVS0C_GDSC>,
3095                                         <&videocc MVS0_GDSC>,
3096                                         <&rpmhpd SM8250_MX>;
3097                         power-domain-names = "venus", "vcodec0", "mx";
3098                         operating-points-v2 = <&venus_opp_table>;
3099
3100                         clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
3101                                  <&videocc VIDEO_CC_MVS0C_CLK>,
3102                                  <&videocc VIDEO_CC_MVS0_CLK>;
3103                         clock-names = "iface", "core", "vcodec0_core";
3104
3105                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
3106                                         <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
3107                         interconnect-names = "cpu-cfg", "video-mem";
3108
3109                         iommus = <&apps_smmu 0x2100 0x0400>;
3110                         memory-region = <&video_mem>;
3111
3112                         resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
3113                                  <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
3114                         reset-names = "bus", "core";
3115
3116                         status = "disabled";
3117
3118                         video-decoder {
3119                                 compatible = "venus-decoder";
3120                         };
3121
3122                         video-encoder {
3123                                 compatible = "venus-encoder";
3124                         };
3125
3126                         venus_opp_table: venus-opp-table {
3127                                 compatible = "operating-points-v2";
3128
3129                                 opp-720000000 {
3130                                         opp-hz = /bits/ 64 <720000000>;
3131                                         required-opps = <&rpmhpd_opp_low_svs>;
3132                                 };
3133
3134                                 opp-1014000000 {
3135                                         opp-hz = /bits/ 64 <1014000000>;
3136                                         required-opps = <&rpmhpd_opp_svs>;
3137                                 };
3138
3139                                 opp-1098000000 {
3140                                         opp-hz = /bits/ 64 <1098000000>;
3141                                         required-opps = <&rpmhpd_opp_svs_l1>;
3142                                 };
3143
3144                                 opp-1332000000 {
3145                                         opp-hz = /bits/ 64 <1332000000>;
3146                                         required-opps = <&rpmhpd_opp_nom>;
3147                                 };
3148                         };
3149                 };
3150
3151                 videocc: clock-controller@abf0000 {
3152                         compatible = "qcom,sm8250-videocc";
3153                         reg = <0 0x0abf0000 0 0x10000>;
3154                         clocks = <&gcc GCC_VIDEO_AHB_CLK>,
3155                                  <&rpmhcc RPMH_CXO_CLK>,
3156                                  <&rpmhcc RPMH_CXO_CLK_A>;
3157                         power-domains = <&rpmhpd SM8250_MMCX>;
3158                         required-opps = <&rpmhpd_opp_low_svs>;
3159                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
3160                         #clock-cells = <1>;
3161                         #reset-cells = <1>;
3162                         #power-domain-cells = <1>;
3163                 };
3164
3165                 cci0: cci@ac4f000 {
3166                         compatible = "qcom,sm8250-cci";
3167                         #address-cells = <1>;
3168                         #size-cells = <0>;
3169
3170                         reg = <0 0x0ac4f000 0 0x1000>;
3171                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3172                         power-domains = <&camcc TITAN_TOP_GDSC>;
3173
3174                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3175                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3176                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3177                                  <&camcc CAM_CC_CCI_0_CLK>,
3178                                  <&camcc CAM_CC_CCI_0_CLK_SRC>;
3179                         clock-names = "camnoc_axi",
3180                                       "slow_ahb_src",
3181                                       "cpas_ahb",
3182                                       "cci",
3183                                       "cci_src";
3184
3185                         pinctrl-0 = <&cci0_default>;
3186                         pinctrl-1 = <&cci0_sleep>;
3187                         pinctrl-names = "default", "sleep";
3188
3189                         status = "disabled";
3190
3191                         cci0_i2c0: i2c-bus@0 {
3192                                 reg = <0>;
3193                                 clock-frequency = <1000000>;
3194                                 #address-cells = <1>;
3195                                 #size-cells = <0>;
3196                         };
3197
3198                         cci0_i2c1: i2c-bus@1 {
3199                                 reg = <1>;
3200                                 clock-frequency = <1000000>;
3201                                 #address-cells = <1>;
3202                                 #size-cells = <0>;
3203                         };
3204                 };
3205
3206                 cci1: cci@ac50000 {
3207                         compatible = "qcom,sm8250-cci";
3208                         #address-cells = <1>;
3209                         #size-cells = <0>;
3210
3211                         reg = <0 0x0ac50000 0 0x1000>;
3212                         interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
3213                         power-domains = <&camcc TITAN_TOP_GDSC>;
3214
3215                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3216                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3217                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3218                                  <&camcc CAM_CC_CCI_1_CLK>,
3219                                  <&camcc CAM_CC_CCI_1_CLK_SRC>;
3220                         clock-names = "camnoc_axi",
3221                                       "slow_ahb_src",
3222                                       "cpas_ahb",
3223                                       "cci",
3224                                       "cci_src";
3225
3226                         pinctrl-0 = <&cci1_default>;
3227                         pinctrl-1 = <&cci1_sleep>;
3228                         pinctrl-names = "default", "sleep";
3229
3230                         status = "disabled";
3231
3232                         cci1_i2c0: i2c-bus@0 {
3233                                 reg = <0>;
3234                                 clock-frequency = <1000000>;
3235                                 #address-cells = <1>;
3236                                 #size-cells = <0>;
3237                         };
3238
3239                         cci1_i2c1: i2c-bus@1 {
3240                                 reg = <1>;
3241                                 clock-frequency = <1000000>;
3242                                 #address-cells = <1>;
3243                                 #size-cells = <0>;
3244                         };
3245                 };
3246
3247                 camss: camss@ac6a000 {
3248                         compatible = "qcom,sm8250-camss";
3249                         status = "disabled";
3250
3251                         reg = <0 0xac6a000 0 0x2000>,
3252                               <0 0xac6c000 0 0x2000>,
3253                               <0 0xac6e000 0 0x1000>,
3254                               <0 0xac70000 0 0x1000>,
3255                               <0 0xac72000 0 0x1000>,
3256                               <0 0xac74000 0 0x1000>,
3257                               <0 0xacb4000 0 0xd000>,
3258                               <0 0xacc3000 0 0xd000>,
3259                               <0 0xacd9000 0 0x2200>,
3260                               <0 0xacdb200 0 0x2200>;
3261                         reg-names = "csiphy0",
3262                                     "csiphy1",
3263                                     "csiphy2",
3264                                     "csiphy3",
3265                                     "csiphy4",
3266                                     "csiphy5",
3267                                     "vfe0",
3268                                     "vfe1",
3269                                     "vfe_lite0",
3270                                     "vfe_lite1";
3271
3272                         interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3273                                      <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3274                                      <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3275                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3276                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
3277                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
3278                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3279                                      <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3280                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3281                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
3282                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3283                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3284                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
3285                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
3286                         interrupt-names = "csiphy0",
3287                                           "csiphy1",
3288                                           "csiphy2",
3289                                           "csiphy3",
3290                                           "csiphy4",
3291                                           "csiphy5",
3292                                           "csid0",
3293                                           "csid1",
3294                                           "csid2",
3295                                           "csid3",
3296                                           "vfe0",
3297                                           "vfe1",
3298                                           "vfe_lite0",
3299                                           "vfe_lite1";
3300
3301                         power-domains = <&camcc IFE_0_GDSC>,
3302                                         <&camcc IFE_1_GDSC>,
3303                                         <&camcc TITAN_TOP_GDSC>;
3304
3305                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3306                                  <&gcc GCC_CAMERA_HF_AXI_CLK>,
3307                                  <&gcc GCC_CAMERA_SF_AXI_CLK>,
3308                                  <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3309                                  <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
3310                                  <&camcc CAM_CC_CORE_AHB_CLK>,
3311                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3312                                  <&camcc CAM_CC_CSIPHY0_CLK>,
3313                                  <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
3314                                  <&camcc CAM_CC_CSIPHY1_CLK>,
3315                                  <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
3316                                  <&camcc CAM_CC_CSIPHY2_CLK>,
3317                                  <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
3318                                  <&camcc CAM_CC_CSIPHY3_CLK>,
3319                                  <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
3320                                  <&camcc CAM_CC_CSIPHY4_CLK>,
3321                                  <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
3322                                  <&camcc CAM_CC_CSIPHY5_CLK>,
3323                                  <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
3324                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3325                                  <&camcc CAM_CC_IFE_0_AHB_CLK>,
3326                                  <&camcc CAM_CC_IFE_0_AXI_CLK>,
3327                                  <&camcc CAM_CC_IFE_0_CLK>,
3328                                  <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
3329                                  <&camcc CAM_CC_IFE_0_CSID_CLK>,
3330                                  <&camcc CAM_CC_IFE_0_AREG_CLK>,
3331                                  <&camcc CAM_CC_IFE_1_AHB_CLK>,
3332                                  <&camcc CAM_CC_IFE_1_AXI_CLK>,
3333                                  <&camcc CAM_CC_IFE_1_CLK>,
3334                                  <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
3335                                  <&camcc CAM_CC_IFE_1_CSID_CLK>,
3336                                  <&camcc CAM_CC_IFE_1_AREG_CLK>,
3337                                  <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
3338                                  <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
3339                                  <&camcc CAM_CC_IFE_LITE_CLK>,
3340                                  <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
3341                                  <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
3342
3343                         clock-names = "cam_ahb_clk",
3344                                       "cam_hf_axi",
3345                                       "cam_sf_axi",
3346                                       "camnoc_axi",
3347                                       "camnoc_axi_src",
3348                                       "core_ahb",
3349                                       "cpas_ahb",
3350                                       "csiphy0",
3351                                       "csiphy0_timer",
3352                                       "csiphy1",
3353                                       "csiphy1_timer",
3354                                       "csiphy2",
3355                                       "csiphy2_timer",
3356                                       "csiphy3",
3357                                       "csiphy3_timer",
3358                                       "csiphy4",
3359                                       "csiphy4_timer",
3360                                       "csiphy5",
3361                                       "csiphy5_timer",
3362                                       "slow_ahb_src",
3363                                       "vfe0_ahb",
3364                                       "vfe0_axi",
3365                                       "vfe0",
3366                                       "vfe0_cphy_rx",
3367                                       "vfe0_csid",
3368                                       "vfe0_areg",
3369                                       "vfe1_ahb",
3370                                       "vfe1_axi",
3371                                       "vfe1",
3372                                       "vfe1_cphy_rx",
3373                                       "vfe1_csid",
3374                                       "vfe1_areg",
3375                                       "vfe_lite_ahb",
3376                                       "vfe_lite_axi",
3377                                       "vfe_lite",
3378                                       "vfe_lite_cphy_rx",
3379                                       "vfe_lite_csid";
3380
3381                         iommus = <&apps_smmu 0x800 0x400>,
3382                                  <&apps_smmu 0x801 0x400>,
3383                                  <&apps_smmu 0x840 0x400>,
3384                                  <&apps_smmu 0x841 0x400>,
3385                                  <&apps_smmu 0xc00 0x400>,
3386                                  <&apps_smmu 0xc01 0x400>,
3387                                  <&apps_smmu 0xc40 0x400>,
3388                                  <&apps_smmu 0xc41 0x400>;
3389
3390                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
3391                                         <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
3392                                         <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
3393                                         <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
3394                         interconnect-names = "cam_ahb",
3395                                              "cam_hf_0_mnoc",
3396                                              "cam_sf_0_mnoc",
3397                                              "cam_sf_icp_mnoc";
3398                 };
3399
3400                 camcc: clock-controller@ad00000 {
3401                         compatible = "qcom,sm8250-camcc";
3402                         reg = <0 0x0ad00000 0 0x10000>;
3403                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3404                                  <&rpmhcc RPMH_CXO_CLK>,
3405                                  <&rpmhcc RPMH_CXO_CLK_A>,
3406                                  <&sleep_clk>;
3407                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3408                         power-domains = <&rpmhpd SM8250_MMCX>;
3409                         required-opps = <&rpmhpd_opp_low_svs>;
3410                         #clock-cells = <1>;
3411                         #reset-cells = <1>;
3412                         #power-domain-cells = <1>;
3413                 };
3414
3415                 mdss: mdss@ae00000 {
3416                         compatible = "qcom,sm8250-mdss";
3417                         reg = <0 0x0ae00000 0 0x1000>;
3418                         reg-names = "mdss";
3419
3420                         interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
3421                                         <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
3422                         interconnect-names = "mdp0-mem", "mdp1-mem";
3423
3424                         power-domains = <&dispcc MDSS_GDSC>;
3425
3426                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3427                                  <&gcc GCC_DISP_HF_AXI_CLK>,
3428                                  <&gcc GCC_DISP_SF_AXI_CLK>,
3429                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
3430                         clock-names = "iface", "bus", "nrt_bus", "core";
3431
3432                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
3433                         assigned-clock-rates = <460000000>;
3434
3435                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3436                         interrupt-controller;
3437                         #interrupt-cells = <1>;
3438
3439                         iommus = <&apps_smmu 0x820 0x402>;
3440
3441                         status = "disabled";
3442
3443                         #address-cells = <2>;
3444                         #size-cells = <2>;
3445                         ranges;
3446
3447                         mdss_mdp: mdp@ae01000 {
3448                                 compatible = "qcom,sm8250-dpu";
3449                                 reg = <0 0x0ae01000 0 0x8f000>,
3450                                       <0 0x0aeb0000 0 0x2008>;
3451                                 reg-names = "mdp", "vbif";
3452
3453                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3454                                          <&gcc GCC_DISP_HF_AXI_CLK>,
3455                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3456                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3457                                 clock-names = "iface", "bus", "core", "vsync";
3458
3459                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
3460                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3461                                 assigned-clock-rates = <460000000>,
3462                                                        <19200000>;
3463
3464                                 operating-points-v2 = <&mdp_opp_table>;
3465                                 power-domains = <&rpmhpd SM8250_MMCX>;
3466
3467                                 interrupt-parent = <&mdss>;
3468                                 interrupts = <0>;
3469
3470                                 ports {
3471                                         #address-cells = <1>;
3472                                         #size-cells = <0>;
3473
3474                                         port@0 {
3475                                                 reg = <0>;
3476                                                 dpu_intf1_out: endpoint {
3477                                                         remote-endpoint = <&dsi0_in>;
3478                                                 };
3479                                         };
3480
3481                                         port@1 {
3482                                                 reg = <1>;
3483                                                 dpu_intf2_out: endpoint {
3484                                                         remote-endpoint = <&dsi1_in>;
3485                                                 };
3486                                         };
3487                                 };
3488
3489                                 mdp_opp_table: mdp-opp-table {
3490                                         compatible = "operating-points-v2";
3491
3492                                         opp-200000000 {
3493                                                 opp-hz = /bits/ 64 <200000000>;
3494                                                 required-opps = <&rpmhpd_opp_low_svs>;
3495                                         };
3496
3497                                         opp-300000000 {
3498                                                 opp-hz = /bits/ 64 <300000000>;
3499                                                 required-opps = <&rpmhpd_opp_svs>;
3500                                         };
3501
3502                                         opp-345000000 {
3503                                                 opp-hz = /bits/ 64 <345000000>;
3504                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3505                                         };
3506
3507                                         opp-460000000 {
3508                                                 opp-hz = /bits/ 64 <460000000>;
3509                                                 required-opps = <&rpmhpd_opp_nom>;
3510                                         };
3511                                 };
3512                         };
3513
3514                         dsi0: dsi@ae94000 {
3515                                 compatible = "qcom,mdss-dsi-ctrl";
3516                                 reg = <0 0x0ae94000 0 0x400>;
3517                                 reg-names = "dsi_ctrl";
3518
3519                                 interrupt-parent = <&mdss>;
3520                                 interrupts = <4>;
3521
3522                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3523                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3524                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3525                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3526                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3527                                         <&gcc GCC_DISP_HF_AXI_CLK>;
3528                                 clock-names = "byte",
3529                                               "byte_intf",
3530                                               "pixel",
3531                                               "core",
3532                                               "iface",
3533                                               "bus";
3534
3535                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3536                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
3537
3538                                 operating-points-v2 = <&dsi_opp_table>;
3539                                 power-domains = <&rpmhpd SM8250_MMCX>;
3540
3541                                 phys = <&dsi0_phy>;
3542                                 phy-names = "dsi";
3543
3544                                 status = "disabled";
3545
3546                                 #address-cells = <1>;
3547                                 #size-cells = <0>;
3548
3549                                 ports {
3550                                         #address-cells = <1>;
3551                                         #size-cells = <0>;
3552
3553                                         port@0 {
3554                                                 reg = <0>;
3555                                                 dsi0_in: endpoint {
3556                                                         remote-endpoint = <&dpu_intf1_out>;
3557                                                 };
3558                                         };
3559
3560                                         port@1 {
3561                                                 reg = <1>;
3562                                                 dsi0_out: endpoint {
3563                                                 };
3564                                         };
3565                                 };
3566                         };
3567
3568                         dsi0_phy: dsi-phy@ae94400 {
3569                                 compatible = "qcom,dsi-phy-7nm";
3570                                 reg = <0 0x0ae94400 0 0x200>,
3571                                       <0 0x0ae94600 0 0x280>,
3572                                       <0 0x0ae94900 0 0x260>;
3573                                 reg-names = "dsi_phy",
3574                                             "dsi_phy_lane",
3575                                             "dsi_pll";
3576
3577                                 #clock-cells = <1>;
3578                                 #phy-cells = <0>;
3579
3580                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3581                                          <&rpmhcc RPMH_CXO_CLK>;
3582                                 clock-names = "iface", "ref";
3583
3584                                 status = "disabled";
3585                         };
3586
3587                         dsi1: dsi@ae96000 {
3588                                 compatible = "qcom,mdss-dsi-ctrl";
3589                                 reg = <0 0x0ae96000 0 0x400>;
3590                                 reg-names = "dsi_ctrl";
3591
3592                                 interrupt-parent = <&mdss>;
3593                                 interrupts = <5>;
3594
3595                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3596                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3597                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3598                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3599                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3600                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3601                                 clock-names = "byte",
3602                                               "byte_intf",
3603                                               "pixel",
3604                                               "core",
3605                                               "iface",
3606                                               "bus";
3607
3608                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3609                                 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
3610
3611                                 operating-points-v2 = <&dsi_opp_table>;
3612                                 power-domains = <&rpmhpd SM8250_MMCX>;
3613
3614                                 phys = <&dsi1_phy>;
3615                                 phy-names = "dsi";
3616
3617                                 status = "disabled";
3618
3619                                 #address-cells = <1>;
3620                                 #size-cells = <0>;
3621
3622                                 ports {
3623                                         #address-cells = <1>;
3624                                         #size-cells = <0>;
3625
3626                                         port@0 {
3627                                                 reg = <0>;
3628                                                 dsi1_in: endpoint {
3629                                                         remote-endpoint = <&dpu_intf2_out>;
3630                                                 };
3631                                         };
3632
3633                                         port@1 {
3634                                                 reg = <1>;
3635                                                 dsi1_out: endpoint {
3636                                                 };
3637                                         };
3638                                 };
3639                         };
3640
3641                         dsi1_phy: dsi-phy@ae96400 {
3642                                 compatible = "qcom,dsi-phy-7nm";
3643                                 reg = <0 0x0ae96400 0 0x200>,
3644                                       <0 0x0ae96600 0 0x280>,
3645                                       <0 0x0ae96900 0 0x260>;
3646                                 reg-names = "dsi_phy",
3647                                             "dsi_phy_lane",
3648                                             "dsi_pll";
3649
3650                                 #clock-cells = <1>;
3651                                 #phy-cells = <0>;
3652
3653                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3654                                          <&rpmhcc RPMH_CXO_CLK>;
3655                                 clock-names = "iface", "ref";
3656
3657                                 status = "disabled";
3658
3659                                 dsi_opp_table: dsi-opp-table {
3660                                         compatible = "operating-points-v2";
3661
3662                                         opp-187500000 {
3663                                                 opp-hz = /bits/ 64 <187500000>;
3664                                                 required-opps = <&rpmhpd_opp_low_svs>;
3665                                         };
3666
3667                                         opp-300000000 {
3668                                                 opp-hz = /bits/ 64 <300000000>;
3669                                                 required-opps = <&rpmhpd_opp_svs>;
3670                                         };
3671
3672                                         opp-358000000 {
3673                                                 opp-hz = /bits/ 64 <358000000>;
3674                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3675                                         };
3676                                 };
3677                         };
3678                 };
3679
3680                 dispcc: clock-controller@af00000 {
3681                         compatible = "qcom,sm8250-dispcc";
3682                         reg = <0 0x0af00000 0 0x10000>;
3683                         power-domains = <&rpmhpd SM8250_MMCX>;
3684                         required-opps = <&rpmhpd_opp_low_svs>;
3685                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3686                                  <&dsi0_phy 0>,
3687                                  <&dsi0_phy 1>,
3688                                  <&dsi1_phy 0>,
3689                                  <&dsi1_phy 1>,
3690                                  <&dp_phy 0>,
3691                                  <&dp_phy 1>;
3692                         clock-names = "bi_tcxo",
3693                                       "dsi0_phy_pll_out_byteclk",
3694                                       "dsi0_phy_pll_out_dsiclk",
3695                                       "dsi1_phy_pll_out_byteclk",
3696                                       "dsi1_phy_pll_out_dsiclk",
3697                                       "dp_phy_pll_link_clk",
3698                                       "dp_phy_pll_vco_div_clk";
3699                         #clock-cells = <1>;
3700                         #reset-cells = <1>;
3701                         #power-domain-cells = <1>;
3702                 };
3703
3704                 pdc: interrupt-controller@b220000 {
3705                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
3706                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
3707                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3708                                           <125 63 1>, <126 716 12>;
3709                         #interrupt-cells = <2>;
3710                         interrupt-parent = <&intc>;
3711                         interrupt-controller;
3712                 };
3713
3714                 tsens0: thermal-sensor@c263000 {
3715                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
3716                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3717                               <0 0x0c222000 0 0x1ff>; /* SROT */
3718                         #qcom,sensors = <16>;
3719                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3720                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3721                         interrupt-names = "uplow", "critical";
3722                         #thermal-sensor-cells = <1>;
3723                 };
3724
3725                 tsens1: thermal-sensor@c265000 {
3726                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
3727                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3728                               <0 0x0c223000 0 0x1ff>; /* SROT */
3729                         #qcom,sensors = <9>;
3730                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3731                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3732                         interrupt-names = "uplow", "critical";
3733                         #thermal-sensor-cells = <1>;
3734                 };
3735
3736                 aoss_qmp: power-controller@c300000 {
3737                         compatible = "qcom,sm8250-aoss-qmp";
3738                         reg = <0 0x0c300000 0 0x400>;
3739                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
3740                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
3741                                                      IRQ_TYPE_EDGE_RISING>;
3742                         mboxes = <&ipcc IPCC_CLIENT_AOP
3743                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
3744
3745                         #clock-cells = <0>;
3746                 };
3747
3748                 sram@c3f0000 {
3749                         compatible = "qcom,rpmh-stats";
3750                         reg = <0 0x0c3f0000 0 0x400>;
3751                 };
3752
3753                 spmi_bus: spmi@c440000 {
3754                         compatible = "qcom,spmi-pmic-arb";
3755                         reg = <0x0 0x0c440000 0x0 0x0001100>,
3756                               <0x0 0x0c600000 0x0 0x2000000>,
3757                               <0x0 0x0e600000 0x0 0x0100000>,
3758                               <0x0 0x0e700000 0x0 0x00a0000>,
3759                               <0x0 0x0c40a000 0x0 0x0026000>;
3760                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3761                         interrupt-names = "periph_irq";
3762                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3763                         qcom,ee = <0>;
3764                         qcom,channel = <0>;
3765                         #address-cells = <2>;
3766                         #size-cells = <0>;
3767                         interrupt-controller;
3768                         #interrupt-cells = <4>;
3769                 };
3770
3771                 tlmm: pinctrl@f100000 {
3772                         compatible = "qcom,sm8250-pinctrl";
3773                         reg = <0 0x0f100000 0 0x300000>,
3774                               <0 0x0f500000 0 0x300000>,
3775                               <0 0x0f900000 0 0x300000>;
3776                         reg-names = "west", "south", "north";
3777                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3778                         gpio-controller;
3779                         #gpio-cells = <2>;
3780                         interrupt-controller;
3781                         #interrupt-cells = <2>;
3782                         gpio-ranges = <&tlmm 0 0 181>;
3783                         wakeup-parent = <&pdc>;
3784
3785                         cci0_default: cci0-default {
3786                                 cci0_i2c0_default: cci0-i2c0-default {
3787                                         /* SDA, SCL */
3788                                         pins = "gpio101", "gpio102";
3789                                         function = "cci_i2c";
3790
3791                                         bias-pull-up;
3792                                         drive-strength = <2>; /* 2 mA */
3793                                 };
3794
3795                                 cci0_i2c1_default: cci0-i2c1-default {
3796                                         /* SDA, SCL */
3797                                         pins = "gpio103", "gpio104";
3798                                         function = "cci_i2c";
3799
3800                                         bias-pull-up;
3801                                         drive-strength = <2>; /* 2 mA */
3802                                 };
3803                         };
3804
3805                         cci0_sleep: cci0-sleep {
3806                                 cci0_i2c0_sleep: cci0-i2c0-sleep {
3807                                         /* SDA, SCL */
3808                                         pins = "gpio101", "gpio102";
3809                                         function = "cci_i2c";
3810
3811                                         drive-strength = <2>; /* 2 mA */
3812                                         bias-pull-down;
3813                                 };
3814
3815                                 cci0_i2c1_sleep: cci0-i2c1-sleep {
3816                                         /* SDA, SCL */
3817                                         pins = "gpio103", "gpio104";
3818                                         function = "cci_i2c";
3819
3820                                         drive-strength = <2>; /* 2 mA */
3821                                         bias-pull-down;
3822                                 };
3823                         };
3824
3825                         cci1_default: cci1-default {
3826                                 cci1_i2c0_default: cci1-i2c0-default {
3827                                         /* SDA, SCL */
3828                                         pins = "gpio105","gpio106";
3829                                         function = "cci_i2c";
3830
3831                                         bias-pull-up;
3832                                         drive-strength = <2>; /* 2 mA */
3833                                 };
3834
3835                                 cci1_i2c1_default: cci1-i2c1-default {
3836                                         /* SDA, SCL */
3837                                         pins = "gpio107","gpio108";
3838                                         function = "cci_i2c";
3839
3840                                         bias-pull-up;
3841                                         drive-strength = <2>; /* 2 mA */
3842                                 };
3843                         };
3844
3845                         cci1_sleep: cci1-sleep {
3846                                 cci1_i2c0_sleep: cci1-i2c0-sleep {
3847                                         /* SDA, SCL */
3848                                         pins = "gpio105","gpio106";
3849                                         function = "cci_i2c";
3850
3851                                         bias-pull-down;
3852                                         drive-strength = <2>; /* 2 mA */
3853                                 };
3854
3855                                 cci1_i2c1_sleep: cci1-i2c1-sleep {
3856                                         /* SDA, SCL */
3857                                         pins = "gpio107","gpio108";
3858                                         function = "cci_i2c";
3859
3860                                         bias-pull-down;
3861                                         drive-strength = <2>; /* 2 mA */
3862                                 };
3863                         };
3864
3865                         pri_mi2s_active: pri-mi2s-active {
3866                                 sclk {
3867                                         pins = "gpio138";
3868                                         function = "mi2s0_sck";
3869                                         drive-strength = <8>;
3870                                         bias-disable;
3871                                 };
3872
3873                                 ws {
3874                                         pins = "gpio141";
3875                                         function = "mi2s0_ws";
3876                                         drive-strength = <8>;
3877                                         output-high;
3878                                 };
3879
3880                                 data0 {
3881                                         pins = "gpio139";
3882                                         function = "mi2s0_data0";
3883                                         drive-strength = <8>;
3884                                         bias-disable;
3885                                         output-high;
3886                                 };
3887
3888                                 data1 {
3889                                         pins = "gpio140";
3890                                         function = "mi2s0_data1";
3891                                         drive-strength = <8>;
3892                                         output-high;
3893                                 };
3894                         };
3895
3896                         qup_i2c0_default: qup-i2c0-default {
3897                                 mux {
3898                                         pins = "gpio28", "gpio29";
3899                                         function = "qup0";
3900                                 };
3901
3902                                 config {
3903                                         pins = "gpio28", "gpio29";
3904                                         drive-strength = <2>;
3905                                         bias-disable;
3906                                 };
3907                         };
3908
3909                         qup_i2c1_default: qup-i2c1-default {
3910                                 pinmux {
3911                                         pins = "gpio4", "gpio5";
3912                                         function = "qup1";
3913                                 };
3914
3915                                 config {
3916                                         pins = "gpio4", "gpio5";
3917                                         drive-strength = <2>;
3918                                         bias-disable;
3919                                 };
3920                         };
3921
3922                         qup_i2c2_default: qup-i2c2-default {
3923                                 mux {
3924                                         pins = "gpio115", "gpio116";
3925                                         function = "qup2";
3926                                 };
3927
3928                                 config {
3929                                         pins = "gpio115", "gpio116";
3930                                         drive-strength = <2>;
3931                                         bias-disable;
3932                                 };
3933                         };
3934
3935                         qup_i2c3_default: qup-i2c3-default {
3936                                 mux {
3937                                         pins = "gpio119", "gpio120";
3938                                         function = "qup3";
3939                                 };
3940
3941                                 config {
3942                                         pins = "gpio119", "gpio120";
3943                                         drive-strength = <2>;
3944                                         bias-disable;
3945                                 };
3946                         };
3947
3948                         qup_i2c4_default: qup-i2c4-default {
3949                                 mux {
3950                                         pins = "gpio8", "gpio9";
3951                                         function = "qup4";
3952                                 };
3953
3954                                 config {
3955                                         pins = "gpio8", "gpio9";
3956                                         drive-strength = <2>;
3957                                         bias-disable;
3958                                 };
3959                         };
3960
3961                         qup_i2c5_default: qup-i2c5-default {
3962                                 mux {
3963                                         pins = "gpio12", "gpio13";
3964                                         function = "qup5";
3965                                 };
3966
3967                                 config {
3968                                         pins = "gpio12", "gpio13";
3969                                         drive-strength = <2>;
3970                                         bias-disable;
3971                                 };
3972                         };
3973
3974                         qup_i2c6_default: qup-i2c6-default {
3975                                 mux {
3976                                         pins = "gpio16", "gpio17";
3977                                         function = "qup6";
3978                                 };
3979
3980                                 config {
3981                                         pins = "gpio16", "gpio17";
3982                                         drive-strength = <2>;
3983                                         bias-disable;
3984                                 };
3985                         };
3986
3987                         qup_i2c7_default: qup-i2c7-default {
3988                                 mux {
3989                                         pins = "gpio20", "gpio21";
3990                                         function = "qup7";
3991                                 };
3992
3993                                 config {
3994                                         pins = "gpio20", "gpio21";
3995                                         drive-strength = <2>;
3996                                         bias-disable;
3997                                 };
3998                         };
3999
4000                         qup_i2c8_default: qup-i2c8-default {
4001                                 mux {
4002                                         pins = "gpio24", "gpio25";
4003                                         function = "qup8";
4004                                 };
4005
4006                                 config {
4007                                         pins = "gpio24", "gpio25";
4008                                         drive-strength = <2>;
4009                                         bias-disable;
4010                                 };
4011                         };
4012
4013                         qup_i2c9_default: qup-i2c9-default {
4014                                 mux {
4015                                         pins = "gpio125", "gpio126";
4016                                         function = "qup9";
4017                                 };
4018
4019                                 config {
4020                                         pins = "gpio125", "gpio126";
4021                                         drive-strength = <2>;
4022                                         bias-disable;
4023                                 };
4024                         };
4025
4026                         qup_i2c10_default: qup-i2c10-default {
4027                                 mux {
4028                                         pins = "gpio129", "gpio130";
4029                                         function = "qup10";
4030                                 };
4031
4032                                 config {
4033                                         pins = "gpio129", "gpio130";
4034                                         drive-strength = <2>;
4035                                         bias-disable;
4036                                 };
4037                         };
4038
4039                         qup_i2c11_default: qup-i2c11-default {
4040                                 mux {
4041                                         pins = "gpio60", "gpio61";
4042                                         function = "qup11";
4043                                 };
4044
4045                                 config {
4046                                         pins = "gpio60", "gpio61";
4047                                         drive-strength = <2>;
4048                                         bias-disable;
4049                                 };
4050                         };
4051
4052                         qup_i2c12_default: qup-i2c12-default {
4053                                 mux {
4054                                         pins = "gpio32", "gpio33";
4055                                         function = "qup12";
4056                                 };
4057
4058                                 config {
4059                                         pins = "gpio32", "gpio33";
4060                                         drive-strength = <2>;
4061                                         bias-disable;
4062                                 };
4063                         };
4064
4065                         qup_i2c13_default: qup-i2c13-default {
4066                                 mux {
4067                                         pins = "gpio36", "gpio37";
4068                                         function = "qup13";
4069                                 };
4070
4071                                 config {
4072                                         pins = "gpio36", "gpio37";
4073                                         drive-strength = <2>;
4074                                         bias-disable;
4075                                 };
4076                         };
4077
4078                         qup_i2c14_default: qup-i2c14-default {
4079                                 mux {
4080                                         pins = "gpio40", "gpio41";
4081                                         function = "qup14";
4082                                 };
4083
4084                                 config {
4085                                         pins = "gpio40", "gpio41";
4086                                         drive-strength = <2>;
4087                                         bias-disable;
4088                                 };
4089                         };
4090
4091                         qup_i2c15_default: qup-i2c15-default {
4092                                 mux {
4093                                         pins = "gpio44", "gpio45";
4094                                         function = "qup15";
4095                                 };
4096
4097                                 config {
4098                                         pins = "gpio44", "gpio45";
4099                                         drive-strength = <2>;
4100                                         bias-disable;
4101                                 };
4102                         };
4103
4104                         qup_i2c16_default: qup-i2c16-default {
4105                                 mux {
4106                                         pins = "gpio48", "gpio49";
4107                                         function = "qup16";
4108                                 };
4109
4110                                 config {
4111                                         pins = "gpio48", "gpio49";
4112                                         drive-strength = <2>;
4113                                         bias-disable;
4114                                 };
4115                         };
4116
4117                         qup_i2c17_default: qup-i2c17-default {
4118                                 mux {
4119                                         pins = "gpio52", "gpio53";
4120                                         function = "qup17";
4121                                 };
4122
4123                                 config {
4124                                         pins = "gpio52", "gpio53";
4125                                         drive-strength = <2>;
4126                                         bias-disable;
4127                                 };
4128                         };
4129
4130                         qup_i2c18_default: qup-i2c18-default {
4131                                 mux {
4132                                         pins = "gpio56", "gpio57";
4133                                         function = "qup18";
4134                                 };
4135
4136                                 config {
4137                                         pins = "gpio56", "gpio57";
4138                                         drive-strength = <2>;
4139                                         bias-disable;
4140                                 };
4141                         };
4142
4143                         qup_i2c19_default: qup-i2c19-default {
4144                                 mux {
4145                                         pins = "gpio0", "gpio1";
4146                                         function = "qup19";
4147                                 };
4148
4149                                 config {
4150                                         pins = "gpio0", "gpio1";
4151                                         drive-strength = <2>;
4152                                         bias-disable;
4153                                 };
4154                         };
4155
4156                         qup_spi0_cs: qup-spi0-cs {
4157                                 pins = "gpio31";
4158                                 function = "qup0";
4159                         };
4160
4161                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
4162                                 pins = "gpio31";
4163                                 function = "gpio";
4164                         };
4165
4166                         qup_spi0_data_clk: qup-spi0-data-clk {
4167                                 pins = "gpio28", "gpio29",
4168                                        "gpio30";
4169                                 function = "qup0";
4170                         };
4171
4172                         qup_spi1_cs: qup-spi1-cs {
4173                                 pins = "gpio7";
4174                                 function = "qup1";
4175                         };
4176
4177                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
4178                                 pins = "gpio7";
4179                                 function = "gpio";
4180                         };
4181
4182                         qup_spi1_data_clk: qup-spi1-data-clk {
4183                                 pins = "gpio4", "gpio5",
4184                                        "gpio6";
4185                                 function = "qup1";
4186                         };
4187
4188                         qup_spi2_cs: qup-spi2-cs {
4189                                 pins = "gpio118";
4190                                 function = "qup2";
4191                         };
4192
4193                         qup_spi2_cs_gpio: qup-spi2-cs-gpio {
4194                                 pins = "gpio118";
4195                                 function = "gpio";
4196                         };
4197
4198                         qup_spi2_data_clk: qup-spi2-data-clk {
4199                                 pins = "gpio115", "gpio116",
4200                                        "gpio117";
4201                                 function = "qup2";
4202                         };
4203
4204                         qup_spi3_cs: qup-spi3-cs {
4205                                 pins = "gpio122";
4206                                 function = "qup3";
4207                         };
4208
4209                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
4210                                 pins = "gpio122";
4211                                 function = "gpio";
4212                         };
4213
4214                         qup_spi3_data_clk: qup-spi3-data-clk {
4215                                 pins = "gpio119", "gpio120",
4216                                        "gpio121";
4217                                 function = "qup3";
4218                         };
4219
4220                         qup_spi4_cs: qup-spi4-cs {
4221                                 pins = "gpio11";
4222                                 function = "qup4";
4223                         };
4224
4225                         qup_spi4_cs_gpio: qup-spi4-cs-gpio {
4226                                 pins = "gpio11";
4227                                 function = "gpio";
4228                         };
4229
4230                         qup_spi4_data_clk: qup-spi4-data-clk {
4231                                 pins = "gpio8", "gpio9",
4232                                        "gpio10";
4233                                 function = "qup4";
4234                         };
4235
4236                         qup_spi5_cs: qup-spi5-cs {
4237                                 pins = "gpio15";
4238                                 function = "qup5";
4239                         };
4240
4241                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
4242                                 pins = "gpio15";
4243                                 function = "gpio";
4244                         };
4245
4246                         qup_spi5_data_clk: qup-spi5-data-clk {
4247                                 pins = "gpio12", "gpio13",
4248                                        "gpio14";
4249                                 function = "qup5";
4250                         };
4251
4252                         qup_spi6_cs: qup-spi6-cs {
4253                                 pins = "gpio19";
4254                                 function = "qup6";
4255                         };
4256
4257                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
4258                                 pins = "gpio19";
4259                                 function = "gpio";
4260                         };
4261
4262                         qup_spi6_data_clk: qup-spi6-data-clk {
4263                                 pins = "gpio16", "gpio17",
4264                                        "gpio18";
4265                                 function = "qup6";
4266                         };
4267
4268                         qup_spi7_cs: qup-spi7-cs {
4269                                 pins = "gpio23";
4270                                 function = "qup7";
4271                         };
4272
4273                         qup_spi7_cs_gpio: qup-spi7-cs-gpio {
4274                                 pins = "gpio23";
4275                                 function = "gpio";
4276                         };
4277
4278                         qup_spi7_data_clk: qup-spi7-data-clk {
4279                                 pins = "gpio20", "gpio21",
4280                                        "gpio22";
4281                                 function = "qup7";
4282                         };
4283
4284                         qup_spi8_cs: qup-spi8-cs {
4285                                 pins = "gpio27";
4286                                 function = "qup8";
4287                         };
4288
4289                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
4290                                 pins = "gpio27";
4291                                 function = "gpio";
4292                         };
4293
4294                         qup_spi8_data_clk: qup-spi8-data-clk {
4295                                 pins = "gpio24", "gpio25",
4296                                        "gpio26";
4297                                 function = "qup8";
4298                         };
4299
4300                         qup_spi9_cs: qup-spi9-cs {
4301                                 pins = "gpio128";
4302                                 function = "qup9";
4303                         };
4304
4305                         qup_spi9_cs_gpio: qup-spi9-cs-gpio {
4306                                 pins = "gpio128";
4307                                 function = "gpio";
4308                         };
4309
4310                         qup_spi9_data_clk: qup-spi9-data-clk {
4311                                 pins = "gpio125", "gpio126",
4312                                        "gpio127";
4313                                 function = "qup9";
4314                         };
4315
4316                         qup_spi10_cs: qup-spi10-cs {
4317                                 pins = "gpio132";
4318                                 function = "qup10";
4319                         };
4320
4321                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
4322                                 pins = "gpio132";
4323                                 function = "gpio";
4324                         };
4325
4326                         qup_spi10_data_clk: qup-spi10-data-clk {
4327                                 pins = "gpio129", "gpio130",
4328                                        "gpio131";
4329                                 function = "qup10";
4330                         };
4331
4332                         qup_spi11_cs: qup-spi11-cs {
4333                                 pins = "gpio63";
4334                                 function = "qup11";
4335                         };
4336
4337                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
4338                                 pins = "gpio63";
4339                                 function = "gpio";
4340                         };
4341
4342                         qup_spi11_data_clk: qup-spi11-data-clk {
4343                                 pins = "gpio60", "gpio61",
4344                                        "gpio62";
4345                                 function = "qup11";
4346                         };
4347
4348                         qup_spi12_cs: qup-spi12-cs {
4349                                 pins = "gpio35";
4350                                 function = "qup12";
4351                         };
4352
4353                         qup_spi12_cs_gpio: qup-spi12-cs-gpio {
4354                                 pins = "gpio35";
4355                                 function = "gpio";
4356                         };
4357
4358                         qup_spi12_data_clk: qup-spi12-data-clk {
4359                                 pins = "gpio32", "gpio33",
4360                                        "gpio34";
4361                                 function = "qup12";
4362                         };
4363
4364                         qup_spi13_cs: qup-spi13-cs {
4365                                 pins = "gpio39";
4366                                 function = "qup13";
4367                         };
4368
4369                         qup_spi13_cs_gpio: qup-spi13-cs-gpio {
4370                                 pins = "gpio39";
4371                                 function = "gpio";
4372                         };
4373
4374                         qup_spi13_data_clk: qup-spi13-data-clk {
4375                                 pins = "gpio36", "gpio37",
4376                                        "gpio38";
4377                                 function = "qup13";
4378                         };
4379
4380                         qup_spi14_cs: qup-spi14-cs {
4381                                 pins = "gpio43";
4382                                 function = "qup14";
4383                         };
4384
4385                         qup_spi14_cs_gpio: qup-spi14-cs-gpio {
4386                                 pins = "gpio43";
4387                                 function = "gpio";
4388                         };
4389
4390                         qup_spi14_data_clk: qup-spi14-data-clk {
4391                                 pins = "gpio40", "gpio41",
4392                                        "gpio42";
4393                                 function = "qup14";
4394                         };
4395
4396                         qup_spi15_cs: qup-spi15-cs {
4397                                 pins = "gpio47";
4398                                 function = "qup15";
4399                         };
4400
4401                         qup_spi15_cs_gpio: qup-spi15-cs-gpio {
4402                                 pins = "gpio47";
4403                                 function = "gpio";
4404                         };
4405
4406                         qup_spi15_data_clk: qup-spi15-data-clk {
4407                                 pins = "gpio44", "gpio45",
4408                                        "gpio46";
4409                                 function = "qup15";
4410                         };
4411
4412                         qup_spi16_cs: qup-spi16-cs {
4413                                 pins = "gpio51";
4414                                 function = "qup16";
4415                         };
4416
4417                         qup_spi16_cs_gpio: qup-spi16-cs-gpio {
4418                                 pins = "gpio51";
4419                                 function = "gpio";
4420                         };
4421
4422                         qup_spi16_data_clk: qup-spi16-data-clk {
4423                                 pins = "gpio48", "gpio49",
4424                                        "gpio50";
4425                                 function = "qup16";
4426                         };
4427
4428                         qup_spi17_cs: qup-spi17-cs {
4429                                 pins = "gpio55";
4430                                 function = "qup17";
4431                         };
4432
4433                         qup_spi17_cs_gpio: qup-spi17-cs-gpio {
4434                                 pins = "gpio55";
4435                                 function = "gpio";
4436                         };
4437
4438                         qup_spi17_data_clk: qup-spi17-data-clk {
4439                                 pins = "gpio52", "gpio53",
4440                                        "gpio54";
4441                                 function = "qup17";
4442                         };
4443
4444                         qup_spi18_cs: qup-spi18-cs {
4445                                 pins = "gpio59";
4446                                 function = "qup18";
4447                         };
4448
4449                         qup_spi18_cs_gpio: qup-spi18-cs-gpio {
4450                                 pins = "gpio59";
4451                                 function = "gpio";
4452                         };
4453
4454                         qup_spi18_data_clk: qup-spi18-data-clk {
4455                                 pins = "gpio56", "gpio57",
4456                                        "gpio58";
4457                                 function = "qup18";
4458                         };
4459
4460                         qup_spi19_cs: qup-spi19-cs {
4461                                 pins = "gpio3";
4462                                 function = "qup19";
4463                         };
4464
4465                         qup_spi19_cs_gpio: qup-spi19-cs-gpio {
4466                                 pins = "gpio3";
4467                                 function = "gpio";
4468                         };
4469
4470                         qup_spi19_data_clk: qup-spi19-data-clk {
4471                                 pins = "gpio0", "gpio1",
4472                                        "gpio2";
4473                                 function = "qup19";
4474                         };
4475
4476                         qup_uart2_default: qup-uart2-default {
4477                                 mux {
4478                                         pins = "gpio117", "gpio118";
4479                                         function = "qup2";
4480                                 };
4481                         };
4482
4483                         qup_uart6_default: qup-uart6-default {
4484                                 mux {
4485                                         pins = "gpio16", "gpio17",
4486                                                 "gpio18", "gpio19";
4487                                         function = "qup6";
4488                                 };
4489                         };
4490
4491                         qup_uart12_default: qup-uart12-default {
4492                                 mux {
4493                                         pins = "gpio34", "gpio35";
4494                                         function = "qup12";
4495                                 };
4496                         };
4497
4498                         qup_uart17_default: qup-uart17-default {
4499                                 mux {
4500                                         pins = "gpio52", "gpio53",
4501                                                 "gpio54", "gpio55";
4502                                         function = "qup17";
4503                                 };
4504                         };
4505
4506                         qup_uart18_default: qup-uart18-default {
4507                                 mux {
4508                                         pins = "gpio58", "gpio59";
4509                                         function = "qup18";
4510                                 };
4511                         };
4512
4513                         tert_mi2s_active: tert-mi2s-active {
4514                                 sck {
4515                                         pins = "gpio133";
4516                                         function = "mi2s2_sck";
4517                                         drive-strength = <8>;
4518                                         bias-disable;
4519                                 };
4520
4521                                 data0 {
4522                                         pins = "gpio134";
4523                                         function = "mi2s2_data0";
4524                                         drive-strength = <8>;
4525                                         bias-disable;
4526                                         output-high;
4527                                 };
4528
4529                                 ws {
4530                                         pins = "gpio135";
4531                                         function = "mi2s2_ws";
4532                                         drive-strength = <8>;
4533                                         output-high;
4534                                 };
4535                         };
4536
4537                         sdc2_sleep_state: sdc2-sleep {
4538                                 clk {
4539                                         pins = "sdc2_clk";
4540                                         drive-strength = <2>;
4541                                         bias-disable;
4542                                 };
4543
4544                                 cmd {
4545                                         pins = "sdc2_cmd";
4546                                         drive-strength = <2>;
4547                                         bias-pull-up;
4548                                 };
4549
4550                                 data {
4551                                         pins = "sdc2_data";
4552                                         drive-strength = <2>;
4553                                         bias-pull-up;
4554                                 };
4555                         };
4556
4557                         pcie0_default_state: pcie0-default {
4558                                 perst {
4559                                         pins = "gpio79";
4560                                         function = "gpio";
4561                                         drive-strength = <2>;
4562                                         bias-pull-down;
4563                                 };
4564
4565                                 clkreq {
4566                                         pins = "gpio80";
4567                                         function = "pci_e0";
4568                                         drive-strength = <2>;
4569                                         bias-pull-up;
4570                                 };
4571
4572                                 wake {
4573                                         pins = "gpio81";
4574                                         function = "gpio";
4575                                         drive-strength = <2>;
4576                                         bias-pull-up;
4577                                 };
4578                         };
4579
4580                         pcie1_default_state: pcie1-default {
4581                                 perst {
4582                                         pins = "gpio82";
4583                                         function = "gpio";
4584                                         drive-strength = <2>;
4585                                         bias-pull-down;
4586                                 };
4587
4588                                 clkreq {
4589                                         pins = "gpio83";
4590                                         function = "pci_e1";
4591                                         drive-strength = <2>;
4592                                         bias-pull-up;
4593                                 };
4594
4595                                 wake {
4596                                         pins = "gpio84";
4597                                         function = "gpio";
4598                                         drive-strength = <2>;
4599                                         bias-pull-up;
4600                                 };
4601                         };
4602
4603                         pcie2_default_state: pcie2-default {
4604                                 perst {
4605                                         pins = "gpio85";
4606                                         function = "gpio";
4607                                         drive-strength = <2>;
4608                                         bias-pull-down;
4609                                 };
4610
4611                                 clkreq {
4612                                         pins = "gpio86";
4613                                         function = "pci_e2";
4614                                         drive-strength = <2>;
4615                                         bias-pull-up;
4616                                 };
4617
4618                                 wake {
4619                                         pins = "gpio87";
4620                                         function = "gpio";
4621                                         drive-strength = <2>;
4622                                         bias-pull-up;
4623                                 };
4624                         };
4625                 };
4626
4627                 apps_smmu: iommu@15000000 {
4628                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
4629                         reg = <0 0x15000000 0 0x100000>;
4630                         #iommu-cells = <2>;
4631                         #global-interrupts = <2>;
4632                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4633                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4634                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4635                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4636                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4637                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4638                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4639                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4640                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4641                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4642                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4643                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4644                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4645                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4646                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4647                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4648                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4649                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4650                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4651                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4652                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4653                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4654                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4655                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4656                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4657                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4658                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4659                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4660                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4661                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4662                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4663                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4664                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4665                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4666                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4667                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4668                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4669                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4670                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4671                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4672                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4673                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4674                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4675                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4676                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4677                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4678                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4679                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4680                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4681                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4682                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4683                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4684                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4685                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4686                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4687                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4688                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4689                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4690                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4691                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4692                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4693                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4694                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4695                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4696                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4697                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4698                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4699                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4700                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4701                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4702                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4703                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4704                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4705                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4706                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4707                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4708                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4709                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4710                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4711                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4712                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4713                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4714                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4715                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4716                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4717                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4718                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4719                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4720                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4721                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4722                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4723                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4724                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4725                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4726                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4727                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4728                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
4729                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
4730                 };
4731
4732                 adsp: remoteproc@17300000 {
4733                         compatible = "qcom,sm8250-adsp-pas";
4734                         reg = <0 0x17300000 0 0x100>;
4735
4736                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
4737                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4738                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
4739                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
4740                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
4741                         interrupt-names = "wdog", "fatal", "ready",
4742                                           "handover", "stop-ack";
4743
4744                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4745                         clock-names = "xo";
4746
4747                         power-domains = <&rpmhpd SM8250_LCX>,
4748                                         <&rpmhpd SM8250_LMX>;
4749                         power-domain-names = "lcx", "lmx";
4750
4751                         memory-region = <&adsp_mem>;
4752
4753                         qcom,qmp = <&aoss_qmp>;
4754
4755                         qcom,smem-states = <&smp2p_adsp_out 0>;
4756                         qcom,smem-state-names = "stop";
4757
4758                         status = "disabled";
4759
4760                         glink-edge {
4761                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4762                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4763                                                              IRQ_TYPE_EDGE_RISING>;
4764                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
4765                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4766
4767                                 label = "lpass";
4768                                 qcom,remote-pid = <2>;
4769
4770                                 apr {
4771                                         compatible = "qcom,apr-v2";
4772                                         qcom,glink-channels = "apr_audio_svc";
4773                                         qcom,domain = <APR_DOMAIN_ADSP>;
4774                                         #address-cells = <1>;
4775                                         #size-cells = <0>;
4776
4777                                         apr-service@3 {
4778                                                 reg = <APR_SVC_ADSP_CORE>;
4779                                                 compatible = "qcom,q6core";
4780                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4781                                         };
4782
4783                                         q6afe: apr-service@4 {
4784                                                 compatible = "qcom,q6afe";
4785                                                 reg = <APR_SVC_AFE>;
4786                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4787                                                 q6afedai: dais {
4788                                                         compatible = "qcom,q6afe-dais";
4789                                                         #address-cells = <1>;
4790                                                         #size-cells = <0>;
4791                                                         #sound-dai-cells = <1>;
4792                                                 };
4793
4794                                                 q6afecc: cc {
4795                                                         compatible = "qcom,q6afe-clocks";
4796                                                         #clock-cells = <2>;
4797                                                 };
4798                                         };
4799
4800                                         q6asm: apr-service@7 {
4801                                                 compatible = "qcom,q6asm";
4802                                                 reg = <APR_SVC_ASM>;
4803                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4804                                                 q6asmdai: dais {
4805                                                         compatible = "qcom,q6asm-dais";
4806                                                         #address-cells = <1>;
4807                                                         #size-cells = <0>;
4808                                                         #sound-dai-cells = <1>;
4809                                                         iommus = <&apps_smmu 0x1801 0x0>;
4810                                                 };
4811                                         };
4812
4813                                         q6adm: apr-service@8 {
4814                                                 compatible = "qcom,q6adm";
4815                                                 reg = <APR_SVC_ADM>;
4816                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4817                                                 q6routing: routing {
4818                                                         compatible = "qcom,q6adm-routing";
4819                                                         #sound-dai-cells = <0>;
4820                                                 };
4821                                         };
4822                                 };
4823
4824                                 fastrpc {
4825                                         compatible = "qcom,fastrpc";
4826                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4827                                         label = "adsp";
4828                                         qcom,non-secure-domain;
4829                                         #address-cells = <1>;
4830                                         #size-cells = <0>;
4831
4832                                         compute-cb@3 {
4833                                                 compatible = "qcom,fastrpc-compute-cb";
4834                                                 reg = <3>;
4835                                                 iommus = <&apps_smmu 0x1803 0x0>;
4836                                         };
4837
4838                                         compute-cb@4 {
4839                                                 compatible = "qcom,fastrpc-compute-cb";
4840                                                 reg = <4>;
4841                                                 iommus = <&apps_smmu 0x1804 0x0>;
4842                                         };
4843
4844                                         compute-cb@5 {
4845                                                 compatible = "qcom,fastrpc-compute-cb";
4846                                                 reg = <5>;
4847                                                 iommus = <&apps_smmu 0x1805 0x0>;
4848                                         };
4849                                 };
4850                         };
4851                 };
4852
4853                 intc: interrupt-controller@17a00000 {
4854                         compatible = "arm,gic-v3";
4855                         #interrupt-cells = <3>;
4856                         interrupt-controller;
4857                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
4858                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
4859                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4860                 };
4861
4862                 watchdog@17c10000 {
4863                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
4864                         reg = <0 0x17c10000 0 0x1000>;
4865                         clocks = <&sleep_clk>;
4866                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4867                 };
4868
4869                 timer@17c20000 {
4870                         #address-cells = <2>;
4871                         #size-cells = <2>;
4872                         ranges;
4873                         compatible = "arm,armv7-timer-mem";
4874                         reg = <0x0 0x17c20000 0x0 0x1000>;
4875                         clock-frequency = <19200000>;
4876
4877                         frame@17c21000 {
4878                                 frame-number = <0>;
4879                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4880                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4881                                 reg = <0x0 0x17c21000 0x0 0x1000>,
4882                                       <0x0 0x17c22000 0x0 0x1000>;
4883                         };
4884
4885                         frame@17c23000 {
4886                                 frame-number = <1>;
4887                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4888                                 reg = <0x0 0x17c23000 0x0 0x1000>;
4889                                 status = "disabled";
4890                         };
4891
4892                         frame@17c25000 {
4893                                 frame-number = <2>;
4894                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4895                                 reg = <0x0 0x17c25000 0x0 0x1000>;
4896                                 status = "disabled";
4897                         };
4898
4899                         frame@17c27000 {
4900                                 frame-number = <3>;
4901                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4902                                 reg = <0x0 0x17c27000 0x0 0x1000>;
4903                                 status = "disabled";
4904                         };
4905
4906                         frame@17c29000 {
4907                                 frame-number = <4>;
4908                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4909                                 reg = <0x0 0x17c29000 0x0 0x1000>;
4910                                 status = "disabled";
4911                         };
4912
4913                         frame@17c2b000 {
4914                                 frame-number = <5>;
4915                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4916                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
4917                                 status = "disabled";
4918                         };
4919
4920                         frame@17c2d000 {
4921                                 frame-number = <6>;
4922                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4923                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
4924                                 status = "disabled";
4925                         };
4926                 };
4927
4928                 apps_rsc: rsc@18200000 {
4929                         label = "apps_rsc";
4930                         compatible = "qcom,rpmh-rsc";
4931                         reg = <0x0 0x18200000 0x0 0x10000>,
4932                                 <0x0 0x18210000 0x0 0x10000>,
4933                                 <0x0 0x18220000 0x0 0x10000>;
4934                         reg-names = "drv-0", "drv-1", "drv-2";
4935                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4936                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4937                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4938                         qcom,tcs-offset = <0xd00>;
4939                         qcom,drv-id = <2>;
4940                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
4941                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
4942
4943                         rpmhcc: clock-controller {
4944                                 compatible = "qcom,sm8250-rpmh-clk";
4945                                 #clock-cells = <1>;
4946                                 clock-names = "xo";
4947                                 clocks = <&xo_board>;
4948                         };
4949
4950                         rpmhpd: power-controller {
4951                                 compatible = "qcom,sm8250-rpmhpd";
4952                                 #power-domain-cells = <1>;
4953                                 operating-points-v2 = <&rpmhpd_opp_table>;
4954
4955                                 rpmhpd_opp_table: opp-table {
4956                                         compatible = "operating-points-v2";
4957
4958                                         rpmhpd_opp_ret: opp1 {
4959                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4960                                         };
4961
4962                                         rpmhpd_opp_min_svs: opp2 {
4963                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964                                         };
4965
4966                                         rpmhpd_opp_low_svs: opp3 {
4967                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4968                                         };
4969
4970                                         rpmhpd_opp_svs: opp4 {
4971                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4972                                         };
4973
4974                                         rpmhpd_opp_svs_l1: opp5 {
4975                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4976                                         };
4977
4978                                         rpmhpd_opp_nom: opp6 {
4979                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4980                                         };
4981
4982                                         rpmhpd_opp_nom_l1: opp7 {
4983                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4984                                         };
4985
4986                                         rpmhpd_opp_nom_l2: opp8 {
4987                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4988                                         };
4989
4990                                         rpmhpd_opp_turbo: opp9 {
4991                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4992                                         };
4993
4994                                         rpmhpd_opp_turbo_l1: opp10 {
4995                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4996                                         };
4997                                 };
4998                         };
4999
5000                         apps_bcm_voter: bcm-voter {
5001                                 compatible = "qcom,bcm-voter";
5002                         };
5003                 };
5004
5005                 epss_l3: interconnect@18590000 {
5006                         compatible = "qcom,sm8250-epss-l3";
5007                         reg = <0 0x18590000 0 0x1000>;
5008
5009                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5010                         clock-names = "xo", "alternate";
5011
5012                         #interconnect-cells = <1>;
5013                 };
5014
5015                 cpufreq_hw: cpufreq@18591000 {
5016                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
5017                         reg = <0 0x18591000 0 0x1000>,
5018                               <0 0x18592000 0 0x1000>,
5019                               <0 0x18593000 0 0x1000>;
5020                         reg-names = "freq-domain0", "freq-domain1",
5021                                     "freq-domain2";
5022
5023                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5024                         clock-names = "xo", "alternate";
5025                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
5026                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5027                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5028                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5029                         #freq-domain-cells = <1>;
5030                 };
5031         };
5032
5033         timer {
5034                 compatible = "arm,armv8-timer";
5035                 interrupts = <GIC_PPI 13
5036                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5037                              <GIC_PPI 14
5038                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5039                              <GIC_PPI 11
5040                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5041                              <GIC_PPI 10
5042                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5043         };
5044
5045         thermal-zones {
5046                 cpu0-thermal {
5047                         polling-delay-passive = <250>;
5048                         polling-delay = <1000>;
5049
5050                         thermal-sensors = <&tsens0 1>;
5051
5052                         trips {
5053                                 cpu0_alert0: trip-point0 {
5054                                         temperature = <90000>;
5055                                         hysteresis = <2000>;
5056                                         type = "passive";
5057                                 };
5058
5059                                 cpu0_alert1: trip-point1 {
5060                                         temperature = <95000>;
5061                                         hysteresis = <2000>;
5062                                         type = "passive";
5063                                 };
5064
5065                                 cpu0_crit: cpu_crit {
5066                                         temperature = <110000>;
5067                                         hysteresis = <1000>;
5068                                         type = "critical";
5069                                 };
5070                         };
5071
5072                         cooling-maps {
5073                                 map0 {
5074                                         trip = <&cpu0_alert0>;
5075                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5078                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5079                                 };
5080                                 map1 {
5081                                         trip = <&cpu0_alert1>;
5082                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5083                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5084                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5085                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5086                                 };
5087                         };
5088                 };
5089
5090                 cpu1-thermal {
5091                         polling-delay-passive = <250>;
5092                         polling-delay = <1000>;
5093
5094                         thermal-sensors = <&tsens0 2>;
5095
5096                         trips {
5097                                 cpu1_alert0: trip-point0 {
5098                                         temperature = <90000>;
5099                                         hysteresis = <2000>;
5100                                         type = "passive";
5101                                 };
5102
5103                                 cpu1_alert1: trip-point1 {
5104                                         temperature = <95000>;
5105                                         hysteresis = <2000>;
5106                                         type = "passive";
5107                                 };
5108
5109                                 cpu1_crit: cpu_crit {
5110                                         temperature = <110000>;
5111                                         hysteresis = <1000>;
5112                                         type = "critical";
5113                                 };
5114                         };
5115
5116                         cooling-maps {
5117                                 map0 {
5118                                         trip = <&cpu1_alert0>;
5119                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5121                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5122                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5123                                 };
5124                                 map1 {
5125                                         trip = <&cpu1_alert1>;
5126                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5127                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5128                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5129                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5130                                 };
5131                         };
5132                 };
5133
5134                 cpu2-thermal {
5135                         polling-delay-passive = <250>;
5136                         polling-delay = <1000>;
5137
5138                         thermal-sensors = <&tsens0 3>;
5139
5140                         trips {
5141                                 cpu2_alert0: trip-point0 {
5142                                         temperature = <90000>;
5143                                         hysteresis = <2000>;
5144                                         type = "passive";
5145                                 };
5146
5147                                 cpu2_alert1: trip-point1 {
5148                                         temperature = <95000>;
5149                                         hysteresis = <2000>;
5150                                         type = "passive";
5151                                 };
5152
5153                                 cpu2_crit: cpu_crit {
5154                                         temperature = <110000>;
5155                                         hysteresis = <1000>;
5156                                         type = "critical";
5157                                 };
5158                         };
5159
5160                         cooling-maps {
5161                                 map0 {
5162                                         trip = <&cpu2_alert0>;
5163                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5164                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5165                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5166                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5167                                 };
5168                                 map1 {
5169                                         trip = <&cpu2_alert1>;
5170                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5171                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5172                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5173                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5174                                 };
5175                         };
5176                 };
5177
5178                 cpu3-thermal {
5179                         polling-delay-passive = <250>;
5180                         polling-delay = <1000>;
5181
5182                         thermal-sensors = <&tsens0 4>;
5183
5184                         trips {
5185                                 cpu3_alert0: trip-point0 {
5186                                         temperature = <90000>;
5187                                         hysteresis = <2000>;
5188                                         type = "passive";
5189                                 };
5190
5191                                 cpu3_alert1: trip-point1 {
5192                                         temperature = <95000>;
5193                                         hysteresis = <2000>;
5194                                         type = "passive";
5195                                 };
5196
5197                                 cpu3_crit: cpu_crit {
5198                                         temperature = <110000>;
5199                                         hysteresis = <1000>;
5200                                         type = "critical";
5201                                 };
5202                         };
5203
5204                         cooling-maps {
5205                                 map0 {
5206                                         trip = <&cpu3_alert0>;
5207                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5208                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5209                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5210                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5211                                 };
5212                                 map1 {
5213                                         trip = <&cpu3_alert1>;
5214                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5215                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5216                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5217                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5218                                 };
5219                         };
5220                 };
5221
5222                 cpu4-top-thermal {
5223                         polling-delay-passive = <250>;
5224                         polling-delay = <1000>;
5225
5226                         thermal-sensors = <&tsens0 7>;
5227
5228                         trips {
5229                                 cpu4_top_alert0: trip-point0 {
5230                                         temperature = <90000>;
5231                                         hysteresis = <2000>;
5232                                         type = "passive";
5233                                 };
5234
5235                                 cpu4_top_alert1: trip-point1 {
5236                                         temperature = <95000>;
5237                                         hysteresis = <2000>;
5238                                         type = "passive";
5239                                 };
5240
5241                                 cpu4_top_crit: cpu_crit {
5242                                         temperature = <110000>;
5243                                         hysteresis = <1000>;
5244                                         type = "critical";
5245                                 };
5246                         };
5247
5248                         cooling-maps {
5249                                 map0 {
5250                                         trip = <&cpu4_top_alert0>;
5251                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5252                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5253                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5254                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5255                                 };
5256                                 map1 {
5257                                         trip = <&cpu4_top_alert1>;
5258                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5259                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5260                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5261                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5262                                 };
5263                         };
5264                 };
5265
5266                 cpu5-top-thermal {
5267                         polling-delay-passive = <250>;
5268                         polling-delay = <1000>;
5269
5270                         thermal-sensors = <&tsens0 8>;
5271
5272                         trips {
5273                                 cpu5_top_alert0: trip-point0 {
5274                                         temperature = <90000>;
5275                                         hysteresis = <2000>;
5276                                         type = "passive";
5277                                 };
5278
5279                                 cpu5_top_alert1: trip-point1 {
5280                                         temperature = <95000>;
5281                                         hysteresis = <2000>;
5282                                         type = "passive";
5283                                 };
5284
5285                                 cpu5_top_crit: cpu_crit {
5286                                         temperature = <110000>;
5287                                         hysteresis = <1000>;
5288                                         type = "critical";
5289                                 };
5290                         };
5291
5292                         cooling-maps {
5293                                 map0 {
5294                                         trip = <&cpu5_top_alert0>;
5295                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5296                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5297                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5298                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5299                                 };
5300                                 map1 {
5301                                         trip = <&cpu5_top_alert1>;
5302                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5303                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5304                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5305                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5306                                 };
5307                         };
5308                 };
5309
5310                 cpu6-top-thermal {
5311                         polling-delay-passive = <250>;
5312                         polling-delay = <1000>;
5313
5314                         thermal-sensors = <&tsens0 9>;
5315
5316                         trips {
5317                                 cpu6_top_alert0: trip-point0 {
5318                                         temperature = <90000>;
5319                                         hysteresis = <2000>;
5320                                         type = "passive";
5321                                 };
5322
5323                                 cpu6_top_alert1: trip-point1 {
5324                                         temperature = <95000>;
5325                                         hysteresis = <2000>;
5326                                         type = "passive";
5327                                 };
5328
5329                                 cpu6_top_crit: cpu_crit {
5330                                         temperature = <110000>;
5331                                         hysteresis = <1000>;
5332                                         type = "critical";
5333                                 };
5334                         };
5335
5336                         cooling-maps {
5337                                 map0 {
5338                                         trip = <&cpu6_top_alert0>;
5339                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5340                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5341                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5342                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5343                                 };
5344                                 map1 {
5345                                         trip = <&cpu6_top_alert1>;
5346                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5347                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5348                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5349                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5350                                 };
5351                         };
5352                 };
5353
5354                 cpu7-top-thermal {
5355                         polling-delay-passive = <250>;
5356                         polling-delay = <1000>;
5357
5358                         thermal-sensors = <&tsens0 10>;
5359
5360                         trips {
5361                                 cpu7_top_alert0: trip-point0 {
5362                                         temperature = <90000>;
5363                                         hysteresis = <2000>;
5364                                         type = "passive";
5365                                 };
5366
5367                                 cpu7_top_alert1: trip-point1 {
5368                                         temperature = <95000>;
5369                                         hysteresis = <2000>;
5370                                         type = "passive";
5371                                 };
5372
5373                                 cpu7_top_crit: cpu_crit {
5374                                         temperature = <110000>;
5375                                         hysteresis = <1000>;
5376                                         type = "critical";
5377                                 };
5378                         };
5379
5380                         cooling-maps {
5381                                 map0 {
5382                                         trip = <&cpu7_top_alert0>;
5383                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5384                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5385                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5386                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5387                                 };
5388                                 map1 {
5389                                         trip = <&cpu7_top_alert1>;
5390                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5391                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5392                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5393                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5394                                 };
5395                         };
5396                 };
5397
5398                 cpu4-bottom-thermal {
5399                         polling-delay-passive = <250>;
5400                         polling-delay = <1000>;
5401
5402                         thermal-sensors = <&tsens0 11>;
5403
5404                         trips {
5405                                 cpu4_bottom_alert0: trip-point0 {
5406                                         temperature = <90000>;
5407                                         hysteresis = <2000>;
5408                                         type = "passive";
5409                                 };
5410
5411                                 cpu4_bottom_alert1: trip-point1 {
5412                                         temperature = <95000>;
5413                                         hysteresis = <2000>;
5414                                         type = "passive";
5415                                 };
5416
5417                                 cpu4_bottom_crit: cpu_crit {
5418                                         temperature = <110000>;
5419                                         hysteresis = <1000>;
5420                                         type = "critical";
5421                                 };
5422                         };
5423
5424                         cooling-maps {
5425                                 map0 {
5426                                         trip = <&cpu4_bottom_alert0>;
5427                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5428                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5429                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5430                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5431                                 };
5432                                 map1 {
5433                                         trip = <&cpu4_bottom_alert1>;
5434                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5435                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5436                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5437                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5438                                 };
5439                         };
5440                 };
5441
5442                 cpu5-bottom-thermal {
5443                         polling-delay-passive = <250>;
5444                         polling-delay = <1000>;
5445
5446                         thermal-sensors = <&tsens0 12>;
5447
5448                         trips {
5449                                 cpu5_bottom_alert0: trip-point0 {
5450                                         temperature = <90000>;
5451                                         hysteresis = <2000>;
5452                                         type = "passive";
5453                                 };
5454
5455                                 cpu5_bottom_alert1: trip-point1 {
5456                                         temperature = <95000>;
5457                                         hysteresis = <2000>;
5458                                         type = "passive";
5459                                 };
5460
5461                                 cpu5_bottom_crit: cpu_crit {
5462                                         temperature = <110000>;
5463                                         hysteresis = <1000>;
5464                                         type = "critical";
5465                                 };
5466                         };
5467
5468                         cooling-maps {
5469                                 map0 {
5470                                         trip = <&cpu5_bottom_alert0>;
5471                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5472                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5473                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5474                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5475                                 };
5476                                 map1 {
5477                                         trip = <&cpu5_bottom_alert1>;
5478                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5479                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5480                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5481                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5482                                 };
5483                         };
5484                 };
5485
5486                 cpu6-bottom-thermal {
5487                         polling-delay-passive = <250>;
5488                         polling-delay = <1000>;
5489
5490                         thermal-sensors = <&tsens0 13>;
5491
5492                         trips {
5493                                 cpu6_bottom_alert0: trip-point0 {
5494                                         temperature = <90000>;
5495                                         hysteresis = <2000>;
5496                                         type = "passive";
5497                                 };
5498
5499                                 cpu6_bottom_alert1: trip-point1 {
5500                                         temperature = <95000>;
5501                                         hysteresis = <2000>;
5502                                         type = "passive";
5503                                 };
5504
5505                                 cpu6_bottom_crit: cpu_crit {
5506                                         temperature = <110000>;
5507                                         hysteresis = <1000>;
5508                                         type = "critical";
5509                                 };
5510                         };
5511
5512                         cooling-maps {
5513                                 map0 {
5514                                         trip = <&cpu6_bottom_alert0>;
5515                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5516                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5517                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5518                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5519                                 };
5520                                 map1 {
5521                                         trip = <&cpu6_bottom_alert1>;
5522                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5523                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5524                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5525                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5526                                 };
5527                         };
5528                 };
5529
5530                 cpu7-bottom-thermal {
5531                         polling-delay-passive = <250>;
5532                         polling-delay = <1000>;
5533
5534                         thermal-sensors = <&tsens0 14>;
5535
5536                         trips {
5537                                 cpu7_bottom_alert0: trip-point0 {
5538                                         temperature = <90000>;
5539                                         hysteresis = <2000>;
5540                                         type = "passive";
5541                                 };
5542
5543                                 cpu7_bottom_alert1: trip-point1 {
5544                                         temperature = <95000>;
5545                                         hysteresis = <2000>;
5546                                         type = "passive";
5547                                 };
5548
5549                                 cpu7_bottom_crit: cpu_crit {
5550                                         temperature = <110000>;
5551                                         hysteresis = <1000>;
5552                                         type = "critical";
5553                                 };
5554                         };
5555
5556                         cooling-maps {
5557                                 map0 {
5558                                         trip = <&cpu7_bottom_alert0>;
5559                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5560                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5561                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5562                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5563                                 };
5564                                 map1 {
5565                                         trip = <&cpu7_bottom_alert1>;
5566                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5567                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5568                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5569                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5570                                 };
5571                         };
5572                 };
5573
5574                 aoss0-thermal {
5575                         polling-delay-passive = <250>;
5576                         polling-delay = <1000>;
5577
5578                         thermal-sensors = <&tsens0 0>;
5579
5580                         trips {
5581                                 aoss0_alert0: trip-point0 {
5582                                         temperature = <90000>;
5583                                         hysteresis = <2000>;
5584                                         type = "hot";
5585                                 };
5586                         };
5587                 };
5588
5589                 cluster0-thermal {
5590                         polling-delay-passive = <250>;
5591                         polling-delay = <1000>;
5592
5593                         thermal-sensors = <&tsens0 5>;
5594
5595                         trips {
5596                                 cluster0_alert0: trip-point0 {
5597                                         temperature = <90000>;
5598                                         hysteresis = <2000>;
5599                                         type = "hot";
5600                                 };
5601                                 cluster0_crit: cluster0_crit {
5602                                         temperature = <110000>;
5603                                         hysteresis = <2000>;
5604                                         type = "critical";
5605                                 };
5606                         };
5607                 };
5608
5609                 cluster1-thermal {
5610                         polling-delay-passive = <250>;
5611                         polling-delay = <1000>;
5612
5613                         thermal-sensors = <&tsens0 6>;
5614
5615                         trips {
5616                                 cluster1_alert0: trip-point0 {
5617                                         temperature = <90000>;
5618                                         hysteresis = <2000>;
5619                                         type = "hot";
5620                                 };
5621                                 cluster1_crit: cluster1_crit {
5622                                         temperature = <110000>;
5623                                         hysteresis = <2000>;
5624                                         type = "critical";
5625                                 };
5626                         };
5627                 };
5628
5629                 gpu-top-thermal {
5630                         polling-delay-passive = <250>;
5631                         polling-delay = <1000>;
5632
5633                         thermal-sensors = <&tsens0 15>;
5634
5635                         trips {
5636                                 gpu1_alert0: trip-point0 {
5637                                         temperature = <90000>;
5638                                         hysteresis = <2000>;
5639                                         type = "hot";
5640                                 };
5641                         };
5642                 };
5643
5644                 aoss1-thermal {
5645                         polling-delay-passive = <250>;
5646                         polling-delay = <1000>;
5647
5648                         thermal-sensors = <&tsens1 0>;
5649
5650                         trips {
5651                                 aoss1_alert0: trip-point0 {
5652                                         temperature = <90000>;
5653                                         hysteresis = <2000>;
5654                                         type = "hot";
5655                                 };
5656                         };
5657                 };
5658
5659                 wlan-thermal {
5660                         polling-delay-passive = <250>;
5661                         polling-delay = <1000>;
5662
5663                         thermal-sensors = <&tsens1 1>;
5664
5665                         trips {
5666                                 wlan_alert0: trip-point0 {
5667                                         temperature = <90000>;
5668                                         hysteresis = <2000>;
5669                                         type = "hot";
5670                                 };
5671                         };
5672                 };
5673
5674                 video-thermal {
5675                         polling-delay-passive = <250>;
5676                         polling-delay = <1000>;
5677
5678                         thermal-sensors = <&tsens1 2>;
5679
5680                         trips {
5681                                 video_alert0: trip-point0 {
5682                                         temperature = <90000>;
5683                                         hysteresis = <2000>;
5684                                         type = "hot";
5685                                 };
5686                         };
5687                 };
5688
5689                 mem-thermal {
5690                         polling-delay-passive = <250>;
5691                         polling-delay = <1000>;
5692
5693                         thermal-sensors = <&tsens1 3>;
5694
5695                         trips {
5696                                 mem_alert0: trip-point0 {
5697                                         temperature = <90000>;
5698                                         hysteresis = <2000>;
5699                                         type = "hot";
5700                                 };
5701                         };
5702                 };
5703
5704                 q6-hvx-thermal {
5705                         polling-delay-passive = <250>;
5706                         polling-delay = <1000>;
5707
5708                         thermal-sensors = <&tsens1 4>;
5709
5710                         trips {
5711                                 q6_hvx_alert0: trip-point0 {
5712                                         temperature = <90000>;
5713                                         hysteresis = <2000>;
5714                                         type = "hot";
5715                                 };
5716                         };
5717                 };
5718
5719                 camera-thermal {
5720                         polling-delay-passive = <250>;
5721                         polling-delay = <1000>;
5722
5723                         thermal-sensors = <&tsens1 5>;
5724
5725                         trips {
5726                                 camera_alert0: trip-point0 {
5727                                         temperature = <90000>;
5728                                         hysteresis = <2000>;
5729                                         type = "hot";
5730                                 };
5731                         };
5732                 };
5733
5734                 compute-thermal {
5735                         polling-delay-passive = <250>;
5736                         polling-delay = <1000>;
5737
5738                         thermal-sensors = <&tsens1 6>;
5739
5740                         trips {
5741                                 compute_alert0: trip-point0 {
5742                                         temperature = <90000>;
5743                                         hysteresis = <2000>;
5744                                         type = "hot";
5745                                 };
5746                         };
5747                 };
5748
5749                 npu-thermal {
5750                         polling-delay-passive = <250>;
5751                         polling-delay = <1000>;
5752
5753                         thermal-sensors = <&tsens1 7>;
5754
5755                         trips {
5756                                 npu_alert0: trip-point0 {
5757                                         temperature = <90000>;
5758                                         hysteresis = <2000>;
5759                                         type = "hot";
5760                                 };
5761                         };
5762                 };
5763
5764                 gpu-bottom-thermal {
5765                         polling-delay-passive = <250>;
5766                         polling-delay = <1000>;
5767
5768                         thermal-sensors = <&tsens1 8>;
5769
5770                         trips {
5771                                 gpu2_alert0: trip-point0 {
5772                                         temperature = <90000>;
5773                                         hysteresis = <2000>;
5774                                         type = "hot";
5775                                 };
5776                         };
5777                 };
5778         };
5779 };