arch/arm64/boot/dts/qcom/sm6115.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
   4  */
   5
   6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
   7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
   8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
   9 #include <dt-bindings/clock/qcom,rpmcc.h>
  10 #include <dt-bindings/dma/qcom-gpi.h>
  11 #include <dt-bindings/firmware/qcom,scm.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
  14 #include <dt-bindings/interconnect/qcom,sm6115.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/power/qcom-rpmpd.h>
  17
  18 / {
  19         interrupt-parent = <&intc>;
  20
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         chosen { };
  25
  26         clocks {
  27                 xo_board: xo-board {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                 };
  31
  32                 sleep_clk: sleep-clk {
  33                         compatible = "fixed-clock";
  34                         #clock-cells = <0>;
  35                 };
  36         };
  37
  38         cpus {
  39                 #address-cells = <2>;
  40                 #size-cells = <0>;
  41
  42                 CPU0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "qcom,kryo260";
  45                         reg = <0x0 0x0>;
  46                         clocks = <&cpufreq_hw 0>;
  47                         capacity-dmips-mhz = <1024>;
  48                         dynamic-power-coefficient = <100>;
  49                         enable-method = "psci";
  50                         next-level-cache = <&L2_0>;
  51                         qcom,freq-domain = <&cpufreq_hw 0>;
  52                         power-domains = <&CPU_PD0>;
  53                         power-domain-names = "psci";
  54                         L2_0: l2-cache {
  55                                 compatible = "cache";
  56                                 cache-level = <2>;
  57                                 cache-unified;
  58                         };
  59                 };
  60
  61                 CPU1: cpu@1 {
  62                         device_type = "cpu";
  63                         compatible = "qcom,kryo260";
  64                         reg = <0x0 0x1>;
  65                         clocks = <&cpufreq_hw 0>;
  66                         capacity-dmips-mhz = <1024>;
  67                         dynamic-power-coefficient = <100>;
  68                         enable-method = "psci";
  69                         next-level-cache = <&L2_0>;
  70                         qcom,freq-domain = <&cpufreq_hw 0>;
  71                         power-domains = <&CPU_PD1>;
  72                         power-domain-names = "psci";
  73                 };
  74
  75                 CPU2: cpu@2 {
  76                         device_type = "cpu";
  77                         compatible = "qcom,kryo260";
  78                         reg = <0x0 0x2>;
  79                         clocks = <&cpufreq_hw 0>;
  80                         capacity-dmips-mhz = <1024>;
  81                         dynamic-power-coefficient = <100>;
  82                         enable-method = "psci";
  83                         next-level-cache = <&L2_0>;
  84                         qcom,freq-domain = <&cpufreq_hw 0>;
  85                         power-domains = <&CPU_PD2>;
  86                         power-domain-names = "psci";
  87                 };
  88
  89                 CPU3: cpu@3 {
  90                         device_type = "cpu";
  91                         compatible = "qcom,kryo260";
  92                         reg = <0x0 0x3>;
  93                         clocks = <&cpufreq_hw 0>;
  94                         capacity-dmips-mhz = <1024>;
  95                         dynamic-power-coefficient = <100>;
  96                         enable-method = "psci";
  97                         next-level-cache = <&L2_0>;
  98                         qcom,freq-domain = <&cpufreq_hw 0>;
  99                         power-domains = <&CPU_PD3>;
 100                         power-domain-names = "psci";
 101                 };
 102
 103                 CPU4: cpu@100 {
 104                         device_type = "cpu";
 105                         compatible = "qcom,kryo260";
 106                         reg = <0x0 0x100>;
 107                         clocks = <&cpufreq_hw 1>;
 108                         enable-method = "psci";
 109                         capacity-dmips-mhz = <1638>;
 110                         dynamic-power-coefficient = <282>;
 111                         next-level-cache = <&L2_1>;
 112                         qcom,freq-domain = <&cpufreq_hw 1>;
 113                         power-domains = <&CPU_PD4>;
 114                         power-domain-names = "psci";
 115                         L2_1: l2-cache {
 116                                 compatible = "cache";
 117                                 cache-level = <2>;
 118                                 cache-unified;
 119                         };
 120                 };
 121
 122                 CPU5: cpu@101 {
 123                         device_type = "cpu";
 124                         compatible = "qcom,kryo260";
 125                         reg = <0x0 0x101>;
 126                         clocks = <&cpufreq_hw 1>;
 127                         capacity-dmips-mhz = <1638>;
 128                         dynamic-power-coefficient = <282>;
 129                         enable-method = "psci";
 130                         next-level-cache = <&L2_1>;
 131                         qcom,freq-domain = <&cpufreq_hw 1>;
 132                         power-domains = <&CPU_PD5>;
 133                         power-domain-names = "psci";
 134                 };
 135
 136                 CPU6: cpu@102 {
 137                         device_type = "cpu";
 138                         compatible = "qcom,kryo260";
 139                         reg = <0x0 0x102>;
 140                         clocks = <&cpufreq_hw 1>;
 141                         capacity-dmips-mhz = <1638>;
 142                         dynamic-power-coefficient = <282>;
 143                         enable-method = "psci";
 144                         next-level-cache = <&L2_1>;
 145                         qcom,freq-domain = <&cpufreq_hw 1>;
 146                         power-domains = <&CPU_PD6>;
 147                         power-domain-names = "psci";
 148                 };
 149
 150                 CPU7: cpu@103 {
 151                         device_type = "cpu";
 152                         compatible = "qcom,kryo260";
 153                         reg = <0x0 0x103>;
 154                         clocks = <&cpufreq_hw 1>;
 155                         capacity-dmips-mhz = <1638>;
 156                         dynamic-power-coefficient = <282>;
 157                         enable-method = "psci";
 158                         next-level-cache = <&L2_1>;
 159                         qcom,freq-domain = <&cpufreq_hw 1>;
 160                         power-domains = <&CPU_PD7>;
 161                         power-domain-names = "psci";
 162                 };
 163
 164                 cpu-map {
 165                         cluster0 {
 166                                 core0 {
 167                                         cpu = <&CPU0>;
 168                                 };
 169
 170                                 core1 {
 171                                         cpu = <&CPU1>;
 172                                 };
 173
 174                                 core2 {
 175                                         cpu = <&CPU2>;
 176                                 };
 177
 178                                 core3 {
 179                                         cpu = <&CPU3>;
 180                                 };
 181                         };
 182
 183                         cluster1 {
 184                                 core0 {
 185                                         cpu = <&CPU4>;
 186                                 };
 187
 188                                 core1 {
 189                                         cpu = <&CPU5>;
 190                                 };
 191
 192                                 core2 {
 193                                         cpu = <&CPU6>;
 194                                 };
 195
 196                                 core3 {
 197                                         cpu = <&CPU7>;
 198                                 };
 199                         };
 200                 };
 201
 202                 idle-states {
 203                         entry-method = "psci";
 204
 205                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 206                                 compatible = "arm,idle-state";
 207                                 idle-state-name = "silver-rail-power-collapse";
 208                                 arm,psci-suspend-param = <0x40000003>;
 209                                 entry-latency-us = <290>;
 210                                 exit-latency-us = <376>;
 211                                 min-residency-us = <1182>;
 212                                 local-timer-stop;
 213                         };
 214
 215                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 216                                 compatible = "arm,idle-state";
 217                                 idle-state-name = "gold-rail-power-collapse";
 218                                 arm,psci-suspend-param = <0x40000003>;
 219                                 entry-latency-us = <297>;
 220                                 exit-latency-us = <324>;
 221                                 min-residency-us = <1110>;
 222                                 local-timer-stop;
 223                         };
 224                 };
 225
 226                 domain-idle-states {
 227                         CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
 228                                 /* GDHS */
 229                                 compatible = "domain-idle-state";
 230                                 arm,psci-suspend-param = <0x40000022>;
 231                                 entry-latency-us = <360>;
 232                                 exit-latency-us = <421>;
 233                                 min-residency-us = <782>;
 234                         };
 235
 236                         CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
 237                                 /* Power Collapse */
 238                                 compatible = "domain-idle-state";
 239                                 arm,psci-suspend-param = <0x41000044>;
 240                                 entry-latency-us = <800>;
 241                                 exit-latency-us = <2118>;
 242                                 min-residency-us = <7376>;
 243                         };
 244
 245                         CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
 246                                 /* GDHS */
 247                                 compatible = "domain-idle-state";
 248                                 arm,psci-suspend-param = <0x40000042>;
 249                                 entry-latency-us = <314>;
 250                                 exit-latency-us = <345>;
 251                                 min-residency-us = <660>;
 252                         };
 253
 254                         CLUSTER_1_SLEEP_1: cluster-sleep-1-1 {
 255                                 /* Power Collapse */
 256                                 compatible = "domain-idle-state";
 257                                 arm,psci-suspend-param = <0x41000044>;
 258                                 entry-latency-us = <640>;
 259                                 exit-latency-us = <1654>;
 260                                 min-residency-us = <8094>;
 261                         };
 262                 };
 263         };
 264
 265         firmware {
 266                 scm: scm {
 267                         compatible = "qcom,scm-sm6115", "qcom,scm";
 268                         #reset-cells = <1>;
 269                         interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
 270                                          &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
 271                 };
 272         };
 273
 274         memory@80000000 {
 275                 device_type = "memory";
 276                 /* We expect the bootloader to fill in the size */
 277                 reg = <0 0x80000000 0 0>;
 278         };
 279
 280         qup_opp_table: opp-table-qup {
 281                 compatible = "operating-points-v2";
 282
 283                 opp-75000000 {
 284                         opp-hz = /bits/ 64 <75000000>;
 285                         required-opps = <&rpmpd_opp_low_svs>;
 286                 };
 287
 288                 opp-100000000 {
 289                         opp-hz = /bits/ 64 <100000000>;
 290                         required-opps = <&rpmpd_opp_svs>;
 291                 };
 292
 293                 opp-128000000 {
 294                         opp-hz = /bits/ 64 <128000000>;
 295                         required-opps = <&rpmpd_opp_nom>;
 296                 };
 297         };
 298
 299         pmu {
 300                 compatible = "arm,armv8-pmuv3";
 301                 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
 302         };
 303
 304         psci {
 305                 compatible = "arm,psci-1.0";
 306                 method = "smc";
 307
 308                 CPU_PD0: power-domain-cpu0 {
 309                         #power-domain-cells = <0>;
 310                         power-domains = <&CLUSTER_0_PD>;
 311                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 312                 };
 313
 314                 CPU_PD1: power-domain-cpu1 {
 315                         #power-domain-cells = <0>;
 316                         power-domains = <&CLUSTER_0_PD>;
 317                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 318                 };
 319
 320                 CPU_PD2: power-domain-cpu2 {
 321                         #power-domain-cells = <0>;
 322                         power-domains = <&CLUSTER_0_PD>;
 323                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 324                 };
 325
 326                 CPU_PD3: power-domain-cpu3 {
 327                         #power-domain-cells = <0>;
 328                         power-domains = <&CLUSTER_0_PD>;
 329                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 330                 };
 331
 332                 CPU_PD4: power-domain-cpu4 {
 333                         #power-domain-cells = <0>;
 334                         power-domains = <&CLUSTER_1_PD>;
 335                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 336                 };
 337
 338                 CPU_PD5: power-domain-cpu5 {
 339                         #power-domain-cells = <0>;
 340                         power-domains = <&CLUSTER_1_PD>;
 341                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 342                 };
 343
 344                 CPU_PD6: power-domain-cpu6 {
 345                         #power-domain-cells = <0>;
 346                         power-domains = <&CLUSTER_1_PD>;
 347                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 348                 };
 349
 350                 CPU_PD7: power-domain-cpu7 {
 351                         #power-domain-cells = <0>;
 352                         power-domains = <&CLUSTER_1_PD>;
 353                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 354                 };
 355
 356                 CLUSTER_0_PD: power-domain-cpu-cluster0 {
 357                         #power-domain-cells = <0>;
 358                         domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>;
 359                 };
 360
 361                 CLUSTER_1_PD: power-domain-cpu-cluster1 {
 362                         #power-domain-cells = <0>;
 363                         domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>;
 364                 };
 365         };
 366
 367         rpm: remoteproc {
 368                 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
 369
 370                 glink-edge {
 371                         compatible = "qcom,glink-rpm";
 372
 373                         interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
 374                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
 375                         mboxes = <&apcs_glb 0>;
 376
 377                         rpm_requests: rpm-requests {
 378                                 compatible = "qcom,rpm-sm6115";
 379                                 qcom,glink-channels = "rpm_requests";
 380
 381                                 rpmcc: clock-controller {
 382                                         compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
 383                                         clocks = <&xo_board>;
 384                                         clock-names = "xo";
 385                                         #clock-cells = <1>;
 386                                 };
 387
 388                                 rpmpd: power-controller {
 389                                         compatible = "qcom,sm6115-rpmpd";
 390                                         #power-domain-cells = <1>;
 391                                         operating-points-v2 = <&rpmpd_opp_table>;
 392
 393                                         rpmpd_opp_table: opp-table {
 394                                                 compatible = "operating-points-v2";
 395
 396                                                 rpmpd_opp_min_svs: opp1 {
 397                                                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
 398                                                 };
 399
 400                                                 rpmpd_opp_low_svs: opp2 {
 401                                                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
 402                                                 };
 403
 404                                                 rpmpd_opp_svs: opp3 {
 405                                                         opp-level = <RPM_SMD_LEVEL_SVS>;
 406                                                 };
 407
 408                                                 rpmpd_opp_svs_plus: opp4 {
 409                                                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
 410                                                 };
 411
 412                                                 rpmpd_opp_nom: opp5 {
 413                                                         opp-level = <RPM_SMD_LEVEL_NOM>;
 414                                                 };
 415
 416                                                 rpmpd_opp_nom_plus: opp6 {
 417                                                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
 418                                                 };
 419
 420                                                 rpmpd_opp_turbo: opp7 {
 421                                                         opp-level = <RPM_SMD_LEVEL_TURBO>;
 422                                                 };
 423
 424                                                 rpmpd_opp_turbo_plus: opp8 {
 425                                                         opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
 426                                                 };
 427                                         };
 428                                 };
 429                         };
 430                 };
 431         };
 432
 433         reserved_memory: reserved-memory {
 434                 #address-cells = <2>;
 435                 #size-cells = <2>;
 436                 ranges;
 437
 438                 hyp_mem: memory@45700000 {
 439                         reg = <0x0 0x45700000 0x0 0x600000>;
 440                         no-map;
 441                 };
 442
 443                 xbl_aop_mem: memory@45e00000 {
 444                         reg = <0x0 0x45e00000 0x0 0x140000>;
 445                         no-map;
 446                 };
 447
 448                 sec_apps_mem: memory@45fff000 {
 449                         reg = <0x0 0x45fff000 0x0 0x1000>;
 450                         no-map;
 451                 };
 452
 453                 smem_mem: memory@46000000 {
 454                         compatible = "qcom,smem";
 455                         reg = <0x0 0x46000000 0x0 0x200000>;
 456                         no-map;
 457
 458                         hwlocks = <&tcsr_mutex 3>;
 459                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
 460                 };
 461
 462                 cdsp_sec_mem: memory@46200000 {
 463                         reg = <0x0 0x46200000 0x0 0x1e00000>;
 464                         no-map;
 465                 };
 466
 467                 pil_modem_mem: memory@4ab00000 {
 468                         reg = <0x0 0x4ab00000 0x0 0x6900000>;
 469                         no-map;
 470                 };
 471
 472                 pil_video_mem: memory@51400000 {
 473                         reg = <0x0 0x51400000 0x0 0x500000>;
 474                         no-map;
 475                 };
 476
 477                 wlan_msa_mem: memory@51900000 {
 478                         reg = <0x0 0x51900000 0x0 0x100000>;
 479                         no-map;
 480                 };
 481
 482                 pil_cdsp_mem: memory@51a00000 {
 483                         reg = <0x0 0x51a00000 0x0 0x1e00000>;
 484                         no-map;
 485                 };
 486
 487                 pil_adsp_mem: memory@53800000 {
 488                         reg = <0x0 0x53800000 0x0 0x2800000>;
 489                         no-map;
 490                 };
 491
 492                 pil_ipa_fw_mem: memory@56100000 {
 493                         reg = <0x0 0x56100000 0x0 0x10000>;
 494                         no-map;
 495                 };
 496
 497                 pil_ipa_gsi_mem: memory@56110000 {
 498                         reg = <0x0 0x56110000 0x0 0x5000>;
 499                         no-map;
 500                 };
 501
 502                 pil_gpu_mem: memory@56115000 {
 503                         reg = <0x0 0x56115000 0x0 0x2000>;
 504                         no-map;
 505                 };
 506
 507                 cont_splash_memory: memory@5c000000 {
 508                         reg = <0x0 0x5c000000 0x0 0x00f00000>;
 509                         no-map;
 510                 };
 511
 512                 dfps_data_memory: memory@5cf00000 {
 513                         reg = <0x0 0x5cf00000 0x0 0x0100000>;
 514                         no-map;
 515                 };
 516
 517                 removed_mem: memory@60000000 {
 518                         reg = <0x0 0x60000000 0x0 0x3900000>;
 519                         no-map;
 520                 };
 521
 522                 rmtfs_mem: memory@89b01000 {
 523                         compatible = "qcom,rmtfs-mem";
 524                         reg = <0x0 0x89b01000 0x0 0x200000>;
 525                         no-map;
 526
 527                         qcom,client-id = <1>;
 528                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
 529                 };
 530         };
 531
 532         smp2p-adsp {
 533                 compatible = "qcom,smp2p";
 534                 qcom,smem = <443>, <429>;
 535
 536                 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
 537
 538                 mboxes = <&apcs_glb 10>;
 539
 540                 qcom,local-pid = <0>;
 541                 qcom,remote-pid = <2>;
 542
 543                 adsp_smp2p_out: master-kernel {
 544                         qcom,entry-name = "master-kernel";
 545                         #qcom,smem-state-cells = <1>;
 546                 };
 547
 548                 adsp_smp2p_in: slave-kernel {
 549                         qcom,entry-name = "slave-kernel";
 550
 551                         interrupt-controller;
 552                         #interrupt-cells = <2>;
 553                 };
 554         };
 555
 556         smp2p-cdsp {
 557                 compatible = "qcom,smp2p";
 558                 qcom,smem = <94>, <432>;
 559
 560                 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
 561
 562                 mboxes = <&apcs_glb 30>;
 563
 564                 qcom,local-pid = <0>;
 565                 qcom,remote-pid = <5>;
 566
 567                 cdsp_smp2p_out: master-kernel {
 568                         qcom,entry-name = "master-kernel";
 569                         #qcom,smem-state-cells = <1>;
 570                 };
 571
 572                 cdsp_smp2p_in: slave-kernel {
 573                         qcom,entry-name = "slave-kernel";
 574
 575                         interrupt-controller;
 576                         #interrupt-cells = <2>;
 577                 };
 578         };
 579
 580         smp2p-mpss {
 581                 compatible = "qcom,smp2p";
 582                 qcom,smem = <435>, <428>;
 583
 584                 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
 585
 586                 mboxes = <&apcs_glb 14>;
 587
 588                 qcom,local-pid = <0>;
 589                 qcom,remote-pid = <1>;
 590
 591                 modem_smp2p_out: master-kernel {
 592                         qcom,entry-name = "master-kernel";
 593                         #qcom,smem-state-cells = <1>;
 594                 };
 595
 596                 modem_smp2p_in: slave-kernel {
 597                         qcom,entry-name = "slave-kernel";
 598
 599                         interrupt-controller;
 600                         #interrupt-cells = <2>;
 601                 };
 602         };
 603
 604         soc: soc@0 {
 605                 compatible = "simple-bus";
 606                 #address-cells = <2>;
 607                 #size-cells = <2>;
 608                 ranges = <0 0 0 0 0x10 0>;
 609                 dma-ranges = <0 0 0 0 0x10 0>;
 610
 611                 tcsr_mutex: hwlock@340000 {
 612                         compatible = "qcom,tcsr-mutex";
 613                         reg = <0x0 0x00340000 0x0 0x20000>;
 614                         #hwlock-cells = <1>;
 615                 };
 616
 617                 tlmm: pinctrl@500000 {
 618                         compatible = "qcom,sm6115-tlmm";
 619                         reg = <0x0 0x00500000 0x0 0x400000>,
 620                               <0x0 0x00900000 0x0 0x400000>,
 621                               <0x0 0x00d00000 0x0 0x400000>;
 622                         reg-names = "west", "south", "east";
 623                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 624                         gpio-controller;
 625                         gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
 626                         #gpio-cells = <2>;
 627                         interrupt-controller;
 628                         #interrupt-cells = <2>;
 629
 630                         qup_i2c0_default: qup-i2c0-default-state {
 631                                 pins = "gpio0", "gpio1";
 632                                 function = "qup0";
 633                                 drive-strength = <2>;
 634                                 bias-pull-up;
 635                         };
 636
 637                         qup_i2c1_default: qup-i2c1-default-state {
 638                                 pins = "gpio4", "gpio5";
 639                                 function = "qup1";
 640                                 drive-strength = <2>;
 641                                 bias-pull-up;
 642                         };
 643
 644                         qup_i2c2_default: qup-i2c2-default-state {
 645                                 pins = "gpio6", "gpio7";
 646                                 function = "qup2";
 647                                 drive-strength = <2>;
 648                                 bias-pull-up;
 649                         };
 650
 651                         qup_i2c3_default: qup-i2c3-default-state {
 652                                 pins = "gpio8", "gpio9";
 653                                 function = "qup3";
 654                                 drive-strength = <2>;
 655                                 bias-pull-up;
 656                         };
 657
 658                         qup_i2c4_default: qup-i2c4-default-state {
 659                                 pins = "gpio12", "gpio13";
 660                                 function = "qup4";
 661                                 drive-strength = <2>;
 662                                 bias-pull-up;
 663                         };
 664
 665                         qup_i2c5_default: qup-i2c5-default-state {
 666                                 pins = "gpio14", "gpio15";
 667                                 function = "qup5";
 668                                 drive-strength = <2>;
 669                                 bias-pull-up;
 670                         };
 671
 672                         qup_spi0_default: qup-spi0-default-state {
 673                                 pins = "gpio0", "gpio1","gpio2", "gpio3";
 674                                 function = "qup0";
 675                                 drive-strength = <2>;
 676                                 bias-pull-up;
 677                         };
 678
 679                         qup_spi1_default: qup-spi1-default-state {
 680                                 pins = "gpio4", "gpio5", "gpio69", "gpio70";
 681                                 function = "qup1";
 682                                 drive-strength = <2>;
 683                                 bias-pull-up;
 684                         };
 685
 686                         qup_spi2_default: qup-spi2-default-state {
 687                                 pins = "gpio6", "gpio7", "gpio71", "gpio80";
 688                                 function = "qup2";
 689                                 drive-strength = <2>;
 690                                 bias-pull-up;
 691                         };
 692
 693                         qup_spi3_default: qup-spi3-default-state {
 694                                 pins = "gpio8", "gpio9", "gpio10", "gpio11";
 695                                 function = "qup3";
 696                                 drive-strength = <2>;
 697                                 bias-pull-up;
 698                         };
 699
 700                         qup_spi4_default: qup-spi4-default-state {
 701                                 pins = "gpio12", "gpio13", "gpio96", "gpio97";
 702                                 function = "qup4";
 703                                 drive-strength = <2>;
 704                                 bias-pull-up;
 705                         };
 706
 707                         qup_spi5_default: qup-spi5-default-state {
 708                                 pins = "gpio14", "gpio15", "gpio16", "gpio17";
 709                                 function = "qup5";
 710                                 drive-strength = <2>;
 711                                 bias-pull-up;
 712                         };
 713
 714                         sdc1_state_on: sdc1-on-state {
 715                                 clk-pins {
 716                                         pins = "sdc1_clk";
 717                                         bias-disable;
 718                                         drive-strength = <16>;
 719                                 };
 720
 721                                 cmd-pins {
 722                                         pins = "sdc1_cmd";
 723                                         bias-pull-up;
 724                                         drive-strength = <10>;
 725                                 };
 726
 727                                 data-pins {
 728                                         pins = "sdc1_data";
 729                                         bias-pull-up;
 730                                         drive-strength = <10>;
 731                                 };
 732
 733                                 rclk-pins {
 734                                         pins = "sdc1_rclk";
 735                                         bias-pull-down;
 736                                 };
 737                         };
 738
 739                         sdc1_state_off: sdc1-off-state {
 740                                 clk-pins {
 741                                         pins = "sdc1_clk";
 742                                         bias-disable;
 743                                         drive-strength = <2>;
 744                                 };
 745
 746                                 cmd-pins {
 747                                         pins = "sdc1_cmd";
 748                                         bias-pull-up;
 749                                         drive-strength = <2>;
 750                                 };
 751
 752                                 data-pins {
 753                                         pins = "sdc1_data";
 754                                         bias-pull-up;
 755                                         drive-strength = <2>;
 756                                 };
 757
 758                                 rclk-pins {
 759                                         pins = "sdc1_rclk";
 760                                         bias-pull-down;
 761                                 };
 762                         };
 763
 764                         sdc2_state_on: sdc2-on-state {
 765                                 clk-pins {
 766                                         pins = "sdc2_clk";
 767                                         bias-disable;
 768                                         drive-strength = <16>;
 769                                 };
 770
 771                                 cmd-pins {
 772                                         pins = "sdc2_cmd";
 773                                         bias-pull-up;
 774                                         drive-strength = <10>;
 775                                 };
 776
 777                                 data-pins {
 778                                         pins = "sdc2_data";
 779                                         bias-pull-up;
 780                                         drive-strength = <10>;
 781                                 };
 782                         };
 783
 784                         sdc2_state_off: sdc2-off-state {
 785                                 clk-pins {
 786                                         pins = "sdc2_clk";
 787                                         bias-disable;
 788                                         drive-strength = <2>;
 789                                 };
 790
 791                                 cmd-pins {
 792                                         pins = "sdc2_cmd";
 793                                         bias-pull-up;
 794                                         drive-strength = <2>;
 795                                 };
 796
 797                                 data-pins {
 798                                         pins = "sdc2_data";
 799                                         bias-pull-up;
 800                                         drive-strength = <2>;
 801                                 };
 802                         };
 803                 };
 804
 805                 gcc: clock-controller@1400000 {
 806                         compatible = "qcom,gcc-sm6115";
 807                         reg = <0x0 0x01400000 0x0 0x1f0000>;
 808                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
 809                         clock-names = "bi_tcxo", "sleep_clk";
 810                         #clock-cells = <1>;
 811                         #reset-cells = <1>;
 812                         #power-domain-cells = <1>;
 813                 };
 814
 815                 usb_hsphy: phy@1613000 {
 816                         compatible = "qcom,sm6115-qusb2-phy";
 817                         reg = <0x0 0x01613000 0x0 0x180>;
 818                         #phy-cells = <0>;
 819
 820                         clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
 821                         clock-names = "cfg_ahb", "ref";
 822
 823                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 824                         nvmem-cells = <&qusb2_hstx_trim>;
 825
 826                         status = "disabled";
 827                 };
 828
 829                 cryptobam: dma-controller@1b04000 {
 830                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
 831                         reg = <0x0 0x01b04000 0x0 0x24000>;
 832                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 833                         clocks = <&rpmcc RPM_SMD_CE1_CLK>;
 834                         clock-names = "bam_clk";
 835                         #dma-cells = <1>;
 836                         qcom,ee = <0>;
 837                         qcom,controlled-remotely;
 838                         iommus = <&apps_smmu 0x92 0>,
 839                                  <&apps_smmu 0x94 0x11>,
 840                                  <&apps_smmu 0x96 0x11>,
 841                                  <&apps_smmu 0x98 0x1>,
 842                                  <&apps_smmu 0x9F 0>;
 843                 };
 844
 845                 crypto: crypto@1b3a000 {
 846                         compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
 847                         reg = <0x0 0x01b3a000 0x0 0x6000>;
 848                         clocks = <&rpmcc RPM_SMD_CE1_CLK>;
 849                         clock-names = "core";
 850
 851                         dmas = <&cryptobam 6>, <&cryptobam 7>;
 852                         dma-names = "rx", "tx";
 853                         iommus = <&apps_smmu 0x92 0>,
 854                                  <&apps_smmu 0x94 0x11>,
 855                                  <&apps_smmu 0x96 0x11>,
 856                                  <&apps_smmu 0x98 0x1>,
 857                                  <&apps_smmu 0x9F 0>;
 858                 };
 859
 860                 usb_qmpphy: phy@1615000 {
 861                         compatible = "qcom,sm6115-qmp-usb3-phy";
 862                         reg = <0x0 0x01615000 0x0 0x1000>;
 863
 864                         clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
 865                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
 866                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
 867                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 868                         clock-names = "cfg_ahb",
 869                                       "ref",
 870                                       "com_aux",
 871                                       "pipe";
 872
 873                         resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
 874                                  <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
 875                         reset-names = "phy", "phy_phy";
 876
 877                         #clock-cells = <0>;
 878                         clock-output-names = "usb3_phy_pipe_clk_src";
 879
 880                         #phy-cells = <0>;
 881
 882                         status = "disabled";
 883                 };
 884
 885                 system_noc: interconnect@1880000 {
 886                         compatible = "qcom,sm6115-snoc";
 887                         reg = <0x0 0x01880000 0x0 0x5f080>;
 888                         clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
 889                                  <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
 890                                  <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
 891                                  <&rpmcc RPM_SMD_IPA_CLK>;
 892                         clock-names = "cpu_axi",
 893                                       "ufs_axi",
 894                                       "usb_axi",
 895                                       "ipa";
 896                         #interconnect-cells = <2>;
 897
 898                         clk_virt: interconnect-clk {
 899                                 compatible = "qcom,sm6115-clk-virt";
 900                                 #interconnect-cells = <2>;
 901                         };
 902
 903                         mmrt_virt: interconnect-mmrt {
 904                                 compatible = "qcom,sm6115-mmrt-virt";
 905                                 #interconnect-cells = <2>;
 906                         };
 907
 908                         mmnrt_virt: interconnect-mmnrt {
 909                                 compatible = "qcom,sm6115-mmnrt-virt";
 910                                 #interconnect-cells = <2>;
 911                         };
 912                 };
 913
 914                 config_noc: interconnect@1900000 {
 915                         compatible = "qcom,sm6115-cnoc";
 916                         reg = <0x0 0x01900000 0x0 0x6200>;
 917                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>;
 918                         clock-names = "usb_axi";
 919                         #interconnect-cells = <2>;
 920                 };
 921
 922                 qfprom@1b40000 {
 923                         compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
 924                         reg = <0x0 0x01b40000 0x0 0x7000>;
 925                         #address-cells = <1>;
 926                         #size-cells = <1>;
 927
 928                         qusb2_hstx_trim: hstx-trim@25b {
 929                                 reg = <0x25b 0x1>;
 930                                 bits = <1 4>;
 931                         };
 932
 933                         gpu_speed_bin: gpu-speed-bin@6006 {
 934                                 reg = <0x6006 0x2>;
 935                                 bits = <5 8>;
 936                         };
 937                 };
 938
 939                 rng: rng@1b53000 {
 940                         compatible = "qcom,prng-ee";
 941                         reg = <0x0 0x01b53000 0x0 0x1000>;
 942                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 943                         clock-names = "core";
 944                 };
 945
 946                 pmu@1b8e300 {
 947                         compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon";
 948                         reg = <0x0 0x01b8e300 0x0 0x600>;
 949                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 950
 951                         operating-points-v2 = <&cpu_bwmon_opp_table>;
 952                         interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
 953                                          &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>;
 954
 955                         cpu_bwmon_opp_table: opp-table {
 956                                 compatible = "operating-points-v2";
 957
 958                                 opp-0 {
 959                                         opp-peak-kBps = <(200 * 4 * 1000)>;
 960                                 };
 961
 962                                 opp-1 {
 963                                         opp-peak-kBps = <(300 * 4 * 1000)>;
 964                                 };
 965
 966                                 opp-2 {
 967                                         opp-peak-kBps = <(451 * 4 * 1000)>;
 968                                 };
 969
 970                                 opp-3 {
 971                                         opp-peak-kBps = <(547 * 4 * 1000)>;
 972                                 };
 973
 974                                 opp-4 {
 975                                         opp-peak-kBps = <(681 * 4 * 1000)>;
 976                                 };
 977
 978                                 opp-5 {
 979                                         opp-peak-kBps = <(768 * 4 * 1000)>;
 980                                 };
 981
 982                                 opp-6 {
 983                                         opp-peak-kBps = <(1017 * 4 * 1000)>;
 984                                 };
 985
 986                                 opp-7 {
 987                                         opp-peak-kBps = <(1353 * 4 * 1000)>;
 988                                 };
 989
 990                                 opp-8 {
 991                                         opp-peak-kBps = <(1555 * 4 * 1000)>;
 992                                 };
 993
 994                                 opp-9 {
 995                                         opp-peak-kBps = <(1804 * 4 * 1000)>;
 996                                 };
 997                         };
 998                 };
 999
1000                 spmi_bus: spmi@1c40000 {
1001                         compatible = "qcom,spmi-pmic-arb";
1002                         reg = <0x0 0x01c40000 0x0 0x1100>,
1003                               <0x0 0x01e00000 0x0 0x2000000>,
1004                               <0x0 0x03e00000 0x0 0x100000>,
1005                               <0x0 0x03f00000 0x0 0xa0000>,
1006                               <0x0 0x01c0a000 0x0 0x26000>;
1007                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1008                         interrupt-names = "periph_irq";
1009                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
1010                         qcom,ee = <0>;
1011                         qcom,channel = <0>;
1012                         #address-cells = <2>;
1013                         #size-cells = <0>;
1014                         interrupt-controller;
1015                         #interrupt-cells = <4>;
1016                 };
1017
1018                 tsens0: thermal-sensor@4411000 {
1019                         compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
1020                         reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */
1021                               <0x0 0x04410000 0x0 0x8>; /* SROT */
1022                         #qcom,sensors = <16>;
1023                         interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1024                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1025                         interrupt-names = "uplow", "critical";
1026                         #thermal-sensor-cells = <1>;
1027                 };
1028
1029                 bimc: interconnect@4480000 {
1030                         compatible = "qcom,sm6115-bimc";
1031                         reg = <0x0 0x04480000 0x0 0x80000>;
1032                         #interconnect-cells = <2>;
1033                 };
1034
1035                 rpm_msg_ram: sram@45f0000 {
1036                         compatible = "qcom,rpm-msg-ram";
1037                         reg = <0x0 0x045f0000 0x0 0x7000>;
1038                 };
1039
1040                 sram@4690000 {
1041                         compatible = "qcom,rpm-stats";
1042                         reg = <0x0 0x04690000 0x0 0x10000>;
1043                 };
1044
1045                 sdhc_1: mmc@4744000 {
1046                         compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1047                         reg = <0x0 0x04744000 0x0 0x1000>,
1048                               <0x0 0x04745000 0x0 0x1000>,
1049                               <0x0 0x04748000 0x0 0x8000>;
1050                         reg-names = "hc", "cqhci", "ice";
1051
1052                         interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
1053                                      <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1054                         interrupt-names = "hc_irq", "pwr_irq";
1055
1056                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1057                                  <&gcc GCC_SDCC1_APPS_CLK>,
1058                                  <&rpmcc RPM_SMD_XO_CLK_SRC>,
1059                                  <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1060                         clock-names = "iface", "core", "xo", "ice";
1061
1062                         power-domains = <&rpmpd SM6115_VDDCX>;
1063                         operating-points-v2 = <&sdhc1_opp_table>;
1064                         interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
1065                                          &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1066                                         <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1067                                          &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>;
1068                         interconnect-names = "sdhc-ddr",
1069                                              "cpu-sdhc";
1070
1071                         bus-width = <8>;
1072                         status = "disabled";
1073
1074                         sdhc1_opp_table: opp-table {
1075                                 compatible = "operating-points-v2";
1076
1077                                 opp-100000000 {
1078                                         opp-hz = /bits/ 64 <100000000>;
1079                                         required-opps = <&rpmpd_opp_low_svs>;
1080                                         opp-peak-kBps = <250000 133320>;
1081                                         opp-avg-kBps = <102400 65000>;
1082                                 };
1083
1084                                 opp-192000000 {
1085                                         opp-hz = /bits/ 64 <192000000>;
1086                                         required-opps = <&rpmpd_opp_low_svs>;
1087                                         opp-peak-kBps = <800000 300000>;
1088                                         opp-avg-kBps = <204800 200000>;
1089                                 };
1090
1091                                 opp-384000000 {
1092                                         opp-hz = /bits/ 64 <384000000>;
1093                                         required-opps = <&rpmpd_opp_svs_plus>;
1094                                         opp-peak-kBps = <800000 300000>;
1095                                         opp-avg-kBps = <204800 200000>;
1096                                 };
1097                         };
1098                 };
1099
1100                 sdhc_2: mmc@4784000 {
1101                         compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1102                         reg = <0x0 0x04784000 0x0 0x1000>;
1103                         reg-names = "hc";
1104
1105                         interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1106                                      <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1107                         interrupt-names = "hc_irq", "pwr_irq";
1108
1109                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1110                                  <&gcc GCC_SDCC2_APPS_CLK>,
1111                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1112                         clock-names = "iface", "core", "xo";
1113
1114                         power-domains = <&rpmpd SM6115_VDDCX>;
1115                         operating-points-v2 = <&sdhc2_opp_table>;
1116                         iommus = <&apps_smmu 0x00a0 0x0>;
1117                         resets = <&gcc GCC_SDCC2_BCR>;
1118                         interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
1119                                          &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1120                                         <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1121                                          &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>;
1122                         interconnect-names = "sdhc-ddr",
1123                                              "cpu-sdhc";
1124
1125                         bus-width = <4>;
1126                         qcom,dll-config = <0x0007642c>;
1127                         qcom,ddr-config = <0x80040868>;
1128                         status = "disabled";
1129
1130                         sdhc2_opp_table: opp-table {
1131                                 compatible = "operating-points-v2";
1132
1133                                 opp-100000000 {
1134                                         opp-hz = /bits/ 64 <100000000>;
1135                                         required-opps = <&rpmpd_opp_low_svs>;
1136                                         opp-peak-kBps = <250000 133320>;
1137                                         opp-avg-kBps = <261438 150000>;
1138                                 };
1139
1140                                 opp-202000000 {
1141                                         opp-hz = /bits/ 64 <202000000>;
1142                                         required-opps = <&rpmpd_opp_nom>;
1143                                         opp-peak-kBps = <800000 300000>;
1144                                         opp-avg-kBps = <261438 300000>;
1145                                 };
1146                         };
1147                 };
1148
1149                 ufs_mem_hc: ufs@4804000 {
1150                         compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1151                         reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
1152                         reg-names = "std", "ice";
1153                         interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1154                         phys = <&ufs_mem_phy>;
1155                         phy-names = "ufsphy";
1156                         lanes-per-direction = <1>;
1157                         #reset-cells = <1>;
1158                         resets = <&gcc GCC_UFS_PHY_BCR>;
1159                         reset-names = "rst";
1160
1161                         power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1162                         iommus = <&apps_smmu 0x100 0>;
1163
1164                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1165                                  <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
1166                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
1167                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1168                                  <&rpmcc RPM_SMD_XO_CLK_SRC>,
1169                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1170                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1171                                  <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1172                         clock-names = "core_clk",
1173                                       "bus_aggr_clk",
1174                                       "iface_clk",
1175                                       "core_clk_unipro",
1176                                       "ref_clk",
1177                                       "tx_lane0_sync_clk",
1178                                       "rx_lane0_sync_clk",
1179                                       "ice_core_clk";
1180
1181                         freq-table-hz = <50000000 200000000>,
1182                                         <0 0>,
1183                                         <0 0>,
1184                                         <37500000 150000000>,
1185                                         <0 0>,
1186                                         <0 0>,
1187                                         <0 0>,
1188                                         <75000000 300000000>;
1189
1190                         status = "disabled";
1191                 };
1192
1193                 ufs_mem_phy: phy@4807000 {
1194                         compatible = "qcom,sm6115-qmp-ufs-phy";
1195                         reg = <0x0 0x04807000 0x0 0x1000>;
1196
1197                         clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1198                         clock-names = "ref", "ref_aux";
1199
1200                         resets = <&ufs_mem_hc 0>;
1201                         reset-names = "ufsphy";
1202
1203                         #phy-cells = <0>;
1204
1205                         status = "disabled";
1206                 };
1207
1208                 gpi_dma0: dma-controller@4a00000 {
1209                         compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1210                         reg = <0x0 0x04a00000 0x0 0x60000>;
1211                         interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1212                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1213                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1214                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1215                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1216                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1217                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1218                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1219                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1220                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1221                         dma-channels = <10>;
1222                         dma-channel-mask = <0xf>;
1223                         iommus = <&apps_smmu 0xf6 0x0>;
1224                         #dma-cells = <3>;
1225                         status = "disabled";
1226                 };
1227
1228                 qupv3_id_0: geniqup@4ac0000 {
1229                         compatible = "qcom,geni-se-qup";
1230                         reg = <0x0 0x04ac0000 0x0 0x2000>;
1231                         clock-names = "m-ahb", "s-ahb";
1232                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1233                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1234                         #address-cells = <2>;
1235                         #size-cells = <2>;
1236                         iommus = <&apps_smmu 0xe3 0x0>;
1237                         ranges;
1238                         status = "disabled";
1239
1240                         i2c0: i2c@4a80000 {
1241                                 compatible = "qcom,geni-i2c";
1242                                 reg = <0x0 0x04a80000 0x0 0x4000>;
1243                                 clock-names = "se";
1244                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1245                                 pinctrl-names = "default";
1246                                 pinctrl-0 = <&qup_i2c0_default>;
1247                                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1248                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1249                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1250                                 dma-names = "tx", "rx";
1251                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1252                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1253                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1254                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1255                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1256                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1257                                 interconnect-names = "qup-core",
1258                                                      "qup-config",
1259                                                      "qup-memory";
1260                                 #address-cells = <1>;
1261                                 #size-cells = <0>;
1262                                 status = "disabled";
1263                         };
1264
1265                         spi0: spi@4a80000 {
1266                                 compatible = "qcom,geni-spi";
1267                                 reg = <0x0 0x04a80000 0x0 0x4000>;
1268                                 clock-names = "se";
1269                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1270                                 pinctrl-names = "default";
1271                                 pinctrl-0 = <&qup_spi0_default>;
1272                                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1273                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1274                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1275                                 dma-names = "tx", "rx";
1276                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1277                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1278                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1279                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1280                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1281                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1282                                 interconnect-names = "qup-core",
1283                                                      "qup-config",
1284                                                      "qup-memory";
1285                                 #address-cells = <1>;
1286                                 #size-cells = <0>;
1287                                 status = "disabled";
1288                         };
1289
1290                         i2c1: i2c@4a84000 {
1291                                 compatible = "qcom,geni-i2c";
1292                                 reg = <0x0 0x04a84000 0x0 0x4000>;
1293                                 clock-names = "se";
1294                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1295                                 pinctrl-names = "default";
1296                                 pinctrl-0 = <&qup_i2c1_default>;
1297                                 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1298                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1299                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1300                                 dma-names = "tx", "rx";
1301                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1302                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1303                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1304                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1305                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1306                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1307                                 #address-cells = <1>;
1308                                 #size-cells = <0>;
1309                                 status = "disabled";
1310                         };
1311
1312                         spi1: spi@4a84000 {
1313                                 compatible = "qcom,geni-spi";
1314                                 reg = <0x0 0x04a84000 0x0 0x4000>;
1315                                 clock-names = "se";
1316                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1317                                 pinctrl-names = "default";
1318                                 pinctrl-0 = <&qup_spi1_default>;
1319                                 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1320                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1321                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1322                                 dma-names = "tx", "rx";
1323                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1324                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1325                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1326                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1327                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1328                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1329                                 interconnect-names = "qup-core",
1330                                                      "qup-config",
1331                                                      "qup-memory";
1332                                 #address-cells = <1>;
1333                                 #size-cells = <0>;
1334                                 status = "disabled";
1335                         };
1336
1337                         i2c2: i2c@4a88000 {
1338                                 compatible = "qcom,geni-i2c";
1339                                 reg = <0x0 0x04a88000 0x0 0x4000>;
1340                                 clock-names = "se";
1341                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1342                                 pinctrl-names = "default";
1343                                 pinctrl-0 = <&qup_i2c2_default>;
1344                                 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1345                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1346                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1347                                 dma-names = "tx", "rx";
1348                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1349                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1350                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1351                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1352                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1353                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1354                                 interconnect-names = "qup-core",
1355                                                      "qup-config",
1356                                                      "qup-memory";
1357                                 #address-cells = <1>;
1358                                 #size-cells = <0>;
1359                                 status = "disabled";
1360                         };
1361
1362                         spi2: spi@4a88000 {
1363                                 compatible = "qcom,geni-spi";
1364                                 reg = <0x0 0x04a88000 0x0 0x4000>;
1365                                 clock-names = "se";
1366                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1367                                 pinctrl-names = "default";
1368                                 pinctrl-0 = <&qup_spi2_default>;
1369                                 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1370                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1371                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1372                                 dma-names = "tx", "rx";
1373                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1374                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1375                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1376                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1377                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1378                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1379                                 interconnect-names = "qup-core",
1380                                                      "qup-config",
1381                                                      "qup-memory";
1382                                 #address-cells = <1>;
1383                                 #size-cells = <0>;
1384                                 status = "disabled";
1385                         };
1386
1387                         i2c3: i2c@4a8c000 {
1388                                 compatible = "qcom,geni-i2c";
1389                                 reg = <0x0 0x04a8c000 0x0 0x4000>;
1390                                 clock-names = "se";
1391                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1392                                 pinctrl-names = "default";
1393                                 pinctrl-0 = <&qup_i2c3_default>;
1394                                 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1395                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1396                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1397                                 dma-names = "tx", "rx";
1398                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1399                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1400                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1401                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1402                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1403                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1404                                 interconnect-names = "qup-core",
1405                                                      "qup-config",
1406                                                      "qup-memory";
1407                                 #address-cells = <1>;
1408                                 #size-cells = <0>;
1409                                 status = "disabled";
1410                         };
1411
1412                         spi3: spi@4a8c000 {
1413                                 compatible = "qcom,geni-spi";
1414                                 reg = <0x0 0x04a8c000 0x0 0x4000>;
1415                                 clock-names = "se";
1416                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1417                                 pinctrl-names = "default";
1418                                 pinctrl-0 = <&qup_spi3_default>;
1419                                 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1420                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1421                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1422                                 dma-names = "tx", "rx";
1423                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1424                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1425                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1426                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1427                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1428                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1429                                 interconnect-names = "qup-core",
1430                                                      "qup-config",
1431                                                      "qup-memory";
1432                                 #address-cells = <1>;
1433                                 #size-cells = <0>;
1434                                 status = "disabled";
1435                         };
1436
1437                         uart3: serial@4a8c000 {
1438                                 compatible = "qcom,geni-uart";
1439                                 reg = <0x0 0x04a8c000 0x0 0x4000>;
1440                                 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1441                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1442                                 clock-names = "se";
1443                                 power-domains = <&rpmpd SM6115_VDDCX>;
1444                                 operating-points-v2 = <&qup_opp_table>;
1445                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1446                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1447                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1448                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
1449                                 interconnect-names = "qup-core",
1450                                                      "qup-config";
1451                                 status = "disabled";
1452                         };
1453
1454                         i2c4: i2c@4a90000 {
1455                                 compatible = "qcom,geni-i2c";
1456                                 reg = <0x0 0x04a90000 0x0 0x4000>;
1457                                 clock-names = "se";
1458                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1459                                 pinctrl-names = "default";
1460                                 pinctrl-0 = <&qup_i2c4_default>;
1461                                 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1462                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1463                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1464                                 dma-names = "tx", "rx";
1465                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1466                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1467                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1468                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1469                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1470                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1471                                 interconnect-names = "qup-core",
1472                                                      "qup-config",
1473                                                      "qup-memory";
1474                                 #address-cells = <1>;
1475                                 #size-cells = <0>;
1476                                 status = "disabled";
1477                         };
1478
1479                         spi4: spi@4a90000 {
1480                                 compatible = "qcom,geni-spi";
1481                                 reg = <0x0 0x04a90000 0x0 0x4000>;
1482                                 clock-names = "se";
1483                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1484                                 pinctrl-names = "default";
1485                                 pinctrl-0 = <&qup_spi4_default>;
1486                                 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1487                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1488                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1489                                 dma-names = "tx", "rx";
1490                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1491                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1492                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1493                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1494                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1495                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1496                                 interconnect-names = "qup-core",
1497                                                      "qup-config",
1498                                                      "qup-memory";
1499                                 #address-cells = <1>;
1500                                 #size-cells = <0>;
1501                                 status = "disabled";
1502                         };
1503
1504                         uart4: serial@4a90000 {
1505                                 compatible = "qcom,geni-debug-uart";
1506                                 reg = <0x0 0x04a90000 0x0 0x4000>;
1507                                 clock-names = "se";
1508                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509                                 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1510                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1511                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1512                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1513                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
1514                                 interconnect-names = "qup-core",
1515                                                      "qup-config";
1516                                 status = "disabled";
1517                         };
1518
1519                         i2c5: i2c@4a94000 {
1520                                 compatible = "qcom,geni-i2c";
1521                                 reg = <0x0 0x04a94000 0x0 0x4000>;
1522                                 clock-names = "se";
1523                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1524                                 pinctrl-names = "default";
1525                                 pinctrl-0 = <&qup_i2c5_default>;
1526                                 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1527                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1528                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1529                                 dma-names = "tx", "rx";
1530                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1531                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1532                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1533                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1534                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1535                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1536                                 interconnect-names = "qup-core",
1537                                                      "qup-config",
1538                                                      "qup-memory";
1539                                 #address-cells = <1>;
1540                                 #size-cells = <0>;
1541                                 status = "disabled";
1542                         };
1543
1544                         spi5: spi@4a94000 {
1545                                 compatible = "qcom,geni-spi";
1546                                 reg = <0x0 0x04a94000 0x0 0x4000>;
1547                                 clock-names = "se";
1548                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1549                                 pinctrl-names = "default";
1550                                 pinctrl-0 = <&qup_spi5_default>;
1551                                 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1552                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1553                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1554                                 dma-names = "tx", "rx";
1555                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1556                                                  &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1557                                                 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1558                                                  &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1559                                                 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1560                                                  &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1561                                 interconnect-names = "qup-core",
1562                                                      "qup-config",
1563                                                      "qup-memory";
1564                                 #address-cells = <1>;
1565                                 #size-cells = <0>;
1566                                 status = "disabled";
1567                         };
1568                 };
1569
1570                 usb: usb@4ef8800 {
1571                         compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1572                         reg = <0x0 0x04ef8800 0x0 0x400>;
1573                         #address-cells = <2>;
1574                         #size-cells = <2>;
1575                         ranges;
1576
1577                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1578                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1579                                  <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1580                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1581                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1582                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1583                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1584
1585                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1586                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1587                         assigned-clock-rates = <19200000>, <66666667>;
1588
1589                         interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1590                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1591                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
1592
1593                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1594                         power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1595                          /* TODO: USB<->IPA path */
1596                         interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG
1597                                          &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1598                                         <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1599                                          &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>;
1600                         interconnect-names = "usb-ddr",
1601                                              "apps-usb";
1602
1603                         qcom,select-utmi-as-pipe-clk;
1604                         status = "disabled";
1605
1606                         usb_dwc3: usb@4e00000 {
1607                                 compatible = "snps,dwc3";
1608                                 reg = <0x0 0x04e00000 0x0 0xcd00>;
1609                                 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1610                                 phys = <&usb_hsphy>, <&usb_qmpphy>;
1611                                 phy-names = "usb2-phy", "usb3-phy";
1612                                 iommus = <&apps_smmu 0x120 0x0>;
1613                                 snps,dis_u2_susphy_quirk;
1614                                 snps,dis_enblslpm_quirk;
1615                                 snps,has-lpm-erratum;
1616                                 snps,hird-threshold = /bits/ 8 <0x10>;
1617                                 snps,usb3_lpm_capable;
1618                         };
1619                 };
1620
1621                 gpu: gpu@5900000 {
1622                         compatible = "qcom,adreno-610.0", "qcom,adreno";
1623                         reg = <0x0 0x05900000 0x0 0x40000>;
1624                         reg-names = "kgsl_3d0_reg_memory";
1625
1626                         /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
1627                         clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
1628                                  <&gpucc GPU_CC_AHB_CLK>,
1629                                  <&gcc GCC_BIMC_GPU_AXI_CLK>,
1630                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1631                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1632                                  <&gpucc GPU_CC_CXO_CLK>;
1633                         clock-names = "core",
1634                                       "iface",
1635                                       "mem_iface",
1636                                       "alt_mem_iface",
1637                                       "gmu",
1638                                       "xo";
1639
1640                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
1641
1642                         iommus = <&adreno_smmu 0 1>;
1643                         operating-points-v2 = <&gpu_opp_table>;
1644                         power-domains = <&rpmpd SM6115_VDDCX>;
1645                         qcom,gmu = <&gmu_wrapper>;
1646
1647                         nvmem-cells = <&gpu_speed_bin>;
1648                         nvmem-cell-names = "speed_bin";
1649
1650                         status = "disabled";
1651
1652                         zap-shader {
1653                                 memory-region = <&pil_gpu_mem>;
1654                         };
1655
1656                         gpu_opp_table: opp-table {
1657                                 compatible = "operating-points-v2";
1658
1659                                 opp-320000000 {
1660                                         opp-hz = /bits/ 64 <320000000>;
1661                                         required-opps = <&rpmpd_opp_low_svs>;
1662                                         opp-supported-hw = <0x1f>;
1663                                 };
1664
1665                                 opp-465000000 {
1666                                         opp-hz = /bits/ 64 <465000000>;
1667                                         required-opps = <&rpmpd_opp_svs>;
1668                                         opp-supported-hw = <0x1f>;
1669                                 };
1670
1671                                 opp-600000000 {
1672                                         opp-hz = /bits/ 64 <600000000>;
1673                                         required-opps = <&rpmpd_opp_svs_plus>;
1674                                         opp-supported-hw = <0x1f>;
1675                                 };
1676
1677                                 opp-745000000 {
1678                                         opp-hz = /bits/ 64 <745000000>;
1679                                         required-opps = <&rpmpd_opp_nom>;
1680                                         opp-supported-hw = <0xf>;
1681                                 };
1682
1683                                 opp-820000000 {
1684                                         opp-hz = /bits/ 64 <820000000>;
1685                                         required-opps = <&rpmpd_opp_nom_plus>;
1686                                         opp-supported-hw = <0x7>;
1687                                 };
1688
1689                                 opp-900000000 {
1690                                         opp-hz = /bits/ 64 <900000000>;
1691                                         required-opps = <&rpmpd_opp_turbo>;
1692                                         opp-supported-hw = <0x7>;
1693                                 };
1694
1695                                 /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */
1696                                 opp-950000000 {
1697                                         opp-hz = /bits/ 64 <950000000>;
1698                                         required-opps = <&rpmpd_opp_turbo_plus>;
1699                                         opp-supported-hw = <0x4>;
1700                                 };
1701
1702                                 opp-980000000 {
1703                                         opp-hz = /bits/ 64 <980000000>;
1704                                         required-opps = <&rpmpd_opp_turbo_plus>;
1705                                         opp-supported-hw = <0x3>;
1706                                 };
1707                         };
1708                 };
1709
1710                 gmu_wrapper: gmu@596a000 {
1711                         compatible = "qcom,adreno-gmu-wrapper";
1712                         reg = <0x0 0x0596a000 0x0 0x30000>;
1713                         reg-names = "gmu";
1714                         power-domains = <&gpucc GPU_CX_GDSC>,
1715                                         <&gpucc GPU_GX_GDSC>;
1716                         power-domain-names = "cx", "gx";
1717                 };
1718
1719                 gpucc: clock-controller@5990000 {
1720                         compatible = "qcom,sm6115-gpucc";
1721                         reg = <0x0 0x05990000 0x0 0x9000>;
1722                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1723                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1724                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1725                         #clock-cells = <1>;
1726                         #reset-cells = <1>;
1727                         #power-domain-cells = <1>;
1728                 };
1729
1730                 adreno_smmu: iommu@59a0000 {
1731                         compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1732                                      "qcom,smmu-500", "arm,mmu-500";
1733                         reg = <0x0 0x059a0000 0x0 0x10000>;
1734                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1735                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1736                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1737                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1738                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1739                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1740                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1741                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1742                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1743
1744                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1745                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1746                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1747                         clock-names = "mem",
1748                                       "hlos",
1749                                       "iface";
1750                         power-domains = <&gpucc GPU_CX_GDSC>;
1751
1752                         #global-interrupts = <1>;
1753                         #iommu-cells = <2>;
1754                 };
1755
1756                 mdss: display-subsystem@5e00000 {
1757                         compatible = "qcom,sm6115-mdss";
1758                         reg = <0x0 0x05e00000 0x0 0x1000>;
1759                         reg-names = "mdss";
1760
1761                         power-domains = <&dispcc MDSS_GDSC>;
1762
1763                         clocks = <&gcc GCC_DISP_AHB_CLK>,
1764                                  <&gcc GCC_DISP_HF_AXI_CLK>,
1765                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
1766
1767                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1768                         interrupt-controller;
1769                         #interrupt-cells = <1>;
1770
1771                         iommus = <&apps_smmu 0x420 0x2>,
1772                                  <&apps_smmu 0x421 0x0>;
1773
1774                         interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG
1775                                          &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1776                                         <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1777                                          &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>;
1778                         interconnect-names = "mdp0-mem",
1779                                              "cpu-cfg";
1780
1781                         #address-cells = <2>;
1782                         #size-cells = <2>;
1783                         ranges;
1784
1785                         status = "disabled";
1786
1787                         mdp: display-controller@5e01000 {
1788                                 compatible = "qcom,sm6115-dpu";
1789                                 reg = <0x0 0x05e01000 0x0 0x8f000>,
1790                                       <0x0 0x05eb0000 0x0 0x2008>;
1791                                 reg-names = "mdp", "vbif";
1792
1793                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1794                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
1795                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
1796                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1797                                          <&dispcc DISP_CC_MDSS_ROT_CLK>,
1798                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1799                                 clock-names = "bus",
1800                                               "iface",
1801                                               "core",
1802                                               "lut",
1803                                               "rot",
1804                                               "vsync";
1805
1806                                 operating-points-v2 = <&mdp_opp_table>;
1807                                 power-domains = <&rpmpd SM6115_VDDCX>;
1808
1809                                 interrupt-parent = <&mdss>;
1810                                 interrupts = <0>;
1811
1812                                 ports {
1813                                         #address-cells = <1>;
1814                                         #size-cells = <0>;
1815
1816                                         port@0 {
1817                                                 reg = <0>;
1818                                                 dpu_intf1_out: endpoint {
1819                                                         remote-endpoint = <&mdss_dsi0_in>;
1820                                                 };
1821                                         };
1822                                 };
1823
1824                                 mdp_opp_table: opp-table {
1825                                         compatible = "operating-points-v2";
1826
1827                                         opp-19200000 {
1828                                                 opp-hz = /bits/ 64 <19200000>;
1829                                                 required-opps = <&rpmpd_opp_min_svs>;
1830                                         };
1831
1832                                         opp-192000000 {
1833                                                 opp-hz = /bits/ 64 <192000000>;
1834                                                 required-opps = <&rpmpd_opp_low_svs>;
1835                                         };
1836
1837                                         opp-256000000 {
1838                                                 opp-hz = /bits/ 64 <256000000>;
1839                                                 required-opps = <&rpmpd_opp_svs>;
1840                                         };
1841
1842                                         opp-307200000 {
1843                                                 opp-hz = /bits/ 64 <307200000>;
1844                                                 required-opps = <&rpmpd_opp_svs_plus>;
1845                                         };
1846
1847                                         opp-384000000 {
1848                                                 opp-hz = /bits/ 64 <384000000>;
1849                                                 required-opps = <&rpmpd_opp_nom>;
1850                                         };
1851                                 };
1852                         };
1853
1854                         mdss_dsi0: dsi@5e94000 {
1855                                 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1856                                 reg = <0x0 0x05e94000 0x0 0x400>;
1857                                 reg-names = "dsi_ctrl";
1858
1859                                 interrupt-parent = <&mdss>;
1860                                 interrupts = <4>;
1861
1862                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1863                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1864                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1865                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1866                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
1867                                          <&gcc GCC_DISP_HF_AXI_CLK>;
1868                                 clock-names = "byte",
1869                                               "byte_intf",
1870                                               "pixel",
1871                                               "core",
1872                                               "iface",
1873                                               "bus";
1874
1875                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1876                                                   <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1877                                 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1878
1879                                 operating-points-v2 = <&dsi_opp_table>;
1880                                 power-domains = <&rpmpd SM6115_VDDCX>;
1881                                 phys = <&mdss_dsi0_phy>;
1882
1883                                 #address-cells = <1>;
1884                                 #size-cells = <0>;
1885
1886                                 status = "disabled";
1887
1888                                 ports {
1889                                         #address-cells = <1>;
1890                                         #size-cells = <0>;
1891
1892                                         port@0 {
1893                                                 reg = <0>;
1894                                                 mdss_dsi0_in: endpoint {
1895                                                         remote-endpoint = <&dpu_intf1_out>;
1896                                                 };
1897                                         };
1898
1899                                         port@1 {
1900                                                 reg = <1>;
1901                                                 mdss_dsi0_out: endpoint {
1902                                                 };
1903                                         };
1904                                 };
1905
1906                                 dsi_opp_table: opp-table {
1907                                         compatible = "operating-points-v2";
1908
1909                                         opp-19200000 {
1910                                                 opp-hz = /bits/ 64 <19200000>;
1911                                                 required-opps = <&rpmpd_opp_min_svs>;
1912                                         };
1913
1914                                         opp-164000000 {
1915                                                 opp-hz = /bits/ 64 <164000000>;
1916                                                 required-opps = <&rpmpd_opp_low_svs>;
1917                                         };
1918
1919                                         opp-187500000 {
1920                                                 opp-hz = /bits/ 64 <187500000>;
1921                                                 required-opps = <&rpmpd_opp_svs>;
1922                                         };
1923                                 };
1924                         };
1925
1926                         mdss_dsi0_phy: phy@5e94400 {
1927                                 compatible = "qcom,dsi-phy-14nm-2290";
1928                                 reg = <0x0 0x05e94400 0x0 0x100>,
1929                                       <0x0 0x05e94500 0x0 0x300>,
1930                                       <0x0 0x05e94800 0x0 0x188>;
1931                                 reg-names = "dsi_phy",
1932                                             "dsi_phy_lane",
1933                                             "dsi_pll";
1934
1935                                 #clock-cells = <1>;
1936                                 #phy-cells = <0>;
1937
1938                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1939                                          <&rpmcc RPM_SMD_XO_CLK_SRC>;
1940                                 clock-names = "iface", "ref";
1941
1942                                 status = "disabled";
1943                         };
1944                 };
1945
1946                 dispcc: clock-controller@5f00000 {
1947                         compatible = "qcom,sm6115-dispcc";
1948                         reg = <0x0 0x05f00000 0 0x20000>;
1949                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1950                                  <&sleep_clk>,
1951                                  <&mdss_dsi0_phy 0>,
1952                                  <&mdss_dsi0_phy 1>,
1953                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
1954                         #clock-cells = <1>;
1955                         #reset-cells = <1>;
1956                         #power-domain-cells = <1>;
1957                 };
1958
1959                 remoteproc_mpss: remoteproc@6080000 {
1960                         compatible = "qcom,sm6115-mpss-pas";
1961                         reg = <0x0 0x06080000 0x0 0x100>;
1962
1963                         interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1964                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1965                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1966                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1967                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1968                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1969                         interrupt-names = "wdog", "fatal", "ready", "handover",
1970                                           "stop-ack", "shutdown-ack";
1971
1972                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1973                         clock-names = "xo";
1974
1975                         power-domains = <&rpmpd SM6115_VDDCX>;
1976
1977                         memory-region = <&pil_modem_mem>;
1978
1979                         qcom,smem-states = <&modem_smp2p_out 0>;
1980                         qcom,smem-state-names = "stop";
1981
1982                         status = "disabled";
1983
1984                         glink-edge {
1985                                 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
1986                                 label = "mpss";
1987                                 qcom,remote-pid = <1>;
1988                                 mboxes = <&apcs_glb 12>;
1989                         };
1990                 };
1991
1992                 stm@8002000 {
1993                         compatible = "arm,coresight-stm", "arm,primecell";
1994                         reg = <0x0 0x08002000 0x0 0x1000>,
1995                               <0x0 0x0e280000 0x0 0x180000>;
1996                         reg-names = "stm-base", "stm-stimulus-base";
1997
1998                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1999                         clock-names = "apb_pclk";
2000
2001                         status = "disabled";
2002
2003                         out-ports {
2004                                 port {
2005                                         stm_out: endpoint {
2006                                                 remote-endpoint = <&funnel_in0_in>;
2007                                         };
2008                                 };
2009                         };
2010                 };
2011
2012                 cti0: cti@8010000 {
2013                         compatible = "arm,coresight-cti", "arm,primecell";
2014                         reg = <0x0 0x08010000 0x0 0x1000>;
2015
2016                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2017                         clock-names = "apb_pclk";
2018
2019                         status = "disabled";
2020                 };
2021
2022                 cti1: cti@8011000 {
2023                         compatible = "arm,coresight-cti", "arm,primecell";
2024                         reg = <0x0 0x08011000 0x0 0x1000>;
2025
2026                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2027                         clock-names = "apb_pclk";
2028
2029                         status = "disabled";
2030                 };
2031
2032                 cti2: cti@8012000 {
2033                         compatible = "arm,coresight-cti", "arm,primecell";
2034                         reg = <0x0 0x08012000 0x0 0x1000>;
2035
2036                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2037                         clock-names = "apb_pclk";
2038
2039                         status = "disabled";
2040                 };
2041
2042                 cti3: cti@8013000 {
2043                         compatible = "arm,coresight-cti", "arm,primecell";
2044                         reg = <0x0 0x08013000 0x0 0x1000>;
2045
2046                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2047                         clock-names = "apb_pclk";
2048
2049                         status = "disabled";
2050                 };
2051
2052                 cti4: cti@8014000 {
2053                         compatible = "arm,coresight-cti", "arm,primecell";
2054                         reg = <0x0 0x08014000 0x0 0x1000>;
2055
2056                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2057                         clock-names = "apb_pclk";
2058
2059                         status = "disabled";
2060                 };
2061
2062                 cti5: cti@8015000 {
2063                         compatible = "arm,coresight-cti", "arm,primecell";
2064                         reg = <0x0 0x08015000 0x0 0x1000>;
2065
2066                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2067                         clock-names = "apb_pclk";
2068
2069                         status = "disabled";
2070                 };
2071
2072                 cti6: cti@8016000 {
2073                         compatible = "arm,coresight-cti", "arm,primecell";
2074                         reg = <0x0 0x08016000 0x0 0x1000>;
2075
2076                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2077                         clock-names = "apb_pclk";
2078
2079                         status = "disabled";
2080                 };
2081
2082                 cti7: cti@8017000 {
2083                         compatible = "arm,coresight-cti", "arm,primecell";
2084                         reg = <0x0 0x08017000 0x0 0x1000>;
2085
2086                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2087                         clock-names = "apb_pclk";
2088
2089                         status = "disabled";
2090                 };
2091
2092                 cti8: cti@8018000 {
2093                         compatible = "arm,coresight-cti", "arm,primecell";
2094                         reg = <0x0 0x08018000 0x0 0x1000>;
2095
2096                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2097                         clock-names = "apb_pclk";
2098
2099                         status = "disabled";
2100                 };
2101
2102                 cti9: cti@8019000 {
2103                         compatible = "arm,coresight-cti", "arm,primecell";
2104                         reg = <0x0 0x08019000 0x0 0x1000>;
2105
2106                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2107                         clock-names = "apb_pclk";
2108
2109                         status = "disabled";
2110                 };
2111
2112                 cti10: cti@801a000 {
2113                         compatible = "arm,coresight-cti", "arm,primecell";
2114                         reg = <0x0 0x0801a000 0x0 0x1000>;
2115
2116                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2117                         clock-names = "apb_pclk";
2118
2119                         status = "disabled";
2120                 };
2121
2122                 cti11: cti@801b000 {
2123                         compatible = "arm,coresight-cti", "arm,primecell";
2124                         reg = <0x0 0x0801b000 0x0 0x1000>;
2125
2126                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2127                         clock-names = "apb_pclk";
2128
2129                         status = "disabled";
2130                 };
2131
2132                 cti12: cti@801c000 {
2133                         compatible = "arm,coresight-cti", "arm,primecell";
2134                         reg = <0x0 0x0801c000 0x0 0x1000>;
2135
2136                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2137                         clock-names = "apb_pclk";
2138
2139                         status = "disabled";
2140                 };
2141
2142                 cti13: cti@801d000 {
2143                         compatible = "arm,coresight-cti", "arm,primecell";
2144                         reg = <0x0 0x0801d000 0x0 0x1000>;
2145
2146                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2147                         clock-names = "apb_pclk";
2148
2149                         status = "disabled";
2150                 };
2151
2152                 cti14: cti@801e000 {
2153                         compatible = "arm,coresight-cti", "arm,primecell";
2154                         reg = <0x0 0x0801e000 0x0 0x1000>;
2155
2156                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2157                         clock-names = "apb_pclk";
2158
2159                         status = "disabled";
2160                 };
2161
2162                 cti15: cti@801f000 {
2163                         compatible = "arm,coresight-cti", "arm,primecell";
2164                         reg = <0x0 0x0801f000 0x0 0x1000>;
2165
2166                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2167                         clock-names = "apb_pclk";
2168
2169                         status = "disabled";
2170                 };
2171
2172                 replicator@8046000 {
2173                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2174                         reg = <0x0 0x08046000 0x0 0x1000>;
2175
2176                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2177                         clock-names = "apb_pclk";
2178
2179                         status = "disabled";
2180
2181                         out-ports {
2182                                 port {
2183                                         replicator_out: endpoint {
2184                                                 remote-endpoint = <&etr_in>;
2185                                         };
2186                                 };
2187                         };
2188
2189                         in-ports {
2190                                 port {
2191                                         replicator_in: endpoint {
2192                                                 remote-endpoint = <&etf_out>;
2193                                         };
2194                                 };
2195                         };
2196                 };
2197
2198                 etf@8047000 {
2199                         compatible = "arm,coresight-tmc", "arm,primecell";
2200                         reg = <0x0 0x08047000 0x0 0x1000>;
2201
2202                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2203                         clock-names = "apb_pclk";
2204
2205                         status = "disabled";
2206
2207                         in-ports {
2208                                 port {
2209                                         etf_in: endpoint {
2210                                                 remote-endpoint = <&merge_funnel_out>;
2211                                         };
2212                                 };
2213                         };
2214
2215                         out-ports {
2216                                 port {
2217                                         etf_out: endpoint {
2218                                                 remote-endpoint = <&replicator_in>;
2219                                         };
2220                                 };
2221                         };
2222                 };
2223
2224                 etr@8048000 {
2225                         compatible = "arm,coresight-tmc", "arm,primecell";
2226                         reg = <0x0 0x08048000 0x0 0x1000>;
2227
2228                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2229                         clock-names = "apb_pclk";
2230
2231                         status = "disabled";
2232
2233                         in-ports {
2234                                 port {
2235                                         etr_in: endpoint {
2236                                                 remote-endpoint = <&replicator_out>;
2237                                         };
2238                                 };
2239                         };
2240                 };
2241
2242                 funnel@8041000 {
2243                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2244                         reg = <0x0 0x08041000 0x0 0x1000>;
2245
2246                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2247                         clock-names = "apb_pclk";
2248
2249                         status = "disabled";
2250
2251                         out-ports {
2252                                 port {
2253                                         funnel_in0_out: endpoint {
2254                                                 remote-endpoint = <&merge_funnel_in0>;
2255                                         };
2256                                 };
2257                         };
2258
2259                         in-ports {
2260                                 port {
2261                                         funnel_in0_in: endpoint {
2262                                                 remote-endpoint = <&stm_out>;
2263                                         };
2264                                 };
2265                         };
2266                 };
2267
2268                 funnel@8042000 {
2269                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2270                         reg = <0x0 0x08042000 0x0 0x1000>;
2271
2272                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2273                         clock-names = "apb_pclk";
2274
2275                         status = "disabled";
2276
2277                         out-ports {
2278                                 port {
2279                                         funnel_in1_out: endpoint {
2280                                                 remote-endpoint = <&merge_funnel_in1>;
2281                                         };
2282                                 };
2283                         };
2284
2285                         in-ports {
2286                                 port {
2287                                         funnel_in1_in: endpoint {
2288                                                 remote-endpoint = <&funnel_apss1_out>;
2289                                         };
2290                                 };
2291                         };
2292                 };
2293
2294                 funnel@8045000 {
2295                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2296                         reg = <0x0 0x08045000 0x0 0x1000>;
2297
2298                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2299                         clock-names = "apb_pclk";
2300
2301                         status = "disabled";
2302
2303                         out-ports {
2304                                 port {
2305                                         merge_funnel_out: endpoint {
2306                                                 remote-endpoint = <&etf_in>;
2307                                         };
2308                                 };
2309                         };
2310
2311                         in-ports {
2312                                 #address-cells = <1>;
2313                                 #size-cells = <0>;
2314
2315                                 port@0 {
2316                                         reg = <0>;
2317                                         merge_funnel_in0: endpoint {
2318                                                 remote-endpoint = <&funnel_in0_out>;
2319                                         };
2320                                 };
2321
2322                                 port@1 {
2323                                         reg = <1>;
2324                                         merge_funnel_in1: endpoint {
2325                                                 remote-endpoint = <&funnel_in1_out>;
2326                                         };
2327                                 };
2328                         };
2329                 };
2330
2331                 etm@9040000 {
2332                         compatible = "arm,coresight-etm4x", "arm,primecell";
2333                         reg = <0x0 0x09040000 0x0 0x1000>;
2334
2335                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2336                         clock-names = "apb_pclk";
2337                         arm,coresight-loses-context-with-cpu;
2338
2339                         cpu = <&CPU0>;
2340
2341                         status = "disabled";
2342
2343                         out-ports {
2344                                 port {
2345                                         etm0_out: endpoint {
2346                                                 remote-endpoint = <&funnel_apss0_in0>;
2347                                         };
2348                                 };
2349                         };
2350                 };
2351
2352                 etm@9140000 {
2353                         compatible = "arm,coresight-etm4x", "arm,primecell";
2354                         reg = <0x0 0x09140000 0x0 0x1000>;
2355
2356                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2357                         clock-names = "apb_pclk";
2358                         arm,coresight-loses-context-with-cpu;
2359
2360                         cpu = <&CPU1>;
2361
2362                         status = "disabled";
2363
2364                         out-ports {
2365                                 port {
2366                                         etm1_out: endpoint {
2367                                                 remote-endpoint = <&funnel_apss0_in1>;
2368                                         };
2369                                 };
2370                         };
2371                 };
2372
2373                 etm@9240000 {
2374                         compatible = "arm,coresight-etm4x", "arm,primecell";
2375                         reg = <0x0 0x09240000 0x0 0x1000>;
2376
2377                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2378                         clock-names = "apb_pclk";
2379                         arm,coresight-loses-context-with-cpu;
2380
2381                         cpu = <&CPU2>;
2382
2383                         status = "disabled";
2384
2385                         out-ports {
2386                                 port {
2387                                         etm2_out: endpoint {
2388                                                 remote-endpoint = <&funnel_apss0_in2>;
2389                                         };
2390                                 };
2391                         };
2392                 };
2393
2394                 etm@9340000 {
2395                         compatible = "arm,coresight-etm4x", "arm,primecell";
2396                         reg = <0x0 0x09340000 0x0 0x1000>;
2397
2398                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2399                         clock-names = "apb_pclk";
2400                         arm,coresight-loses-context-with-cpu;
2401
2402                         cpu = <&CPU3>;
2403
2404                         status = "disabled";
2405
2406                         out-ports {
2407                                 port {
2408                                         etm3_out: endpoint {
2409                                                 remote-endpoint = <&funnel_apss0_in3>;
2410                                         };
2411                                 };
2412                         };
2413                 };
2414
2415                 etm@9440000 {
2416                         compatible = "arm,coresight-etm4x", "arm,primecell";
2417                         reg = <0x0 0x09440000 0x0 0x1000>;
2418
2419                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2420                         clock-names = "apb_pclk";
2421                         arm,coresight-loses-context-with-cpu;
2422
2423                         cpu = <&CPU4>;
2424
2425                         status = "disabled";
2426
2427                         out-ports {
2428                                 port {
2429                                         etm4_out: endpoint {
2430                                                 remote-endpoint = <&funnel_apss0_in4>;
2431                                         };
2432                                 };
2433                         };
2434                 };
2435
2436                 etm@9540000 {
2437                         compatible = "arm,coresight-etm4x", "arm,primecell";
2438                         reg = <0x0 0x09540000 0x0 0x1000>;
2439
2440                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2441                         clock-names = "apb_pclk";
2442                         arm,coresight-loses-context-with-cpu;
2443
2444                         cpu = <&CPU5>;
2445
2446                         status = "disabled";
2447
2448                         out-ports {
2449                                 port {
2450                                         etm5_out: endpoint {
2451                                                 remote-endpoint = <&funnel_apss0_in5>;
2452                                         };
2453                                 };
2454                         };
2455                 };
2456
2457                 etm@9640000 {
2458                         compatible = "arm,coresight-etm4x", "arm,primecell";
2459                         reg = <0x0 0x09640000 0x0 0x1000>;
2460
2461                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2462                         clock-names = "apb_pclk";
2463                         arm,coresight-loses-context-with-cpu;
2464
2465                         cpu = <&CPU6>;
2466
2467                         status = "disabled";
2468
2469                         out-ports {
2470                                 port {
2471                                         etm6_out: endpoint {
2472                                                 remote-endpoint = <&funnel_apss0_in6>;
2473                                         };
2474                                 };
2475                         };
2476                 };
2477
2478                 etm@9740000 {
2479                         compatible = "arm,coresight-etm4x", "arm,primecell";
2480                         reg = <0x0 0x09740000 0x0 0x1000>;
2481
2482                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2483                         clock-names = "apb_pclk";
2484                         arm,coresight-loses-context-with-cpu;
2485
2486                         cpu = <&CPU7>;
2487
2488                         status = "disabled";
2489
2490                         out-ports {
2491                                 port {
2492                                         etm7_out: endpoint {
2493                                                 remote-endpoint = <&funnel_apss0_in7>;
2494                                         };
2495                                 };
2496                         };
2497                 };
2498
2499                 funnel@9800000 {
2500                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2501                         reg = <0x0 0x09800000 0x0 0x1000>;
2502
2503                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2504                         clock-names = "apb_pclk";
2505
2506                         status = "disabled";
2507
2508                         out-ports {
2509                                 port {
2510                                         funnel_apss0_out: endpoint {
2511                                                 remote-endpoint = <&funnel_apss1_in>;
2512                                         };
2513                                 };
2514                         };
2515
2516                         in-ports {
2517                                 #address-cells = <1>;
2518                                 #size-cells = <0>;
2519
2520                                 port@0 {
2521                                         reg = <0>;
2522                                         funnel_apss0_in0: endpoint {
2523                                                 remote-endpoint = <&etm0_out>;
2524                                         };
2525                                 };
2526
2527                                 port@1 {
2528                                         reg = <1>;
2529                                         funnel_apss0_in1: endpoint {
2530                                                 remote-endpoint = <&etm1_out>;
2531                                         };
2532                                 };
2533
2534                                 port@2 {
2535                                         reg = <2>;
2536                                         funnel_apss0_in2: endpoint {
2537                                                 remote-endpoint = <&etm2_out>;
2538                                         };
2539                                 };
2540
2541                                 port@3 {
2542                                         reg = <3>;
2543                                         funnel_apss0_in3: endpoint {
2544                                                 remote-endpoint = <&etm3_out>;
2545                                         };
2546                                 };
2547
2548                                 port@4 {
2549                                         reg = <4>;
2550                                         funnel_apss0_in4: endpoint {
2551                                                 remote-endpoint = <&etm4_out>;
2552                                         };
2553                                 };
2554
2555                                 port@5 {
2556                                         reg = <5>;
2557                                         funnel_apss0_in5: endpoint {
2558                                                 remote-endpoint = <&etm5_out>;
2559                                         };
2560                                 };
2561
2562                                 port@6 {
2563                                         reg = <6>;
2564                                         funnel_apss0_in6: endpoint {
2565                                                 remote-endpoint = <&etm6_out>;
2566                                         };
2567                                 };
2568
2569                                 port@7 {
2570                                         reg = <7>;
2571                                         funnel_apss0_in7: endpoint {
2572                                                 remote-endpoint = <&etm7_out>;
2573                                         };
2574                                 };
2575                         };
2576                 };
2577
2578                 funnel@9810000 {
2579                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2580                         reg = <0x0 0x09810000 0x0 0x1000>;
2581
2582                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2583                         clock-names = "apb_pclk";
2584
2585                         status = "disabled";
2586
2587                         out-ports {
2588                                 port {
2589                                         funnel_apss1_out: endpoint {
2590                                                 remote-endpoint = <&funnel_in1_in>;
2591                                         };
2592                                 };
2593                         };
2594
2595                         in-ports {
2596                                 port {
2597                                         funnel_apss1_in: endpoint {
2598                                                 remote-endpoint = <&funnel_apss0_out>;
2599                                         };
2600                                 };
2601                         };
2602                 };
2603
2604                 remoteproc_adsp: remoteproc@ab00000 {
2605                         compatible = "qcom,sm6115-adsp-pas";
2606                         reg = <0x0 0x0ab00000 0x0 0x100>;
2607
2608                         interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2609                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2610                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2611                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2612                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2613                         interrupt-names = "wdog", "fatal", "ready",
2614                                           "handover", "stop-ack";
2615
2616                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2617                         clock-names = "xo";
2618
2619                         power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2620                                         <&rpmpd SM6115_VDD_LPI_MX>;
2621
2622                         memory-region = <&pil_adsp_mem>;
2623
2624                         qcom,smem-states = <&adsp_smp2p_out 0>;
2625                         qcom,smem-state-names = "stop";
2626
2627                         status = "disabled";
2628
2629                         glink-edge {
2630                                 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
2631                                 label = "lpass";
2632                                 qcom,remote-pid = <2>;
2633                                 mboxes = <&apcs_glb 8>;
2634
2635                                 fastrpc {
2636                                         compatible = "qcom,fastrpc";
2637                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2638                                         label = "adsp";
2639                                         qcom,non-secure-domain;
2640                                         #address-cells = <1>;
2641                                         #size-cells = <0>;
2642
2643                                         compute-cb@3 {
2644                                                 compatible = "qcom,fastrpc-compute-cb";
2645                                                 reg = <3>;
2646                                                 iommus = <&apps_smmu 0x01c3 0x0>;
2647                                         };
2648
2649                                         compute-cb@4 {
2650                                                 compatible = "qcom,fastrpc-compute-cb";
2651                                                 reg = <4>;
2652                                                 iommus = <&apps_smmu 0x01c4 0x0>;
2653                                         };
2654
2655                                         compute-cb@5 {
2656                                                 compatible = "qcom,fastrpc-compute-cb";
2657                                                 reg = <5>;
2658                                                 iommus = <&apps_smmu 0x01c5 0x0>;
2659                                         };
2660
2661                                         compute-cb@6 {
2662                                                 compatible = "qcom,fastrpc-compute-cb";
2663                                                 reg = <6>;
2664                                                 iommus = <&apps_smmu 0x01c6 0x0>;
2665                                         };
2666
2667                                         compute-cb@7 {
2668                                                 compatible = "qcom,fastrpc-compute-cb";
2669                                                 reg = <7>;
2670                                                 iommus = <&apps_smmu 0x01c7 0x0>;
2671                                         };
2672                                 };
2673                         };
2674                 };
2675
2676                 remoteproc_cdsp: remoteproc@b300000 {
2677                         compatible = "qcom,sm6115-cdsp-pas";
2678                         reg = <0x0 0x0b300000 0x0 0x100000>;
2679
2680                         interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2681                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2682                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2683                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2684                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2685                         interrupt-names = "wdog", "fatal", "ready",
2686                                           "handover", "stop-ack";
2687
2688                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2689                         clock-names = "xo";
2690
2691                         power-domains = <&rpmpd SM6115_VDDCX>;
2692
2693                         memory-region = <&pil_cdsp_mem>;
2694
2695                         qcom,smem-states = <&cdsp_smp2p_out 0>;
2696                         qcom,smem-state-names = "stop";
2697
2698                         status = "disabled";
2699
2700                         glink-edge {
2701                                 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
2702                                 label = "cdsp";
2703                                 qcom,remote-pid = <5>;
2704                                 mboxes = <&apcs_glb 28>;
2705
2706                                 fastrpc {
2707                                         compatible = "qcom,fastrpc";
2708                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2709                                         label = "cdsp";
2710                                         qcom,non-secure-domain;
2711                                         #address-cells = <1>;
2712                                         #size-cells = <0>;
2713
2714                                         compute-cb@1 {
2715                                                 compatible = "qcom,fastrpc-compute-cb";
2716                                                 reg = <1>;
2717                                                 iommus = <&apps_smmu 0x0c01 0x0>;
2718                                         };
2719
2720                                         compute-cb@2 {
2721                                                 compatible = "qcom,fastrpc-compute-cb";
2722                                                 reg = <2>;
2723                                                 iommus = <&apps_smmu 0x0c02 0x0>;
2724                                         };
2725
2726                                         compute-cb@3 {
2727                                                 compatible = "qcom,fastrpc-compute-cb";
2728                                                 reg = <3>;
2729                                                 iommus = <&apps_smmu 0x0c03 0x0>;
2730                                         };
2731
2732                                         compute-cb@4 {
2733                                                 compatible = "qcom,fastrpc-compute-cb";
2734                                                 reg = <4>;
2735                                                 iommus = <&apps_smmu 0x0c04 0x0>;
2736                                         };
2737
2738                                         compute-cb@5 {
2739                                                 compatible = "qcom,fastrpc-compute-cb";
2740                                                 reg = <5>;
2741                                                 iommus = <&apps_smmu 0x0c05 0x0>;
2742                                         };
2743
2744                                         compute-cb@6 {
2745                                                 compatible = "qcom,fastrpc-compute-cb";
2746                                                 reg = <6>;
2747                                                 iommus = <&apps_smmu 0x0c06 0x0>;
2748                                         };
2749
2750                                         /* note: secure cb9 in downstream */
2751                                 };
2752                         };
2753                 };
2754
2755                 apps_smmu: iommu@c600000 {
2756                         compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2757                         reg = <0x0 0x0c600000 0x0 0x80000>;
2758                         #iommu-cells = <2>;
2759                         #global-interrupts = <1>;
2760
2761                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
2762                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
2763                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
2764                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
2765                                      <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
2766                                      <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
2767                                      <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
2768                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
2769                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
2770                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
2771                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2772                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2773                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2774                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2775                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2776                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2777                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2778                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2779                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2780                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2781                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2782                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2783                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2784                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2785                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2786                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2787                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2788                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2789                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2790                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2791                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2792                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2793                                      <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
2794                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
2795                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
2796                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
2797                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
2798                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2799                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2800                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2801                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2802                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
2803                                      <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
2804                                      <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2805                                      <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2806                                      <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
2807                                      <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2808                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2809                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2810                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2811                                      <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
2812                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
2813                                      <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2814                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
2815                                      <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2816                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2817                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2818                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2819                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2820                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2821                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2822                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2823                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2824                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
2825                                      <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
2826                 };
2827
2828                 wifi: wifi@c800000 {
2829                         compatible = "qcom,wcn3990-wifi";
2830                         reg = <0x0 0x0c800000 0x0 0x800000>;
2831                         reg-names = "membase";
2832                         memory-region = <&wlan_msa_mem>;
2833                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
2834                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
2835                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
2836                                      <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
2837                                      <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
2838                                      <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
2839                                      <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
2840                                      <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
2841                                      <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
2842                                      <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
2843                                      <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
2844                                      <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
2845                         iommus = <&apps_smmu 0x1a0 0x1>;
2846                         qcom,msa-fixed-perm;
2847                         status = "disabled";
2848                 };
2849
2850                 watchdog@f017000 {
2851                         compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
2852                         reg = <0x0 0x0f017000 0x0 0x1000>;
2853                         clocks = <&sleep_clk>;
2854                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2855                 };
2856
2857                 apcs_glb: mailbox@f111000 {
2858                         compatible = "qcom,sm6115-apcs-hmss-global",
2859                                      "qcom,msm8994-apcs-kpss-global";
2860                         reg = <0x0 0x0f111000 0x0 0x1000>;
2861
2862                         #mbox-cells = <1>;
2863                 };
2864
2865                 timer@f120000 {
2866                         compatible = "arm,armv7-timer-mem";
2867                         reg = <0x0 0x0f120000 0x0 0x1000>;
2868                         #address-cells = <2>;
2869                         #size-cells = <1>;
2870                         ranges = <0x0 0x0 0x0 0x0 0x20000000>;
2871                         clock-frequency = <19200000>;
2872
2873                         frame@f121000 {
2874                                 reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>;
2875                                 frame-number = <0>;
2876                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2877                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2878                         };
2879
2880                         frame@f123000 {
2881                                 reg = <0x0 0x0f123000 0x1000>;
2882                                 frame-number = <1>;
2883                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2884                                 status = "disabled";
2885                         };
2886
2887                         frame@f124000 {
2888                                 reg = <0x0 0x0f124000 0x1000>;
2889                                 frame-number = <2>;
2890                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2891                                 status = "disabled";
2892                         };
2893
2894                         frame@f125000 {
2895                                 reg = <0x0 0x0f125000 0x1000>;
2896                                 frame-number = <3>;
2897                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2898                                 status = "disabled";
2899                         };
2900
2901                         frame@f126000 {
2902                                 reg = <0x0 0x0f126000 0x1000>;
2903                                 frame-number = <4>;
2904                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2905                                 status = "disabled";
2906                         };
2907
2908                         frame@f127000 {
2909                                 reg = <0x0 0x0f127000 0x1000>;
2910                                 frame-number = <5>;
2911                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2912                                 status = "disabled";
2913                         };
2914
2915                         frame@f128000 {
2916                                 reg = <0x0 0x0f128000 0x1000>;
2917                                 frame-number = <6>;
2918                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2919                                 status = "disabled";
2920                         };
2921                 };
2922
2923                 intc: interrupt-controller@f200000 {
2924                         compatible = "arm,gic-v3";
2925                         reg = <0x0 0x0f200000 0x0 0x10000>,
2926                               <0x0 0x0f300000 0x0 0x100000>;
2927                         #interrupt-cells = <3>;
2928                         interrupt-controller;
2929                         interrupt-parent = <&intc>;
2930                         #redistributor-regions = <1>;
2931                         redistributor-stride = <0x0 0x20000>;
2932                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2933                 };
2934
2935                 cpufreq_hw: cpufreq@f521000 {
2936                         compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
2937                         reg = <0x0 0x0f521000 0x0 0x1000>,
2938                               <0x0 0x0f523000 0x0 0x1000>;
2939
2940                         reg-names = "freq-domain0", "freq-domain1";
2941                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
2942                         clock-names = "xo", "alternate";
2943
2944                         #freq-domain-cells = <1>;
2945                         #clock-cells = <1>;
2946                 };
2947         };
2948
2949         thermal-zones {
2950                 mapss-thermal {
2951                         polling-delay-passive = <0>;
2952                         polling-delay = <0>;
2953                         thermal-sensors = <&tsens0 0>;
2954
2955                         trips {
2956                                 trip-point0 {
2957                                         temperature = <115000>;
2958                                         hysteresis = <5000>;
2959                                         type = "passive";
2960                                 };
2961
2962                                 trip-point1 {
2963                                         temperature = <125000>;
2964                                         hysteresis = <1000>;
2965                                         type = "passive";
2966                                 };
2967                         };
2968                 };
2969
2970                 cdsp-hvx-thermal {
2971                         polling-delay-passive = <0>;
2972                         polling-delay = <0>;
2973                         thermal-sensors = <&tsens0 1>;
2974
2975                         trips {
2976                                 trip-point0 {
2977                                         temperature = <115000>;
2978                                         hysteresis = <5000>;
2979                                         type = "passive";
2980                                 };
2981
2982                                 trip-point1 {
2983                                         temperature = <125000>;
2984                                         hysteresis = <1000>;
2985                                         type = "passive";
2986                                 };
2987                         };
2988                 };
2989
2990                 wlan-thermal {
2991                         polling-delay-passive = <0>;
2992                         polling-delay = <0>;
2993                         thermal-sensors = <&tsens0 2>;
2994
2995                         trips {
2996                                 trip-point0 {
2997                                         temperature = <115000>;
2998                                         hysteresis = <5000>;
2999                                         type = "passive";
3000                                 };
3001
3002                                 trip-point1 {
3003                                         temperature = <125000>;
3004                                         hysteresis = <1000>;
3005                                         type = "passive";
3006                                 };
3007                         };
3008                 };
3009
3010                 camera-thermal {
3011                         polling-delay-passive = <0>;
3012                         polling-delay = <0>;
3013                         thermal-sensors = <&tsens0 3>;
3014
3015                         trips {
3016                                 trip-point0 {
3017                                         temperature = <115000>;
3018                                         hysteresis = <5000>;
3019                                         type = "passive";
3020                                 };
3021
3022                                 trip-point1 {
3023                                         temperature = <125000>;
3024                                         hysteresis = <1000>;
3025                                         type = "passive";
3026                                 };
3027                         };
3028                 };
3029
3030                 video-thermal {
3031                         polling-delay-passive = <0>;
3032                         polling-delay = <0>;
3033                         thermal-sensors = <&tsens0 4>;
3034
3035                         trips {
3036                                 trip-point0 {
3037                                         temperature = <115000>;
3038                                         hysteresis = <5000>;
3039                                         type = "passive";
3040                                 };
3041
3042                                 trip-point1 {
3043                                         temperature = <125000>;
3044                                         hysteresis = <1000>;
3045                                         type = "passive";
3046                                 };
3047                         };
3048                 };
3049
3050                 modem1-thermal {
3051                         polling-delay-passive = <0>;
3052                         polling-delay = <0>;
3053                         thermal-sensors = <&tsens0 5>;
3054
3055                         trips {
3056                                 trip-point0 {
3057                                         temperature = <115000>;
3058                                         hysteresis = <5000>;
3059                                         type = "passive";
3060                                 };
3061
3062                                 trip-point1 {
3063                                         temperature = <125000>;
3064                                         hysteresis = <1000>;
3065                                         type = "passive";
3066                                 };
3067                         };
3068                 };
3069
3070                 cpu4-thermal {
3071                         polling-delay-passive = <0>;
3072                         polling-delay = <0>;
3073                         thermal-sensors = <&tsens0 6>;
3074
3075                         trips {
3076                                 cpu4_alert0: trip-point0 {
3077                                         temperature = <90000>;
3078                                         hysteresis = <2000>;
3079                                         type = "passive";
3080                                 };
3081
3082                                 cpu4_alert1: trip-point1 {
3083                                         temperature = <95000>;
3084                                         hysteresis = <2000>;
3085                                         type = "passive";
3086                                 };
3087
3088                                 cpu4_crit: cpu_crit {
3089                                         temperature = <110000>;
3090                                         hysteresis = <1000>;
3091                                         type = "critical";
3092                                 };
3093                         };
3094                 };
3095
3096                 cpu5-thermal {
3097                         polling-delay-passive = <0>;
3098                         polling-delay = <0>;
3099                         thermal-sensors = <&tsens0 7>;
3100
3101                         trips {
3102                                 cpu5_alert0: trip-point0 {
3103                                         temperature = <90000>;
3104                                         hysteresis = <2000>;
3105                                         type = "passive";
3106                                 };
3107
3108                                 cpu5_alert1: trip-point1 {
3109                                         temperature = <95000>;
3110                                         hysteresis = <2000>;
3111                                         type = "passive";
3112                                 };
3113
3114                                 cpu5_crit: cpu_crit {
3115                                         temperature = <110000>;
3116                                         hysteresis = <1000>;
3117                                         type = "critical";
3118                                 };
3119                         };
3120                 };
3121
3122                 cpu6-thermal {
3123                         polling-delay-passive = <0>;
3124                         polling-delay = <0>;
3125                         thermal-sensors = <&tsens0 8>;
3126
3127                         trips {
3128                                 cpu6_alert0: trip-point0 {
3129                                         temperature = <90000>;
3130                                         hysteresis = <2000>;
3131                                         type = "passive";
3132                                 };
3133
3134                                 cpu6_alert1: trip-point1 {
3135                                         temperature = <95000>;
3136                                         hysteresis = <2000>;
3137                                         type = "passive";
3138                                 };
3139
3140                                 cpu6_crit: cpu_crit {
3141                                         temperature = <110000>;
3142                                         hysteresis = <1000>;
3143                                         type = "critical";
3144                                 };
3145                         };
3146                 };
3147
3148                 cpu7-thermal {
3149                         polling-delay-passive = <0>;
3150                         polling-delay = <0>;
3151                         thermal-sensors = <&tsens0 9>;
3152
3153                         trips {
3154                                 cpu7_alert0: trip-point0 {
3155                                         temperature = <90000>;
3156                                         hysteresis = <2000>;
3157                                         type = "passive";
3158                                 };
3159
3160                                 cpu7_alert1: trip-point1 {
3161                                         temperature = <95000>;
3162                                         hysteresis = <2000>;
3163                                         type = "passive";
3164                                 };
3165
3166                                 cpu7_crit: cpu_crit {
3167                                         temperature = <110000>;
3168                                         hysteresis = <1000>;
3169                                         type = "critical";
3170                                 };
3171                         };
3172                 };
3173
3174                 cpu45-thermal {
3175                         polling-delay-passive = <0>;
3176                         polling-delay = <0>;
3177                         thermal-sensors = <&tsens0 10>;
3178
3179                         trips {
3180                                 cpu45_alert0: trip-point0 {
3181                                         temperature = <90000>;
3182                                         hysteresis = <2000>;
3183                                         type = "passive";
3184                                 };
3185
3186                                 cpu45_alert1: trip-point1 {
3187                                         temperature = <95000>;
3188                                         hysteresis = <2000>;
3189                                         type = "passive";
3190                                 };
3191
3192                                 cpu45_crit: cpu_crit {
3193                                         temperature = <110000>;
3194                                         hysteresis = <1000>;
3195                                         type = "critical";
3196                                 };
3197                         };
3198                 };
3199
3200                 cpu67-thermal {
3201                         polling-delay-passive = <0>;
3202                         polling-delay = <0>;
3203                         thermal-sensors = <&tsens0 11>;
3204
3205                         trips {
3206                                 cpu67_alert0: trip-point0 {
3207                                         temperature = <90000>;
3208                                         hysteresis = <2000>;
3209                                         type = "passive";
3210                                 };
3211
3212                                 cpu67_alert1: trip-point1 {
3213                                         temperature = <95000>;
3214                                         hysteresis = <2000>;
3215                                         type = "passive";
3216                                 };
3217
3218                                 cpu67_crit: cpu_crit {
3219                                         temperature = <110000>;
3220                                         hysteresis = <1000>;
3221                                         type = "critical";
3222                                 };
3223                         };
3224                 };
3225
3226                 cpu0123-thermal {
3227                         polling-delay-passive = <0>;
3228                         polling-delay = <0>;
3229                         thermal-sensors = <&tsens0 12>;
3230
3231                         trips {
3232                                 cpu0123_alert0: trip-point0 {
3233                                         temperature = <90000>;
3234                                         hysteresis = <2000>;
3235                                         type = "passive";
3236                                 };
3237
3238                                 cpu0123_alert1: trip-point1 {
3239                                         temperature = <95000>;
3240                                         hysteresis = <2000>;
3241                                         type = "passive";
3242                                 };
3243
3244                                 cpu0123_crit: cpu_crit {
3245                                         temperature = <110000>;
3246                                         hysteresis = <1000>;
3247                                         type = "critical";
3248                                 };
3249                         };
3250                 };
3251
3252                 modem0-thermal {
3253                         polling-delay-passive = <0>;
3254                         polling-delay = <0>;
3255                         thermal-sensors = <&tsens0 13>;
3256
3257                         trips {
3258                                 trip-point0 {
3259                                         temperature = <115000>;
3260                                         hysteresis = <5000>;
3261                                         type = "passive";
3262                                 };
3263
3264                                 trip-point1 {
3265                                         temperature = <125000>;
3266                                         hysteresis = <1000>;
3267                                         type = "passive";
3268                                 };
3269                         };
3270                 };
3271
3272                 display-thermal {
3273                         polling-delay-passive = <0>;
3274                         polling-delay = <0>;
3275                         thermal-sensors = <&tsens0 14>;
3276
3277                         trips {
3278                                 trip-point0 {
3279                                         temperature = <115000>;
3280                                         hysteresis = <5000>;
3281                                         type = "passive";
3282                                 };
3283
3284                                 trip-point1 {
3285                                         temperature = <125000>;
3286                                         hysteresis = <1000>;
3287                                         type = "passive";
3288                                 };
3289                         };
3290                 };
3291
3292                 gpu-thermal {
3293                         polling-delay-passive = <0>;
3294                         polling-delay = <0>;
3295                         thermal-sensors = <&tsens0 15>;
3296
3297                         trips {
3298                                 trip-point0 {
3299                                         temperature = <115000>;
3300                                         hysteresis = <5000>;
3301                                         type = "passive";
3302                                 };
3303
3304                                 trip-point1 {
3305                                         temperature = <125000>;
3306                                         hysteresis = <1000>;
3307                                         type = "passive";
3308                                 };
3309                         };
3310                 };
3311         };
3312
3313         timer {
3314                 compatible = "arm,armv8-timer";
3315                 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3316                              <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3317                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3318                              <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3319         };
3320 };