1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited
7 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/interconnect/qcom,osm-l3.h>
10 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/phy/phy-qcom-qmp.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&intc>;
25 xo_board_clk: xo-board-clk {
26 compatible = "fixed-clock";
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
33 clock-frequency = <32764>;
37 cpu0_opp_table: cpu0-opp-table {
38 compatible = "operating-points-v2";
42 opp-hz = /bits/ 64 <300000000>;
43 opp-peak-kBps = <(300000 * 32)>;
46 opp-hz = /bits/ 64 <403200000>;
47 opp-peak-kBps = <(384000 * 32)>;
50 opp-hz = /bits/ 64 <499200000>;
51 opp-peak-kBps = <(480000 * 32)>;
54 opp-hz = /bits/ 64 <595200000>;
55 opp-peak-kBps = <(576000 * 32)>;
58 opp-hz = /bits/ 64 <691200000>;
59 opp-peak-kBps = <(672000 * 32)>;
62 opp-hz = /bits/ 64 <806400000>;
63 opp-peak-kBps = <(768000 * 32)>;
66 opp-hz = /bits/ 64 <902400000>;
67 opp-peak-kBps = <(864000 * 32)>;
70 opp-hz = /bits/ 64 <1017600000>;
71 opp-peak-kBps = <(960000 * 32)>;
74 opp-hz = /bits/ 64 <1113600000>;
75 opp-peak-kBps = <(1075200 * 32)>;
78 opp-hz = /bits/ 64 <1209600000>;
79 opp-peak-kBps = <(1171200 * 32)>;
82 opp-hz = /bits/ 64 <1324800000>;
83 opp-peak-kBps = <(1267200 * 32)>;
86 opp-hz = /bits/ 64 <1440000000>;
87 opp-peak-kBps = <(1363200 * 32)>;
90 opp-hz = /bits/ 64 <1555200000>;
91 opp-peak-kBps = <(1536000 * 32)>;
94 opp-hz = /bits/ 64 <1670400000>;
95 opp-peak-kBps = <(1612800 * 32)>;
98 opp-hz = /bits/ 64 <1785600000>;
99 opp-peak-kBps = <(1689600 * 32)>;
102 opp-hz = /bits/ 64 <1881600000>;
103 opp-peak-kBps = <(1689600 * 32)>;
106 opp-hz = /bits/ 64 <1996800000>;
107 opp-peak-kBps = <(1689600 * 32)>;
110 opp-hz = /bits/ 64 <2112000000>;
111 opp-peak-kBps = <(1689600 * 32)>;
114 opp-hz = /bits/ 64 <2227200000>;
115 opp-peak-kBps = <(1689600 * 32)>;
118 opp-hz = /bits/ 64 <2342400000>;
119 opp-peak-kBps = <(1689600 * 32)>;
122 opp-hz = /bits/ 64 <2438400000>;
123 opp-peak-kBps = <(1689600 * 32)>;
127 cpu4_opp_table: cpu4-opp-table {
128 compatible = "operating-points-v2";
132 opp-hz = /bits/ 64 <825600000>;
133 opp-peak-kBps = <(768000 * 32)>;
136 opp-hz = /bits/ 64 <940800000>;
137 opp-peak-kBps = <(864000 * 32)>;
140 opp-hz = /bits/ 64 <1056000000>;
141 opp-peak-kBps = <(960000 * 32)>;
144 opp-hz = /bits/ 64 <1171200000>;
145 opp-peak-kBps = <(1171200 * 32)>;
148 opp-hz = /bits/ 64 <1286400000>;
149 opp-peak-kBps = <(1267200 * 32)>;
152 opp-hz = /bits/ 64 <1401600000>;
153 opp-peak-kBps = <(1363200 * 32)>;
156 opp-hz = /bits/ 64 <1516800000>;
157 opp-peak-kBps = <(1459200 * 32)>;
160 opp-hz = /bits/ 64 <1632000000>;
161 opp-peak-kBps = <(1612800 * 32)>;
164 opp-hz = /bits/ 64 <1747200000>;
165 opp-peak-kBps = <(1689600 * 32)>;
168 opp-hz = /bits/ 64 <1862400000>;
169 opp-peak-kBps = <(1689600 * 32)>;
172 opp-hz = /bits/ 64 <1977600000>;
173 opp-peak-kBps = <(1689600 * 32)>;
176 opp-hz = /bits/ 64 <2073600000>;
177 opp-peak-kBps = <(1689600 * 32)>;
180 opp-hz = /bits/ 64 <2169600000>;
181 opp-peak-kBps = <(1689600 * 32)>;
184 opp-hz = /bits/ 64 <2284800000>;
185 opp-peak-kBps = <(1689600 * 32)>;
188 opp-hz = /bits/ 64 <2400000000>;
189 opp-peak-kBps = <(1689600 * 32)>;
192 opp-hz = /bits/ 64 <2496000000>;
193 opp-peak-kBps = <(1689600 * 32)>;
196 opp-hz = /bits/ 64 <2592000000>;
197 opp-peak-kBps = <(1689600 * 32)>;
200 opp-hz = /bits/ 64 <2688000000>;
201 opp-peak-kBps = <(1689600 * 32)>;
204 opp-hz = /bits/ 64 <2803200000>;
205 opp-peak-kBps = <(1689600 * 32)>;
208 opp-hz = /bits/ 64 <2899200000>;
209 opp-peak-kBps = <(1689600 * 32)>;
212 opp-hz = /bits/ 64 <2995200000>;
213 opp-peak-kBps = <(1689600 * 32)>;
218 #address-cells = <2>;
223 compatible = "qcom,kryo";
225 enable-method = "psci";
226 capacity-dmips-mhz = <602>;
227 next-level-cache = <&L2_0>;
228 power-domains = <&CPU_PD0>;
229 power-domain-names = "psci";
230 qcom,freq-domain = <&cpufreq_hw 0>;
231 operating-points-v2 = <&cpu0_opp_table>;
232 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
233 #cooling-cells = <2>;
235 compatible = "cache";
236 next-level-cache = <&L3_0>;
238 compatible = "cache";
245 compatible = "qcom,kryo";
247 enable-method = "psci";
248 capacity-dmips-mhz = <602>;
249 next-level-cache = <&L2_100>;
250 power-domains = <&CPU_PD1>;
251 power-domain-names = "psci";
252 qcom,freq-domain = <&cpufreq_hw 0>;
253 operating-points-v2 = <&cpu0_opp_table>;
254 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
255 #cooling-cells = <2>;
257 compatible = "cache";
258 next-level-cache = <&L3_0>;
264 compatible = "qcom,kryo";
266 enable-method = "psci";
267 capacity-dmips-mhz = <602>;
268 next-level-cache = <&L2_200>;
269 power-domains = <&CPU_PD2>;
270 power-domain-names = "psci";
271 qcom,freq-domain = <&cpufreq_hw 0>;
272 operating-points-v2 = <&cpu0_opp_table>;
273 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
274 #cooling-cells = <2>;
276 compatible = "cache";
277 next-level-cache = <&L3_0>;
283 compatible = "qcom,kryo";
285 enable-method = "psci";
286 capacity-dmips-mhz = <602>;
287 next-level-cache = <&L2_300>;
288 power-domains = <&CPU_PD3>;
289 power-domain-names = "psci";
290 qcom,freq-domain = <&cpufreq_hw 0>;
291 operating-points-v2 = <&cpu0_opp_table>;
292 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
293 #cooling-cells = <2>;
295 compatible = "cache";
296 next-level-cache = <&L3_0>;
302 compatible = "qcom,kryo";
304 enable-method = "psci";
305 capacity-dmips-mhz = <1024>;
306 next-level-cache = <&L2_400>;
307 power-domains = <&CPU_PD4>;
308 power-domain-names = "psci";
309 qcom,freq-domain = <&cpufreq_hw 1>;
310 operating-points-v2 = <&cpu4_opp_table>;
311 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
312 #cooling-cells = <2>;
314 compatible = "cache";
315 next-level-cache = <&L3_0>;
321 compatible = "qcom,kryo";
323 enable-method = "psci";
324 capacity-dmips-mhz = <1024>;
325 next-level-cache = <&L2_500>;
326 power-domains = <&CPU_PD5>;
327 power-domain-names = "psci";
328 qcom,freq-domain = <&cpufreq_hw 1>;
329 operating-points-v2 = <&cpu4_opp_table>;
330 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
331 #cooling-cells = <2>;
333 compatible = "cache";
334 next-level-cache = <&L3_0>;
340 compatible = "qcom,kryo";
342 enable-method = "psci";
343 capacity-dmips-mhz = <1024>;
344 next-level-cache = <&L2_600>;
345 power-domains = <&CPU_PD6>;
346 power-domain-names = "psci";
347 qcom,freq-domain = <&cpufreq_hw 1>;
348 operating-points-v2 = <&cpu4_opp_table>;
349 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
350 #cooling-cells = <2>;
352 compatible = "cache";
353 next-level-cache = <&L3_0>;
359 compatible = "qcom,kryo";
361 enable-method = "psci";
362 capacity-dmips-mhz = <1024>;
363 next-level-cache = <&L2_700>;
364 power-domains = <&CPU_PD7>;
365 power-domain-names = "psci";
366 qcom,freq-domain = <&cpufreq_hw 1>;
367 operating-points-v2 = <&cpu4_opp_table>;
368 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
369 #cooling-cells = <2>;
371 compatible = "cache";
372 next-level-cache = <&L3_0>;
413 entry-method = "psci";
415 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
416 compatible = "arm,idle-state";
417 idle-state-name = "little-rail-power-collapse";
418 arm,psci-suspend-param = <0x40000004>;
419 entry-latency-us = <355>;
420 exit-latency-us = <909>;
421 min-residency-us = <3934>;
425 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
426 compatible = "arm,idle-state";
427 idle-state-name = "big-rail-power-collapse";
428 arm,psci-suspend-param = <0x40000004>;
429 entry-latency-us = <241>;
430 exit-latency-us = <1461>;
431 min-residency-us = <4488>;
437 CLUSTER_SLEEP_0: cluster-sleep-0 {
438 compatible = "domain-idle-state";
439 idle-state-name = "cluster-power-collapse";
440 arm,psci-suspend-param = <0x4100c344>;
441 entry-latency-us = <3263>;
442 exit-latency-us = <6562>;
443 min-residency-us = <9987>;
450 compatible = "qcom,scm-sc8280xp", "qcom,scm";
454 aggre1_noc: interconnect-aggre1-noc {
455 compatible = "qcom,sc8280xp-aggre1-noc";
456 #interconnect-cells = <2>;
457 qcom,bcm-voters = <&apps_bcm_voter>;
460 aggre2_noc: interconnect-aggre2-noc {
461 compatible = "qcom,sc8280xp-aggre2-noc";
462 #interconnect-cells = <2>;
463 qcom,bcm-voters = <&apps_bcm_voter>;
466 clk_virt: interconnect-clk-virt {
467 compatible = "qcom,sc8280xp-clk-virt";
468 #interconnect-cells = <2>;
469 qcom,bcm-voters = <&apps_bcm_voter>;
472 config_noc: interconnect-config-noc {
473 compatible = "qcom,sc8280xp-config-noc";
474 #interconnect-cells = <2>;
475 qcom,bcm-voters = <&apps_bcm_voter>;
478 dc_noc: interconnect-dc-noc {
479 compatible = "qcom,sc8280xp-dc-noc";
480 #interconnect-cells = <2>;
481 qcom,bcm-voters = <&apps_bcm_voter>;
484 gem_noc: interconnect-gem-noc {
485 compatible = "qcom,sc8280xp-gem-noc";
486 #interconnect-cells = <2>;
487 qcom,bcm-voters = <&apps_bcm_voter>;
490 lpass_noc: interconnect-lpass-ag-noc {
491 compatible = "qcom,sc8280xp-lpass-ag-noc";
492 #interconnect-cells = <2>;
493 qcom,bcm-voters = <&apps_bcm_voter>;
496 mc_virt: interconnect-mc-virt {
497 compatible = "qcom,sc8280xp-mc-virt";
498 #interconnect-cells = <2>;
499 qcom,bcm-voters = <&apps_bcm_voter>;
502 mmss_noc: interconnect-mmss-noc {
503 compatible = "qcom,sc8280xp-mmss-noc";
504 #interconnect-cells = <2>;
505 qcom,bcm-voters = <&apps_bcm_voter>;
508 nspa_noc: interconnect-nspa-noc {
509 compatible = "qcom,sc8280xp-nspa-noc";
510 #interconnect-cells = <2>;
511 qcom,bcm-voters = <&apps_bcm_voter>;
514 nspb_noc: interconnect-nspb-noc {
515 compatible = "qcom,sc8280xp-nspb-noc";
516 #interconnect-cells = <2>;
517 qcom,bcm-voters = <&apps_bcm_voter>;
520 system_noc: interconnect-system-noc {
521 compatible = "qcom,sc8280xp-system-noc";
522 #interconnect-cells = <2>;
523 qcom,bcm-voters = <&apps_bcm_voter>;
527 device_type = "memory";
528 /* We expect the bootloader to fill in the size */
529 reg = <0x0 0x80000000 0x0 0x0>;
533 compatible = "arm,armv8-pmuv3";
534 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
538 compatible = "arm,psci-1.0";
542 #power-domain-cells = <0>;
543 power-domains = <&CLUSTER_PD>;
544 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
548 #power-domain-cells = <0>;
549 power-domains = <&CLUSTER_PD>;
550 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
554 #power-domain-cells = <0>;
555 power-domains = <&CLUSTER_PD>;
556 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
560 #power-domain-cells = <0>;
561 power-domains = <&CLUSTER_PD>;
562 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
566 #power-domain-cells = <0>;
567 power-domains = <&CLUSTER_PD>;
568 domain-idle-states = <&BIG_CPU_SLEEP_0>;
572 #power-domain-cells = <0>;
573 power-domains = <&CLUSTER_PD>;
574 domain-idle-states = <&BIG_CPU_SLEEP_0>;
578 #power-domain-cells = <0>;
579 power-domains = <&CLUSTER_PD>;
580 domain-idle-states = <&BIG_CPU_SLEEP_0>;
584 #power-domain-cells = <0>;
585 power-domains = <&CLUSTER_PD>;
586 domain-idle-states = <&BIG_CPU_SLEEP_0>;
589 CLUSTER_PD: cpu-cluster0 {
590 #power-domain-cells = <0>;
591 domain-idle-states = <&CLUSTER_SLEEP_0>;
595 qup_opp_table_100mhz: qup-100mhz-opp-table {
596 compatible = "operating-points-v2";
599 opp-hz = /bits/ 64 <75000000>;
600 required-opps = <&rpmhpd_opp_low_svs>;
604 opp-hz = /bits/ 64 <100000000>;
605 required-opps = <&rpmhpd_opp_svs>;
610 #address-cells = <2>;
614 reserved-region@80000000 {
615 reg = <0 0x80000000 0 0x860000>;
619 cmd_db: cmd-db-region@80860000 {
620 compatible = "qcom,cmd-db";
621 reg = <0 0x80860000 0 0x20000>;
625 reserved-region@80880000 {
626 reg = <0 0x80880000 0 0x80000>;
630 smem_mem: smem-region@80900000 {
631 compatible = "qcom,smem";
632 reg = <0 0x80900000 0 0x200000>;
634 hwlocks = <&tcsr_mutex 3>;
637 reserved-region@80b00000 {
638 reg = <0 0x80b00000 0 0x100000>;
642 reserved-region@83b00000 {
643 reg = <0 0x83b00000 0 0x1700000>;
647 reserved-region@85b00000 {
648 reg = <0 0x85b00000 0 0xc00000>;
652 pil_adsp_mem: adsp-region@86c00000 {
653 reg = <0 0x86c00000 0 0x2000000>;
657 pil_nsp0_mem: cdsp0-region@8a100000 {
658 reg = <0 0x8a100000 0 0x1e00000>;
662 pil_nsp1_mem: cdsp1-region@8c600000 {
663 reg = <0 0x8c600000 0 0x1e00000>;
667 reserved-region@aeb00000 {
668 reg = <0 0xaeb00000 0 0x16600000>;
674 compatible = "qcom,smp2p";
675 qcom,smem = <443>, <429>;
676 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
677 IPCC_MPROC_SIGNAL_SMP2P
678 IRQ_TYPE_EDGE_RISING>;
679 mboxes = <&ipcc IPCC_CLIENT_LPASS
680 IPCC_MPROC_SIGNAL_SMP2P>;
682 qcom,local-pid = <0>;
683 qcom,remote-pid = <2>;
685 smp2p_adsp_out: master-kernel {
686 qcom,entry-name = "master-kernel";
687 #qcom,smem-state-cells = <1>;
690 smp2p_adsp_in: slave-kernel {
691 qcom,entry-name = "slave-kernel";
692 interrupt-controller;
693 #interrupt-cells = <2>;
698 compatible = "qcom,smp2p";
699 qcom,smem = <94>, <432>;
700 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
701 IPCC_MPROC_SIGNAL_SMP2P
702 IRQ_TYPE_EDGE_RISING>;
703 mboxes = <&ipcc IPCC_CLIENT_CDSP
704 IPCC_MPROC_SIGNAL_SMP2P>;
706 qcom,local-pid = <0>;
707 qcom,remote-pid = <5>;
709 smp2p_nsp0_out: master-kernel {
710 qcom,entry-name = "master-kernel";
711 #qcom,smem-state-cells = <1>;
714 smp2p_nsp0_in: slave-kernel {
715 qcom,entry-name = "slave-kernel";
716 interrupt-controller;
717 #interrupt-cells = <2>;
722 compatible = "qcom,smp2p";
723 qcom,smem = <617>, <616>;
724 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
725 IPCC_MPROC_SIGNAL_SMP2P
726 IRQ_TYPE_EDGE_RISING>;
727 mboxes = <&ipcc IPCC_CLIENT_NSP1
728 IPCC_MPROC_SIGNAL_SMP2P>;
730 qcom,local-pid = <0>;
731 qcom,remote-pid = <12>;
733 smp2p_nsp1_out: master-kernel {
734 qcom,entry-name = "master-kernel";
735 #qcom,smem-state-cells = <1>;
738 smp2p_nsp1_in: slave-kernel {
739 qcom,entry-name = "slave-kernel";
740 interrupt-controller;
741 #interrupt-cells = <2>;
746 compatible = "simple-bus";
747 #address-cells = <2>;
749 ranges = <0 0 0 0 0x10 0>;
750 dma-ranges = <0 0 0 0 0x10 0>;
752 gcc: clock-controller@100000 {
753 compatible = "qcom,gcc-sc8280xp";
754 reg = <0x0 0x00100000 0x0 0x1f0000>;
757 #power-domain-cells = <1>;
758 clocks = <&rpmhcc RPMH_CXO_CLK>,
766 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
774 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
791 power-domains = <&rpmhpd SC8280XP_CX>;
794 ipcc: mailbox@408000 {
795 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
796 reg = <0 0x00408000 0 0x1000>;
797 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
798 interrupt-controller;
799 #interrupt-cells = <3>;
803 qup2: geniqup@8c0000 {
804 compatible = "qcom,geni-se-qup";
805 reg = <0 0x008c0000 0 0x2000>;
806 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
807 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
808 clock-names = "m-ahb", "s-ahb";
809 iommus = <&apps_smmu 0xa3 0>;
811 #address-cells = <2>;
817 qup2_uart17: serial@884000 {
818 compatible = "qcom,geni-uart";
819 reg = <0 0x00884000 0 0x4000>;
820 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
822 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
823 operating-points-v2 = <&qup_opp_table_100mhz>;
824 power-domains = <&rpmhpd SC8280XP_CX>;
825 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
826 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
827 interconnect-names = "qup-core", "qup-config";
831 qup2_i2c5: i2c@894000 {
832 compatible = "qcom,geni-i2c";
833 reg = <0 0x00894000 0 0x4000>;
835 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
836 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
837 #address-cells = <1>;
839 power-domains = <&rpmhpd SC8280XP_CX>;
840 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
841 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
842 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
843 interconnect-names = "qup-core", "qup-config", "qup-memory";
848 qup0: geniqup@9c0000 {
849 compatible = "qcom,geni-se-qup";
850 reg = <0 0x009c0000 0 0x6000>;
851 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
852 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
853 clock-names = "m-ahb", "s-ahb";
854 iommus = <&apps_smmu 0x563 0>;
856 #address-cells = <2>;
862 qup0_i2c4: i2c@990000 {
863 compatible = "qcom,geni-i2c";
864 reg = <0 0x00990000 0 0x4000>;
866 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
867 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
868 #address-cells = <1>;
870 power-domains = <&rpmhpd SC8280XP_CX>;
871 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
872 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
873 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
874 interconnect-names = "qup-core", "qup-config", "qup-memory";
879 qup1: geniqup@ac0000 {
880 compatible = "qcom,geni-se-qup";
881 reg = <0 0x00ac0000 0 0x6000>;
882 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
883 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
884 clock-names = "m-ahb", "s-ahb";
885 iommus = <&apps_smmu 0x83 0>;
887 #address-cells = <2>;
894 pcie4: pcie@1c00000 {
896 compatible = "qcom,pcie-sc8280xp";
897 reg = <0x0 0x01c00000 0x0 0x3000>,
898 <0x0 0x30000000 0x0 0xf1d>,
899 <0x0 0x30000f20 0x0 0xa8>,
900 <0x0 0x30001000 0x0 0x1000>,
901 <0x0 0x30100000 0x0 0x100000>;
902 reg-names = "parf", "dbi", "elbi", "atu", "config";
903 #address-cells = <3>;
905 ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
906 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
907 bus-range = <0x00 0xff>;
911 linux,pci-domain = <6>;
914 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
918 interrupt-names = "msi0", "msi1", "msi2", "msi3";
920 #interrupt-cells = <1>;
921 interrupt-map-mask = <0 0 0 0x7>;
922 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
923 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
924 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
925 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
928 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
929 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
930 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
931 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
932 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
933 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
934 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
935 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
946 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
947 assigned-clock-rates = <19200000>;
949 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
950 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
951 interconnect-names = "pcie-mem", "cpu-pcie";
953 resets = <&gcc GCC_PCIE_4_BCR>;
956 power-domains = <&gcc PCIE_4_GDSC>;
959 phy-names = "pciephy";
964 pcie4_phy: phy@1c06000 {
965 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
966 reg = <0x0 0x01c06000 0x0 0x2000>;
968 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
969 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
970 <&gcc GCC_PCIE_4_CLKREF_CLK>,
971 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
972 <&gcc GCC_PCIE_4_PIPE_CLK>,
973 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
974 clock-names = "aux", "cfg_ahb", "ref", "rchng",
977 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
978 assigned-clock-rates = <100000000>;
980 power-domains = <&gcc PCIE_4_GDSC>;
982 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
986 clock-output-names = "pcie_4_pipe_clk";
993 pcie3b: pcie@1c08000 {
995 compatible = "qcom,pcie-sc8280xp";
996 reg = <0x0 0x01c08000 0x0 0x3000>,
997 <0x0 0x32000000 0x0 0xf1d>,
998 <0x0 0x32000f20 0x0 0xa8>,
999 <0x0 0x32001000 0x0 0x1000>,
1000 <0x0 0x32100000 0x0 0x100000>;
1001 reg-names = "parf", "dbi", "elbi", "atu", "config";
1002 #address-cells = <3>;
1004 ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
1005 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1006 bus-range = <0x00 0xff>;
1010 linux,pci-domain = <5>;
1013 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1014 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1017 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1019 #interrupt-cells = <1>;
1020 interrupt-map-mask = <0 0 0 0x7>;
1021 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1022 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1023 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1024 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1027 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1028 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1029 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1030 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1031 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1032 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1033 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1034 clock-names = "aux",
1041 "noc_aggr_south_sf";
1043 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1044 assigned-clock-rates = <19200000>;
1046 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1047 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1048 interconnect-names = "pcie-mem", "cpu-pcie";
1050 resets = <&gcc GCC_PCIE_3B_BCR>;
1051 reset-names = "pci";
1053 power-domains = <&gcc PCIE_3B_GDSC>;
1055 phys = <&pcie3b_phy>;
1056 phy-names = "pciephy";
1058 status = "disabled";
1061 pcie3b_phy: phy@1c0e000 {
1062 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1063 reg = <0x0 0x01c0e000 0x0 0x2000>;
1065 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1066 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1067 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1068 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1069 <&gcc GCC_PCIE_3B_PIPE_CLK>,
1070 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1071 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1074 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1075 assigned-clock-rates = <100000000>;
1077 power-domains = <&gcc PCIE_3B_GDSC>;
1079 resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1080 reset-names = "phy";
1083 clock-output-names = "pcie_3b_pipe_clk";
1087 status = "disabled";
1090 pcie3a: pcie@1c10000 {
1091 device_type = "pci";
1092 compatible = "qcom,pcie-sc8280xp";
1093 reg = <0x0 0x01c10000 0x0 0x3000>,
1094 <0x0 0x34000000 0x0 0xf1d>,
1095 <0x0 0x34000f20 0x0 0xa8>,
1096 <0x0 0x34001000 0x0 0x1000>,
1097 <0x0 0x34100000 0x0 0x100000>;
1098 reg-names = "parf", "dbi", "elbi", "atu", "config";
1099 #address-cells = <3>;
1101 ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
1102 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1103 bus-range = <0x00 0xff>;
1107 linux,pci-domain = <4>;
1110 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1114 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1116 #interrupt-cells = <1>;
1117 interrupt-map-mask = <0 0 0 0x7>;
1118 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1119 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1120 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1121 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1123 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1124 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1125 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1126 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1127 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1128 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1129 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1130 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1131 clock-names = "aux",
1138 "noc_aggr_south_sf";
1140 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
1141 assigned-clock-rates = <19200000>;
1143 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
1144 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
1145 interconnect-names = "pcie-mem", "cpu-pcie";
1147 resets = <&gcc GCC_PCIE_3A_BCR>;
1148 reset-names = "pci";
1150 power-domains = <&gcc PCIE_3A_GDSC>;
1152 phys = <&pcie3a_phy>;
1153 phy-names = "pciephy";
1155 status = "disabled";
1158 pcie3a_phy: phy@1c14000 {
1159 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1160 reg = <0x0 0x01c14000 0x0 0x2000>,
1161 <0x0 0x01c16000 0x0 0x2000>;
1163 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1164 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1165 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1166 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
1167 <&gcc GCC_PCIE_3A_PIPE_CLK>,
1168 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
1169 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1172 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
1173 assigned-clock-rates = <100000000>;
1175 power-domains = <&gcc PCIE_3A_GDSC>;
1177 resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
1178 reset-names = "phy";
1180 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
1183 clock-output-names = "pcie_3a_pipe_clk";
1187 status = "disabled";
1190 pcie2b: pcie@1c18000 {
1191 device_type = "pci";
1192 compatible = "qcom,pcie-sc8280xp";
1193 reg = <0x0 0x01c18000 0x0 0x3000>,
1194 <0x0 0x38000000 0x0 0xf1d>,
1195 <0x0 0x38000f20 0x0 0xa8>,
1196 <0x0 0x38001000 0x0 0x1000>,
1197 <0x0 0x38100000 0x0 0x100000>;
1198 reg-names = "parf", "dbi", "elbi", "atu", "config";
1199 #address-cells = <3>;
1201 ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
1202 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
1203 bus-range = <0x00 0xff>;
1207 linux,pci-domain = <3>;
1210 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1212 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1213 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
1214 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1216 #interrupt-cells = <1>;
1217 interrupt-map-mask = <0 0 0 0x7>;
1218 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
1219 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
1220 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
1221 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
1224 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
1225 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
1226 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
1227 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
1228 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1229 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1230 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1231 clock-names = "aux",
1238 "noc_aggr_south_sf";
1240 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
1241 assigned-clock-rates = <19200000>;
1243 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
1244 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
1245 interconnect-names = "pcie-mem", "cpu-pcie";
1247 resets = <&gcc GCC_PCIE_2B_BCR>;
1248 reset-names = "pci";
1250 power-domains = <&gcc PCIE_2B_GDSC>;
1252 phys = <&pcie2b_phy>;
1253 phy-names = "pciephy";
1255 status = "disabled";
1258 pcie2b_phy: phy@1c1e000 {
1259 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1260 reg = <0x0 0x01c1e000 0x0 0x2000>;
1262 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
1263 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
1264 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
1265 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
1266 <&gcc GCC_PCIE_2B_PIPE_CLK>,
1267 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
1268 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1271 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
1272 assigned-clock-rates = <100000000>;
1274 power-domains = <&gcc PCIE_2B_GDSC>;
1276 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
1277 reset-names = "phy";
1280 clock-output-names = "pcie_2b_pipe_clk";
1284 status = "disabled";
1287 pcie2a: pcie@1c20000 {
1288 device_type = "pci";
1289 compatible = "qcom,pcie-sc8280xp";
1290 reg = <0x0 0x01c20000 0x0 0x3000>,
1291 <0x0 0x3c000000 0x0 0xf1d>,
1292 <0x0 0x3c000f20 0x0 0xa8>,
1293 <0x0 0x3c001000 0x0 0x1000>,
1294 <0x0 0x3c100000 0x0 0x100000>;
1295 reg-names = "parf", "dbi", "elbi", "atu", "config";
1296 #address-cells = <3>;
1298 ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
1299 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
1300 bus-range = <0x00 0xff>;
1304 linux,pci-domain = <2>;
1307 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
1308 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
1309 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
1310 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
1311 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1313 #interrupt-cells = <1>;
1314 interrupt-map-mask = <0 0 0 0x7>;
1315 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
1316 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
1317 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
1318 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
1320 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
1321 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
1322 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
1323 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
1324 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
1325 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1326 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1327 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1328 clock-names = "aux",
1335 "noc_aggr_south_sf";
1337 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
1338 assigned-clock-rates = <19200000>;
1340 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
1341 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
1342 interconnect-names = "pcie-mem", "cpu-pcie";
1344 resets = <&gcc GCC_PCIE_2A_BCR>;
1345 reset-names = "pci";
1347 power-domains = <&gcc PCIE_2A_GDSC>;
1349 phys = <&pcie2a_phy>;
1350 phy-names = "pciephy";
1352 status = "disabled";
1355 pcie2a_phy: phy@1c24000 {
1356 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1357 reg = <0x0 0x01c24000 0x0 0x2000>,
1358 <0x0 0x01c26000 0x0 0x2000>;
1360 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
1361 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
1362 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
1363 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
1364 <&gcc GCC_PCIE_2A_PIPE_CLK>,
1365 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
1366 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1369 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
1370 assigned-clock-rates = <100000000>;
1372 power-domains = <&gcc PCIE_2A_GDSC>;
1374 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
1375 reset-names = "phy";
1377 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
1380 clock-output-names = "pcie_2a_pipe_clk";
1384 status = "disabled";
1387 ufs_mem_hc: ufs@1d84000 {
1388 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
1390 reg = <0 0x01d84000 0 0x3000>;
1391 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1392 phys = <&ufs_mem_phy>;
1393 phy-names = "ufsphy";
1394 lanes-per-direction = <2>;
1396 resets = <&gcc GCC_UFS_PHY_BCR>;
1397 reset-names = "rst";
1399 power-domains = <&gcc UFS_PHY_GDSC>;
1400 required-opps = <&rpmhpd_opp_nom>;
1402 iommus = <&apps_smmu 0xe0 0x0>;
1405 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1406 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1407 <&gcc GCC_UFS_PHY_AHB_CLK>,
1408 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1409 <&gcc GCC_UFS_REF_CLKREF_CLK>,
1410 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1411 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1412 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1413 clock-names = "core_clk",
1418 "tx_lane0_sync_clk",
1419 "rx_lane0_sync_clk",
1420 "rx_lane1_sync_clk";
1421 freq-table-hz = <75000000 300000000>,
1424 <75000000 300000000>,
1429 status = "disabled";
1432 ufs_mem_phy: phy@1d87000 {
1433 compatible = "qcom,sc8280xp-qmp-ufs-phy";
1434 reg = <0 0x01d87000 0 0x1000>;
1436 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
1437 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1438 clock-names = "ref", "ref_aux";
1440 power-domains = <&gcc UFS_PHY_GDSC>;
1442 resets = <&ufs_mem_hc 0>;
1443 reset-names = "ufsphy";
1447 status = "disabled";
1450 ufs_card_hc: ufs@1da4000 {
1451 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
1453 reg = <0 0x01da4000 0 0x3000>;
1454 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1455 phys = <&ufs_card_phy>;
1456 phy-names = "ufsphy";
1457 lanes-per-direction = <2>;
1459 resets = <&gcc GCC_UFS_CARD_BCR>;
1460 reset-names = "rst";
1462 power-domains = <&gcc UFS_CARD_GDSC>;
1464 iommus = <&apps_smmu 0x4a0 0x0>;
1467 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
1468 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
1469 <&gcc GCC_UFS_CARD_AHB_CLK>,
1470 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
1471 <&gcc GCC_UFS_REF_CLKREF_CLK>,
1472 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
1473 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
1474 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
1475 clock-names = "core_clk",
1480 "tx_lane0_sync_clk",
1481 "rx_lane0_sync_clk",
1482 "rx_lane1_sync_clk";
1483 freq-table-hz = <75000000 300000000>,
1486 <75000000 300000000>,
1491 status = "disabled";
1494 ufs_card_phy: phy@1da7000 {
1495 compatible = "qcom,sc8280xp-qmp-ufs-phy";
1496 reg = <0 0x01da7000 0 0x1000>;
1498 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
1499 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
1500 clock-names = "ref", "ref_aux";
1502 power-domains = <&gcc UFS_CARD_GDSC>;
1504 resets = <&ufs_card_hc 0>;
1505 reset-names = "ufsphy";
1509 status = "disabled";
1512 tcsr_mutex: hwlock@1f40000 {
1513 compatible = "qcom,tcsr-mutex";
1514 reg = <0x0 0x01f40000 0x0 0x20000>;
1515 #hwlock-cells = <1>;
1518 tcsr: syscon@1fc0000 {
1519 compatible = "qcom,sc8280xp-tcsr", "syscon";
1520 reg = <0x0 0x01fc0000 0x0 0x30000>;
1523 usb_0_hsphy: phy@88e5000 {
1524 compatible = "qcom,sc8280xp-usb-hs-phy",
1525 "qcom,usb-snps-hs-5nm-phy";
1526 reg = <0 0x088e5000 0 0x400>;
1527 clocks = <&rpmhcc RPMH_CXO_CLK>;
1528 clock-names = "ref";
1529 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1533 status = "disabled";
1536 usb_2_hsphy0: phy@88e7000 {
1537 compatible = "qcom,sc8280xp-usb-hs-phy",
1538 "qcom,usb-snps-hs-5nm-phy";
1539 reg = <0 0x088e7000 0 0x400>;
1540 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
1541 clock-names = "ref";
1542 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
1546 status = "disabled";
1549 usb_2_hsphy1: phy@88e8000 {
1550 compatible = "qcom,sc8280xp-usb-hs-phy",
1551 "qcom,usb-snps-hs-5nm-phy";
1552 reg = <0 0x088e8000 0 0x400>;
1553 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
1554 clock-names = "ref";
1555 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
1559 status = "disabled";
1562 usb_2_hsphy2: phy@88e9000 {
1563 compatible = "qcom,sc8280xp-usb-hs-phy",
1564 "qcom,usb-snps-hs-5nm-phy";
1565 reg = <0 0x088e9000 0 0x400>;
1566 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
1567 clock-names = "ref";
1568 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
1572 status = "disabled";
1575 usb_2_hsphy3: phy@88ea000 {
1576 compatible = "qcom,sc8280xp-usb-hs-phy",
1577 "qcom,usb-snps-hs-5nm-phy";
1578 reg = <0 0x088ea000 0 0x400>;
1579 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
1580 clock-names = "ref";
1581 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
1585 status = "disabled";
1588 usb_2_qmpphy0: phy@88ef000 {
1589 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1590 reg = <0 0x088ef000 0 0x2000>;
1592 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1593 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
1594 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
1595 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
1596 clock-names = "aux", "ref", "com_aux", "pipe";
1598 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
1599 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
1600 reset-names = "phy", "phy_phy";
1602 power-domains = <&gcc USB30_MP_GDSC>;
1605 clock-output-names = "usb2_phy0_pipe_clk";
1609 status = "disabled";
1612 usb_2_qmpphy1: phy@88f1000 {
1613 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1614 reg = <0 0x088f1000 0 0x2000>;
1616 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1617 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
1618 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
1619 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
1620 clock-names = "aux", "ref", "com_aux", "pipe";
1622 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
1623 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
1624 reset-names = "phy", "phy_phy";
1626 power-domains = <&gcc USB30_MP_GDSC>;
1629 clock-output-names = "usb2_phy1_pipe_clk";
1633 status = "disabled";
1636 remoteproc_adsp: remoteproc@3000000 {
1637 compatible = "qcom,sc8280xp-adsp-pas";
1638 reg = <0 0x03000000 0 0x100>;
1640 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1641 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1642 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1643 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1644 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
1645 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
1646 interrupt-names = "wdog", "fatal", "ready",
1647 "handover", "stop-ack", "shutdown-ack";
1649 clocks = <&rpmhcc RPMH_CXO_CLK>;
1652 power-domains = <&rpmhpd SC8280XP_LCX>,
1653 <&rpmhpd SC8280XP_LMX>;
1654 power-domain-names = "lcx", "lmx";
1656 memory-region = <&pil_adsp_mem>;
1658 qcom,qmp = <&aoss_qmp>;
1660 qcom,smem-states = <&smp2p_adsp_out 0>;
1661 qcom,smem-state-names = "stop";
1663 status = "disabled";
1665 remoteproc_adsp_glink: glink-edge {
1666 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1667 IPCC_MPROC_SIGNAL_GLINK_QMP
1668 IRQ_TYPE_EDGE_RISING>;
1669 mboxes = <&ipcc IPCC_CLIENT_LPASS
1670 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1673 qcom,remote-pid = <2>;
1677 usb_0_qmpphy: phy@88eb000 {
1678 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1679 reg = <0 0x088eb000 0 0x4000>;
1681 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1682 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
1683 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
1684 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1685 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1687 power-domains = <&gcc USB30_PRIM_GDSC>;
1689 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1690 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
1691 reset-names = "phy", "common";
1696 status = "disabled";
1699 usb_1_hsphy: phy@8902000 {
1700 compatible = "qcom,sc8280xp-usb-hs-phy",
1701 "qcom,usb-snps-hs-5nm-phy";
1702 reg = <0 0x08902000 0 0x400>;
1705 clocks = <&rpmhcc RPMH_CXO_CLK>;
1706 clock-names = "ref";
1708 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1710 status = "disabled";
1713 usb_1_qmpphy: phy@8903000 {
1714 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1715 reg = <0 0x08903000 0 0x4000>;
1717 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1718 <&gcc GCC_USB4_CLKREF_CLK>,
1719 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
1720 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1721 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1723 power-domains = <&gcc USB30_SEC_GDSC>;
1725 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1726 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
1727 reset-names = "phy", "common";
1732 status = "disabled";
1736 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
1737 reg = <0 0x9091000 0 0x1000>;
1739 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1741 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
1743 operating-points-v2 = <&llcc_bwmon_opp_table>;
1745 llcc_bwmon_opp_table: opp-table {
1746 compatible = "operating-points-v2";
1749 opp-peak-kBps = <762000>;
1752 opp-peak-kBps = <1720000>;
1755 opp-peak-kBps = <2086000>;
1758 opp-peak-kBps = <2597000>;
1761 opp-peak-kBps = <2929000>;
1764 opp-peak-kBps = <3879000>;
1767 opp-peak-kBps = <5161000>;
1770 opp-peak-kBps = <5931000>;
1773 opp-peak-kBps = <6515000>;
1776 opp-peak-kBps = <7980000>;
1779 opp-peak-kBps = <8136000>;
1782 opp-peak-kBps = <10437000>;
1785 opp-peak-kBps = <12191000>;
1791 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
1792 reg = <0 0x090b6400 0 0x600>;
1794 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
1796 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
1797 operating-points-v2 = <&cpu_bwmon_opp_table>;
1799 cpu_bwmon_opp_table: opp-table {
1800 compatible = "operating-points-v2";
1803 opp-peak-kBps = <2288000>;
1806 opp-peak-kBps = <4577000>;
1809 opp-peak-kBps = <7110000>;
1812 opp-peak-kBps = <9155000>;
1815 opp-peak-kBps = <12298000>;
1818 opp-peak-kBps = <14236000>;
1821 opp-peak-kBps = <15258001>;
1826 system-cache-controller@9200000 {
1827 compatible = "qcom,sc8280xp-llcc";
1828 reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
1829 reg-names = "llcc_base", "llcc_broadcast_base";
1830 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1833 usb_0: usb@a6f8800 {
1834 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1835 reg = <0 0x0a6f8800 0 0x400>;
1836 #address-cells = <2>;
1840 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1841 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1842 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1843 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1844 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1845 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1846 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1847 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1848 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1849 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1850 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1852 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1853 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1854 assigned-clock-rates = <19200000>, <200000000>;
1856 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
1857 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1858 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1859 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
1860 interrupt-names = "pwr_event",
1865 power-domains = <&gcc USB30_PRIM_GDSC>;
1867 resets = <&gcc GCC_USB30_PRIM_BCR>;
1869 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1870 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
1871 interconnect-names = "usb-ddr", "apps-usb";
1875 status = "disabled";
1877 usb_0_dwc3: usb@a600000 {
1878 compatible = "snps,dwc3";
1879 reg = <0 0x0a600000 0 0xcd00>;
1880 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1881 iommus = <&apps_smmu 0x820 0x0>;
1882 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
1883 phy-names = "usb2-phy", "usb3-phy";
1887 usb_1: usb@a8f8800 {
1888 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1889 reg = <0 0x0a8f8800 0 0x400>;
1890 #address-cells = <2>;
1894 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1895 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1896 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1897 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1898 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1899 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1900 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1901 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1902 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1903 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1904 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1906 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1907 <&gcc GCC_USB30_SEC_MASTER_CLK>;
1908 assigned-clock-rates = <19200000>, <200000000>;
1910 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
1911 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1912 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1913 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
1914 interrupt-names = "pwr_event",
1919 power-domains = <&gcc USB30_SEC_GDSC>;
1921 resets = <&gcc GCC_USB30_SEC_BCR>;
1923 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
1924 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
1925 interconnect-names = "usb-ddr", "apps-usb";
1929 status = "disabled";
1931 usb_1_dwc3: usb@a800000 {
1932 compatible = "snps,dwc3";
1933 reg = <0 0x0a800000 0 0xcd00>;
1934 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
1935 iommus = <&apps_smmu 0x860 0x0>;
1936 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
1937 phy-names = "usb2-phy", "usb3-phy";
1941 pdc: interrupt-controller@b220000 {
1942 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
1943 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1944 qcom,pdc-ranges = <0 480 40>,
2001 #interrupt-cells = <2>;
2002 interrupt-parent = <&intc>;
2003 interrupt-controller;
2006 tsens0: thermal-sensor@c263000 {
2007 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
2008 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2009 <0 0x0c222000 0 0x8>; /* SROT */
2010 #qcom,sensors = <14>;
2011 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2012 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2013 interrupt-names = "uplow", "critical";
2014 #thermal-sensor-cells = <1>;
2017 tsens1: thermal-sensor@c265000 {
2018 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
2019 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2020 <0 0x0c223000 0 0x8>; /* SROT */
2021 #qcom,sensors = <16>;
2022 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2023 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2024 interrupt-names = "uplow", "critical";
2025 #thermal-sensor-cells = <1>;
2028 aoss_qmp: power-controller@c300000 {
2029 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
2030 reg = <0 0x0c300000 0 0x400>;
2031 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
2032 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2038 compatible = "qcom,rpmh-stats";
2039 reg = <0 0x0c3f0000 0 0x400>;
2042 spmi_bus: spmi@c440000 {
2043 compatible = "qcom,spmi-pmic-arb";
2044 reg = <0 0x0c440000 0 0x1100>,
2045 <0 0x0c600000 0 0x2000000>,
2046 <0 0x0e600000 0 0x100000>,
2047 <0 0x0e700000 0 0xa0000>,
2048 <0 0x0c40a000 0 0x26000>;
2049 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2050 interrupt-names = "periph_irq";
2051 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2054 #address-cells = <1>;
2056 interrupt-controller;
2057 #interrupt-cells = <4>;
2060 tlmm: pinctrl@f100000 {
2061 compatible = "qcom,sc8280xp-tlmm";
2062 reg = <0 0x0f100000 0 0x300000>;
2063 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2066 interrupt-controller;
2067 #interrupt-cells = <2>;
2068 gpio-ranges = <&tlmm 0 0 230>;
2071 apps_smmu: iommu@15000000 {
2072 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
2073 reg = <0 0x15000000 0 0x100000>;
2075 #global-interrupts = <2>;
2076 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
2077 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2078 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2079 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2080 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2081 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2082 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2083 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2084 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2085 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2086 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2087 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2088 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2089 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2090 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2091 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2092 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2093 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2094 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2095 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2096 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2098 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2099 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2100 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2101 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2102 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2103 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2104 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2105 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2106 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2107 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2108 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2109 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2110 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2111 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2112 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2113 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2114 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2115 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2116 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2117 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2118 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2119 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2120 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2121 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2122 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2123 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2124 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2125 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2126 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2127 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2128 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2129 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2130 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2131 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2132 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2133 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2134 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2135 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2136 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2137 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2138 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2139 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2140 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2141 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2142 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2143 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2144 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2145 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2146 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2147 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2153 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2154 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2155 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2156 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
2157 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2159 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2160 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
2161 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2162 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2163 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2164 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2165 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2166 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2167 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2168 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2169 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
2170 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2171 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2172 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2173 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
2174 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
2175 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
2176 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
2177 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
2178 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2179 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
2180 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
2181 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
2182 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
2183 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
2184 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
2185 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
2186 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
2187 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
2188 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
2189 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
2190 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
2191 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
2192 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
2193 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
2194 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
2195 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
2196 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
2197 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
2198 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
2199 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
2200 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
2201 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
2202 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
2203 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
2204 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
2205 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
2208 intc: interrupt-controller@17a00000 {
2209 compatible = "arm,gic-v3";
2210 interrupt-controller;
2211 #interrupt-cells = <3>;
2212 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2213 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2214 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2215 #redistributor-regions = <1>;
2216 redistributor-stride = <0 0x20000>;
2218 #address-cells = <2>;
2223 compatible = "arm,gic-v3-its";
2224 reg = <0 0x17a40000 0 0x20000>;
2231 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
2232 reg = <0 0x17c10000 0 0x1000>;
2233 clocks = <&sleep_clk>;
2234 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2238 compatible = "arm,armv7-timer-mem";
2239 reg = <0x0 0x17c20000 0x0 0x1000>;
2240 #address-cells = <1>;
2242 ranges = <0x0 0x0 0x0 0x20000000>;
2246 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2248 reg = <0x17c21000 0x1000>,
2249 <0x17c22000 0x1000>;
2254 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2255 reg = <0x17c23000 0x1000>;
2256 status = "disabled";
2261 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2262 reg = <0x17c25000 0x1000>;
2263 status = "disabled";
2268 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2269 reg = <0x17c26000 0x1000>;
2270 status = "disabled";
2275 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2276 reg = <0x17c29000 0x1000>;
2277 status = "disabled";
2282 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2283 reg = <0x17c2b000 0x1000>;
2284 status = "disabled";
2289 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2290 reg = <0x17c2d000 0x1000>;
2291 status = "disabled";
2295 apps_rsc: rsc@18200000 {
2296 compatible = "qcom,rpmh-rsc";
2297 reg = <0x0 0x18200000 0x0 0x10000>,
2298 <0x0 0x18210000 0x0 0x10000>,
2299 <0x0 0x18220000 0x0 0x10000>;
2300 reg-names = "drv-0", "drv-1", "drv-2";
2301 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2302 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2303 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2304 qcom,tcs-offset = <0xd00>;
2306 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2307 <WAKE_TCS 3>, <CONTROL_TCS 1>;
2310 apps_bcm_voter: bcm-voter {
2311 compatible = "qcom,bcm-voter";
2314 rpmhcc: clock-controller {
2315 compatible = "qcom,sc8280xp-rpmh-clk";
2318 clocks = <&xo_board_clk>;
2321 rpmhpd: power-controller {
2322 compatible = "qcom,sc8280xp-rpmhpd";
2323 #power-domain-cells = <1>;
2324 operating-points-v2 = <&rpmhpd_opp_table>;
2326 rpmhpd_opp_table: opp-table {
2327 compatible = "operating-points-v2";
2329 rpmhpd_opp_ret: opp1 {
2330 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2333 rpmhpd_opp_min_svs: opp2 {
2334 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2337 rpmhpd_opp_low_svs: opp3 {
2338 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2341 rpmhpd_opp_svs: opp4 {
2342 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2345 rpmhpd_opp_svs_l1: opp5 {
2346 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2349 rpmhpd_opp_nom: opp6 {
2350 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2353 rpmhpd_opp_nom_l1: opp7 {
2354 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2357 rpmhpd_opp_nom_l2: opp8 {
2358 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2361 rpmhpd_opp_turbo: opp9 {
2362 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2365 rpmhpd_opp_turbo_l1: opp10 {
2366 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2372 epss_l3: interconnect@18590000 {
2373 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
2374 reg = <0 0x18590000 0 0x1000>;
2376 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2377 clock-names = "xo", "alternate";
2379 #interconnect-cells = <1>;
2382 cpufreq_hw: cpufreq@18591000 {
2383 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
2384 reg = <0 0x18591000 0 0x1000>,
2385 <0 0x18592000 0 0x1000>;
2386 reg-names = "freq-domain0", "freq-domain1";
2388 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2389 clock-names = "xo", "alternate";
2391 #freq-domain-cells = <1>;
2394 remoteproc_nsp0: remoteproc@1b300000 {
2395 compatible = "qcom,sc8280xp-nsp0-pas";
2396 reg = <0 0x1b300000 0 0x100>;
2398 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2399 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
2400 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
2401 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
2402 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
2403 interrupt-names = "wdog", "fatal", "ready",
2404 "handover", "stop-ack";
2406 clocks = <&rpmhcc RPMH_CXO_CLK>;
2409 power-domains = <&rpmhpd SC8280XP_NSP>;
2410 power-domain-names = "nsp";
2412 memory-region = <&pil_nsp0_mem>;
2414 qcom,smem-states = <&smp2p_nsp0_out 0>;
2415 qcom,smem-state-names = "stop";
2417 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
2419 status = "disabled";
2422 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2423 IPCC_MPROC_SIGNAL_GLINK_QMP
2424 IRQ_TYPE_EDGE_RISING>;
2425 mboxes = <&ipcc IPCC_CLIENT_CDSP
2426 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2429 qcom,remote-pid = <5>;
2432 compatible = "qcom,fastrpc";
2433 qcom,glink-channels = "fastrpcglink-apps-dsp";
2435 #address-cells = <1>;
2439 compatible = "qcom,fastrpc-compute-cb";
2441 iommus = <&apps_smmu 0x3181 0x0420>;
2445 compatible = "qcom,fastrpc-compute-cb";
2447 iommus = <&apps_smmu 0x3182 0x0420>;
2451 compatible = "qcom,fastrpc-compute-cb";
2453 iommus = <&apps_smmu 0x3183 0x0420>;
2457 compatible = "qcom,fastrpc-compute-cb";
2459 iommus = <&apps_smmu 0x3184 0x0420>;
2463 compatible = "qcom,fastrpc-compute-cb";
2465 iommus = <&apps_smmu 0x3185 0x0420>;
2469 compatible = "qcom,fastrpc-compute-cb";
2471 iommus = <&apps_smmu 0x3186 0x0420>;
2475 compatible = "qcom,fastrpc-compute-cb";
2477 iommus = <&apps_smmu 0x3187 0x0420>;
2481 compatible = "qcom,fastrpc-compute-cb";
2483 iommus = <&apps_smmu 0x3188 0x0420>;
2487 compatible = "qcom,fastrpc-compute-cb";
2489 iommus = <&apps_smmu 0x318b 0x0420>;
2493 compatible = "qcom,fastrpc-compute-cb";
2495 iommus = <&apps_smmu 0x318b 0x0420>;
2499 compatible = "qcom,fastrpc-compute-cb";
2501 iommus = <&apps_smmu 0x318c 0x0420>;
2505 compatible = "qcom,fastrpc-compute-cb";
2507 iommus = <&apps_smmu 0x318d 0x0420>;
2511 compatible = "qcom,fastrpc-compute-cb";
2513 iommus = <&apps_smmu 0x318e 0x0420>;
2517 compatible = "qcom,fastrpc-compute-cb";
2519 iommus = <&apps_smmu 0x318f 0x0420>;
2525 remoteproc_nsp1: remoteproc@21300000 {
2526 compatible = "qcom,sc8280xp-nsp1-pas";
2527 reg = <0 0x21300000 0 0x100>;
2529 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
2530 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
2531 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
2532 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
2533 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
2534 interrupt-names = "wdog", "fatal", "ready",
2535 "handover", "stop-ack";
2537 clocks = <&rpmhcc RPMH_CXO_CLK>;
2540 power-domains = <&rpmhpd SC8280XP_NSP>;
2541 power-domain-names = "nsp";
2543 memory-region = <&pil_nsp1_mem>;
2545 qcom,smem-states = <&smp2p_nsp1_out 0>;
2546 qcom,smem-state-names = "stop";
2548 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
2550 status = "disabled";
2553 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
2554 IPCC_MPROC_SIGNAL_GLINK_QMP
2555 IRQ_TYPE_EDGE_RISING>;
2556 mboxes = <&ipcc IPCC_CLIENT_NSP1
2557 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2560 qcom,remote-pid = <12>;
2567 polling-delay-passive = <250>;
2568 polling-delay = <1000>;
2570 thermal-sensors = <&tsens0 1>;
2574 temperature = <110000>;
2575 hysteresis = <1000>;
2582 polling-delay-passive = <250>;
2583 polling-delay = <1000>;
2585 thermal-sensors = <&tsens0 2>;
2589 temperature = <110000>;
2590 hysteresis = <1000>;
2597 polling-delay-passive = <250>;
2598 polling-delay = <1000>;
2600 thermal-sensors = <&tsens0 3>;
2604 temperature = <110000>;
2605 hysteresis = <1000>;
2612 polling-delay-passive = <250>;
2613 polling-delay = <1000>;
2615 thermal-sensors = <&tsens0 4>;
2619 temperature = <110000>;
2620 hysteresis = <1000>;
2627 polling-delay-passive = <250>;
2628 polling-delay = <1000>;
2630 thermal-sensors = <&tsens0 5>;
2634 temperature = <110000>;
2635 hysteresis = <1000>;
2642 polling-delay-passive = <250>;
2643 polling-delay = <1000>;
2645 thermal-sensors = <&tsens0 6>;
2649 temperature = <110000>;
2650 hysteresis = <1000>;
2657 polling-delay-passive = <250>;
2658 polling-delay = <1000>;
2660 thermal-sensors = <&tsens0 7>;
2664 temperature = <110000>;
2665 hysteresis = <1000>;
2672 polling-delay-passive = <250>;
2673 polling-delay = <1000>;
2675 thermal-sensors = <&tsens0 8>;
2679 temperature = <110000>;
2680 hysteresis = <1000>;
2687 polling-delay-passive = <250>;
2688 polling-delay = <1000>;
2690 thermal-sensors = <&tsens0 9>;
2694 temperature = <110000>;
2695 hysteresis = <1000>;
2702 polling-delay-passive = <250>;
2703 polling-delay = <1000>;
2705 thermal-sensors = <&tsens1 15>;
2709 temperature = <90000>;
2710 hysteresis = <2000>;
2718 compatible = "arm,armv8-timer";
2719 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2720 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2721 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2722 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;