arch/arm64/boot/dts/qcom/sc7280.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * sc7280 SoC device tree source
   4  *
   5  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   6  */
   7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
   8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
  11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
  12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
  13 #include <dt-bindings/clock/qcom,rpmh.h>
  14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
  15 #include <dt-bindings/dma/qcom-gpi.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  18 #include <dt-bindings/interconnect/qcom,sc7280.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/mailbox/qcom-ipcc.h>
  21 #include <dt-bindings/power/qcom-rpmpd.h>
  22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  25 #include <dt-bindings/sound/qcom,lpass.h>
  26 #include <dt-bindings/thermal/thermal.h>
  27
  28 / {
  29         interrupt-parent = <&intc>;
  30
  31         #address-cells = <2>;
  32         #size-cells = <2>;
  33
  34         chosen { };
  35
  36         aliases {
  37                 i2c0 = &i2c0;
  38                 i2c1 = &i2c1;
  39                 i2c2 = &i2c2;
  40                 i2c3 = &i2c3;
  41                 i2c4 = &i2c4;
  42                 i2c5 = &i2c5;
  43                 i2c6 = &i2c6;
  44                 i2c7 = &i2c7;
  45                 i2c8 = &i2c8;
  46                 i2c9 = &i2c9;
  47                 i2c10 = &i2c10;
  48                 i2c11 = &i2c11;
  49                 i2c12 = &i2c12;
  50                 i2c13 = &i2c13;
  51                 i2c14 = &i2c14;
  52                 i2c15 = &i2c15;
  53                 mmc1 = &sdhc_1;
  54                 mmc2 = &sdhc_2;
  55                 spi0 = &spi0;
  56                 spi1 = &spi1;
  57                 spi2 = &spi2;
  58                 spi3 = &spi3;
  59                 spi4 = &spi4;
  60                 spi5 = &spi5;
  61                 spi6 = &spi6;
  62                 spi7 = &spi7;
  63                 spi8 = &spi8;
  64                 spi9 = &spi9;
  65                 spi10 = &spi10;
  66                 spi11 = &spi11;
  67                 spi12 = &spi12;
  68                 spi13 = &spi13;
  69                 spi14 = &spi14;
  70                 spi15 = &spi15;
  71         };
  72
  73         clocks {
  74                 xo_board: xo-board {
  75                         compatible = "fixed-clock";
  76                         clock-frequency = <76800000>;
  77                         #clock-cells = <0>;
  78                 };
  79
  80                 sleep_clk: sleep-clk {
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <32000>;
  83                         #clock-cells = <0>;
  84                 };
  85         };
  86
  87         reserved-memory {
  88                 #address-cells = <2>;
  89                 #size-cells = <2>;
  90                 ranges;
  91
  92                 wlan_ce_mem: memory@4cd000 {
  93                         no-map;
  94                         reg = <0x0 0x004cd000 0x0 0x1000>;
  95                 };
  96
  97                 hyp_mem: memory@80000000 {
  98                         reg = <0x0 0x80000000 0x0 0x600000>;
  99                         no-map;
 100                 };
 101
 102                 xbl_mem: memory@80600000 {
 103                         reg = <0x0 0x80600000 0x0 0x200000>;
 104                         no-map;
 105                 };
 106
 107                 aop_mem: memory@80800000 {
 108                         reg = <0x0 0x80800000 0x0 0x60000>;
 109                         no-map;
 110                 };
 111
 112                 aop_cmd_db_mem: memory@80860000 {
 113                         reg = <0x0 0x80860000 0x0 0x20000>;
 114                         compatible = "qcom,cmd-db";
 115                         no-map;
 116                 };
 117
 118                 reserved_xbl_uefi_log: memory@80880000 {
 119                         reg = <0x0 0x80884000 0x0 0x10000>;
 120                         no-map;
 121                 };
 122
 123                 sec_apps_mem: memory@808ff000 {
 124                         reg = <0x0 0x808ff000 0x0 0x1000>;
 125                         no-map;
 126                 };
 127
 128                 smem_mem: memory@80900000 {
 129                         reg = <0x0 0x80900000 0x0 0x200000>;
 130                         no-map;
 131                 };
 132
 133                 cpucp_mem: memory@80b00000 {
 134                         no-map;
 135                         reg = <0x0 0x80b00000 0x0 0x100000>;
 136                 };
 137
 138                 wlan_fw_mem: memory@80c00000 {
 139                         reg = <0x0 0x80c00000 0x0 0xc00000>;
 140                         no-map;
 141                 };
 142
 143                 video_mem: memory@8b200000 {
 144                         reg = <0x0 0x8b200000 0x0 0x500000>;
 145                         no-map;
 146                 };
 147
 148                 ipa_fw_mem: memory@8b700000 {
 149                         reg = <0 0x8b700000 0 0x10000>;
 150                         no-map;
 151                 };
 152
 153                 rmtfs_mem: memory@9c900000 {
 154                         compatible = "qcom,rmtfs-mem";
 155                         reg = <0x0 0x9c900000 0x0 0x280000>;
 156                         no-map;
 157
 158                         qcom,client-id = <1>;
 159                         qcom,vmid = <15>;
 160                 };
 161         };
 162
 163         cpus {
 164                 #address-cells = <2>;
 165                 #size-cells = <0>;
 166
 167                 CPU0: cpu@0 {
 168                         device_type = "cpu";
 169                         compatible = "qcom,kryo";
 170                         reg = <0x0 0x0>;
 171                         enable-method = "psci";
 172                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 173                                            &LITTLE_CPU_SLEEP_1
 174                                            &CLUSTER_SLEEP_0>;
 175                         next-level-cache = <&L2_0>;
 176                         operating-points-v2 = <&cpu0_opp_table>;
 177                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 178                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 179                         qcom,freq-domain = <&cpufreq_hw 0>;
 180                         #cooling-cells = <2>;
 181                         L2_0: l2-cache {
 182                                 compatible = "cache";
 183                                 cache-level = <2>;
 184                                 next-level-cache = <&L3_0>;
 185                                 L3_0: l3-cache {
 186                                         compatible = "cache";
 187                                         cache-level = <3>;
 188                                 };
 189                         };
 190                 };
 191
 192                 CPU1: cpu@100 {
 193                         device_type = "cpu";
 194                         compatible = "qcom,kryo";
 195                         reg = <0x0 0x100>;
 196                         enable-method = "psci";
 197                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 198                                            &LITTLE_CPU_SLEEP_1
 199                                            &CLUSTER_SLEEP_0>;
 200                         next-level-cache = <&L2_100>;
 201                         operating-points-v2 = <&cpu0_opp_table>;
 202                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 203                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 204                         qcom,freq-domain = <&cpufreq_hw 0>;
 205                         #cooling-cells = <2>;
 206                         L2_100: l2-cache {
 207                                 compatible = "cache";
 208                                 cache-level = <2>;
 209                                 next-level-cache = <&L3_0>;
 210                         };
 211                 };
 212
 213                 CPU2: cpu@200 {
 214                         device_type = "cpu";
 215                         compatible = "qcom,kryo";
 216                         reg = <0x0 0x200>;
 217                         enable-method = "psci";
 218                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 219                                            &LITTLE_CPU_SLEEP_1
 220                                            &CLUSTER_SLEEP_0>;
 221                         next-level-cache = <&L2_200>;
 222                         operating-points-v2 = <&cpu0_opp_table>;
 223                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 224                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 225                         qcom,freq-domain = <&cpufreq_hw 0>;
 226                         #cooling-cells = <2>;
 227                         L2_200: l2-cache {
 228                                 compatible = "cache";
 229                                 cache-level = <2>;
 230                                 next-level-cache = <&L3_0>;
 231                         };
 232                 };
 233
 234                 CPU3: cpu@300 {
 235                         device_type = "cpu";
 236                         compatible = "qcom,kryo";
 237                         reg = <0x0 0x300>;
 238                         enable-method = "psci";
 239                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 240                                            &LITTLE_CPU_SLEEP_1
 241                                            &CLUSTER_SLEEP_0>;
 242                         next-level-cache = <&L2_300>;
 243                         operating-points-v2 = <&cpu0_opp_table>;
 244                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 245                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 246                         qcom,freq-domain = <&cpufreq_hw 0>;
 247                         #cooling-cells = <2>;
 248                         L2_300: l2-cache {
 249                                 compatible = "cache";
 250                                 cache-level = <2>;
 251                                 next-level-cache = <&L3_0>;
 252                         };
 253                 };
 254
 255                 CPU4: cpu@400 {
 256                         device_type = "cpu";
 257                         compatible = "qcom,kryo";
 258                         reg = <0x0 0x400>;
 259                         enable-method = "psci";
 260                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 261                                            &BIG_CPU_SLEEP_1
 262                                            &CLUSTER_SLEEP_0>;
 263                         next-level-cache = <&L2_400>;
 264                         operating-points-v2 = <&cpu4_opp_table>;
 265                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 266                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 267                         qcom,freq-domain = <&cpufreq_hw 1>;
 268                         #cooling-cells = <2>;
 269                         L2_400: l2-cache {
 270                                 compatible = "cache";
 271                                 cache-level = <2>;
 272                                 next-level-cache = <&L3_0>;
 273                         };
 274                 };
 275
 276                 CPU5: cpu@500 {
 277                         device_type = "cpu";
 278                         compatible = "qcom,kryo";
 279                         reg = <0x0 0x500>;
 280                         enable-method = "psci";
 281                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 282                                            &BIG_CPU_SLEEP_1
 283                                            &CLUSTER_SLEEP_0>;
 284                         next-level-cache = <&L2_500>;
 285                         operating-points-v2 = <&cpu4_opp_table>;
 286                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 287                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 288                         qcom,freq-domain = <&cpufreq_hw 1>;
 289                         #cooling-cells = <2>;
 290                         L2_500: l2-cache {
 291                                 compatible = "cache";
 292                                 cache-level = <2>;
 293                                 next-level-cache = <&L3_0>;
 294                         };
 295                 };
 296
 297                 CPU6: cpu@600 {
 298                         device_type = "cpu";
 299                         compatible = "qcom,kryo";
 300                         reg = <0x0 0x600>;
 301                         enable-method = "psci";
 302                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 303                                            &BIG_CPU_SLEEP_1
 304                                            &CLUSTER_SLEEP_0>;
 305                         next-level-cache = <&L2_600>;
 306                         operating-points-v2 = <&cpu4_opp_table>;
 307                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 308                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 309                         qcom,freq-domain = <&cpufreq_hw 1>;
 310                         #cooling-cells = <2>;
 311                         L2_600: l2-cache {
 312                                 compatible = "cache";
 313                                 cache-level = <2>;
 314                                 next-level-cache = <&L3_0>;
 315                         };
 316                 };
 317
 318                 CPU7: cpu@700 {
 319                         device_type = "cpu";
 320                         compatible = "qcom,kryo";
 321                         reg = <0x0 0x700>;
 322                         enable-method = "psci";
 323                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 324                                            &BIG_CPU_SLEEP_1
 325                                            &CLUSTER_SLEEP_0>;
 326                         next-level-cache = <&L2_700>;
 327                         operating-points-v2 = <&cpu7_opp_table>;
 328                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 329                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 330                         qcom,freq-domain = <&cpufreq_hw 2>;
 331                         #cooling-cells = <2>;
 332                         L2_700: l2-cache {
 333                                 compatible = "cache";
 334                                 cache-level = <2>;
 335                                 next-level-cache = <&L3_0>;
 336                         };
 337                 };
 338
 339                 cpu-map {
 340                         cluster0 {
 341                                 core0 {
 342                                         cpu = <&CPU0>;
 343                                 };
 344
 345                                 core1 {
 346                                         cpu = <&CPU1>;
 347                                 };
 348
 349                                 core2 {
 350                                         cpu = <&CPU2>;
 351                                 };
 352
 353                                 core3 {
 354                                         cpu = <&CPU3>;
 355                                 };
 356
 357                                 core4 {
 358                                         cpu = <&CPU4>;
 359                                 };
 360
 361                                 core5 {
 362                                         cpu = <&CPU5>;
 363                                 };
 364
 365                                 core6 {
 366                                         cpu = <&CPU6>;
 367                                 };
 368
 369                                 core7 {
 370                                         cpu = <&CPU7>;
 371                                 };
 372                         };
 373                 };
 374
 375                 idle-states {
 376                         entry-method = "psci";
 377
 378                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 379                                 compatible = "arm,idle-state";
 380                                 idle-state-name = "little-power-down";
 381                                 arm,psci-suspend-param = <0x40000003>;
 382                                 entry-latency-us = <549>;
 383                                 exit-latency-us = <901>;
 384                                 min-residency-us = <1774>;
 385                                 local-timer-stop;
 386                         };
 387
 388                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 389                                 compatible = "arm,idle-state";
 390                                 idle-state-name = "little-rail-power-down";
 391                                 arm,psci-suspend-param = <0x40000004>;
 392                                 entry-latency-us = <702>;
 393                                 exit-latency-us = <915>;
 394                                 min-residency-us = <4001>;
 395                                 local-timer-stop;
 396                         };
 397
 398                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 399                                 compatible = "arm,idle-state";
 400                                 idle-state-name = "big-power-down";
 401                                 arm,psci-suspend-param = <0x40000003>;
 402                                 entry-latency-us = <523>;
 403                                 exit-latency-us = <1244>;
 404                                 min-residency-us = <2207>;
 405                                 local-timer-stop;
 406                         };
 407
 408                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 409                                 compatible = "arm,idle-state";
 410                                 idle-state-name = "big-rail-power-down";
 411                                 arm,psci-suspend-param = <0x40000004>;
 412                                 entry-latency-us = <526>;
 413                                 exit-latency-us = <1854>;
 414                                 min-residency-us = <5555>;
 415                                 local-timer-stop;
 416                         };
 417
 418                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 419                                 compatible = "arm,idle-state";
 420                                 idle-state-name = "cluster-power-down";
 421                                 arm,psci-suspend-param = <0x40003444>;
 422                                 entry-latency-us = <3263>;
 423                                 exit-latency-us = <6562>;
 424                                 min-residency-us = <9926>;
 425                                 local-timer-stop;
 426                         };
 427                 };
 428         };
 429
 430         cpu0_opp_table: opp-table-cpu0 {
 431                 compatible = "operating-points-v2";
 432                 opp-shared;
 433
 434                 cpu0_opp_300mhz: opp-300000000 {
 435                         opp-hz = /bits/ 64 <300000000>;
 436                         opp-peak-kBps = <800000 9600000>;
 437                 };
 438
 439                 cpu0_opp_691mhz: opp-691200000 {
 440                         opp-hz = /bits/ 64 <691200000>;
 441                         opp-peak-kBps = <800000 17817600>;
 442                 };
 443
 444                 cpu0_opp_806mhz: opp-806400000 {
 445                         opp-hz = /bits/ 64 <806400000>;
 446                         opp-peak-kBps = <800000 20889600>;
 447                 };
 448
 449                 cpu0_opp_941mhz: opp-940800000 {
 450                         opp-hz = /bits/ 64 <940800000>;
 451                         opp-peak-kBps = <1804000 24576000>;
 452                 };
 453
 454                 cpu0_opp_1152mhz: opp-1152000000 {
 455                         opp-hz = /bits/ 64 <1152000000>;
 456                         opp-peak-kBps = <2188000 27033600>;
 457                 };
 458
 459                 cpu0_opp_1325mhz: opp-1324800000 {
 460                         opp-hz = /bits/ 64 <1324800000>;
 461                         opp-peak-kBps = <2188000 33792000>;
 462                 };
 463
 464                 cpu0_opp_1517mhz: opp-1516800000 {
 465                         opp-hz = /bits/ 64 <1516800000>;
 466                         opp-peak-kBps = <3072000 38092800>;
 467                 };
 468
 469                 cpu0_opp_1651mhz: opp-1651200000 {
 470                         opp-hz = /bits/ 64 <1651200000>;
 471                         opp-peak-kBps = <3072000 41779200>;
 472                 };
 473
 474                 cpu0_opp_1805mhz: opp-1804800000 {
 475                         opp-hz = /bits/ 64 <1804800000>;
 476                         opp-peak-kBps = <4068000 48537600>;
 477                 };
 478
 479                 cpu0_opp_1958mhz: opp-1958400000 {
 480                         opp-hz = /bits/ 64 <1958400000>;
 481                         opp-peak-kBps = <4068000 48537600>;
 482                 };
 483
 484                 cpu0_opp_2016mhz: opp-2016000000 {
 485                         opp-hz = /bits/ 64 <2016000000>;
 486                         opp-peak-kBps = <6220000 48537600>;
 487                 };
 488         };
 489
 490         cpu4_opp_table: opp-table-cpu4 {
 491                 compatible = "operating-points-v2";
 492                 opp-shared;
 493
 494                 cpu4_opp_691mhz: opp-691200000 {
 495                         opp-hz = /bits/ 64 <691200000>;
 496                         opp-peak-kBps = <1804000 9600000>;
 497                 };
 498
 499                 cpu4_opp_941mhz: opp-940800000 {
 500                         opp-hz = /bits/ 64 <940800000>;
 501                         opp-peak-kBps = <2188000 17817600>;
 502                 };
 503
 504                 cpu4_opp_1229mhz: opp-1228800000 {
 505                         opp-hz = /bits/ 64 <1228800000>;
 506                         opp-peak-kBps = <4068000 24576000>;
 507                 };
 508
 509                 cpu4_opp_1344mhz: opp-1344000000 {
 510                         opp-hz = /bits/ 64 <1344000000>;
 511                         opp-peak-kBps = <4068000 24576000>;
 512                 };
 513
 514                 cpu4_opp_1517mhz: opp-1516800000 {
 515                         opp-hz = /bits/ 64 <1516800000>;
 516                         opp-peak-kBps = <4068000 24576000>;
 517                 };
 518
 519                 cpu4_opp_1651mhz: opp-1651200000 {
 520                         opp-hz = /bits/ 64 <1651200000>;
 521                         opp-peak-kBps = <6220000 38092800>;
 522                 };
 523
 524                 cpu4_opp_1901mhz: opp-1900800000 {
 525                         opp-hz = /bits/ 64 <1900800000>;
 526                         opp-peak-kBps = <6220000 44851200>;
 527                 };
 528
 529                 cpu4_opp_2054mhz: opp-2054400000 {
 530                         opp-hz = /bits/ 64 <2054400000>;
 531                         opp-peak-kBps = <6220000 44851200>;
 532                 };
 533
 534                 cpu4_opp_2112mhz: opp-2112000000 {
 535                         opp-hz = /bits/ 64 <2112000000>;
 536                         opp-peak-kBps = <6220000 44851200>;
 537                 };
 538
 539                 cpu4_opp_2131mhz: opp-2131200000 {
 540                         opp-hz = /bits/ 64 <2131200000>;
 541                         opp-peak-kBps = <6220000 44851200>;
 542                 };
 543
 544                 cpu4_opp_2208mhz: opp-2208000000 {
 545                         opp-hz = /bits/ 64 <2208000000>;
 546                         opp-peak-kBps = <6220000 44851200>;
 547                 };
 548
 549                 cpu4_opp_2400mhz: opp-2400000000 {
 550                         opp-hz = /bits/ 64 <2400000000>;
 551                         opp-peak-kBps = <8532000 48537600>;
 552                 };
 553
 554                 cpu4_opp_2611mhz: opp-2611200000 {
 555                         opp-hz = /bits/ 64 <2611200000>;
 556                         opp-peak-kBps = <8532000 48537600>;
 557                 };
 558         };
 559
 560         cpu7_opp_table: opp-table-cpu7 {
 561                 compatible = "operating-points-v2";
 562                 opp-shared;
 563
 564                 cpu7_opp_806mhz: opp-806400000 {
 565                         opp-hz = /bits/ 64 <806400000>;
 566                         opp-peak-kBps = <1804000 9600000>;
 567                 };
 568
 569                 cpu7_opp_1056mhz: opp-1056000000 {
 570                         opp-hz = /bits/ 64 <1056000000>;
 571                         opp-peak-kBps = <2188000 17817600>;
 572                 };
 573
 574                 cpu7_opp_1325mhz: opp-1324800000 {
 575                         opp-hz = /bits/ 64 <1324800000>;
 576                         opp-peak-kBps = <4068000 24576000>;
 577                 };
 578
 579                 cpu7_opp_1517mhz: opp-1516800000 {
 580                         opp-hz = /bits/ 64 <1516800000>;
 581                         opp-peak-kBps = <4068000 24576000>;
 582                 };
 583
 584                 cpu7_opp_1766mhz: opp-1766400000 {
 585                         opp-hz = /bits/ 64 <1766400000>;
 586                         opp-peak-kBps = <6220000 38092800>;
 587                 };
 588
 589                 cpu7_opp_1862mhz: opp-1862400000 {
 590                         opp-hz = /bits/ 64 <1862400000>;
 591                         opp-peak-kBps = <6220000 38092800>;
 592                 };
 593
 594                 cpu7_opp_2035mhz: opp-2035200000 {
 595                         opp-hz = /bits/ 64 <2035200000>;
 596                         opp-peak-kBps = <6220000 38092800>;
 597                 };
 598
 599                 cpu7_opp_2112mhz: opp-2112000000 {
 600                         opp-hz = /bits/ 64 <2112000000>;
 601                         opp-peak-kBps = <6220000 44851200>;
 602                 };
 603
 604                 cpu7_opp_2208mhz: opp-2208000000 {
 605                         opp-hz = /bits/ 64 <2208000000>;
 606                         opp-peak-kBps = <6220000 44851200>;
 607                 };
 608
 609                 cpu7_opp_2381mhz: opp-2380800000 {
 610                         opp-hz = /bits/ 64 <2380800000>;
 611                         opp-peak-kBps = <6832000 44851200>;
 612                 };
 613
 614                 cpu7_opp_2400mhz: opp-2400000000 {
 615                         opp-hz = /bits/ 64 <2400000000>;
 616                         opp-peak-kBps = <8532000 48537600>;
 617                 };
 618
 619                 cpu7_opp_2515mhz: opp-2515200000 {
 620                         opp-hz = /bits/ 64 <2515200000>;
 621                         opp-peak-kBps = <8532000 48537600>;
 622                 };
 623
 624                 cpu7_opp_2707mhz: opp-2707200000 {
 625                         opp-hz = /bits/ 64 <2707200000>;
 626                         opp-peak-kBps = <8532000 48537600>;
 627                 };
 628
 629                 cpu7_opp_3014mhz: opp-3014400000 {
 630                         opp-hz = /bits/ 64 <3014400000>;
 631                         opp-peak-kBps = <8532000 48537600>;
 632                 };
 633         };
 634
 635         memory@80000000 {
 636                 device_type = "memory";
 637                 /* We expect the bootloader to fill in the size */
 638                 reg = <0 0x80000000 0 0>;
 639         };
 640
 641         firmware {
 642                 scm {
 643                         compatible = "qcom,scm-sc7280", "qcom,scm";
 644                 };
 645         };
 646
 647         clk_virt: interconnect {
 648                 compatible = "qcom,sc7280-clk-virt";
 649                 #interconnect-cells = <2>;
 650                 qcom,bcm-voters = <&apps_bcm_voter>;
 651         };
 652
 653         smem {
 654                 compatible = "qcom,smem";
 655                 memory-region = <&smem_mem>;
 656                 hwlocks = <&tcsr_mutex 3>;
 657         };
 658
 659         smp2p-adsp {
 660                 compatible = "qcom,smp2p";
 661                 qcom,smem = <443>, <429>;
 662                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 663                                              IPCC_MPROC_SIGNAL_SMP2P
 664                                              IRQ_TYPE_EDGE_RISING>;
 665                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 666                                 IPCC_MPROC_SIGNAL_SMP2P>;
 667
 668                 qcom,local-pid = <0>;
 669                 qcom,remote-pid = <2>;
 670
 671                 adsp_smp2p_out: master-kernel {
 672                         qcom,entry-name = "master-kernel";
 673                         #qcom,smem-state-cells = <1>;
 674                 };
 675
 676                 adsp_smp2p_in: slave-kernel {
 677                         qcom,entry-name = "slave-kernel";
 678                         interrupt-controller;
 679                         #interrupt-cells = <2>;
 680                 };
 681         };
 682
 683         smp2p-cdsp {
 684                 compatible = "qcom,smp2p";
 685                 qcom,smem = <94>, <432>;
 686                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 687                                              IPCC_MPROC_SIGNAL_SMP2P
 688                                              IRQ_TYPE_EDGE_RISING>;
 689                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 690                                 IPCC_MPROC_SIGNAL_SMP2P>;
 691
 692                 qcom,local-pid = <0>;
 693                 qcom,remote-pid = <5>;
 694
 695                 cdsp_smp2p_out: master-kernel {
 696                         qcom,entry-name = "master-kernel";
 697                         #qcom,smem-state-cells = <1>;
 698                 };
 699
 700                 cdsp_smp2p_in: slave-kernel {
 701                         qcom,entry-name = "slave-kernel";
 702                         interrupt-controller;
 703                         #interrupt-cells = <2>;
 704                 };
 705         };
 706
 707         smp2p-mpss {
 708                 compatible = "qcom,smp2p";
 709                 qcom,smem = <435>, <428>;
 710                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 711                                              IPCC_MPROC_SIGNAL_SMP2P
 712                                              IRQ_TYPE_EDGE_RISING>;
 713                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 714                                 IPCC_MPROC_SIGNAL_SMP2P>;
 715
 716                 qcom,local-pid = <0>;
 717                 qcom,remote-pid = <1>;
 718
 719                 modem_smp2p_out: master-kernel {
 720                         qcom,entry-name = "master-kernel";
 721                         #qcom,smem-state-cells = <1>;
 722                 };
 723
 724                 modem_smp2p_in: slave-kernel {
 725                         qcom,entry-name = "slave-kernel";
 726                         interrupt-controller;
 727                         #interrupt-cells = <2>;
 728                 };
 729
 730                 ipa_smp2p_out: ipa-ap-to-modem {
 731                         qcom,entry-name = "ipa";
 732                         #qcom,smem-state-cells = <1>;
 733                 };
 734
 735                 ipa_smp2p_in: ipa-modem-to-ap {
 736                         qcom,entry-name = "ipa";
 737                         interrupt-controller;
 738                         #interrupt-cells = <2>;
 739                 };
 740         };
 741
 742         smp2p-wpss {
 743                 compatible = "qcom,smp2p";
 744                 qcom,smem = <617>, <616>;
 745                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
 746                                              IPCC_MPROC_SIGNAL_SMP2P
 747                                              IRQ_TYPE_EDGE_RISING>;
 748                 mboxes = <&ipcc IPCC_CLIENT_WPSS
 749                                 IPCC_MPROC_SIGNAL_SMP2P>;
 750
 751                 qcom,local-pid = <0>;
 752                 qcom,remote-pid = <13>;
 753
 754                 wpss_smp2p_out: master-kernel {
 755                         qcom,entry-name = "master-kernel";
 756                         #qcom,smem-state-cells = <1>;
 757                 };
 758
 759                 wpss_smp2p_in: slave-kernel {
 760                         qcom,entry-name = "slave-kernel";
 761                         interrupt-controller;
 762                         #interrupt-cells = <2>;
 763                 };
 764
 765                 wlan_smp2p_out: wlan-ap-to-wpss {
 766                         qcom,entry-name = "wlan";
 767                         #qcom,smem-state-cells = <1>;
 768                 };
 769
 770                 wlan_smp2p_in: wlan-wpss-to-ap {
 771                         qcom,entry-name = "wlan";
 772                         interrupt-controller;
 773                         #interrupt-cells = <2>;
 774                 };
 775         };
 776
 777         pmu {
 778                 compatible = "arm,armv8-pmuv3";
 779                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 780         };
 781
 782         psci {
 783                 compatible = "arm,psci-1.0";
 784                 method = "smc";
 785         };
 786
 787         qspi_opp_table: opp-table-qspi {
 788                 compatible = "operating-points-v2";
 789
 790                 opp-75000000 {
 791                         opp-hz = /bits/ 64 <75000000>;
 792                         required-opps = <&rpmhpd_opp_low_svs>;
 793                 };
 794
 795                 opp-150000000 {
 796                         opp-hz = /bits/ 64 <150000000>;
 797                         required-opps = <&rpmhpd_opp_svs>;
 798                 };
 799
 800                 opp-200000000 {
 801                         opp-hz = /bits/ 64 <200000000>;
 802                         required-opps = <&rpmhpd_opp_svs_l1>;
 803                 };
 804
 805                 opp-300000000 {
 806                         opp-hz = /bits/ 64 <300000000>;
 807                         required-opps = <&rpmhpd_opp_nom>;
 808                 };
 809         };
 810
 811         qup_opp_table: opp-table-qup {
 812                 compatible = "operating-points-v2";
 813
 814                 opp-75000000 {
 815                         opp-hz = /bits/ 64 <75000000>;
 816                         required-opps = <&rpmhpd_opp_low_svs>;
 817                 };
 818
 819                 opp-100000000 {
 820                         opp-hz = /bits/ 64 <100000000>;
 821                         required-opps = <&rpmhpd_opp_svs>;
 822                 };
 823
 824                 opp-128000000 {
 825                         opp-hz = /bits/ 64 <128000000>;
 826                         required-opps = <&rpmhpd_opp_nom>;
 827                 };
 828         };
 829
 830         soc: soc@0 {
 831                 #address-cells = <2>;
 832                 #size-cells = <2>;
 833                 ranges = <0 0 0 0 0x10 0>;
 834                 dma-ranges = <0 0 0 0 0x10 0>;
 835                 compatible = "simple-bus";
 836
 837                 gcc: clock-controller@100000 {
 838                         compatible = "qcom,gcc-sc7280";
 839                         reg = <0 0x00100000 0 0x1f0000>;
 840                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 841                                  <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
 842                                  <0>, <&pcie1_lane>,
 843                                  <0>, <0>, <0>, <0>;
 844                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
 845                                       "pcie_0_pipe_clk", "pcie_1_pipe_clk",
 846                                       "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
 847                                       "ufs_phy_tx_symbol_0_clk",
 848                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 849                         #clock-cells = <1>;
 850                         #reset-cells = <1>;
 851                         #power-domain-cells = <1>;
 852                         power-domains = <&rpmhpd SC7280_CX>;
 853                 };
 854
 855                 ipcc: mailbox@408000 {
 856                         compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
 857                         reg = <0 0x00408000 0 0x1000>;
 858                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 859                         interrupt-controller;
 860                         #interrupt-cells = <3>;
 861                         #mbox-cells = <2>;
 862                 };
 863
 864                 qfprom: efuse@784000 {
 865                         compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
 866                         reg = <0 0x00784000 0 0xa20>,
 867                               <0 0x00780000 0 0xa20>,
 868                               <0 0x00782000 0 0x120>,
 869                               <0 0x00786000 0 0x1fff>;
 870                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 871                         clock-names = "core";
 872                         power-domains = <&rpmhpd SC7280_MX>;
 873                         #address-cells = <1>;
 874                         #size-cells = <1>;
 875
 876                         gpu_speed_bin: gpu_speed_bin@1e9 {
 877                                 reg = <0x1e9 0x2>;
 878                                 bits = <5 8>;
 879                         };
 880                 };
 881
 882                 sdhc_1: mmc@7c4000 {
 883                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
 884                         pinctrl-names = "default", "sleep";
 885                         pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
 886                         pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
 887                         status = "disabled";
 888
 889                         reg = <0 0x007c4000 0 0x1000>,
 890                               <0 0x007c5000 0 0x1000>;
 891                         reg-names = "hc", "cqhci";
 892
 893                         iommus = <&apps_smmu 0xc0 0x0>;
 894                         interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
 895                                      <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
 896                         interrupt-names = "hc_irq", "pwr_irq";
 897
 898                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 899                                  <&gcc GCC_SDCC1_APPS_CLK>,
 900                                  <&rpmhcc RPMH_CXO_CLK>;
 901                         clock-names = "iface", "core", "xo";
 902                         interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
 903                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
 904                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 905                         power-domains = <&rpmhpd SC7280_CX>;
 906                         operating-points-v2 = <&sdhc1_opp_table>;
 907
 908                         bus-width = <8>;
 909                         supports-cqe;
 910
 911                         qcom,dll-config = <0x0007642c>;
 912                         qcom,ddr-config = <0x80040868>;
 913
 914                         mmc-ddr-1_8v;
 915                         mmc-hs200-1_8v;
 916                         mmc-hs400-1_8v;
 917                         mmc-hs400-enhanced-strobe;
 918
 919                         resets = <&gcc GCC_SDCC1_BCR>;
 920
 921                         sdhc1_opp_table: opp-table {
 922                                 compatible = "operating-points-v2";
 923
 924                                 opp-100000000 {
 925                                         opp-hz = /bits/ 64 <100000000>;
 926                                         required-opps = <&rpmhpd_opp_low_svs>;
 927                                         opp-peak-kBps = <1800000 400000>;
 928                                         opp-avg-kBps = <100000 0>;
 929                                 };
 930
 931                                 opp-384000000 {
 932                                         opp-hz = /bits/ 64 <384000000>;
 933                                         required-opps = <&rpmhpd_opp_nom>;
 934                                         opp-peak-kBps = <5400000 1600000>;
 935                                         opp-avg-kBps = <390000 0>;
 936                                 };
 937                         };
 938
 939                 };
 940
 941                 gpi_dma0: dma-controller@900000 {
 942                         #dma-cells = <3>;
 943                         compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
 944                         reg = <0 0x00900000 0 0x60000>;
 945                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 946                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 947                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 948                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 949                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 950                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 951                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 952                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 953                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 954                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 955                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 956                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 957                         dma-channels = <12>;
 958                         dma-channel-mask = <0x7f>;
 959                         iommus = <&apps_smmu 0x0136 0x0>;
 960                         status = "disabled";
 961                 };
 962
 963                 qupv3_id_0: geniqup@9c0000 {
 964                         compatible = "qcom,geni-se-qup";
 965                         reg = <0 0x009c0000 0 0x2000>;
 966                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 967                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 968                         clock-names = "m-ahb", "s-ahb";
 969                         #address-cells = <2>;
 970                         #size-cells = <2>;
 971                         ranges;
 972                         iommus = <&apps_smmu 0x123 0x0>;
 973                         status = "disabled";
 974
 975                         i2c0: i2c@980000 {
 976                                 compatible = "qcom,geni-i2c";
 977                                 reg = <0 0x00980000 0 0x4000>;
 978                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 979                                 clock-names = "se";
 980                                 pinctrl-names = "default";
 981                                 pinctrl-0 = <&qup_i2c0_data_clk>;
 982                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 983                                 #address-cells = <1>;
 984                                 #size-cells = <0>;
 985                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 986                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
 987                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 988                                 interconnect-names = "qup-core", "qup-config",
 989                                                         "qup-memory";
 990                                 power-domains = <&rpmhpd SC7280_CX>;
 991                                 required-opps = <&rpmhpd_opp_low_svs>;
 992                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 993                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 994                                 dma-names = "tx", "rx";
 995                                 status = "disabled";
 996                         };
 997
 998                         spi0: spi@980000 {
 999                                 compatible = "qcom,geni-spi";
1000                                 reg = <0 0x00980000 0 0x4000>;
1001                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1002                                 clock-names = "se";
1003                                 pinctrl-names = "default";
1004                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1005                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1006                                 #address-cells = <1>;
1007                                 #size-cells = <0>;
1008                                 power-domains = <&rpmhpd SC7280_CX>;
1009                                 operating-points-v2 = <&qup_opp_table>;
1010                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1011                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1012                                 interconnect-names = "qup-core", "qup-config";
1013                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1014                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1015                                 dma-names = "tx", "rx";
1016                                 status = "disabled";
1017                         };
1018
1019                         uart0: serial@980000 {
1020                                 compatible = "qcom,geni-uart";
1021                                 reg = <0 0x00980000 0 0x4000>;
1022                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1023                                 clock-names = "se";
1024                                 pinctrl-names = "default";
1025                                 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1026                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1027                                 power-domains = <&rpmhpd SC7280_CX>;
1028                                 operating-points-v2 = <&qup_opp_table>;
1029                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1030                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1031                                 interconnect-names = "qup-core", "qup-config";
1032                                 status = "disabled";
1033                         };
1034
1035                         i2c1: i2c@984000 {
1036                                 compatible = "qcom,geni-i2c";
1037                                 reg = <0 0x00984000 0 0x4000>;
1038                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1039                                 clock-names = "se";
1040                                 pinctrl-names = "default";
1041                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1042                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1043                                 #address-cells = <1>;
1044                                 #size-cells = <0>;
1045                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1046                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1047                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1048                                 interconnect-names = "qup-core", "qup-config",
1049                                                         "qup-memory";
1050                                 power-domains = <&rpmhpd SC7280_CX>;
1051                                 required-opps = <&rpmhpd_opp_low_svs>;
1052                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1053                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1054                                 dma-names = "tx", "rx";
1055                                 status = "disabled";
1056                         };
1057
1058                         spi1: spi@984000 {
1059                                 compatible = "qcom,geni-spi";
1060                                 reg = <0 0x00984000 0 0x4000>;
1061                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1062                                 clock-names = "se";
1063                                 pinctrl-names = "default";
1064                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1065                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1066                                 #address-cells = <1>;
1067                                 #size-cells = <0>;
1068                                 power-domains = <&rpmhpd SC7280_CX>;
1069                                 operating-points-v2 = <&qup_opp_table>;
1070                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1071                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1072                                 interconnect-names = "qup-core", "qup-config";
1073                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1074                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1075                                 dma-names = "tx", "rx";
1076                                 status = "disabled";
1077                         };
1078
1079                         uart1: serial@984000 {
1080                                 compatible = "qcom,geni-uart";
1081                                 reg = <0 0x00984000 0 0x4000>;
1082                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1083                                 clock-names = "se";
1084                                 pinctrl-names = "default";
1085                                 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1086                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1087                                 power-domains = <&rpmhpd SC7280_CX>;
1088                                 operating-points-v2 = <&qup_opp_table>;
1089                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1090                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1091                                 interconnect-names = "qup-core", "qup-config";
1092                                 status = "disabled";
1093                         };
1094
1095                         i2c2: i2c@988000 {
1096                                 compatible = "qcom,geni-i2c";
1097                                 reg = <0 0x00988000 0 0x4000>;
1098                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1099                                 clock-names = "se";
1100                                 pinctrl-names = "default";
1101                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1102                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1103                                 #address-cells = <1>;
1104                                 #size-cells = <0>;
1105                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1106                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1107                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1108                                 interconnect-names = "qup-core", "qup-config",
1109                                                         "qup-memory";
1110                                 power-domains = <&rpmhpd SC7280_CX>;
1111                                 required-opps = <&rpmhpd_opp_low_svs>;
1112                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1113                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1114                                 dma-names = "tx", "rx";
1115                                 status = "disabled";
1116                         };
1117
1118                         spi2: spi@988000 {
1119                                 compatible = "qcom,geni-spi";
1120                                 reg = <0 0x00988000 0 0x4000>;
1121                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1122                                 clock-names = "se";
1123                                 pinctrl-names = "default";
1124                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1125                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1126                                 #address-cells = <1>;
1127                                 #size-cells = <0>;
1128                                 power-domains = <&rpmhpd SC7280_CX>;
1129                                 operating-points-v2 = <&qup_opp_table>;
1130                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1131                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1132                                 interconnect-names = "qup-core", "qup-config";
1133                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1134                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1135                                 dma-names = "tx", "rx";
1136                                 status = "disabled";
1137                         };
1138
1139                         uart2: serial@988000 {
1140                                 compatible = "qcom,geni-uart";
1141                                 reg = <0 0x00988000 0 0x4000>;
1142                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1143                                 clock-names = "se";
1144                                 pinctrl-names = "default";
1145                                 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1146                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1147                                 power-domains = <&rpmhpd SC7280_CX>;
1148                                 operating-points-v2 = <&qup_opp_table>;
1149                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1150                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1151                                 interconnect-names = "qup-core", "qup-config";
1152                                 status = "disabled";
1153                         };
1154
1155                         i2c3: i2c@98c000 {
1156                                 compatible = "qcom,geni-i2c";
1157                                 reg = <0 0x0098c000 0 0x4000>;
1158                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1159                                 clock-names = "se";
1160                                 pinctrl-names = "default";
1161                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1162                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1163                                 #address-cells = <1>;
1164                                 #size-cells = <0>;
1165                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1167                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168                                 interconnect-names = "qup-core", "qup-config",
1169                                                         "qup-memory";
1170                                 power-domains = <&rpmhpd SC7280_CX>;
1171                                 required-opps = <&rpmhpd_opp_low_svs>;
1172                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1173                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1174                                 dma-names = "tx", "rx";
1175                                 status = "disabled";
1176                         };
1177
1178                         spi3: spi@98c000 {
1179                                 compatible = "qcom,geni-spi";
1180                                 reg = <0 0x0098c000 0 0x4000>;
1181                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1182                                 clock-names = "se";
1183                                 pinctrl-names = "default";
1184                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1185                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1186                                 #address-cells = <1>;
1187                                 #size-cells = <0>;
1188                                 power-domains = <&rpmhpd SC7280_CX>;
1189                                 operating-points-v2 = <&qup_opp_table>;
1190                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1191                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1192                                 interconnect-names = "qup-core", "qup-config";
1193                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1194                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1195                                 dma-names = "tx", "rx";
1196                                 status = "disabled";
1197                         };
1198
1199                         uart3: serial@98c000 {
1200                                 compatible = "qcom,geni-uart";
1201                                 reg = <0 0x0098c000 0 0x4000>;
1202                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1203                                 clock-names = "se";
1204                                 pinctrl-names = "default";
1205                                 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1206                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1207                                 power-domains = <&rpmhpd SC7280_CX>;
1208                                 operating-points-v2 = <&qup_opp_table>;
1209                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1210                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1211                                 interconnect-names = "qup-core", "qup-config";
1212                                 status = "disabled";
1213                         };
1214
1215                         i2c4: i2c@990000 {
1216                                 compatible = "qcom,geni-i2c";
1217                                 reg = <0 0x00990000 0 0x4000>;
1218                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1219                                 clock-names = "se";
1220                                 pinctrl-names = "default";
1221                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1222                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1223                                 #address-cells = <1>;
1224                                 #size-cells = <0>;
1225                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1226                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1227                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1228                                 interconnect-names = "qup-core", "qup-config",
1229                                                         "qup-memory";
1230                                 power-domains = <&rpmhpd SC7280_CX>;
1231                                 required-opps = <&rpmhpd_opp_low_svs>;
1232                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1233                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1234                                 dma-names = "tx", "rx";
1235                                 status = "disabled";
1236                         };
1237
1238                         spi4: spi@990000 {
1239                                 compatible = "qcom,geni-spi";
1240                                 reg = <0 0x00990000 0 0x4000>;
1241                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1242                                 clock-names = "se";
1243                                 pinctrl-names = "default";
1244                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1245                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1246                                 #address-cells = <1>;
1247                                 #size-cells = <0>;
1248                                 power-domains = <&rpmhpd SC7280_CX>;
1249                                 operating-points-v2 = <&qup_opp_table>;
1250                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1251                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1252                                 interconnect-names = "qup-core", "qup-config";
1253                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1254                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1255                                 dma-names = "tx", "rx";
1256                                 status = "disabled";
1257                         };
1258
1259                         uart4: serial@990000 {
1260                                 compatible = "qcom,geni-uart";
1261                                 reg = <0 0x00990000 0 0x4000>;
1262                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1263                                 clock-names = "se";
1264                                 pinctrl-names = "default";
1265                                 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1266                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1267                                 power-domains = <&rpmhpd SC7280_CX>;
1268                                 operating-points-v2 = <&qup_opp_table>;
1269                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1270                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1271                                 interconnect-names = "qup-core", "qup-config";
1272                                 status = "disabled";
1273                         };
1274
1275                         i2c5: i2c@994000 {
1276                                 compatible = "qcom,geni-i2c";
1277                                 reg = <0 0x00994000 0 0x4000>;
1278                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1279                                 clock-names = "se";
1280                                 pinctrl-names = "default";
1281                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1282                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1283                                 #address-cells = <1>;
1284                                 #size-cells = <0>;
1285                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1286                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1287                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1288                                 interconnect-names = "qup-core", "qup-config",
1289                                                         "qup-memory";
1290                                 power-domains = <&rpmhpd SC7280_CX>;
1291                                 required-opps = <&rpmhpd_opp_low_svs>;
1292                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1293                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1294                                 dma-names = "tx", "rx";
1295                                 status = "disabled";
1296                         };
1297
1298                         spi5: spi@994000 {
1299                                 compatible = "qcom,geni-spi";
1300                                 reg = <0 0x00994000 0 0x4000>;
1301                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1302                                 clock-names = "se";
1303                                 pinctrl-names = "default";
1304                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1305                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1306                                 #address-cells = <1>;
1307                                 #size-cells = <0>;
1308                                 power-domains = <&rpmhpd SC7280_CX>;
1309                                 operating-points-v2 = <&qup_opp_table>;
1310                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1311                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1312                                 interconnect-names = "qup-core", "qup-config";
1313                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1314                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1315                                 dma-names = "tx", "rx";
1316                                 status = "disabled";
1317                         };
1318
1319                         uart5: serial@994000 {
1320                                 compatible = "qcom,geni-uart";
1321                                 reg = <0 0x00994000 0 0x4000>;
1322                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1323                                 clock-names = "se";
1324                                 pinctrl-names = "default";
1325                                 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1326                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1327                                 power-domains = <&rpmhpd SC7280_CX>;
1328                                 operating-points-v2 = <&qup_opp_table>;
1329                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1330                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1331                                 interconnect-names = "qup-core", "qup-config";
1332                                 status = "disabled";
1333                         };
1334
1335                         i2c6: i2c@998000 {
1336                                 compatible = "qcom,geni-i2c";
1337                                 reg = <0 0x00998000 0 0x4000>;
1338                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1339                                 clock-names = "se";
1340                                 pinctrl-names = "default";
1341                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1342                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1343                                 #address-cells = <1>;
1344                                 #size-cells = <0>;
1345                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1346                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1347                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1348                                 interconnect-names = "qup-core", "qup-config",
1349                                                         "qup-memory";
1350                                 power-domains = <&rpmhpd SC7280_CX>;
1351                                 required-opps = <&rpmhpd_opp_low_svs>;
1352                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1353                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1354                                 dma-names = "tx", "rx";
1355                                 status = "disabled";
1356                         };
1357
1358                         spi6: spi@998000 {
1359                                 compatible = "qcom,geni-spi";
1360                                 reg = <0 0x00998000 0 0x4000>;
1361                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1362                                 clock-names = "se";
1363                                 pinctrl-names = "default";
1364                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1365                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1366                                 #address-cells = <1>;
1367                                 #size-cells = <0>;
1368                                 power-domains = <&rpmhpd SC7280_CX>;
1369                                 operating-points-v2 = <&qup_opp_table>;
1370                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1371                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1372                                 interconnect-names = "qup-core", "qup-config";
1373                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1374                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1375                                 dma-names = "tx", "rx";
1376                                 status = "disabled";
1377                         };
1378
1379                         uart6: serial@998000 {
1380                                 compatible = "qcom,geni-uart";
1381                                 reg = <0 0x00998000 0 0x4000>;
1382                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1383                                 clock-names = "se";
1384                                 pinctrl-names = "default";
1385                                 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1386                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1387                                 power-domains = <&rpmhpd SC7280_CX>;
1388                                 operating-points-v2 = <&qup_opp_table>;
1389                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1390                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1391                                 interconnect-names = "qup-core", "qup-config";
1392                                 status = "disabled";
1393                         };
1394
1395                         i2c7: i2c@99c000 {
1396                                 compatible = "qcom,geni-i2c";
1397                                 reg = <0 0x0099c000 0 0x4000>;
1398                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1399                                 clock-names = "se";
1400                                 pinctrl-names = "default";
1401                                 pinctrl-0 = <&qup_i2c7_data_clk>;
1402                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1403                                 #address-cells = <1>;
1404                                 #size-cells = <0>;
1405                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1406                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1407                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1408                                 interconnect-names = "qup-core", "qup-config",
1409                                                         "qup-memory";
1410                                 power-domains = <&rpmhpd SC7280_CX>;
1411                                 required-opps = <&rpmhpd_opp_low_svs>;
1412                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1413                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1414                                 dma-names = "tx", "rx";
1415                                 status = "disabled";
1416                         };
1417
1418                         spi7: spi@99c000 {
1419                                 compatible = "qcom,geni-spi";
1420                                 reg = <0 0x0099c000 0 0x4000>;
1421                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1422                                 clock-names = "se";
1423                                 pinctrl-names = "default";
1424                                 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1425                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1426                                 #address-cells = <1>;
1427                                 #size-cells = <0>;
1428                                 power-domains = <&rpmhpd SC7280_CX>;
1429                                 operating-points-v2 = <&qup_opp_table>;
1430                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1431                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1432                                 interconnect-names = "qup-core", "qup-config";
1433                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1434                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1435                                 dma-names = "tx", "rx";
1436                                 status = "disabled";
1437                         };
1438
1439                         uart7: serial@99c000 {
1440                                 compatible = "qcom,geni-uart";
1441                                 reg = <0 0x0099c000 0 0x4000>;
1442                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1443                                 clock-names = "se";
1444                                 pinctrl-names = "default";
1445                                 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1446                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1447                                 power-domains = <&rpmhpd SC7280_CX>;
1448                                 operating-points-v2 = <&qup_opp_table>;
1449                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1450                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1451                                 interconnect-names = "qup-core", "qup-config";
1452                                 status = "disabled";
1453                         };
1454                 };
1455
1456                 gpi_dma1: dma-controller@a00000 {
1457                         #dma-cells = <3>;
1458                         compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1459                         reg = <0 0x00a00000 0 0x60000>;
1460                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1461                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1462                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1463                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1464                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1465                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1466                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1467                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1468                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1469                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1470                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1471                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1472                         dma-channels = <12>;
1473                         dma-channel-mask = <0x1e>;
1474                         iommus = <&apps_smmu 0x56 0x0>;
1475                         status = "disabled";
1476                 };
1477
1478                 qupv3_id_1: geniqup@ac0000 {
1479                         compatible = "qcom,geni-se-qup";
1480                         reg = <0 0x00ac0000 0 0x2000>;
1481                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1482                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1483                         clock-names = "m-ahb", "s-ahb";
1484                         #address-cells = <2>;
1485                         #size-cells = <2>;
1486                         ranges;
1487                         iommus = <&apps_smmu 0x43 0x0>;
1488                         status = "disabled";
1489
1490                         i2c8: i2c@a80000 {
1491                                 compatible = "qcom,geni-i2c";
1492                                 reg = <0 0x00a80000 0 0x4000>;
1493                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1494                                 clock-names = "se";
1495                                 pinctrl-names = "default";
1496                                 pinctrl-0 = <&qup_i2c8_data_clk>;
1497                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1498                                 #address-cells = <1>;
1499                                 #size-cells = <0>;
1500                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1501                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1502                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1503                                 interconnect-names = "qup-core", "qup-config",
1504                                                         "qup-memory";
1505                                 power-domains = <&rpmhpd SC7280_CX>;
1506                                 required-opps = <&rpmhpd_opp_low_svs>;
1507                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1508                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1509                                 dma-names = "tx", "rx";
1510                                 status = "disabled";
1511                         };
1512
1513                         spi8: spi@a80000 {
1514                                 compatible = "qcom,geni-spi";
1515                                 reg = <0 0x00a80000 0 0x4000>;
1516                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1517                                 clock-names = "se";
1518                                 pinctrl-names = "default";
1519                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1520                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1521                                 #address-cells = <1>;
1522                                 #size-cells = <0>;
1523                                 power-domains = <&rpmhpd SC7280_CX>;
1524                                 operating-points-v2 = <&qup_opp_table>;
1525                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1527                                 interconnect-names = "qup-core", "qup-config";
1528                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1529                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1530                                 dma-names = "tx", "rx";
1531                                 status = "disabled";
1532                         };
1533
1534                         uart8: serial@a80000 {
1535                                 compatible = "qcom,geni-uart";
1536                                 reg = <0 0x00a80000 0 0x4000>;
1537                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1538                                 clock-names = "se";
1539                                 pinctrl-names = "default";
1540                                 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1541                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1542                                 power-domains = <&rpmhpd SC7280_CX>;
1543                                 operating-points-v2 = <&qup_opp_table>;
1544                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1545                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1546                                 interconnect-names = "qup-core", "qup-config";
1547                                 status = "disabled";
1548                         };
1549
1550                         i2c9: i2c@a84000 {
1551                                 compatible = "qcom,geni-i2c";
1552                                 reg = <0 0x00a84000 0 0x4000>;
1553                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1554                                 clock-names = "se";
1555                                 pinctrl-names = "default";
1556                                 pinctrl-0 = <&qup_i2c9_data_clk>;
1557                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1558                                 #address-cells = <1>;
1559                                 #size-cells = <0>;
1560                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1561                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1562                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1563                                 interconnect-names = "qup-core", "qup-config",
1564                                                         "qup-memory";
1565                                 power-domains = <&rpmhpd SC7280_CX>;
1566                                 required-opps = <&rpmhpd_opp_low_svs>;
1567                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1568                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1569                                 dma-names = "tx", "rx";
1570                                 status = "disabled";
1571                         };
1572
1573                         spi9: spi@a84000 {
1574                                 compatible = "qcom,geni-spi";
1575                                 reg = <0 0x00a84000 0 0x4000>;
1576                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1577                                 clock-names = "se";
1578                                 pinctrl-names = "default";
1579                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1580                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1581                                 #address-cells = <1>;
1582                                 #size-cells = <0>;
1583                                 power-domains = <&rpmhpd SC7280_CX>;
1584                                 operating-points-v2 = <&qup_opp_table>;
1585                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1586                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1587                                 interconnect-names = "qup-core", "qup-config";
1588                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1589                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1590                                 dma-names = "tx", "rx";
1591                                 status = "disabled";
1592                         };
1593
1594                         uart9: serial@a84000 {
1595                                 compatible = "qcom,geni-uart";
1596                                 reg = <0 0x00a84000 0 0x4000>;
1597                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1598                                 clock-names = "se";
1599                                 pinctrl-names = "default";
1600                                 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1601                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1602                                 power-domains = <&rpmhpd SC7280_CX>;
1603                                 operating-points-v2 = <&qup_opp_table>;
1604                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1605                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1606                                 interconnect-names = "qup-core", "qup-config";
1607                                 status = "disabled";
1608                         };
1609
1610                         i2c10: i2c@a88000 {
1611                                 compatible = "qcom,geni-i2c";
1612                                 reg = <0 0x00a88000 0 0x4000>;
1613                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1614                                 clock-names = "se";
1615                                 pinctrl-names = "default";
1616                                 pinctrl-0 = <&qup_i2c10_data_clk>;
1617                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1618                                 #address-cells = <1>;
1619                                 #size-cells = <0>;
1620                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1621                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1622                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1623                                 interconnect-names = "qup-core", "qup-config",
1624                                                         "qup-memory";
1625                                 power-domains = <&rpmhpd SC7280_CX>;
1626                                 required-opps = <&rpmhpd_opp_low_svs>;
1627                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1628                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1629                                 dma-names = "tx", "rx";
1630                                 status = "disabled";
1631                         };
1632
1633                         spi10: spi@a88000 {
1634                                 compatible = "qcom,geni-spi";
1635                                 reg = <0 0x00a88000 0 0x4000>;
1636                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1637                                 clock-names = "se";
1638                                 pinctrl-names = "default";
1639                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1640                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1641                                 #address-cells = <1>;
1642                                 #size-cells = <0>;
1643                                 power-domains = <&rpmhpd SC7280_CX>;
1644                                 operating-points-v2 = <&qup_opp_table>;
1645                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1647                                 interconnect-names = "qup-core", "qup-config";
1648                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1649                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1650                                 dma-names = "tx", "rx";
1651                                 status = "disabled";
1652                         };
1653
1654                         uart10: serial@a88000 {
1655                                 compatible = "qcom,geni-uart";
1656                                 reg = <0 0x00a88000 0 0x4000>;
1657                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1658                                 clock-names = "se";
1659                                 pinctrl-names = "default";
1660                                 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1661                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1662                                 power-domains = <&rpmhpd SC7280_CX>;
1663                                 operating-points-v2 = <&qup_opp_table>;
1664                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1665                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1666                                 interconnect-names = "qup-core", "qup-config";
1667                                 status = "disabled";
1668                         };
1669
1670                         i2c11: i2c@a8c000 {
1671                                 compatible = "qcom,geni-i2c";
1672                                 reg = <0 0x00a8c000 0 0x4000>;
1673                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1674                                 clock-names = "se";
1675                                 pinctrl-names = "default";
1676                                 pinctrl-0 = <&qup_i2c11_data_clk>;
1677                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1678                                 #address-cells = <1>;
1679                                 #size-cells = <0>;
1680                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1681                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1682                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1683                                 interconnect-names = "qup-core", "qup-config",
1684                                                         "qup-memory";
1685                                 power-domains = <&rpmhpd SC7280_CX>;
1686                                 required-opps = <&rpmhpd_opp_low_svs>;
1687                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1688                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1689                                 dma-names = "tx", "rx";
1690                                 status = "disabled";
1691                         };
1692
1693                         spi11: spi@a8c000 {
1694                                 compatible = "qcom,geni-spi";
1695                                 reg = <0 0x00a8c000 0 0x4000>;
1696                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1697                                 clock-names = "se";
1698                                 pinctrl-names = "default";
1699                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1700                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1701                                 #address-cells = <1>;
1702                                 #size-cells = <0>;
1703                                 power-domains = <&rpmhpd SC7280_CX>;
1704                                 operating-points-v2 = <&qup_opp_table>;
1705                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1706                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1707                                 interconnect-names = "qup-core", "qup-config";
1708                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1709                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1710                                 dma-names = "tx", "rx";
1711                                 status = "disabled";
1712                         };
1713
1714                         uart11: serial@a8c000 {
1715                                 compatible = "qcom,geni-uart";
1716                                 reg = <0 0x00a8c000 0 0x4000>;
1717                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1718                                 clock-names = "se";
1719                                 pinctrl-names = "default";
1720                                 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1721                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1722                                 power-domains = <&rpmhpd SC7280_CX>;
1723                                 operating-points-v2 = <&qup_opp_table>;
1724                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1725                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1726                                 interconnect-names = "qup-core", "qup-config";
1727                                 status = "disabled";
1728                         };
1729
1730                         i2c12: i2c@a90000 {
1731                                 compatible = "qcom,geni-i2c";
1732                                 reg = <0 0x00a90000 0 0x4000>;
1733                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1734                                 clock-names = "se";
1735                                 pinctrl-names = "default";
1736                                 pinctrl-0 = <&qup_i2c12_data_clk>;
1737                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1738                                 #address-cells = <1>;
1739                                 #size-cells = <0>;
1740                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1741                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1742                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1743                                 interconnect-names = "qup-core", "qup-config",
1744                                                         "qup-memory";
1745                                 power-domains = <&rpmhpd SC7280_CX>;
1746                                 required-opps = <&rpmhpd_opp_low_svs>;
1747                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1748                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1749                                 dma-names = "tx", "rx";
1750                                 status = "disabled";
1751                         };
1752
1753                         spi12: spi@a90000 {
1754                                 compatible = "qcom,geni-spi";
1755                                 reg = <0 0x00a90000 0 0x4000>;
1756                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1757                                 clock-names = "se";
1758                                 pinctrl-names = "default";
1759                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1760                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1761                                 #address-cells = <1>;
1762                                 #size-cells = <0>;
1763                                 power-domains = <&rpmhpd SC7280_CX>;
1764                                 operating-points-v2 = <&qup_opp_table>;
1765                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1766                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1767                                 interconnect-names = "qup-core", "qup-config";
1768                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1769                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1770                                 dma-names = "tx", "rx";
1771                                 status = "disabled";
1772                         };
1773
1774                         uart12: serial@a90000 {
1775                                 compatible = "qcom,geni-uart";
1776                                 reg = <0 0x00a90000 0 0x4000>;
1777                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1778                                 clock-names = "se";
1779                                 pinctrl-names = "default";
1780                                 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1781                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1782                                 power-domains = <&rpmhpd SC7280_CX>;
1783                                 operating-points-v2 = <&qup_opp_table>;
1784                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1785                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1786                                 interconnect-names = "qup-core", "qup-config";
1787                                 status = "disabled";
1788                         };
1789
1790                         i2c13: i2c@a94000 {
1791                                 compatible = "qcom,geni-i2c";
1792                                 reg = <0 0x00a94000 0 0x4000>;
1793                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1794                                 clock-names = "se";
1795                                 pinctrl-names = "default";
1796                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1797                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1798                                 #address-cells = <1>;
1799                                 #size-cells = <0>;
1800                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1801                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1802                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1803                                 interconnect-names = "qup-core", "qup-config",
1804                                                         "qup-memory";
1805                                 power-domains = <&rpmhpd SC7280_CX>;
1806                                 required-opps = <&rpmhpd_opp_low_svs>;
1807                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1808                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1809                                 dma-names = "tx", "rx";
1810                                 status = "disabled";
1811                         };
1812
1813                         spi13: spi@a94000 {
1814                                 compatible = "qcom,geni-spi";
1815                                 reg = <0 0x00a94000 0 0x4000>;
1816                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1817                                 clock-names = "se";
1818                                 pinctrl-names = "default";
1819                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1820                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1821                                 #address-cells = <1>;
1822                                 #size-cells = <0>;
1823                                 power-domains = <&rpmhpd SC7280_CX>;
1824                                 operating-points-v2 = <&qup_opp_table>;
1825                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1826                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1827                                 interconnect-names = "qup-core", "qup-config";
1828                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1829                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1830                                 dma-names = "tx", "rx";
1831                                 status = "disabled";
1832                         };
1833
1834                         uart13: serial@a94000 {
1835                                 compatible = "qcom,geni-uart";
1836                                 reg = <0 0x00a94000 0 0x4000>;
1837                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1838                                 clock-names = "se";
1839                                 pinctrl-names = "default";
1840                                 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1841                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1842                                 power-domains = <&rpmhpd SC7280_CX>;
1843                                 operating-points-v2 = <&qup_opp_table>;
1844                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1845                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1846                                 interconnect-names = "qup-core", "qup-config";
1847                                 status = "disabled";
1848                         };
1849
1850                         i2c14: i2c@a98000 {
1851                                 compatible = "qcom,geni-i2c";
1852                                 reg = <0 0x00a98000 0 0x4000>;
1853                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1854                                 clock-names = "se";
1855                                 pinctrl-names = "default";
1856                                 pinctrl-0 = <&qup_i2c14_data_clk>;
1857                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1858                                 #address-cells = <1>;
1859                                 #size-cells = <0>;
1860                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1861                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1862                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1863                                 interconnect-names = "qup-core", "qup-config",
1864                                                         "qup-memory";
1865                                 power-domains = <&rpmhpd SC7280_CX>;
1866                                 required-opps = <&rpmhpd_opp_low_svs>;
1867                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1868                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1869                                 dma-names = "tx", "rx";
1870                                 status = "disabled";
1871                         };
1872
1873                         spi14: spi@a98000 {
1874                                 compatible = "qcom,geni-spi";
1875                                 reg = <0 0x00a98000 0 0x4000>;
1876                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1877                                 clock-names = "se";
1878                                 pinctrl-names = "default";
1879                                 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1880                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1881                                 #address-cells = <1>;
1882                                 #size-cells = <0>;
1883                                 power-domains = <&rpmhpd SC7280_CX>;
1884                                 operating-points-v2 = <&qup_opp_table>;
1885                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1886                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1887                                 interconnect-names = "qup-core", "qup-config";
1888                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1889                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1890                                 dma-names = "tx", "rx";
1891                                 status = "disabled";
1892                         };
1893
1894                         uart14: serial@a98000 {
1895                                 compatible = "qcom,geni-uart";
1896                                 reg = <0 0x00a98000 0 0x4000>;
1897                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1898                                 clock-names = "se";
1899                                 pinctrl-names = "default";
1900                                 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1901                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1902                                 power-domains = <&rpmhpd SC7280_CX>;
1903                                 operating-points-v2 = <&qup_opp_table>;
1904                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1905                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1906                                 interconnect-names = "qup-core", "qup-config";
1907                                 status = "disabled";
1908                         };
1909
1910                         i2c15: i2c@a9c000 {
1911                                 compatible = "qcom,geni-i2c";
1912                                 reg = <0 0x00a9c000 0 0x4000>;
1913                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1914                                 clock-names = "se";
1915                                 pinctrl-names = "default";
1916                                 pinctrl-0 = <&qup_i2c15_data_clk>;
1917                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1918                                 #address-cells = <1>;
1919                                 #size-cells = <0>;
1920                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1921                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1922                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1923                                 interconnect-names = "qup-core", "qup-config",
1924                                                         "qup-memory";
1925                                 power-domains = <&rpmhpd SC7280_CX>;
1926                                 required-opps = <&rpmhpd_opp_low_svs>;
1927                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1928                                        <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1929                                 dma-names = "tx", "rx";
1930                                 status = "disabled";
1931                         };
1932
1933                         spi15: spi@a9c000 {
1934                                 compatible = "qcom,geni-spi";
1935                                 reg = <0 0x00a9c000 0 0x4000>;
1936                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1937                                 clock-names = "se";
1938                                 pinctrl-names = "default";
1939                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1940                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1941                                 #address-cells = <1>;
1942                                 #size-cells = <0>;
1943                                 power-domains = <&rpmhpd SC7280_CX>;
1944                                 operating-points-v2 = <&qup_opp_table>;
1945                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1946                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1947                                 interconnect-names = "qup-core", "qup-config";
1948                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1949                                        <&gpi_dma1 1 7 QCOM_GPI_SPI>;
1950                                 dma-names = "tx", "rx";
1951                                 status = "disabled";
1952                         };
1953
1954                         uart15: serial@a9c000 {
1955                                 compatible = "qcom,geni-uart";
1956                                 reg = <0 0x00a9c000 0 0x4000>;
1957                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1958                                 clock-names = "se";
1959                                 pinctrl-names = "default";
1960                                 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
1961                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1962                                 power-domains = <&rpmhpd SC7280_CX>;
1963                                 operating-points-v2 = <&qup_opp_table>;
1964                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1965                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1966                                 interconnect-names = "qup-core", "qup-config";
1967                                 status = "disabled";
1968                         };
1969                 };
1970
1971                 cnoc2: interconnect@1500000 {
1972                         reg = <0 0x01500000 0 0x1000>;
1973                         compatible = "qcom,sc7280-cnoc2";
1974                         #interconnect-cells = <2>;
1975                         qcom,bcm-voters = <&apps_bcm_voter>;
1976                 };
1977
1978                 cnoc3: interconnect@1502000 {
1979                         reg = <0 0x01502000 0 0x1000>;
1980                         compatible = "qcom,sc7280-cnoc3";
1981                         #interconnect-cells = <2>;
1982                         qcom,bcm-voters = <&apps_bcm_voter>;
1983                 };
1984
1985                 mc_virt: interconnect@1580000 {
1986                         reg = <0 0x01580000 0 0x4>;
1987                         compatible = "qcom,sc7280-mc-virt";
1988                         #interconnect-cells = <2>;
1989                         qcom,bcm-voters = <&apps_bcm_voter>;
1990                 };
1991
1992                 system_noc: interconnect@1680000 {
1993                         reg = <0 0x01680000 0 0x15480>;
1994                         compatible = "qcom,sc7280-system-noc";
1995                         #interconnect-cells = <2>;
1996                         qcom,bcm-voters = <&apps_bcm_voter>;
1997                 };
1998
1999                 aggre1_noc: interconnect@16e0000 {
2000                         compatible = "qcom,sc7280-aggre1-noc";
2001                         reg = <0 0x016e0000 0 0x1c080>;
2002                         #interconnect-cells = <2>;
2003                         qcom,bcm-voters = <&apps_bcm_voter>;
2004                 };
2005
2006                 aggre2_noc: interconnect@1700000 {
2007                         reg = <0 0x01700000 0 0x2b080>;
2008                         compatible = "qcom,sc7280-aggre2-noc";
2009                         #interconnect-cells = <2>;
2010                         qcom,bcm-voters = <&apps_bcm_voter>;
2011                 };
2012
2013                 mmss_noc: interconnect@1740000 {
2014                         reg = <0 0x01740000 0 0x1e080>;
2015                         compatible = "qcom,sc7280-mmss-noc";
2016                         #interconnect-cells = <2>;
2017                         qcom,bcm-voters = <&apps_bcm_voter>;
2018                 };
2019
2020                 wifi: wifi@17a10040 {
2021                         compatible = "qcom,wcn6750-wifi";
2022                         reg = <0 0x17a10040 0 0x0>;
2023                         iommus = <&apps_smmu 0x1c00 0x1>;
2024                         interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
2025                                      <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
2026                                      <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
2027                                      <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
2028                                      <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
2029                                      <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
2030                                      <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
2031                                      <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
2032                                      <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
2033                                      <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
2034                                      <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
2035                                      <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
2036                                      <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
2037                                      <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
2038                                      <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
2039                                      <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
2040                                      <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
2041                                      <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
2042                                      <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
2043                                      <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
2044                                      <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
2045                                      <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
2046                                      <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
2047                                      <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
2048                                      <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
2049                                      <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
2050                                      <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
2051                                      <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
2052                                      <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
2053                                      <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
2054                                      <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
2055                                      <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
2056                         qcom,rproc = <&remoteproc_wpss>;
2057                         memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2058                         status = "disabled";
2059                         qcom,smem-states = <&wlan_smp2p_out 0>;
2060                         qcom,smem-state-names = "wlan-smp2p-out";
2061                 };
2062
2063                 pcie1: pci@1c08000 {
2064                         compatible = "qcom,pcie-sc7280";
2065                         reg = <0 0x01c08000 0 0x3000>,
2066                               <0 0x40000000 0 0xf1d>,
2067                               <0 0x40000f20 0 0xa8>,
2068                               <0 0x40001000 0 0x1000>,
2069                               <0 0x40100000 0 0x100000>;
2070
2071                         reg-names = "parf", "dbi", "elbi", "atu", "config";
2072                         device_type = "pci";
2073                         linux,pci-domain = <1>;
2074                         bus-range = <0x00 0xff>;
2075                         num-lanes = <2>;
2076
2077                         #address-cells = <3>;
2078                         #size-cells = <2>;
2079
2080                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2081                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2082
2083                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2084                         interrupt-names = "msi";
2085                         #interrupt-cells = <1>;
2086                         interrupt-map-mask = <0 0 0 0x7>;
2087                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2088                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2089                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2090                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2091
2092                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2093                                  <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
2094                                  <&pcie1_lane>,
2095                                  <&rpmhcc RPMH_CXO_CLK>,
2096                                  <&gcc GCC_PCIE_1_AUX_CLK>,
2097                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2098                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2099                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2100                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2101                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2102                                  <&gcc GCC_DDRSS_PCIE_SF_CLK>,
2103                                  <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
2104                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
2105
2106                         clock-names = "pipe",
2107                                       "pipe_mux",
2108                                       "phy_pipe",
2109                                       "ref",
2110                                       "aux",
2111                                       "cfg",
2112                                       "bus_master",
2113                                       "bus_slave",
2114                                       "slave_q2a",
2115                                       "tbu",
2116                                       "ddrss_sf_tbu",
2117                                       "aggre0",
2118                                       "aggre1";
2119
2120                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2121                         assigned-clock-rates = <19200000>;
2122
2123                         resets = <&gcc GCC_PCIE_1_BCR>;
2124                         reset-names = "pci";
2125
2126                         power-domains = <&gcc GCC_PCIE_1_GDSC>;
2127
2128                         phys = <&pcie1_lane>;
2129                         phy-names = "pciephy";
2130
2131                         pinctrl-names = "default";
2132                         pinctrl-0 = <&pcie1_clkreq_n>;
2133
2134                         iommus = <&apps_smmu 0x1c80 0x1>;
2135
2136                         iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2137                                     <0x100 &apps_smmu 0x1c81 0x1>;
2138
2139                         status = "disabled";
2140                 };
2141
2142                 pcie1_phy: phy@1c0e000 {
2143                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2144                         reg = <0 0x01c0e000 0 0x1c0>;
2145                         #address-cells = <2>;
2146                         #size-cells = <2>;
2147                         ranges;
2148                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2149                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2150                                  <&gcc GCC_PCIE_CLKREF_EN>,
2151                                  <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2152                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2153
2154                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2155                         reset-names = "phy";
2156
2157                         assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2158                         assigned-clock-rates = <100000000>;
2159
2160                         status = "disabled";
2161
2162                         pcie1_lane: phy@1c0e200 {
2163                                 reg = <0 0x01c0e200 0 0x170>,
2164                                       <0 0x01c0e400 0 0x200>,
2165                                       <0 0x01c0ea00 0 0x1f0>,
2166                                       <0 0x01c0e600 0 0x170>,
2167                                       <0 0x01c0e800 0 0x200>,
2168                                       <0 0x01c0ee00 0 0xf4>;
2169                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2170                                 clock-names = "pipe0";
2171
2172                                 #phy-cells = <0>;
2173                                 #clock-cells = <0>;
2174                                 clock-output-names = "pcie_1_pipe_clk";
2175                         };
2176                 };
2177
2178                 ipa: ipa@1e40000 {
2179                         compatible = "qcom,sc7280-ipa";
2180
2181                         iommus = <&apps_smmu 0x480 0x0>,
2182                                  <&apps_smmu 0x482 0x0>;
2183                         reg = <0 0x01e40000 0 0x8000>,
2184                               <0 0x01e50000 0 0x4ad0>,
2185                               <0 0x01e04000 0 0x23000>;
2186                         reg-names = "ipa-reg",
2187                                     "ipa-shared",
2188                                     "gsi";
2189
2190                         interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2191                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2192                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2193                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2194                         interrupt-names = "ipa",
2195                                           "gsi",
2196                                           "ipa-clock-query",
2197                                           "ipa-setup-ready";
2198
2199                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2200                         clock-names = "core";
2201
2202                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2203                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2204                         interconnect-names = "memory",
2205                                              "config";
2206
2207                         qcom,qmp = <&aoss_qmp>;
2208
2209                         qcom,smem-states = <&ipa_smp2p_out 0>,
2210                                            <&ipa_smp2p_out 1>;
2211                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2212                                                 "ipa-clock-enabled";
2213
2214                         status = "disabled";
2215                 };
2216
2217                 tcsr_mutex: hwlock@1f40000 {
2218                         compatible = "qcom,tcsr-mutex";
2219                         reg = <0 0x01f40000 0 0x20000>;
2220                         #hwlock-cells = <1>;
2221                 };
2222
2223                 tcsr_1: syscon@1f60000 {
2224                         compatible = "qcom,sc7280-tcsr", "syscon";
2225                         reg = <0 0x01f60000 0 0x20000>;
2226                 };
2227
2228                 tcsr_2: syscon@1fc0000 {
2229                         compatible = "qcom,sc7280-tcsr", "syscon";
2230                         reg = <0 0x01fc0000 0 0x30000>;
2231                 };
2232
2233                 lpasscc: lpasscc@3000000 {
2234                         compatible = "qcom,sc7280-lpasscc";
2235                         reg = <0 0x03000000 0 0x40>,
2236                               <0 0x03c04000 0 0x4>;
2237                         reg-names = "qdsp6ss", "top_cc";
2238                         clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
2239                         clock-names = "iface";
2240                         #clock-cells = <1>;
2241                 };
2242
2243                 lpass_rx_macro: codec@3200000 {
2244                         compatible = "qcom,sc7280-lpass-rx-macro";
2245                         reg = <0 0x03200000 0 0x1000>;
2246
2247                         pinctrl-names = "default";
2248                         pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2249
2250                         clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2251                                  <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2252                                  <&lpass_va_macro>;
2253                         clock-names = "mclk", "npl", "fsgen";
2254
2255                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2256                                         <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2257                         power-domain-names = "macro", "dcodec";
2258
2259                         #clock-cells = <0>;
2260                         #sound-dai-cells = <1>;
2261
2262                         status = "disabled";
2263                 };
2264
2265                 swr0: soundwire@3210000 {
2266                         compatible = "qcom,soundwire-v1.6.0";
2267                         reg = <0 0x03210000 0 0x2000>;
2268
2269                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2270                         clocks = <&lpass_rx_macro>;
2271                         clock-names = "iface";
2272
2273                         qcom,din-ports = <0>;
2274                         qcom,dout-ports = <5>;
2275
2276                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2277                         reset-names = "swr_audio_cgcr";
2278
2279                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2280                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2281                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2282                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2283                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2284                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2285                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2286                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2287                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2288
2289                         #sound-dai-cells = <1>;
2290                         #address-cells = <2>;
2291                         #size-cells = <0>;
2292
2293                         status = "disabled";
2294                 };
2295
2296                 lpass_tx_macro: codec@3220000 {
2297                         compatible = "qcom,sc7280-lpass-tx-macro";
2298                         reg = <0 0x03220000 0 0x1000>;
2299
2300                         pinctrl-names = "default";
2301                         pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2302
2303                         clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2304                                  <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2305                                  <&lpass_va_macro>;
2306                         clock-names = "mclk", "npl", "fsgen";
2307
2308                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2309                                         <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2310                         power-domain-names = "macro", "dcodec";
2311
2312                         #clock-cells = <0>;
2313                         #sound-dai-cells = <1>;
2314
2315                         status = "disabled";
2316                 };
2317
2318                 swr1: soundwire@3230000 {
2319                         compatible = "qcom,soundwire-v1.6.0";
2320                         reg = <0 0x03230000 0 0x2000>;
2321
2322                         interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2323                                               <&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
2324                         clocks = <&lpass_tx_macro>;
2325                         clock-names = "iface";
2326
2327                         qcom,din-ports = <3>;
2328                         qcom,dout-ports = <0>;
2329
2330                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;
2331                         reset-names = "swr_audio_cgcr";
2332
2333                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x03 0x03>;
2334                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x00 0x02>;
2335                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00>;
2336                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff>;
2337                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff>;
2338                         qcom,ports-word-length =        /bits/ 8 <0xff 0x00 0xff>;
2339                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff>;
2340                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff>;
2341                         qcom,ports-lane-control =       /bits/ 8 <0x00 0x01 0x00>;
2342
2343                         #sound-dai-cells = <1>;
2344                         #address-cells = <2>;
2345                         #size-cells = <0>;
2346
2347                         status = "disabled";
2348                 };
2349
2350                 lpass_audiocc: clock-controller@3300000 {
2351                         compatible = "qcom,sc7280-lpassaudiocc";
2352                         reg = <0 0x03300000 0 0x30000>,
2353                               <0 0x032a9000 0 0x1000>;
2354                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2355                                <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
2356                         clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2357                         power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2358                         #clock-cells = <1>;
2359                         #power-domain-cells = <1>;
2360                         #reset-cells = <1>;
2361                 };
2362
2363                 lpass_va_macro: codec@3370000 {
2364                         compatible = "qcom,sc7280-lpass-va-macro";
2365                         reg = <0 0x03370000 0 0x1000>;
2366
2367                         pinctrl-names = "default";
2368                         pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2369
2370                         clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>;
2371                         clock-names = "mclk";
2372
2373                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2374                                         <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2375                         power-domain-names = "macro", "dcodec";
2376
2377                         #clock-cells = <0>;
2378                         #sound-dai-cells = <1>;
2379
2380                         status = "disabled";
2381                 };
2382
2383                 lpass_aon: clock-controller@3380000 {
2384                         compatible = "qcom,sc7280-lpassaoncc";
2385                         reg = <0 0x03380000 0 0x30000>;
2386                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2387                                <&rpmhcc RPMH_CXO_CLK_A>,
2388                                <&lpass_core LPASS_CORE_CC_CORE_CLK>;
2389                         clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2390                         #clock-cells = <1>;
2391                         #power-domain-cells = <1>;
2392                 };
2393
2394                 lpass_core: clock-controller@3900000 {
2395                         compatible = "qcom,sc7280-lpasscorecc";
2396                         reg = <0 0x03900000 0 0x50000>;
2397                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2398                         clock-names = "bi_tcxo";
2399                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2400                         #clock-cells = <1>;
2401                         #power-domain-cells = <1>;
2402                 };
2403
2404                 lpass_cpu: audio@3987000 {
2405                         compatible = "qcom,sc7280-lpass-cpu";
2406
2407                         reg = <0 0x03987000 0 0x68000>,
2408                               <0 0x03b00000 0 0x29000>,
2409                               <0 0x03260000 0 0xc000>,
2410                               <0 0x03280000 0 0x29000>,
2411                               <0 0x03340000 0 0x29000>,
2412                               <0 0x0336c000 0 0x3000>;
2413                         reg-names = "lpass-hdmiif",
2414                                     "lpass-lpaif",
2415                                     "lpass-rxtx-cdc-dma-lpm",
2416                                     "lpass-rxtx-lpaif",
2417                                     "lpass-va-lpaif",
2418                                     "lpass-va-cdc-dma-lpm";
2419
2420                         iommus = <&apps_smmu 0x1820 0>,
2421                                  <&apps_smmu 0x1821 0>,
2422                                  <&apps_smmu 0x1832 0>;
2423
2424                         power-domains = <&rpmhpd SC7280_LCX>;
2425                         power-domain-names = "lcx";
2426                         required-opps = <&rpmhpd_opp_nom>;
2427
2428                         clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>,
2429                                  <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>,
2430                                  <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>,
2431                                  <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>,
2432                                  <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>,
2433                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>,
2434                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>,
2435                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>,
2436                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>,
2437                                  <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>;
2438                         clock-names = "aon_cc_audio_hm_h",
2439                                       "audio_cc_ext_mclk0",
2440                                       "core_cc_sysnoc_mport_core",
2441                                       "core_cc_ext_if0_ibit",
2442                                       "core_cc_ext_if1_ibit",
2443                                       "audio_cc_codec_mem",
2444                                       "audio_cc_codec_mem0",
2445                                       "audio_cc_codec_mem1",
2446                                       "audio_cc_codec_mem2",
2447                                       "aon_cc_va_mem0";
2448
2449                         #sound-dai-cells = <1>;
2450                         #address-cells = <1>;
2451                         #size-cells = <0>;
2452
2453                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
2454                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2455                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
2456                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
2457                         interrupt-names = "lpass-irq-lpaif",
2458                                           "lpass-irq-hdmi",
2459                                           "lpass-irq-vaif",
2460                                           "lpass-irq-rxtxif";
2461
2462                         status = "disabled";
2463                 };
2464
2465                 lpass_hm: clock-controller@3c00000 {
2466                         compatible = "qcom,sc7280-lpasshm";
2467                         reg = <0 0x03c00000 0 0x28>;
2468                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2469                         clock-names = "bi_tcxo";
2470                         #clock-cells = <1>;
2471                         #power-domain-cells = <1>;
2472                 };
2473
2474                 lpass_ag_noc: interconnect@3c40000 {
2475                         reg = <0 0x03c40000 0 0xf080>;
2476                         compatible = "qcom,sc7280-lpass-ag-noc";
2477                         #interconnect-cells = <2>;
2478                         qcom,bcm-voters = <&apps_bcm_voter>;
2479                 };
2480
2481                 lpass_tlmm: pinctrl@33c0000 {
2482                         compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2483                         reg = <0 0x033c0000 0x0 0x20000>,
2484                                 <0 0x03550000 0x0 0x10000>;
2485                         qcom,adsp-bypass-mode;
2486                         gpio-controller;
2487                         #gpio-cells = <2>;
2488                         gpio-ranges = <&lpass_tlmm 0 0 15>;
2489
2490                         lpass_dmic01_clk: dmic01-clk-state {
2491                                 pins = "gpio6";
2492                                 function = "dmic1_clk";
2493                         };
2494
2495                         lpass_dmic01_data: dmic01-data-state {
2496                                 pins = "gpio7";
2497                                 function = "dmic1_data";
2498                         };
2499
2500                         lpass_dmic23_clk: dmic23-clk-state {
2501                                 pins = "gpio8";
2502                                 function = "dmic2_clk";
2503                         };
2504
2505                         lpass_dmic23_data: dmic23-data-state {
2506                                 pins = "gpio9";
2507                                 function = "dmic2_data";
2508                         };
2509
2510                         lpass_rx_swr_clk: rx-swr-clk-state {
2511                                 pins = "gpio3";
2512                                 function = "swr_rx_clk";
2513                         };
2514
2515                         lpass_rx_swr_data: rx-swr-data-state {
2516                                 pins = "gpio4", "gpio5";
2517                                 function = "swr_rx_data";
2518                         };
2519
2520                         lpass_tx_swr_clk: tx-swr-clk-state {
2521                                 pins = "gpio0";
2522                                 function = "swr_tx_clk";
2523                         };
2524
2525                         lpass_tx_swr_data: tx-swr-data-state {
2526                                 pins = "gpio1", "gpio2", "gpio14";
2527                                 function = "swr_tx_data";
2528                         };
2529                 };
2530
2531                 gpu: gpu@3d00000 {
2532                         compatible = "qcom,adreno-635.0", "qcom,adreno";
2533                         reg = <0 0x03d00000 0 0x40000>,
2534                               <0 0x03d9e000 0 0x1000>,
2535                               <0 0x03d61000 0 0x800>;
2536                         reg-names = "kgsl_3d0_reg_memory",
2537                                     "cx_mem",
2538                                     "cx_dbgc";
2539                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2540                         iommus = <&adreno_smmu 0 0x401>;
2541                         operating-points-v2 = <&gpu_opp_table>;
2542                         qcom,gmu = <&gmu>;
2543                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2544                         interconnect-names = "gfx-mem";
2545                         #cooling-cells = <2>;
2546
2547                         nvmem-cells = <&gpu_speed_bin>;
2548                         nvmem-cell-names = "speed_bin";
2549
2550                         gpu_opp_table: opp-table {
2551                                 compatible = "operating-points-v2";
2552
2553                                 opp-315000000 {
2554                                         opp-hz = /bits/ 64 <315000000>;
2555                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2556                                         opp-peak-kBps = <1804000>;
2557                                         opp-supported-hw = <0x03>;
2558                                 };
2559
2560                                 opp-450000000 {
2561                                         opp-hz = /bits/ 64 <450000000>;
2562                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2563                                         opp-peak-kBps = <4068000>;
2564                                         opp-supported-hw = <0x03>;
2565                                 };
2566
2567                                 /* Only applicable for SKUs which has 550Mhz as Fmax */
2568                                 opp-550000000-0 {
2569                                         opp-hz = /bits/ 64 <550000000>;
2570                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2571                                         opp-peak-kBps = <8368000>;
2572                                         opp-supported-hw = <0x01>;
2573                                 };
2574
2575                                 opp-550000000-1 {
2576                                         opp-hz = /bits/ 64 <550000000>;
2577                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2578                                         opp-peak-kBps = <6832000>;
2579                                         opp-supported-hw = <0x02>;
2580                                 };
2581
2582                                 opp-608000000 {
2583                                         opp-hz = /bits/ 64 <608000000>;
2584                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2585                                         opp-peak-kBps = <8368000>;
2586                                         opp-supported-hw = <0x02>;
2587                                 };
2588
2589                                 opp-700000000 {
2590                                         opp-hz = /bits/ 64 <700000000>;
2591                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2592                                         opp-peak-kBps = <8532000>;
2593                                         opp-supported-hw = <0x02>;
2594                                 };
2595
2596                                 opp-812000000 {
2597                                         opp-hz = /bits/ 64 <812000000>;
2598                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2599                                         opp-peak-kBps = <8532000>;
2600                                         opp-supported-hw = <0x02>;
2601                                 };
2602
2603                                 opp-840000000 {
2604                                         opp-hz = /bits/ 64 <840000000>;
2605                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2606                                         opp-peak-kBps = <8532000>;
2607                                         opp-supported-hw = <0x02>;
2608                                 };
2609
2610                                 opp-900000000 {
2611                                         opp-hz = /bits/ 64 <900000000>;
2612                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2613                                         opp-peak-kBps = <8532000>;
2614                                         opp-supported-hw = <0x02>;
2615                                 };
2616                         };
2617                 };
2618
2619                 gmu: gmu@3d6a000 {
2620                         compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2621                         reg = <0 0x03d6a000 0 0x34000>,
2622                                 <0 0x3de0000 0 0x10000>,
2623                                 <0 0x0b290000 0 0x10000>;
2624                         reg-names = "gmu", "rscc", "gmu_pdc";
2625                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2626                                         <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2627                         interrupt-names = "hfi", "gmu";
2628                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2629                                  <&gpucc GPU_CC_CXO_CLK>,
2630                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2631                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2632                                  <&gpucc GPU_CC_AHB_CLK>,
2633                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2634                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2635                         clock-names = "gmu",
2636                                       "cxo",
2637                                       "axi",
2638                                       "memnoc",
2639                                       "ahb",
2640                                       "hub",
2641                                       "smmu_vote";
2642                         power-domains = <&gpucc GPU_CC_CX_GDSC>,
2643                                         <&gpucc GPU_CC_GX_GDSC>;
2644                         power-domain-names = "cx",
2645                                              "gx";
2646                         iommus = <&adreno_smmu 5 0x400>;
2647                         operating-points-v2 = <&gmu_opp_table>;
2648
2649                         gmu_opp_table: opp-table {
2650                                 compatible = "operating-points-v2";
2651
2652                                 opp-200000000 {
2653                                         opp-hz = /bits/ 64 <200000000>;
2654                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2655                                 };
2656                         };
2657                 };
2658
2659                 gpucc: clock-controller@3d90000 {
2660                         compatible = "qcom,sc7280-gpucc";
2661                         reg = <0 0x03d90000 0 0x9000>;
2662                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2663                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2664                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2665                         clock-names = "bi_tcxo",
2666                                       "gcc_gpu_gpll0_clk_src",
2667                                       "gcc_gpu_gpll0_div_clk_src";
2668                         #clock-cells = <1>;
2669                         #reset-cells = <1>;
2670                         #power-domain-cells = <1>;
2671                 };
2672
2673                 dma@117f000 {
2674                         compatible = "qcom,sc7280-dcc", "qcom,dcc";
2675                         reg = <0x0 0x0117f000 0x0 0x1000>,
2676                               <0x0 0x01112000 0x0 0x6000>;
2677                 };
2678
2679                 adreno_smmu: iommu@3da0000 {
2680                         compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2681                         reg = <0 0x03da0000 0 0x20000>;
2682                         #iommu-cells = <2>;
2683                         #global-interrupts = <2>;
2684                         interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2685                                         <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
2686                                         <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2687                                         <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2688                                         <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2689                                         <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2690                                         <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2691                                         <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2692                                         <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2693                                         <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2694                                         <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2695                                         <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
2696
2697                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2698                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2699                                  <&gpucc GPU_CC_AHB_CLK>,
2700                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2701                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2702                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2703                                  <&gpucc GPU_CC_HUB_AON_CLK>;
2704                         clock-names = "gcc_gpu_memnoc_gfx_clk",
2705                                         "gcc_gpu_snoc_dvm_gfx_clk",
2706                                         "gpu_cc_ahb_clk",
2707                                         "gpu_cc_hlos1_vote_gpu_smmu_clk",
2708                                         "gpu_cc_cx_gmu_clk",
2709                                         "gpu_cc_hub_cx_int_clk",
2710                                         "gpu_cc_hub_aon_clk";
2711
2712                         power-domains = <&gpucc GPU_CC_CX_GDSC>;
2713                 };
2714
2715                 remoteproc_mpss: remoteproc@4080000 {
2716                         compatible = "qcom,sc7280-mpss-pas";
2717                         reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
2718                         reg-names = "qdsp6", "rmb";
2719
2720                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2721                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2722                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2723                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2724                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2725                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2726                         interrupt-names = "wdog", "fatal", "ready", "handover",
2727                                           "stop-ack", "shutdown-ack";
2728
2729                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2730                         clock-names = "xo";
2731
2732                         power-domains = <&rpmhpd SC7280_CX>,
2733                                         <&rpmhpd SC7280_MSS>;
2734                         power-domain-names = "cx", "mss";
2735
2736                         memory-region = <&mpss_mem>;
2737
2738                         qcom,qmp = <&aoss_qmp>;
2739
2740                         qcom,smem-states = <&modem_smp2p_out 0>;
2741                         qcom,smem-state-names = "stop";
2742
2743                         status = "disabled";
2744
2745                         glink-edge {
2746                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2747                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2748                                                              IRQ_TYPE_EDGE_RISING>;
2749                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2750                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2751                                 label = "modem";
2752                                 qcom,remote-pid = <1>;
2753                         };
2754                 };
2755
2756                 stm@6002000 {
2757                         compatible = "arm,coresight-stm", "arm,primecell";
2758                         reg = <0 0x06002000 0 0x1000>,
2759                               <0 0x16280000 0 0x180000>;
2760                         reg-names = "stm-base", "stm-stimulus-base";
2761
2762                         clocks = <&aoss_qmp>;
2763                         clock-names = "apb_pclk";
2764
2765                         out-ports {
2766                                 port {
2767                                         stm_out: endpoint {
2768                                                 remote-endpoint = <&funnel0_in7>;
2769                                         };
2770                                 };
2771                         };
2772                 };
2773
2774                 funnel@6041000 {
2775                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2776                         reg = <0 0x06041000 0 0x1000>;
2777
2778                         clocks = <&aoss_qmp>;
2779                         clock-names = "apb_pclk";
2780
2781                         out-ports {
2782                                 port {
2783                                         funnel0_out: endpoint {
2784                                                 remote-endpoint = <&merge_funnel_in0>;
2785                                         };
2786                                 };
2787                         };
2788
2789                         in-ports {
2790                                 #address-cells = <1>;
2791                                 #size-cells = <0>;
2792
2793                                 port@7 {
2794                                         reg = <7>;
2795                                         funnel0_in7: endpoint {
2796                                                 remote-endpoint = <&stm_out>;
2797                                         };
2798                                 };
2799                         };
2800                 };
2801
2802                 funnel@6042000 {
2803                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2804                         reg = <0 0x06042000 0 0x1000>;
2805
2806                         clocks = <&aoss_qmp>;
2807                         clock-names = "apb_pclk";
2808
2809                         out-ports {
2810                                 port {
2811                                         funnel1_out: endpoint {
2812                                                 remote-endpoint = <&merge_funnel_in1>;
2813                                         };
2814                                 };
2815                         };
2816
2817                         in-ports {
2818                                 #address-cells = <1>;
2819                                 #size-cells = <0>;
2820
2821                                 port@4 {
2822                                         reg = <4>;
2823                                         funnel1_in4: endpoint {
2824                                                 remote-endpoint = <&apss_merge_funnel_out>;
2825                                         };
2826                                 };
2827                         };
2828                 };
2829
2830                 funnel@6045000 {
2831                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2832                         reg = <0 0x06045000 0 0x1000>;
2833
2834                         clocks = <&aoss_qmp>;
2835                         clock-names = "apb_pclk";
2836
2837                         out-ports {
2838                                 port {
2839                                         merge_funnel_out: endpoint {
2840                                                 remote-endpoint = <&swao_funnel_in>;
2841                                         };
2842                                 };
2843                         };
2844
2845                         in-ports {
2846                                 #address-cells = <1>;
2847                                 #size-cells = <0>;
2848
2849                                 port@0 {
2850                                         reg = <0>;
2851                                         merge_funnel_in0: endpoint {
2852                                                 remote-endpoint = <&funnel0_out>;
2853                                         };
2854                                 };
2855
2856                                 port@1 {
2857                                         reg = <1>;
2858                                         merge_funnel_in1: endpoint {
2859                                                 remote-endpoint = <&funnel1_out>;
2860                                         };
2861                                 };
2862                         };
2863                 };
2864
2865                 replicator@6046000 {
2866                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2867                         reg = <0 0x06046000 0 0x1000>;
2868
2869                         clocks = <&aoss_qmp>;
2870                         clock-names = "apb_pclk";
2871
2872                         out-ports {
2873                                 port {
2874                                         replicator_out: endpoint {
2875                                                 remote-endpoint = <&etr_in>;
2876                                         };
2877                                 };
2878                         };
2879
2880                         in-ports {
2881                                 port {
2882                                         replicator_in: endpoint {
2883                                                 remote-endpoint = <&swao_replicator_out>;
2884                                         };
2885                                 };
2886                         };
2887                 };
2888
2889                 etr@6048000 {
2890                         compatible = "arm,coresight-tmc", "arm,primecell";
2891                         reg = <0 0x06048000 0 0x1000>;
2892                         iommus = <&apps_smmu 0x04c0 0>;
2893
2894                         clocks = <&aoss_qmp>;
2895                         clock-names = "apb_pclk";
2896                         arm,scatter-gather;
2897
2898                         in-ports {
2899                                 port {
2900                                         etr_in: endpoint {
2901                                                 remote-endpoint = <&replicator_out>;
2902                                         };
2903                                 };
2904                         };
2905                 };
2906
2907                 funnel@6b04000 {
2908                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2909                         reg = <0 0x06b04000 0 0x1000>;
2910
2911                         clocks = <&aoss_qmp>;
2912                         clock-names = "apb_pclk";
2913
2914                         out-ports {
2915                                 port {
2916                                         swao_funnel_out: endpoint {
2917                                                 remote-endpoint = <&etf_in>;
2918                                         };
2919                                 };
2920                         };
2921
2922                         in-ports {
2923                                 #address-cells = <1>;
2924                                 #size-cells = <0>;
2925
2926                                 port@7 {
2927                                         reg = <7>;
2928                                         swao_funnel_in: endpoint {
2929                                                 remote-endpoint = <&merge_funnel_out>;
2930                                         };
2931                                 };
2932                         };
2933                 };
2934
2935                 etf@6b05000 {
2936                         compatible = "arm,coresight-tmc", "arm,primecell";
2937                         reg = <0 0x06b05000 0 0x1000>;
2938
2939                         clocks = <&aoss_qmp>;
2940                         clock-names = "apb_pclk";
2941
2942                         out-ports {
2943                                 port {
2944                                         etf_out: endpoint {
2945                                                 remote-endpoint = <&swao_replicator_in>;
2946                                         };
2947                                 };
2948                         };
2949
2950                         in-ports {
2951                                 port {
2952                                         etf_in: endpoint {
2953                                                 remote-endpoint = <&swao_funnel_out>;
2954                                         };
2955                                 };
2956                         };
2957                 };
2958
2959                 replicator@6b06000 {
2960                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2961                         reg = <0 0x06b06000 0 0x1000>;
2962
2963                         clocks = <&aoss_qmp>;
2964                         clock-names = "apb_pclk";
2965                         qcom,replicator-loses-context;
2966
2967                         out-ports {
2968                                 port {
2969                                         swao_replicator_out: endpoint {
2970                                                 remote-endpoint = <&replicator_in>;
2971                                         };
2972                                 };
2973                         };
2974
2975                         in-ports {
2976                                 port {
2977                                         swao_replicator_in: endpoint {
2978                                                 remote-endpoint = <&etf_out>;
2979                                         };
2980                                 };
2981                         };
2982                 };
2983
2984                 etm@7040000 {
2985                         compatible = "arm,coresight-etm4x", "arm,primecell";
2986                         reg = <0 0x07040000 0 0x1000>;
2987
2988                         cpu = <&CPU0>;
2989
2990                         clocks = <&aoss_qmp>;
2991                         clock-names = "apb_pclk";
2992                         arm,coresight-loses-context-with-cpu;
2993                         qcom,skip-power-up;
2994
2995                         out-ports {
2996                                 port {
2997                                         etm0_out: endpoint {
2998                                                 remote-endpoint = <&apss_funnel_in0>;
2999                                         };
3000                                 };
3001                         };
3002                 };
3003
3004                 etm@7140000 {
3005                         compatible = "arm,coresight-etm4x", "arm,primecell";
3006                         reg = <0 0x07140000 0 0x1000>;
3007
3008                         cpu = <&CPU1>;
3009
3010                         clocks = <&aoss_qmp>;
3011                         clock-names = "apb_pclk";
3012                         arm,coresight-loses-context-with-cpu;
3013                         qcom,skip-power-up;
3014
3015                         out-ports {
3016                                 port {
3017                                         etm1_out: endpoint {
3018                                                 remote-endpoint = <&apss_funnel_in1>;
3019                                         };
3020                                 };
3021                         };
3022                 };
3023
3024                 etm@7240000 {
3025                         compatible = "arm,coresight-etm4x", "arm,primecell";
3026                         reg = <0 0x07240000 0 0x1000>;
3027
3028                         cpu = <&CPU2>;
3029
3030                         clocks = <&aoss_qmp>;
3031                         clock-names = "apb_pclk";
3032                         arm,coresight-loses-context-with-cpu;
3033                         qcom,skip-power-up;
3034
3035                         out-ports {
3036                                 port {
3037                                         etm2_out: endpoint {
3038                                                 remote-endpoint = <&apss_funnel_in2>;
3039                                         };
3040                                 };
3041                         };
3042                 };
3043
3044                 etm@7340000 {
3045                         compatible = "arm,coresight-etm4x", "arm,primecell";
3046                         reg = <0 0x07340000 0 0x1000>;
3047
3048                         cpu = <&CPU3>;
3049
3050                         clocks = <&aoss_qmp>;
3051                         clock-names = "apb_pclk";
3052                         arm,coresight-loses-context-with-cpu;
3053                         qcom,skip-power-up;
3054
3055                         out-ports {
3056                                 port {
3057                                         etm3_out: endpoint {
3058                                                 remote-endpoint = <&apss_funnel_in3>;
3059                                         };
3060                                 };
3061                         };
3062                 };
3063
3064                 etm@7440000 {
3065                         compatible = "arm,coresight-etm4x", "arm,primecell";
3066                         reg = <0 0x07440000 0 0x1000>;
3067
3068                         cpu = <&CPU4>;
3069
3070                         clocks = <&aoss_qmp>;
3071                         clock-names = "apb_pclk";
3072                         arm,coresight-loses-context-with-cpu;
3073                         qcom,skip-power-up;
3074
3075                         out-ports {
3076                                 port {
3077                                         etm4_out: endpoint {
3078                                                 remote-endpoint = <&apss_funnel_in4>;
3079                                         };
3080                                 };
3081                         };
3082                 };
3083
3084                 etm@7540000 {
3085                         compatible = "arm,coresight-etm4x", "arm,primecell";
3086                         reg = <0 0x07540000 0 0x1000>;
3087
3088                         cpu = <&CPU5>;
3089
3090                         clocks = <&aoss_qmp>;
3091                         clock-names = "apb_pclk";
3092                         arm,coresight-loses-context-with-cpu;
3093                         qcom,skip-power-up;
3094
3095                         out-ports {
3096                                 port {
3097                                         etm5_out: endpoint {
3098                                                 remote-endpoint = <&apss_funnel_in5>;
3099                                         };
3100                                 };
3101                         };
3102                 };
3103
3104                 etm@7640000 {
3105                         compatible = "arm,coresight-etm4x", "arm,primecell";
3106                         reg = <0 0x07640000 0 0x1000>;
3107
3108                         cpu = <&CPU6>;
3109
3110                         clocks = <&aoss_qmp>;
3111                         clock-names = "apb_pclk";
3112                         arm,coresight-loses-context-with-cpu;
3113                         qcom,skip-power-up;
3114
3115                         out-ports {
3116                                 port {
3117                                         etm6_out: endpoint {
3118                                                 remote-endpoint = <&apss_funnel_in6>;
3119                                         };
3120                                 };
3121                         };
3122                 };
3123
3124                 etm@7740000 {
3125                         compatible = "arm,coresight-etm4x", "arm,primecell";
3126                         reg = <0 0x07740000 0 0x1000>;
3127
3128                         cpu = <&CPU7>;
3129
3130                         clocks = <&aoss_qmp>;
3131                         clock-names = "apb_pclk";
3132                         arm,coresight-loses-context-with-cpu;
3133                         qcom,skip-power-up;
3134
3135                         out-ports {
3136                                 port {
3137                                         etm7_out: endpoint {
3138                                                 remote-endpoint = <&apss_funnel_in7>;
3139                                         };
3140                                 };
3141                         };
3142                 };
3143
3144                 funnel@7800000 { /* APSS Funnel */
3145                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3146                         reg = <0 0x07800000 0 0x1000>;
3147
3148                         clocks = <&aoss_qmp>;
3149                         clock-names = "apb_pclk";
3150
3151                         out-ports {
3152                                 port {
3153                                         apss_funnel_out: endpoint {
3154                                                 remote-endpoint = <&apss_merge_funnel_in>;
3155                                         };
3156                                 };
3157                         };
3158
3159                         in-ports {
3160                                 #address-cells = <1>;
3161                                 #size-cells = <0>;
3162
3163                                 port@0 {
3164                                         reg = <0>;
3165                                         apss_funnel_in0: endpoint {
3166                                                 remote-endpoint = <&etm0_out>;
3167                                         };
3168                                 };
3169
3170                                 port@1 {
3171                                         reg = <1>;
3172                                         apss_funnel_in1: endpoint {
3173                                                 remote-endpoint = <&etm1_out>;
3174                                         };
3175                                 };
3176
3177                                 port@2 {
3178                                         reg = <2>;
3179                                         apss_funnel_in2: endpoint {
3180                                                 remote-endpoint = <&etm2_out>;
3181                                         };
3182                                 };
3183
3184                                 port@3 {
3185                                         reg = <3>;
3186                                         apss_funnel_in3: endpoint {
3187                                                 remote-endpoint = <&etm3_out>;
3188                                         };
3189                                 };
3190
3191                                 port@4 {
3192                                         reg = <4>;
3193                                         apss_funnel_in4: endpoint {
3194                                                 remote-endpoint = <&etm4_out>;
3195                                         };
3196                                 };
3197
3198                                 port@5 {
3199                                         reg = <5>;
3200                                         apss_funnel_in5: endpoint {
3201                                                 remote-endpoint = <&etm5_out>;
3202                                         };
3203                                 };
3204
3205                                 port@6 {
3206                                         reg = <6>;
3207                                         apss_funnel_in6: endpoint {
3208                                                 remote-endpoint = <&etm6_out>;
3209                                         };
3210                                 };
3211
3212                                 port@7 {
3213                                         reg = <7>;
3214                                         apss_funnel_in7: endpoint {
3215                                                 remote-endpoint = <&etm7_out>;
3216                                         };
3217                                 };
3218                         };
3219                 };
3220
3221                 funnel@7810000 {
3222                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3223                         reg = <0 0x07810000 0 0x1000>;
3224
3225                         clocks = <&aoss_qmp>;
3226                         clock-names = "apb_pclk";
3227
3228                         out-ports {
3229                                 port {
3230                                         apss_merge_funnel_out: endpoint {
3231                                                 remote-endpoint = <&funnel1_in4>;
3232                                         };
3233                                 };
3234                         };
3235
3236                         in-ports {
3237                                 port {
3238                                         apss_merge_funnel_in: endpoint {
3239                                                 remote-endpoint = <&apss_funnel_out>;
3240                                         };
3241                                 };
3242                         };
3243                 };
3244
3245                 sdhc_2: mmc@8804000 {
3246                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3247                         pinctrl-names = "default", "sleep";
3248                         pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3249                         pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3250                         status = "disabled";
3251
3252                         reg = <0 0x08804000 0 0x1000>;
3253
3254                         iommus = <&apps_smmu 0x100 0x0>;
3255                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3256                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3257                         interrupt-names = "hc_irq", "pwr_irq";
3258
3259                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3260                                  <&gcc GCC_SDCC2_APPS_CLK>,
3261                                  <&rpmhcc RPMH_CXO_CLK>;
3262                         clock-names = "iface", "core", "xo";
3263                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3264                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3265                         interconnect-names = "sdhc-ddr","cpu-sdhc";
3266                         power-domains = <&rpmhpd SC7280_CX>;
3267                         operating-points-v2 = <&sdhc2_opp_table>;
3268
3269                         bus-width = <4>;
3270
3271                         qcom,dll-config = <0x0007642c>;
3272
3273                         resets = <&gcc GCC_SDCC2_BCR>;
3274
3275                         sdhc2_opp_table: opp-table {
3276                                 compatible = "operating-points-v2";
3277
3278                                 opp-100000000 {
3279                                         opp-hz = /bits/ 64 <100000000>;
3280                                         required-opps = <&rpmhpd_opp_low_svs>;
3281                                         opp-peak-kBps = <1800000 400000>;
3282                                         opp-avg-kBps = <100000 0>;
3283                                 };
3284
3285                                 opp-202000000 {
3286                                         opp-hz = /bits/ 64 <202000000>;
3287                                         required-opps = <&rpmhpd_opp_nom>;
3288                                         opp-peak-kBps = <5400000 1600000>;
3289                                         opp-avg-kBps = <200000 0>;
3290                                 };
3291                         };
3292
3293                 };
3294
3295                 usb_1_hsphy: phy@88e3000 {
3296                         compatible = "qcom,sc7280-usb-hs-phy",
3297                                      "qcom,usb-snps-hs-7nm-phy";
3298                         reg = <0 0x088e3000 0 0x400>;
3299                         status = "disabled";
3300                         #phy-cells = <0>;
3301
3302                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3303                         clock-names = "ref";
3304
3305                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3306                 };
3307
3308                 usb_2_hsphy: phy@88e4000 {
3309                         compatible = "qcom,sc7280-usb-hs-phy",
3310                                      "qcom,usb-snps-hs-7nm-phy";
3311                         reg = <0 0x088e4000 0 0x400>;
3312                         status = "disabled";
3313                         #phy-cells = <0>;
3314
3315                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3316                         clock-names = "ref";
3317
3318                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3319                 };
3320
3321                 usb_1_qmpphy: phy-wrapper@88e9000 {
3322                         compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3323                                      "qcom,sm8250-qmp-usb3-dp-phy";
3324                         reg = <0 0x088e9000 0 0x200>,
3325                               <0 0x088e8000 0 0x40>,
3326                               <0 0x088ea000 0 0x200>;
3327                         status = "disabled";
3328                         #address-cells = <2>;
3329                         #size-cells = <2>;
3330                         ranges;
3331
3332                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3333                                  <&rpmhcc RPMH_CXO_CLK>,
3334                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3335                         clock-names = "aux", "ref_clk_src", "com_aux";
3336
3337                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3338                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3339                         reset-names = "phy", "common";
3340
3341                         usb_1_ssphy: usb3-phy@88e9200 {
3342                                 reg = <0 0x088e9200 0 0x200>,
3343                                       <0 0x088e9400 0 0x200>,
3344                                       <0 0x088e9c00 0 0x400>,
3345                                       <0 0x088e9600 0 0x200>,
3346                                       <0 0x088e9800 0 0x200>,
3347                                       <0 0x088e9a00 0 0x100>;
3348                                 #clock-cells = <0>;
3349                                 #phy-cells = <0>;
3350                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3351                                 clock-names = "pipe0";
3352                                 clock-output-names = "usb3_phy_pipe_clk_src";
3353                         };
3354
3355                         dp_phy: dp-phy@88ea200 {
3356                                 reg = <0 0x088ea200 0 0x200>,
3357                                       <0 0x088ea400 0 0x200>,
3358                                       <0 0x088eaa00 0 0x200>,
3359                                       <0 0x088ea600 0 0x200>,
3360                                       <0 0x088ea800 0 0x200>;
3361                                 #phy-cells = <0>;
3362                                 #clock-cells = <1>;
3363                         };
3364                 };
3365
3366                 usb_2: usb@8cf8800 {
3367                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3368                         reg = <0 0x08cf8800 0 0x400>;
3369                         status = "disabled";
3370                         #address-cells = <2>;
3371                         #size-cells = <2>;
3372                         ranges;
3373                         dma-ranges;
3374
3375                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3376                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3377                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3378                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3379                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
3380                         clock-names = "cfg_noc",
3381                                       "core",
3382                                       "iface",
3383                                       "sleep",
3384                                       "mock_utmi";
3385
3386                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3387                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3388                         assigned-clock-rates = <19200000>, <200000000>;
3389
3390                         interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
3391                                               <&pdc 12 IRQ_TYPE_EDGE_RISING>,
3392                                               <&pdc 13 IRQ_TYPE_EDGE_RISING>;
3393                         interrupt-names = "hs_phy_irq",
3394                                           "dp_hs_phy_irq",
3395                                           "dm_hs_phy_irq";
3396
3397                         power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3398                         required-opps = <&rpmhpd_opp_nom>;
3399
3400                         resets = <&gcc GCC_USB30_SEC_BCR>;
3401
3402                         interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3403                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3404                         interconnect-names = "usb-ddr", "apps-usb";
3405
3406                         usb_2_dwc3: usb@8c00000 {
3407                                 compatible = "snps,dwc3";
3408                                 reg = <0 0x08c00000 0 0xe000>;
3409                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
3410                                 iommus = <&apps_smmu 0xa0 0x0>;
3411                                 snps,dis_u2_susphy_quirk;
3412                                 snps,dis_enblslpm_quirk;
3413                                 phys = <&usb_2_hsphy>;
3414                                 phy-names = "usb2-phy";
3415                                 maximum-speed = "high-speed";
3416                                 usb-role-switch;
3417                                 port {
3418                                         usb2_role_switch: endpoint {
3419                                                 remote-endpoint = <&eud_ep>;
3420                                         };
3421                                 };
3422                         };
3423                 };
3424
3425                 qspi: spi@88dc000 {
3426                         compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3427                         reg = <0 0x088dc000 0 0x1000>;
3428                         #address-cells = <1>;
3429                         #size-cells = <0>;
3430                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3431                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3432                                  <&gcc GCC_QSPI_CORE_CLK>;
3433                         clock-names = "iface", "core";
3434                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
3435                                         &cnoc2 SLAVE_QSPI_0 0>;
3436                         interconnect-names = "qspi-config";
3437                         power-domains = <&rpmhpd SC7280_CX>;
3438                         operating-points-v2 = <&qspi_opp_table>;
3439                         status = "disabled";
3440                 };
3441
3442                 remoteproc_wpss: remoteproc@8a00000 {
3443                         compatible = "qcom,sc7280-wpss-pil";
3444                         reg = <0 0x08a00000 0 0x10000>;
3445
3446                         interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3447                                               <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3448                                               <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3449                                               <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3450                                               <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3451                                               <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3452                         interrupt-names = "wdog", "fatal", "ready", "handover",
3453                                           "stop-ack", "shutdown-ack";
3454
3455                         clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
3456                                  <&gcc GCC_WPSS_AHB_CLK>,
3457                                  <&gcc GCC_WPSS_RSCP_CLK>,
3458                                  <&rpmhcc RPMH_CXO_CLK>;
3459                         clock-names = "ahb_bdg", "ahb",
3460                                       "rscp", "xo";
3461
3462                         power-domains = <&rpmhpd SC7280_CX>,
3463                                         <&rpmhpd SC7280_MX>;
3464                         power-domain-names = "cx", "mx";
3465
3466                         memory-region = <&wpss_mem>;
3467
3468                         qcom,qmp = <&aoss_qmp>;
3469
3470                         qcom,smem-states = <&wpss_smp2p_out 0>;
3471                         qcom,smem-state-names = "stop";
3472
3473                         resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
3474                                  <&pdc_reset PDC_WPSS_SYNC_RESET>;
3475                         reset-names = "restart", "pdc_sync";
3476
3477                         qcom,halt-regs = <&tcsr_1 0x17000>;
3478
3479                         status = "disabled";
3480
3481                         glink-edge {
3482                                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3483                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3484                                                              IRQ_TYPE_EDGE_RISING>;
3485                                 mboxes = <&ipcc IPCC_CLIENT_WPSS
3486                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3487
3488                                 label = "wpss";
3489                                 qcom,remote-pid = <13>;
3490                         };
3491                 };
3492
3493                 pmu@9091000 {
3494                         compatible = "qcom,sc7280-llcc-bwmon";
3495                         reg = <0 0x09091000 0 0x1000>;
3496
3497                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3498
3499                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3500
3501                         operating-points-v2 = <&llcc_bwmon_opp_table>;
3502
3503                         llcc_bwmon_opp_table: opp-table {
3504                                 compatible = "operating-points-v2";
3505
3506                                 opp-0 {
3507                                         opp-peak-kBps = <800000>;
3508                                 };
3509                                 opp-1 {
3510                                         opp-peak-kBps = <1804000>;
3511                                 };
3512                                 opp-2 {
3513                                         opp-peak-kBps = <2188000>;
3514                                 };
3515                                 opp-3 {
3516                                         opp-peak-kBps = <3072000>;
3517                                 };
3518                                 opp-4 {
3519                                         opp-peak-kBps = <4068000>;
3520                                 };
3521                                 opp-5 {
3522                                         opp-peak-kBps = <6220000>;
3523                                 };
3524                                 opp-6 {
3525                                         opp-peak-kBps = <6832000>;
3526                                 };
3527                                 opp-7 {
3528                                         opp-peak-kBps = <8532000>;
3529                                 };
3530                         };
3531                 };
3532
3533                 pmu@90b6400 {
3534                         compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon";
3535                         reg = <0 0x090b6400 0 0x600>;
3536
3537                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3538
3539                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3540                         operating-points-v2 = <&cpu_bwmon_opp_table>;
3541
3542                         cpu_bwmon_opp_table: opp-table {
3543                                 compatible = "operating-points-v2";
3544
3545                                 opp-0 {
3546                                         opp-peak-kBps = <2400000>;
3547                                 };
3548                                 opp-1 {
3549                                         opp-peak-kBps = <4800000>;
3550                                 };
3551                                 opp-2 {
3552                                         opp-peak-kBps = <7456000>;
3553                                 };
3554                                 opp-3 {
3555                                         opp-peak-kBps = <9600000>;
3556                                 };
3557                                 opp-4 {
3558                                         opp-peak-kBps = <12896000>;
3559                                 };
3560                                 opp-5 {
3561                                         opp-peak-kBps = <14928000>;
3562                                 };
3563                                 opp-6 {
3564                                         opp-peak-kBps = <17056000>;
3565                                 };
3566                         };
3567                 };
3568
3569                 dc_noc: interconnect@90e0000 {
3570                         reg = <0 0x090e0000 0 0x5080>;
3571                         compatible = "qcom,sc7280-dc-noc";
3572                         #interconnect-cells = <2>;
3573                         qcom,bcm-voters = <&apps_bcm_voter>;
3574                 };
3575
3576                 gem_noc: interconnect@9100000 {
3577                         reg = <0 0x09100000 0 0xe2200>;
3578                         compatible = "qcom,sc7280-gem-noc";
3579                         #interconnect-cells = <2>;
3580                         qcom,bcm-voters = <&apps_bcm_voter>;
3581                 };
3582
3583                 system-cache-controller@9200000 {
3584                         compatible = "qcom,sc7280-llcc";
3585                         reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
3586                         reg-names = "llcc_base", "llcc_broadcast_base";
3587                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3588                 };
3589
3590                 eud: eud@88e0000 {
3591                         compatible = "qcom,sc7280-eud","qcom,eud";
3592                         reg = <0 0x088e0000 0 0x2000>,
3593                               <0 0x088e2000 0 0x1000>;
3594                         interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3595                         ports {
3596                                 port@0 {
3597                                         eud_ep: endpoint {
3598                                                 remote-endpoint = <&usb2_role_switch>;
3599                                         };
3600                                 };
3601                                 port@1 {
3602                                         eud_con: endpoint {
3603                                                 remote-endpoint = <&con_eud>;
3604                                         };
3605                                 };
3606                         };
3607                 };
3608
3609                 eud_typec: connector {
3610                         compatible = "usb-c-connector";
3611                         ports {
3612                                 port@0 {
3613                                         con_eud: endpoint {
3614                                                 remote-endpoint = <&eud_con>;
3615                                         };
3616                                 };
3617                         };
3618                 };
3619
3620                 nsp_noc: interconnect@a0c0000 {
3621                         reg = <0 0x0a0c0000 0 0x10000>;
3622                         compatible = "qcom,sc7280-nsp-noc";
3623                         #interconnect-cells = <2>;
3624                         qcom,bcm-voters = <&apps_bcm_voter>;
3625                 };
3626
3627                 usb_1: usb@a6f8800 {
3628                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3629                         reg = <0 0x0a6f8800 0 0x400>;
3630                         status = "disabled";
3631                         #address-cells = <2>;
3632                         #size-cells = <2>;
3633                         ranges;
3634                         dma-ranges;
3635
3636                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3637                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3638                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3639                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3640                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3641                         clock-names = "cfg_noc",
3642                                       "core",
3643                                       "iface",
3644                                       "sleep",
3645                                       "mock_utmi";
3646
3647                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3648                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3649                         assigned-clock-rates = <19200000>, <200000000>;
3650
3651                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3652                                               <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
3653                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3654                                               <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
3655                         interrupt-names = "hs_phy_irq",
3656                                           "dp_hs_phy_irq",
3657                                           "dm_hs_phy_irq",
3658                                           "ss_phy_irq";
3659
3660                         power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
3661                         required-opps = <&rpmhpd_opp_nom>;
3662
3663                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3664
3665                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3666                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
3667                         interconnect-names = "usb-ddr", "apps-usb";
3668
3669                         wakeup-source;
3670
3671                         usb_1_dwc3: usb@a600000 {
3672                                 compatible = "snps,dwc3";
3673                                 reg = <0 0x0a600000 0 0xe000>;
3674                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3675                                 iommus = <&apps_smmu 0xe0 0x0>;
3676                                 snps,dis_u2_susphy_quirk;
3677                                 snps,dis_enblslpm_quirk;
3678                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3679                                 phy-names = "usb2-phy", "usb3-phy";
3680                                 maximum-speed = "super-speed";
3681                         };
3682                 };
3683
3684                 venus: video-codec@aa00000 {
3685                         compatible = "qcom,sc7280-venus";
3686                         reg = <0 0x0aa00000 0 0xd0600>;
3687                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3688
3689                         clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
3690                                  <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
3691                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3692                                  <&videocc VIDEO_CC_MVS0_CORE_CLK>,
3693                                  <&videocc VIDEO_CC_MVS0_AXI_CLK>;
3694                         clock-names = "core", "bus", "iface",
3695                                       "vcodec_core", "vcodec_bus";
3696
3697                         power-domains = <&videocc MVSC_GDSC>,
3698                                         <&videocc MVS0_GDSC>,
3699                                         <&rpmhpd SC7280_CX>;
3700                         power-domain-names = "venus", "vcodec0", "cx";
3701                         operating-points-v2 = <&venus_opp_table>;
3702
3703                         interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
3704                                         <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
3705                         interconnect-names = "cpu-cfg", "video-mem";
3706
3707                         iommus = <&apps_smmu 0x2180 0x20>,
3708                                  <&apps_smmu 0x2184 0x20>;
3709                         memory-region = <&video_mem>;
3710
3711                         video-decoder {
3712                                 compatible = "venus-decoder";
3713                         };
3714
3715                         video-encoder {
3716                                 compatible = "venus-encoder";
3717                         };
3718
3719                         video-firmware {
3720                                 iommus = <&apps_smmu 0x21a2 0x0>;
3721                         };
3722
3723                         venus_opp_table: opp-table {
3724                                 compatible = "operating-points-v2";
3725
3726                                 opp-133330000 {
3727                                         opp-hz = /bits/ 64 <133330000>;
3728                                         required-opps = <&rpmhpd_opp_low_svs>;
3729                                 };
3730
3731                                 opp-240000000 {
3732                                         opp-hz = /bits/ 64 <240000000>;
3733                                         required-opps = <&rpmhpd_opp_svs>;
3734                                 };
3735
3736                                 opp-335000000 {
3737                                         opp-hz = /bits/ 64 <335000000>;
3738                                         required-opps = <&rpmhpd_opp_svs_l1>;
3739                                 };
3740
3741                                 opp-424000000 {
3742                                         opp-hz = /bits/ 64 <424000000>;
3743                                         required-opps = <&rpmhpd_opp_nom>;
3744                                 };
3745
3746                                 opp-460000048 {
3747                                         opp-hz = /bits/ 64 <460000048>;
3748                                         required-opps = <&rpmhpd_opp_turbo>;
3749                                 };
3750                         };
3751
3752                 };
3753
3754                 videocc: clock-controller@aaf0000 {
3755                         compatible = "qcom,sc7280-videocc";
3756                         reg = <0 0x0aaf0000 0 0x10000>;
3757                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3758                                 <&rpmhcc RPMH_CXO_CLK_A>;
3759                         clock-names = "bi_tcxo", "bi_tcxo_ao";
3760                         #clock-cells = <1>;
3761                         #reset-cells = <1>;
3762                         #power-domain-cells = <1>;
3763                 };
3764
3765                 camcc: clock-controller@ad00000 {
3766                         compatible = "qcom,sc7280-camcc";
3767                         reg = <0 0x0ad00000 0 0x10000>;
3768                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3769                                 <&rpmhcc RPMH_CXO_CLK_A>,
3770                                 <&sleep_clk>;
3771                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3772                         #clock-cells = <1>;
3773                         #reset-cells = <1>;
3774                         #power-domain-cells = <1>;
3775                 };
3776
3777                 dispcc: clock-controller@af00000 {
3778                         compatible = "qcom,sc7280-dispcc";
3779                         reg = <0 0x0af00000 0 0x20000>;
3780                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3781                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3782                                  <&mdss_dsi_phy 0>,
3783                                  <&mdss_dsi_phy 1>,
3784                                  <&dp_phy 0>,
3785                                  <&dp_phy 1>,
3786                                  <&mdss_edp_phy 0>,
3787                                  <&mdss_edp_phy 1>;
3788                         clock-names = "bi_tcxo",
3789                                       "gcc_disp_gpll0_clk",
3790                                       "dsi0_phy_pll_out_byteclk",
3791                                       "dsi0_phy_pll_out_dsiclk",
3792                                       "dp_phy_pll_link_clk",
3793                                       "dp_phy_pll_vco_div_clk",
3794                                       "edp_phy_pll_link_clk",
3795                                       "edp_phy_pll_vco_div_clk";
3796                         #clock-cells = <1>;
3797                         #reset-cells = <1>;
3798                         #power-domain-cells = <1>;
3799                 };
3800
3801                 mdss: display-subsystem@ae00000 {
3802                         compatible = "qcom,sc7280-mdss";
3803                         reg = <0 0x0ae00000 0 0x1000>;
3804                         reg-names = "mdss";
3805
3806                         power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
3807
3808                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3809                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
3810                                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3811                         clock-names = "iface",
3812                                       "ahb",
3813                                       "core";
3814
3815                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3816                         interrupt-controller;
3817                         #interrupt-cells = <1>;
3818
3819                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3820                         interconnect-names = "mdp0-mem";
3821
3822                         iommus = <&apps_smmu 0x900 0x402>;
3823
3824                         #address-cells = <2>;
3825                         #size-cells = <2>;
3826                         ranges;
3827
3828                         status = "disabled";
3829
3830                         mdss_mdp: display-controller@ae01000 {
3831                                 compatible = "qcom,sc7280-dpu";
3832                                 reg = <0 0x0ae01000 0 0x8f030>,
3833                                         <0 0x0aeb0000 0 0x2008>;
3834                                 reg-names = "mdp", "vbif";
3835
3836                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3837                                         <&gcc GCC_DISP_SF_AXI_CLK>,
3838                                         <&dispcc DISP_CC_MDSS_AHB_CLK>,
3839                                         <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3840                                         <&dispcc DISP_CC_MDSS_MDP_CLK>,
3841                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3842                                 clock-names = "bus",
3843                                               "nrt_bus",
3844                                               "iface",
3845                                               "lut",
3846                                               "core",
3847                                               "vsync";
3848                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3849                                                 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3850                                 assigned-clock-rates = <19200000>,
3851                                                         <19200000>;
3852                                 operating-points-v2 = <&mdp_opp_table>;
3853                                 power-domains = <&rpmhpd SC7280_CX>;
3854
3855                                 interrupt-parent = <&mdss>;
3856                                 interrupts = <0>;
3857
3858                                 status = "disabled";
3859
3860                                 ports {
3861                                         #address-cells = <1>;
3862                                         #size-cells = <0>;
3863
3864                                         port@0 {
3865                                                 reg = <0>;
3866                                                 dpu_intf1_out: endpoint {
3867                                                         remote-endpoint = <&dsi0_in>;
3868                                                 };
3869                                         };
3870
3871                                         port@1 {
3872                                                 reg = <1>;
3873                                                 dpu_intf5_out: endpoint {
3874                                                         remote-endpoint = <&edp_in>;
3875                                                 };
3876                                         };
3877
3878                                         port@2 {
3879                                                 reg = <2>;
3880                                                 dpu_intf0_out: endpoint {
3881                                                         remote-endpoint = <&dp_in>;
3882                                                 };
3883                                         };
3884                                 };
3885
3886                                 mdp_opp_table: opp-table {
3887                                         compatible = "operating-points-v2";
3888
3889                                         opp-200000000 {
3890                                                 opp-hz = /bits/ 64 <200000000>;
3891                                                 required-opps = <&rpmhpd_opp_low_svs>;
3892                                         };
3893
3894                                         opp-300000000 {
3895                                                 opp-hz = /bits/ 64 <300000000>;
3896                                                 required-opps = <&rpmhpd_opp_svs>;
3897                                         };
3898
3899                                         opp-380000000 {
3900                                                 opp-hz = /bits/ 64 <380000000>;
3901                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3902                                         };
3903
3904                                         opp-506666667 {
3905                                                 opp-hz = /bits/ 64 <506666667>;
3906                                                 required-opps = <&rpmhpd_opp_nom>;
3907                                         };
3908                                 };
3909                         };
3910
3911                         mdss_dsi: dsi@ae94000 {
3912                                 compatible = "qcom,sc7280-dsi-ctrl",
3913                                              "qcom,mdss-dsi-ctrl";
3914                                 reg = <0 0x0ae94000 0 0x400>;
3915                                 reg-names = "dsi_ctrl";
3916
3917                                 interrupt-parent = <&mdss>;
3918                                 interrupts = <4>;
3919
3920                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3921                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3922                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3923                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3924                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3925                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3926                                 clock-names = "byte",
3927                                               "byte_intf",
3928                                               "pixel",
3929                                               "core",
3930                                               "iface",
3931                                               "bus";
3932
3933                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3934                                 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
3935
3936                                 operating-points-v2 = <&dsi_opp_table>;
3937                                 power-domains = <&rpmhpd SC7280_CX>;
3938
3939                                 phys = <&mdss_dsi_phy>;
3940
3941                                 #address-cells = <1>;
3942                                 #size-cells = <0>;
3943
3944                                 status = "disabled";
3945
3946                                 ports {
3947                                         #address-cells = <1>;
3948                                         #size-cells = <0>;
3949
3950                                         port@0 {
3951                                                 reg = <0>;
3952                                                 dsi0_in: endpoint {
3953                                                         remote-endpoint = <&dpu_intf1_out>;
3954                                                 };
3955                                         };
3956
3957                                         port@1 {
3958                                                 reg = <1>;
3959                                                 dsi0_out: endpoint {
3960                                                 };
3961                                         };
3962                                 };
3963
3964                                 dsi_opp_table: opp-table {
3965                                         compatible = "operating-points-v2";
3966
3967                                         opp-187500000 {
3968                                                 opp-hz = /bits/ 64 <187500000>;
3969                                                 required-opps = <&rpmhpd_opp_low_svs>;
3970                                         };
3971
3972                                         opp-300000000 {
3973                                                 opp-hz = /bits/ 64 <300000000>;
3974                                                 required-opps = <&rpmhpd_opp_svs>;
3975                                         };
3976
3977                                         opp-358000000 {
3978                                                 opp-hz = /bits/ 64 <358000000>;
3979                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3980                                         };
3981                                 };
3982                         };
3983
3984                         mdss_dsi_phy: phy@ae94400 {
3985                                 compatible = "qcom,sc7280-dsi-phy-7nm";
3986                                 reg = <0 0x0ae94400 0 0x200>,
3987                                       <0 0x0ae94600 0 0x280>,
3988                                       <0 0x0ae94900 0 0x280>;
3989                                 reg-names = "dsi_phy",
3990                                             "dsi_phy_lane",
3991                                             "dsi_pll";
3992
3993                                 #clock-cells = <1>;
3994                                 #phy-cells = <0>;
3995
3996                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3997                                          <&rpmhcc RPMH_CXO_CLK>;
3998                                 clock-names = "iface", "ref";
3999
4000                                 status = "disabled";
4001                         };
4002
4003                         mdss_edp: edp@aea0000 {
4004                                 compatible = "qcom,sc7280-edp";
4005                                 pinctrl-names = "default";
4006                                 pinctrl-0 = <&edp_hot_plug_det>;
4007
4008                                 reg = <0 0x0aea0000 0 0x200>,
4009                                       <0 0x0aea0200 0 0x200>,
4010                                       <0 0x0aea0400 0 0xc00>,
4011                                       <0 0x0aea1000 0 0x400>;
4012
4013                                 interrupt-parent = <&mdss>;
4014                                 interrupts = <14>;
4015
4016                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4017                                          <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
4018                                          <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
4019                                          <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
4020                                          <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
4021                                 clock-names = "core_iface",
4022                                               "core_aux",
4023                                               "ctrl_link",
4024                                               "ctrl_link_iface",
4025                                               "stream_pixel";
4026                                 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4027                                                   <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
4028                                 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4029
4030                                 phys = <&mdss_edp_phy>;
4031                                 phy-names = "dp";
4032
4033                                 operating-points-v2 = <&edp_opp_table>;
4034                                 power-domains = <&rpmhpd SC7280_CX>;
4035
4036                                 status = "disabled";
4037
4038                                 ports {
4039                                         #address-cells = <1>;
4040                                         #size-cells = <0>;
4041
4042                                         port@0 {
4043                                                 reg = <0>;
4044                                                 edp_in: endpoint {
4045                                                         remote-endpoint = <&dpu_intf5_out>;
4046                                                 };
4047                                         };
4048
4049                                         port@1 {
4050                                                 reg = <1>;
4051                                                 mdss_edp_out: endpoint { };
4052                                         };
4053                                 };
4054
4055                                 edp_opp_table: opp-table {
4056                                         compatible = "operating-points-v2";
4057
4058                                         opp-160000000 {
4059                                                 opp-hz = /bits/ 64 <160000000>;
4060                                                 required-opps = <&rpmhpd_opp_low_svs>;
4061                                         };
4062
4063                                         opp-270000000 {
4064                                                 opp-hz = /bits/ 64 <270000000>;
4065                                                 required-opps = <&rpmhpd_opp_svs>;
4066                                         };
4067
4068                                         opp-540000000 {
4069                                                 opp-hz = /bits/ 64 <540000000>;
4070                                                 required-opps = <&rpmhpd_opp_nom>;
4071                                         };
4072
4073                                         opp-810000000 {
4074                                                 opp-hz = /bits/ 64 <810000000>;
4075                                                 required-opps = <&rpmhpd_opp_nom>;
4076                                         };
4077                                 };
4078                         };
4079
4080                         mdss_edp_phy: phy@aec2a00 {
4081                                 compatible = "qcom,sc7280-edp-phy";
4082
4083                                 reg = <0 0x0aec2a00 0 0x19c>,
4084                                       <0 0x0aec2200 0 0xa0>,
4085                                       <0 0x0aec2600 0 0xa0>,
4086                                       <0 0x0aec2000 0 0x1c0>;
4087
4088                                 clocks = <&rpmhcc RPMH_CXO_CLK>,
4089                                          <&gcc GCC_EDP_CLKREF_EN>;
4090                                 clock-names = "aux",
4091                                               "cfg_ahb";
4092
4093                                 #clock-cells = <1>;
4094                                 #phy-cells = <0>;
4095
4096                                 status = "disabled";
4097                         };
4098
4099                         mdss_dp: displayport-controller@ae90000 {
4100                                 compatible = "qcom,sc7280-dp";
4101
4102                                 reg = <0 0x0ae90000 0 0x200>,
4103                                       <0 0x0ae90200 0 0x200>,
4104                                       <0 0x0ae90400 0 0xc00>,
4105                                       <0 0x0ae91000 0 0x400>,
4106                                       <0 0x0ae91400 0 0x400>;
4107
4108                                 interrupt-parent = <&mdss>;
4109                                 interrupts = <12>;
4110
4111                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4112                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4113                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4114                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4115                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4116                                 clock-names = "core_iface",
4117                                                 "core_aux",
4118                                                 "ctrl_link",
4119                                                 "ctrl_link_iface",
4120                                                 "stream_pixel";
4121                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4122                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4123                                 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4124                                 phys = <&dp_phy>;
4125                                 phy-names = "dp";
4126
4127                                 operating-points-v2 = <&dp_opp_table>;
4128                                 power-domains = <&rpmhpd SC7280_CX>;
4129
4130                                 #sound-dai-cells = <0>;
4131
4132                                 status = "disabled";
4133
4134                                 ports {
4135                                         #address-cells = <1>;
4136                                         #size-cells = <0>;
4137
4138                                         port@0 {
4139                                                 reg = <0>;
4140                                                 dp_in: endpoint {
4141                                                         remote-endpoint = <&dpu_intf0_out>;
4142                                                 };
4143                                         };
4144
4145                                         port@1 {
4146                                                 reg = <1>;
4147                                                 mdss_dp_out: endpoint { };
4148                                         };
4149                                 };
4150
4151                                 dp_opp_table: opp-table {
4152                                         compatible = "operating-points-v2";
4153
4154                                         opp-160000000 {
4155                                                 opp-hz = /bits/ 64 <160000000>;
4156                                                 required-opps = <&rpmhpd_opp_low_svs>;
4157                                         };
4158
4159                                         opp-270000000 {
4160                                                 opp-hz = /bits/ 64 <270000000>;
4161                                                 required-opps = <&rpmhpd_opp_svs>;
4162                                         };
4163
4164                                         opp-540000000 {
4165                                                 opp-hz = /bits/ 64 <540000000>;
4166                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4167                                         };
4168
4169                                         opp-810000000 {
4170                                                 opp-hz = /bits/ 64 <810000000>;
4171                                                 required-opps = <&rpmhpd_opp_nom>;
4172                                         };
4173                                 };
4174                         };
4175                 };
4176
4177                 pdc: interrupt-controller@b220000 {
4178                         compatible = "qcom,sc7280-pdc", "qcom,pdc";
4179                         reg = <0 0x0b220000 0 0x30000>;
4180                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4181                                           <55 306 4>, <59 312 3>, <62 374 2>,
4182                                           <64 434 2>, <66 438 3>, <69 86 1>,
4183                                           <70 520 54>, <124 609 31>, <155 63 1>,
4184                                           <156 716 12>;
4185                         #interrupt-cells = <2>;
4186                         interrupt-parent = <&intc>;
4187                         interrupt-controller;
4188                 };
4189
4190                 pdc_reset: reset-controller@b5e0000 {
4191                         compatible = "qcom,sc7280-pdc-global";
4192                         reg = <0 0x0b5e0000 0 0x20000>;
4193                         #reset-cells = <1>;
4194                 };
4195
4196                 tsens0: thermal-sensor@c263000 {
4197                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4198                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4199                                 <0 0x0c222000 0 0x1ff>; /* SROT */
4200                         #qcom,sensors = <15>;
4201                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4202                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4203                         interrupt-names = "uplow","critical";
4204                         #thermal-sensor-cells = <1>;
4205                 };
4206
4207                 tsens1: thermal-sensor@c265000 {
4208                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4209                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4210                                 <0 0x0c223000 0 0x1ff>; /* SROT */
4211                         #qcom,sensors = <12>;
4212                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4213                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4214                         interrupt-names = "uplow","critical";
4215                         #thermal-sensor-cells = <1>;
4216                 };
4217
4218                 aoss_reset: reset-controller@c2a0000 {
4219                         compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4220                         reg = <0 0x0c2a0000 0 0x31000>;
4221                         #reset-cells = <1>;
4222                 };
4223
4224                 aoss_qmp: power-management@c300000 {
4225                         compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4226                         reg = <0 0x0c300000 0 0x400>;
4227                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4228                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
4229                                                      IRQ_TYPE_EDGE_RISING>;
4230                         mboxes = <&ipcc IPCC_CLIENT_AOP
4231                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
4232
4233                         #clock-cells = <0>;
4234                 };
4235
4236                 sram@c3f0000 {
4237                         compatible = "qcom,rpmh-stats";
4238                         reg = <0 0x0c3f0000 0 0x400>;
4239                 };
4240
4241                 spmi_bus: spmi@c440000 {
4242                         compatible = "qcom,spmi-pmic-arb";
4243                         reg = <0 0x0c440000 0 0x1100>,
4244                               <0 0x0c600000 0 0x2000000>,
4245                               <0 0x0e600000 0 0x100000>,
4246                               <0 0x0e700000 0 0xa0000>,
4247                               <0 0x0c40a000 0 0x26000>;
4248                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4249                         interrupt-names = "periph_irq";
4250                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4251                         qcom,ee = <0>;
4252                         qcom,channel = <0>;
4253                         #address-cells = <2>;
4254                         #size-cells = <0>;
4255                         interrupt-controller;
4256                         #interrupt-cells = <4>;
4257                 };
4258
4259                 tlmm: pinctrl@f100000 {
4260                         compatible = "qcom,sc7280-pinctrl";
4261                         reg = <0 0x0f100000 0 0x300000>;
4262                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4263                         gpio-controller;
4264                         #gpio-cells = <2>;
4265                         interrupt-controller;
4266                         #interrupt-cells = <2>;
4267                         gpio-ranges = <&tlmm 0 0 175>;
4268                         wakeup-parent = <&pdc>;
4269
4270                         dp_hot_plug_det: dp-hot-plug-det-state {
4271                                 pins = "gpio47";
4272                                 function = "dp_hot";
4273                         };
4274
4275                         edp_hot_plug_det: edp-hot-plug-det-state {
4276                                 pins = "gpio60";
4277                                 function = "edp_hot";
4278                         };
4279
4280                         mi2s0_data0: mi2s0-data0-state {
4281                                 pins = "gpio98";
4282                                 function = "mi2s0_data0";
4283                         };
4284
4285                         mi2s0_data1: mi2s0-data1-state {
4286                                 pins = "gpio99";
4287                                 function = "mi2s0_data1";
4288                         };
4289
4290                         mi2s0_mclk: mi2s0-mclk-state {
4291                                 pins = "gpio96";
4292                                 function = "pri_mi2s";
4293                         };
4294
4295                         mi2s0_sclk: mi2s0-sclk-state {
4296                                 pins = "gpio97";
4297                                 function = "mi2s0_sck";
4298                         };
4299
4300                         mi2s0_ws: mi2s0-ws-state {
4301                                 pins = "gpio100";
4302                                 function = "mi2s0_ws";
4303                         };
4304
4305                         mi2s1_data0: mi2s1-data0-state {
4306                                 pins = "gpio107";
4307                                 function = "mi2s1_data0";
4308                         };
4309
4310                         mi2s1_sclk: mi2s1-sclk-state {
4311                                 pins = "gpio106";
4312                                 function = "mi2s1_sck";
4313                         };
4314
4315                         mi2s1_ws: mi2s1-ws-state {
4316                                 pins = "gpio108";
4317                                 function = "mi2s1_ws";
4318                         };
4319
4320                         pcie1_clkreq_n: pcie1-clkreq-n-state {
4321                                 pins = "gpio79";
4322                                 function = "pcie1_clkreqn";
4323                         };
4324
4325                         qspi_clk: qspi-clk-state {
4326                                 pins = "gpio14";
4327                                 function = "qspi_clk";
4328                         };
4329
4330                         qspi_cs0: qspi-cs0-state {
4331                                 pins = "gpio15";
4332                                 function = "qspi_cs";
4333                         };
4334
4335                         qspi_cs1: qspi-cs1-state {
4336                                 pins = "gpio19";
4337                                 function = "qspi_cs";
4338                         };
4339
4340                         qspi_data01: qspi-data01-state {
4341                                 pins = "gpio12", "gpio13";
4342                                 function = "qspi_data";
4343                         };
4344
4345                         qspi_data12: qspi-data12-state {
4346                                 pins = "gpio16", "gpio17";
4347                                 function = "qspi_data";
4348                         };
4349
4350                         qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4351                                 pins = "gpio0", "gpio1";
4352                                 function = "qup00";
4353                         };
4354
4355                         qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4356                                 pins = "gpio4", "gpio5";
4357                                 function = "qup01";
4358                         };
4359
4360                         qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4361                                 pins = "gpio8", "gpio9";
4362                                 function = "qup02";
4363                         };
4364
4365                         qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4366                                 pins = "gpio12", "gpio13";
4367                                 function = "qup03";
4368                         };
4369
4370                         qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4371                                 pins = "gpio16", "gpio17";
4372                                 function = "qup04";
4373                         };
4374
4375                         qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4376                                 pins = "gpio20", "gpio21";
4377                                 function = "qup05";
4378                         };
4379
4380                         qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4381                                 pins = "gpio24", "gpio25";
4382                                 function = "qup06";
4383                         };
4384
4385                         qup_i2c7_data_clk: qup-i2c7-data-clk-state {
4386                                 pins = "gpio28", "gpio29";
4387                                 function = "qup07";
4388                         };
4389
4390                         qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4391                                 pins = "gpio32", "gpio33";
4392                                 function = "qup10";
4393                         };
4394
4395                         qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4396                                 pins = "gpio36", "gpio37";
4397                                 function = "qup11";
4398                         };
4399
4400                         qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4401                                 pins = "gpio40", "gpio41";
4402                                 function = "qup12";
4403                         };
4404
4405                         qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4406                                 pins = "gpio44", "gpio45";
4407                                 function = "qup13";
4408                         };
4409
4410                         qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4411                                 pins = "gpio48", "gpio49";
4412                                 function = "qup14";
4413                         };
4414
4415                         qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4416                                 pins = "gpio52", "gpio53";
4417                                 function = "qup15";
4418                         };
4419
4420                         qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4421                                 pins = "gpio56", "gpio57";
4422                                 function = "qup16";
4423                         };
4424
4425                         qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4426                                 pins = "gpio60", "gpio61";
4427                                 function = "qup17";
4428                         };
4429
4430                         qup_spi0_data_clk: qup-spi0-data-clk-state {
4431                                 pins = "gpio0", "gpio1", "gpio2";
4432                                 function = "qup00";
4433                         };
4434
4435                         qup_spi0_cs: qup-spi0-cs-state {
4436                                 pins = "gpio3";
4437                                 function = "qup00";
4438                         };
4439
4440                         qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
4441                                 pins = "gpio3";
4442                                 function = "gpio";
4443                         };
4444
4445                         qup_spi1_data_clk: qup-spi1-data-clk-state {
4446                                 pins = "gpio4", "gpio5", "gpio6";
4447                                 function = "qup01";
4448                         };
4449
4450                         qup_spi1_cs: qup-spi1-cs-state {
4451                                 pins = "gpio7";
4452                                 function = "qup01";
4453                         };
4454
4455                         qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
4456                                 pins = "gpio7";
4457                                 function = "gpio";
4458                         };
4459
4460                         qup_spi2_data_clk: qup-spi2-data-clk-state {
4461                                 pins = "gpio8", "gpio9", "gpio10";
4462                                 function = "qup02";
4463                         };
4464
4465                         qup_spi2_cs: qup-spi2-cs-state {
4466                                 pins = "gpio11";
4467                                 function = "qup02";
4468                         };
4469
4470                         qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
4471                                 pins = "gpio11";
4472                                 function = "gpio";
4473                         };
4474
4475                         qup_spi3_data_clk: qup-spi3-data-clk-state {
4476                                 pins = "gpio12", "gpio13", "gpio14";
4477                                 function = "qup03";
4478                         };
4479
4480                         qup_spi3_cs: qup-spi3-cs-state {
4481                                 pins = "gpio15";
4482                                 function = "qup03";
4483                         };
4484
4485                         qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
4486                                 pins = "gpio15";
4487                                 function = "gpio";
4488                         };
4489
4490                         qup_spi4_data_clk: qup-spi4-data-clk-state {
4491                                 pins = "gpio16", "gpio17", "gpio18";
4492                                 function = "qup04";
4493                         };
4494
4495                         qup_spi4_cs: qup-spi4-cs-state {
4496                                 pins = "gpio19";
4497                                 function = "qup04";
4498                         };
4499
4500                         qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
4501                                 pins = "gpio19";
4502                                 function = "gpio";
4503                         };
4504
4505                         qup_spi5_data_clk: qup-spi5-data-clk-state {
4506                                 pins = "gpio20", "gpio21", "gpio22";
4507                                 function = "qup05";
4508                         };
4509
4510                         qup_spi5_cs: qup-spi5-cs-state {
4511                                 pins = "gpio23";
4512                                 function = "qup05";
4513                         };
4514
4515                         qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
4516                                 pins = "gpio23";
4517                                 function = "gpio";
4518                         };
4519
4520                         qup_spi6_data_clk: qup-spi6-data-clk-state {
4521                                 pins = "gpio24", "gpio25", "gpio26";
4522                                 function = "qup06";
4523                         };
4524
4525                         qup_spi6_cs: qup-spi6-cs-state {
4526                                 pins = "gpio27";
4527                                 function = "qup06";
4528                         };
4529
4530                         qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
4531                                 pins = "gpio27";
4532                                 function = "gpio";
4533                         };
4534
4535                         qup_spi7_data_clk: qup-spi7-data-clk-state {
4536                                 pins = "gpio28", "gpio29", "gpio30";
4537                                 function = "qup07";
4538                         };
4539
4540                         qup_spi7_cs: qup-spi7-cs-state {
4541                                 pins = "gpio31";
4542                                 function = "qup07";
4543                         };
4544
4545                         qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
4546                                 pins = "gpio31";
4547                                 function = "gpio";
4548                         };
4549
4550                         qup_spi8_data_clk: qup-spi8-data-clk-state {
4551                                 pins = "gpio32", "gpio33", "gpio34";
4552                                 function = "qup10";
4553                         };
4554
4555                         qup_spi8_cs: qup-spi8-cs-state {
4556                                 pins = "gpio35";
4557                                 function = "qup10";
4558                         };
4559
4560                         qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
4561                                 pins = "gpio35";
4562                                 function = "gpio";
4563                         };
4564
4565                         qup_spi9_data_clk: qup-spi9-data-clk-state {
4566                                 pins = "gpio36", "gpio37", "gpio38";
4567                                 function = "qup11";
4568                         };
4569
4570                         qup_spi9_cs: qup-spi9-cs-state {
4571                                 pins = "gpio39";
4572                                 function = "qup11";
4573                         };
4574
4575                         qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
4576                                 pins = "gpio39";
4577                                 function = "gpio";
4578                         };
4579
4580                         qup_spi10_data_clk: qup-spi10-data-clk-state {
4581                                 pins = "gpio40", "gpio41", "gpio42";
4582                                 function = "qup12";
4583                         };
4584
4585                         qup_spi10_cs: qup-spi10-cs-state {
4586                                 pins = "gpio43";
4587                                 function = "qup12";
4588                         };
4589
4590                         qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
4591                                 pins = "gpio43";
4592                                 function = "gpio";
4593                         };
4594
4595                         qup_spi11_data_clk: qup-spi11-data-clk-state {
4596                                 pins = "gpio44", "gpio45", "gpio46";
4597                                 function = "qup13";
4598                         };
4599
4600                         qup_spi11_cs: qup-spi11-cs-state {
4601                                 pins = "gpio47";
4602                                 function = "qup13";
4603                         };
4604
4605                         qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
4606                                 pins = "gpio47";
4607                                 function = "gpio";
4608                         };
4609
4610                         qup_spi12_data_clk: qup-spi12-data-clk-state {
4611                                 pins = "gpio48", "gpio49", "gpio50";
4612                                 function = "qup14";
4613                         };
4614
4615                         qup_spi12_cs: qup-spi12-cs-state {
4616                                 pins = "gpio51";
4617                                 function = "qup14";
4618                         };
4619
4620                         qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
4621                                 pins = "gpio51";
4622                                 function = "gpio";
4623                         };
4624
4625                         qup_spi13_data_clk: qup-spi13-data-clk-state {
4626                                 pins = "gpio52", "gpio53", "gpio54";
4627                                 function = "qup15";
4628                         };
4629
4630                         qup_spi13_cs: qup-spi13-cs-state {
4631                                 pins = "gpio55";
4632                                 function = "qup15";
4633                         };
4634
4635                         qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
4636                                 pins = "gpio55";
4637                                 function = "gpio";
4638                         };
4639
4640                         qup_spi14_data_clk: qup-spi14-data-clk-state {
4641                                 pins = "gpio56", "gpio57", "gpio58";
4642                                 function = "qup16";
4643                         };
4644
4645                         qup_spi14_cs: qup-spi14-cs-state {
4646                                 pins = "gpio59";
4647                                 function = "qup16";
4648                         };
4649
4650                         qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
4651                                 pins = "gpio59";
4652                                 function = "gpio";
4653                         };
4654
4655                         qup_spi15_data_clk: qup-spi15-data-clk-state {
4656                                 pins = "gpio60", "gpio61", "gpio62";
4657                                 function = "qup17";
4658                         };
4659
4660                         qup_spi15_cs: qup-spi15-cs-state {
4661                                 pins = "gpio63";
4662                                 function = "qup17";
4663                         };
4664
4665                         qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
4666                                 pins = "gpio63";
4667                                 function = "gpio";
4668                         };
4669
4670                         qup_uart0_cts: qup-uart0-cts-state {
4671                                 pins = "gpio0";
4672                                 function = "qup00";
4673                         };
4674
4675                         qup_uart0_rts: qup-uart0-rts-state {
4676                                 pins = "gpio1";
4677                                 function = "qup00";
4678                         };
4679
4680                         qup_uart0_tx: qup-uart0-tx-state {
4681                                 pins = "gpio2";
4682                                 function = "qup00";
4683                         };
4684
4685                         qup_uart0_rx: qup-uart0-rx-state {
4686                                 pins = "gpio3";
4687                                 function = "qup00";
4688                         };
4689
4690                         qup_uart1_cts: qup-uart1-cts-state {
4691                                 pins = "gpio4";
4692                                 function = "qup01";
4693                         };
4694
4695                         qup_uart1_rts: qup-uart1-rts-state {
4696                                 pins = "gpio5";
4697                                 function = "qup01";
4698                         };
4699
4700                         qup_uart1_tx: qup-uart1-tx-state {
4701                                 pins = "gpio6";
4702                                 function = "qup01";
4703                         };
4704
4705                         qup_uart1_rx: qup-uart1-rx-state {
4706                                 pins = "gpio7";
4707                                 function = "qup01";
4708                         };
4709
4710                         qup_uart2_cts: qup-uart2-cts-state {
4711                                 pins = "gpio8";
4712                                 function = "qup02";
4713                         };
4714
4715                         qup_uart2_rts: qup-uart2-rts-state {
4716                                 pins = "gpio9";
4717                                 function = "qup02";
4718                         };
4719
4720                         qup_uart2_tx: qup-uart2-tx-state {
4721                                 pins = "gpio10";
4722                                 function = "qup02";
4723                         };
4724
4725                         qup_uart2_rx: qup-uart2-rx-state {
4726                                 pins = "gpio11";
4727                                 function = "qup02";
4728                         };
4729
4730                         qup_uart3_cts: qup-uart3-cts-state {
4731                                 pins = "gpio12";
4732                                 function = "qup03";
4733                         };
4734
4735                         qup_uart3_rts: qup-uart3-rts-state {
4736                                 pins = "gpio13";
4737                                 function = "qup03";
4738                         };
4739
4740                         qup_uart3_tx: qup-uart3-tx-state {
4741                                 pins = "gpio14";
4742                                 function = "qup03";
4743                         };
4744
4745                         qup_uart3_rx: qup-uart3-rx-state {
4746                                 pins = "gpio15";
4747                                 function = "qup03";
4748                         };
4749
4750                         qup_uart4_cts: qup-uart4-cts-state {
4751                                 pins = "gpio16";
4752                                 function = "qup04";
4753                         };
4754
4755                         qup_uart4_rts: qup-uart4-rts-state {
4756                                 pins = "gpio17";
4757                                 function = "qup04";
4758                         };
4759
4760                         qup_uart4_tx: qup-uart4-tx-state {
4761                                 pins = "gpio18";
4762                                 function = "qup04";
4763                         };
4764
4765                         qup_uart4_rx: qup-uart4-rx-state {
4766                                 pins = "gpio19";
4767                                 function = "qup04";
4768                         };
4769
4770                         qup_uart5_cts: qup-uart5-cts-state {
4771                                 pins = "gpio20";
4772                                 function = "qup05";
4773                         };
4774
4775                         qup_uart5_rts: qup-uart5-rts-state {
4776                                 pins = "gpio21";
4777                                 function = "qup05";
4778                         };
4779
4780                         qup_uart5_tx: qup-uart5-tx-state {
4781                                 pins = "gpio22";
4782                                 function = "qup05";
4783                         };
4784
4785                         qup_uart5_rx: qup-uart5-rx-state {
4786                                 pins = "gpio23";
4787                                 function = "qup05";
4788                         };
4789
4790                         qup_uart6_cts: qup-uart6-cts-state {
4791                                 pins = "gpio24";
4792                                 function = "qup06";
4793                         };
4794
4795                         qup_uart6_rts: qup-uart6-rts-state {
4796                                 pins = "gpio25";
4797                                 function = "qup06";
4798                         };
4799
4800                         qup_uart6_tx: qup-uart6-tx-state {
4801                                 pins = "gpio26";
4802                                 function = "qup06";
4803                         };
4804
4805                         qup_uart6_rx: qup-uart6-rx-state {
4806                                 pins = "gpio27";
4807                                 function = "qup06";
4808                         };
4809
4810                         qup_uart7_cts: qup-uart7-cts-state {
4811                                 pins = "gpio28";
4812                                 function = "qup07";
4813                         };
4814
4815                         qup_uart7_rts: qup-uart7-rts-state {
4816                                 pins = "gpio29";
4817                                 function = "qup07";
4818                         };
4819
4820                         qup_uart7_tx: qup-uart7-tx-state {
4821                                 pins = "gpio30";
4822                                 function = "qup07";
4823                         };
4824
4825                         qup_uart7_rx: qup-uart7-rx-state {
4826                                 pins = "gpio31";
4827                                 function = "qup07";
4828                         };
4829
4830                         qup_uart8_cts: qup-uart8-cts-state {
4831                                 pins = "gpio32";
4832                                 function = "qup10";
4833                         };
4834
4835                         qup_uart8_rts: qup-uart8-rts-state {
4836                                 pins = "gpio33";
4837                                 function = "qup10";
4838                         };
4839
4840                         qup_uart8_tx: qup-uart8-tx-state {
4841                                 pins = "gpio34";
4842                                 function = "qup10";
4843                         };
4844
4845                         qup_uart8_rx: qup-uart8-rx-state {
4846                                 pins = "gpio35";
4847                                 function = "qup10";
4848                         };
4849
4850                         qup_uart9_cts: qup-uart9-cts-state {
4851                                 pins = "gpio36";
4852                                 function = "qup11";
4853                         };
4854
4855                         qup_uart9_rts: qup-uart9-rts-state {
4856                                 pins = "gpio37";
4857                                 function = "qup11";
4858                         };
4859
4860                         qup_uart9_tx: qup-uart9-tx-state {
4861                                 pins = "gpio38";
4862                                 function = "qup11";
4863                         };
4864
4865                         qup_uart9_rx: qup-uart9-rx-state {
4866                                 pins = "gpio39";
4867                                 function = "qup11";
4868                         };
4869
4870                         qup_uart10_cts: qup-uart10-cts-state {
4871                                 pins = "gpio40";
4872                                 function = "qup12";
4873                         };
4874
4875                         qup_uart10_rts: qup-uart10-rts-state {
4876                                 pins = "gpio41";
4877                                 function = "qup12";
4878                         };
4879
4880                         qup_uart10_tx: qup-uart10-tx-state {
4881                                 pins = "gpio42";
4882                                 function = "qup12";
4883                         };
4884
4885                         qup_uart10_rx: qup-uart10-rx-state {
4886                                 pins = "gpio43";
4887                                 function = "qup12";
4888                         };
4889
4890                         qup_uart11_cts: qup-uart11-cts-state {
4891                                 pins = "gpio44";
4892                                 function = "qup13";
4893                         };
4894
4895                         qup_uart11_rts: qup-uart11-rts-state {
4896                                 pins = "gpio45";
4897                                 function = "qup13";
4898                         };
4899
4900                         qup_uart11_tx: qup-uart11-tx-state {
4901                                 pins = "gpio46";
4902                                 function = "qup13";
4903                         };
4904
4905                         qup_uart11_rx: qup-uart11-rx-state {
4906                                 pins = "gpio47";
4907                                 function = "qup13";
4908                         };
4909
4910                         qup_uart12_cts: qup-uart12-cts-state {
4911                                 pins = "gpio48";
4912                                 function = "qup14";
4913                         };
4914
4915                         qup_uart12_rts: qup-uart12-rts-state {
4916                                 pins = "gpio49";
4917                                 function = "qup14";
4918                         };
4919
4920                         qup_uart12_tx: qup-uart12-tx-state {
4921                                 pins = "gpio50";
4922                                 function = "qup14";
4923                         };
4924
4925                         qup_uart12_rx: qup-uart12-rx-state {
4926                                 pins = "gpio51";
4927                                 function = "qup14";
4928                         };
4929
4930                         qup_uart13_cts: qup-uart13-cts-state {
4931                                 pins = "gpio52";
4932                                 function = "qup15";
4933                         };
4934
4935                         qup_uart13_rts: qup-uart13-rts-state {
4936                                 pins = "gpio53";
4937                                 function = "qup15";
4938                         };
4939
4940                         qup_uart13_tx: qup-uart13-tx-state {
4941                                 pins = "gpio54";
4942                                 function = "qup15";
4943                         };
4944
4945                         qup_uart13_rx: qup-uart13-rx-state {
4946                                 pins = "gpio55";
4947                                 function = "qup15";
4948                         };
4949
4950                         qup_uart14_cts: qup-uart14-cts-state {
4951                                 pins = "gpio56";
4952                                 function = "qup16";
4953                         };
4954
4955                         qup_uart14_rts: qup-uart14-rts-state {
4956                                 pins = "gpio57";
4957                                 function = "qup16";
4958                         };
4959
4960                         qup_uart14_tx: qup-uart14-tx-state {
4961                                 pins = "gpio58";
4962                                 function = "qup16";
4963                         };
4964
4965                         qup_uart14_rx: qup-uart14-rx-state {
4966                                 pins = "gpio59";
4967                                 function = "qup16";
4968                         };
4969
4970                         qup_uart15_cts: qup-uart15-cts-state {
4971                                 pins = "gpio60";
4972                                 function = "qup17";
4973                         };
4974
4975                         qup_uart15_rts: qup-uart15-rts-state {
4976                                 pins = "gpio61";
4977                                 function = "qup17";
4978                         };
4979
4980                         qup_uart15_tx: qup-uart15-tx-state {
4981                                 pins = "gpio62";
4982                                 function = "qup17";
4983                         };
4984
4985                         qup_uart15_rx: qup-uart15-rx-state {
4986                                 pins = "gpio63";
4987                                 function = "qup17";
4988                         };
4989
4990                         sdc1_clk: sdc1-clk-state {
4991                                 pins = "sdc1_clk";
4992                         };
4993
4994                         sdc1_cmd: sdc1-cmd-state {
4995                                 pins = "sdc1_cmd";
4996                         };
4997
4998                         sdc1_data: sdc1-data-state {
4999                                 pins = "sdc1_data";
5000                         };
5001
5002                         sdc1_rclk: sdc1-rclk-state {
5003                                 pins = "sdc1_rclk";
5004                         };
5005
5006                         sdc1_clk_sleep: sdc1-clk-sleep-state {
5007                                 pins = "sdc1_clk";
5008                                 drive-strength = <2>;
5009                                 bias-bus-hold;
5010                         };
5011
5012                         sdc1_cmd_sleep: sdc1-cmd-sleep-state {
5013                                 pins = "sdc1_cmd";
5014                                 drive-strength = <2>;
5015                                 bias-bus-hold;
5016                         };
5017
5018                         sdc1_data_sleep: sdc1-data-sleep-state {
5019                                 pins = "sdc1_data";
5020                                 drive-strength = <2>;
5021                                 bias-bus-hold;
5022                         };
5023
5024                         sdc1_rclk_sleep: sdc1-rclk-sleep-state {
5025                                 pins = "sdc1_rclk";
5026                                 drive-strength = <2>;
5027                                 bias-bus-hold;
5028                         };
5029
5030                         sdc2_clk: sdc2-clk-state {
5031                                 pins = "sdc2_clk";
5032                         };
5033
5034                         sdc2_cmd: sdc2-cmd-state {
5035                                 pins = "sdc2_cmd";
5036                         };
5037
5038                         sdc2_data: sdc2-data-state {
5039                                 pins = "sdc2_data";
5040                         };
5041
5042                         sdc2_clk_sleep: sdc2-clk-sleep-state {
5043                                 pins = "sdc2_clk";
5044                                 drive-strength = <2>;
5045                                 bias-bus-hold;
5046                         };
5047
5048                         sdc2_cmd_sleep: sdc2-cmd-sleep-state {
5049                                 pins = "sdc2_cmd";
5050                                 drive-strength = <2>;
5051                                 bias-bus-hold;
5052                         };
5053
5054                         sdc2_data_sleep: sdc2-data-sleep-state {
5055                                 pins = "sdc2_data";
5056                                 drive-strength = <2>;
5057                                 bias-bus-hold;
5058                         };
5059                 };
5060
5061                 sram@146a5000 {
5062                         compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5063                         reg = <0 0x146a5000 0 0x6000>;
5064
5065                         #address-cells = <1>;
5066                         #size-cells = <1>;
5067
5068                         ranges = <0 0 0x146a5000 0x6000>;
5069
5070                         pil-reloc@594c {
5071                                 compatible = "qcom,pil-reloc-info";
5072                                 reg = <0x594c 0xc8>;
5073                         };
5074                 };
5075
5076                 apps_smmu: iommu@15000000 {
5077                         compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5078                         reg = <0 0x15000000 0 0x100000>;
5079                         #iommu-cells = <2>;
5080                         #global-interrupts = <1>;
5081                         dma-coherent;
5082                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5083                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5084                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5085                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5086                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5087                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5088                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5089                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5090                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5091                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5092                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5093                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5094                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5095                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5096                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5097                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5098                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5099                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5100                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5101                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5102                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5103                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5104                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5105                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5106                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5107                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5108                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5109                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5110                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5111                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5112                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5113                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5114                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5115                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5116                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5117                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5118                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5119                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5120                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5121                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5122                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5123                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5124                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5125                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5126                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5127                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5128                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5129                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5130                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5131                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5132                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5133                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5134                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5135                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5136                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5137                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5138                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5139                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5140                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5141                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5142                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5143                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5144                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5145                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5146                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5147                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5148                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5149                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5150                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5151                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5152                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5153                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5154                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5155                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5156                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5157                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5158                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5159                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5160                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5161                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5162                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
5163                 };
5164
5165                 intc: interrupt-controller@17a00000 {
5166                         compatible = "arm,gic-v3";
5167                         #address-cells = <2>;
5168                         #size-cells = <2>;
5169                         ranges;
5170                         #interrupt-cells = <3>;
5171                         interrupt-controller;
5172                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
5173                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
5174                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
5175
5176                         gic-its@17a40000 {
5177                                 compatible = "arm,gic-v3-its";
5178                                 msi-controller;
5179                                 #msi-cells = <1>;
5180                                 reg = <0 0x17a40000 0 0x20000>;
5181                                 status = "disabled";
5182                         };
5183                 };
5184
5185                 watchdog@17c10000 {
5186                         compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5187                         reg = <0 0x17c10000 0 0x1000>;
5188                         clocks = <&sleep_clk>;
5189                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5190                 };
5191
5192                 timer@17c20000 {
5193                         #address-cells = <1>;
5194                         #size-cells = <1>;
5195                         ranges = <0 0 0 0x20000000>;
5196                         compatible = "arm,armv7-timer-mem";
5197                         reg = <0 0x17c20000 0 0x1000>;
5198
5199                         frame@17c21000 {
5200                                 frame-number = <0>;
5201                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5202                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5203                                 reg = <0x17c21000 0x1000>,
5204                                       <0x17c22000 0x1000>;
5205                         };
5206
5207                         frame@17c23000 {
5208                                 frame-number = <1>;
5209                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5210                                 reg = <0x17c23000 0x1000>;
5211                                 status = "disabled";
5212                         };
5213
5214                         frame@17c25000 {
5215                                 frame-number = <2>;
5216                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5217                                 reg = <0x17c25000 0x1000>;
5218                                 status = "disabled";
5219                         };
5220
5221                         frame@17c27000 {
5222                                 frame-number = <3>;
5223                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5224                                 reg = <0x17c27000 0x1000>;
5225                                 status = "disabled";
5226                         };
5227
5228                         frame@17c29000 {
5229                                 frame-number = <4>;
5230                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5231                                 reg = <0x17c29000 0x1000>;
5232                                 status = "disabled";
5233                         };
5234
5235                         frame@17c2b000 {
5236                                 frame-number = <5>;
5237                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5238                                 reg = <0x17c2b000 0x1000>;
5239                                 status = "disabled";
5240                         };
5241
5242                         frame@17c2d000 {
5243                                 frame-number = <6>;
5244                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5245                                 reg = <0x17c2d000 0x1000>;
5246                                 status = "disabled";
5247                         };
5248                 };
5249
5250                 apps_rsc: rsc@18200000 {
5251                         compatible = "qcom,rpmh-rsc";
5252                         reg = <0 0x18200000 0 0x10000>,
5253                               <0 0x18210000 0 0x10000>,
5254                               <0 0x18220000 0 0x10000>;
5255                         reg-names = "drv-0", "drv-1", "drv-2";
5256                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5257                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5258                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5259                         qcom,tcs-offset = <0xd00>;
5260                         qcom,drv-id = <2>;
5261                         qcom,tcs-config = <ACTIVE_TCS  2>,
5262                                           <SLEEP_TCS   3>,
5263                                           <WAKE_TCS    3>,
5264                                           <CONTROL_TCS 1>;
5265
5266                         apps_bcm_voter: bcm-voter {
5267                                 compatible = "qcom,bcm-voter";
5268                         };
5269
5270                         rpmhpd: power-controller {
5271                                 compatible = "qcom,sc7280-rpmhpd";
5272                                 #power-domain-cells = <1>;
5273                                 operating-points-v2 = <&rpmhpd_opp_table>;
5274
5275                                 rpmhpd_opp_table: opp-table {
5276                                         compatible = "operating-points-v2";
5277
5278                                         rpmhpd_opp_ret: opp1 {
5279                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5280                                         };
5281
5282                                         rpmhpd_opp_low_svs: opp2 {
5283                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5284                                         };
5285
5286                                         rpmhpd_opp_svs: opp3 {
5287                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5288                                         };
5289
5290                                         rpmhpd_opp_svs_l1: opp4 {
5291                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5292                                         };
5293
5294                                         rpmhpd_opp_svs_l2: opp5 {
5295                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5296                                         };
5297
5298                                         rpmhpd_opp_nom: opp6 {
5299                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5300                                         };
5301
5302                                         rpmhpd_opp_nom_l1: opp7 {
5303                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5304                                         };
5305
5306                                         rpmhpd_opp_turbo: opp8 {
5307                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5308                                         };
5309
5310                                         rpmhpd_opp_turbo_l1: opp9 {
5311                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5312                                         };
5313                                 };
5314                         };
5315
5316                         rpmhcc: clock-controller {
5317                                 compatible = "qcom,sc7280-rpmh-clk";
5318                                 clocks = <&xo_board>;
5319                                 clock-names = "xo";
5320                                 #clock-cells = <1>;
5321                         };
5322                 };
5323
5324                 epss_l3: interconnect@18590000 {
5325                         compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
5326                         reg = <0 0x18590000 0 0x1000>;
5327                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5328                         clock-names = "xo", "alternate";
5329                         #interconnect-cells = <1>;
5330                 };
5331
5332                 cpufreq_hw: cpufreq@18591000 {
5333                         compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
5334                         reg = <0 0x18591000 0 0x1000>,
5335                               <0 0x18592000 0 0x1000>,
5336                               <0 0x18593000 0 0x1000>;
5337                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5338                         clock-names = "xo", "alternate";
5339                         #freq-domain-cells = <1>;
5340                 };
5341         };
5342
5343         thermal_zones: thermal-zones {
5344                 cpu0-thermal {
5345                         polling-delay-passive = <250>;
5346                         polling-delay = <0>;
5347
5348                         thermal-sensors = <&tsens0 1>;
5349
5350                         trips {
5351                                 cpu0_alert0: trip-point0 {
5352                                         temperature = <90000>;
5353                                         hysteresis = <2000>;
5354                                         type = "passive";
5355                                 };
5356
5357                                 cpu0_alert1: trip-point1 {
5358                                         temperature = <95000>;
5359                                         hysteresis = <2000>;
5360                                         type = "passive";
5361                                 };
5362
5363                                 cpu0_crit: cpu-crit {
5364                                         temperature = <110000>;
5365                                         hysteresis = <0>;
5366                                         type = "critical";
5367                                 };
5368                         };
5369
5370                         cooling-maps {
5371                                 map0 {
5372                                         trip = <&cpu0_alert0>;
5373                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5374                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5375                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5376                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5377                                 };
5378                                 map1 {
5379                                         trip = <&cpu0_alert1>;
5380                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5381                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5382                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5383                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5384                                 };
5385                         };
5386                 };
5387
5388                 cpu1-thermal {
5389                         polling-delay-passive = <250>;
5390                         polling-delay = <0>;
5391
5392                         thermal-sensors = <&tsens0 2>;
5393
5394                         trips {
5395                                 cpu1_alert0: trip-point0 {
5396                                         temperature = <90000>;
5397                                         hysteresis = <2000>;
5398                                         type = "passive";
5399                                 };
5400
5401                                 cpu1_alert1: trip-point1 {
5402                                         temperature = <95000>;
5403                                         hysteresis = <2000>;
5404                                         type = "passive";
5405                                 };
5406
5407                                 cpu1_crit: cpu-crit {
5408                                         temperature = <110000>;
5409                                         hysteresis = <0>;
5410                                         type = "critical";
5411                                 };
5412                         };
5413
5414                         cooling-maps {
5415                                 map0 {
5416                                         trip = <&cpu1_alert0>;
5417                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5418                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5419                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5420                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5421                                 };
5422                                 map1 {
5423                                         trip = <&cpu1_alert1>;
5424                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5425                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5426                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5427                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5428                                 };
5429                         };
5430                 };
5431
5432                 cpu2-thermal {
5433                         polling-delay-passive = <250>;
5434                         polling-delay = <0>;
5435
5436                         thermal-sensors = <&tsens0 3>;
5437
5438                         trips {
5439                                 cpu2_alert0: trip-point0 {
5440                                         temperature = <90000>;
5441                                         hysteresis = <2000>;
5442                                         type = "passive";
5443                                 };
5444
5445                                 cpu2_alert1: trip-point1 {
5446                                         temperature = <95000>;
5447                                         hysteresis = <2000>;
5448                                         type = "passive";
5449                                 };
5450
5451                                 cpu2_crit: cpu-crit {
5452                                         temperature = <110000>;
5453                                         hysteresis = <0>;
5454                                         type = "critical";
5455                                 };
5456                         };
5457
5458                         cooling-maps {
5459                                 map0 {
5460                                         trip = <&cpu2_alert0>;
5461                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5462                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5463                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5464                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5465                                 };
5466                                 map1 {
5467                                         trip = <&cpu2_alert1>;
5468                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5469                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5470                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5471                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5472                                 };
5473                         };
5474                 };
5475
5476                 cpu3-thermal {
5477                         polling-delay-passive = <250>;
5478                         polling-delay = <0>;
5479
5480                         thermal-sensors = <&tsens0 4>;
5481
5482                         trips {
5483                                 cpu3_alert0: trip-point0 {
5484                                         temperature = <90000>;
5485                                         hysteresis = <2000>;
5486                                         type = "passive";
5487                                 };
5488
5489                                 cpu3_alert1: trip-point1 {
5490                                         temperature = <95000>;
5491                                         hysteresis = <2000>;
5492                                         type = "passive";
5493                                 };
5494
5495                                 cpu3_crit: cpu-crit {
5496                                         temperature = <110000>;
5497                                         hysteresis = <0>;
5498                                         type = "critical";
5499                                 };
5500                         };
5501
5502                         cooling-maps {
5503                                 map0 {
5504                                         trip = <&cpu3_alert0>;
5505                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5506                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5507                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5508                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5509                                 };
5510                                 map1 {
5511                                         trip = <&cpu3_alert1>;
5512                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5513                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5514                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5515                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5516                                 };
5517                         };
5518                 };
5519
5520                 cpu4-thermal {
5521                         polling-delay-passive = <250>;
5522                         polling-delay = <0>;
5523
5524                         thermal-sensors = <&tsens0 7>;
5525
5526                         trips {
5527                                 cpu4_alert0: trip-point0 {
5528                                         temperature = <90000>;
5529                                         hysteresis = <2000>;
5530                                         type = "passive";
5531                                 };
5532
5533                                 cpu4_alert1: trip-point1 {
5534                                         temperature = <95000>;
5535                                         hysteresis = <2000>;
5536                                         type = "passive";
5537                                 };
5538
5539                                 cpu4_crit: cpu-crit {
5540                                         temperature = <110000>;
5541                                         hysteresis = <0>;
5542                                         type = "critical";
5543                                 };
5544                         };
5545
5546                         cooling-maps {
5547                                 map0 {
5548                                         trip = <&cpu4_alert0>;
5549                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5550                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5551                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5552                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5553                                 };
5554                                 map1 {
5555                                         trip = <&cpu4_alert1>;
5556                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5557                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5558                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5559                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5560                                 };
5561                         };
5562                 };
5563
5564                 cpu5-thermal {
5565                         polling-delay-passive = <250>;
5566                         polling-delay = <0>;
5567
5568                         thermal-sensors = <&tsens0 8>;
5569
5570                         trips {
5571                                 cpu5_alert0: trip-point0 {
5572                                         temperature = <90000>;
5573                                         hysteresis = <2000>;
5574                                         type = "passive";
5575                                 };
5576
5577                                 cpu5_alert1: trip-point1 {
5578                                         temperature = <95000>;
5579                                         hysteresis = <2000>;
5580                                         type = "passive";
5581                                 };
5582
5583                                 cpu5_crit: cpu-crit {
5584                                         temperature = <110000>;
5585                                         hysteresis = <0>;
5586                                         type = "critical";
5587                                 };
5588                         };
5589
5590                         cooling-maps {
5591                                 map0 {
5592                                         trip = <&cpu5_alert0>;
5593                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5594                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5595                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5596                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5597                                 };
5598                                 map1 {
5599                                         trip = <&cpu5_alert1>;
5600                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5601                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5602                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5603                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5604                                 };
5605                         };
5606                 };
5607
5608                 cpu6-thermal {
5609                         polling-delay-passive = <250>;
5610                         polling-delay = <0>;
5611
5612                         thermal-sensors = <&tsens0 9>;
5613
5614                         trips {
5615                                 cpu6_alert0: trip-point0 {
5616                                         temperature = <90000>;
5617                                         hysteresis = <2000>;
5618                                         type = "passive";
5619                                 };
5620
5621                                 cpu6_alert1: trip-point1 {
5622                                         temperature = <95000>;
5623                                         hysteresis = <2000>;
5624                                         type = "passive";
5625                                 };
5626
5627                                 cpu6_crit: cpu-crit {
5628                                         temperature = <110000>;
5629                                         hysteresis = <0>;
5630                                         type = "critical";
5631                                 };
5632                         };
5633
5634                         cooling-maps {
5635                                 map0 {
5636                                         trip = <&cpu6_alert0>;
5637                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5638                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5639                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5640                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5641                                 };
5642                                 map1 {
5643                                         trip = <&cpu6_alert1>;
5644                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5645                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5646                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5647                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5648                                 };
5649                         };
5650                 };
5651
5652                 cpu7-thermal {
5653                         polling-delay-passive = <250>;
5654                         polling-delay = <0>;
5655
5656                         thermal-sensors = <&tsens0 10>;
5657
5658                         trips {
5659                                 cpu7_alert0: trip-point0 {
5660                                         temperature = <90000>;
5661                                         hysteresis = <2000>;
5662                                         type = "passive";
5663                                 };
5664
5665                                 cpu7_alert1: trip-point1 {
5666                                         temperature = <95000>;
5667                                         hysteresis = <2000>;
5668                                         type = "passive";
5669                                 };
5670
5671                                 cpu7_crit: cpu-crit {
5672                                         temperature = <110000>;
5673                                         hysteresis = <0>;
5674                                         type = "critical";
5675                                 };
5676                         };
5677
5678                         cooling-maps {
5679                                 map0 {
5680                                         trip = <&cpu7_alert0>;
5681                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5682                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5683                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5684                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5685                                 };
5686                                 map1 {
5687                                         trip = <&cpu7_alert1>;
5688                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5689                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5690                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5691                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5692                                 };
5693                         };
5694                 };
5695
5696                 cpu8-thermal {
5697                         polling-delay-passive = <250>;
5698                         polling-delay = <0>;
5699
5700                         thermal-sensors = <&tsens0 11>;
5701
5702                         trips {
5703                                 cpu8_alert0: trip-point0 {
5704                                         temperature = <90000>;
5705                                         hysteresis = <2000>;
5706                                         type = "passive";
5707                                 };
5708
5709                                 cpu8_alert1: trip-point1 {
5710                                         temperature = <95000>;
5711                                         hysteresis = <2000>;
5712                                         type = "passive";
5713                                 };
5714
5715                                 cpu8_crit: cpu-crit {
5716                                         temperature = <110000>;
5717                                         hysteresis = <0>;
5718                                         type = "critical";
5719                                 };
5720                         };
5721
5722                         cooling-maps {
5723                                 map0 {
5724                                         trip = <&cpu8_alert0>;
5725                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5726                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5727                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5728                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5729                                 };
5730                                 map1 {
5731                                         trip = <&cpu8_alert1>;
5732                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5733                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5734                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5735                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5736                                 };
5737                         };
5738                 };
5739
5740                 cpu9-thermal {
5741                         polling-delay-passive = <250>;
5742                         polling-delay = <0>;
5743
5744                         thermal-sensors = <&tsens0 12>;
5745
5746                         trips {
5747                                 cpu9_alert0: trip-point0 {
5748                                         temperature = <90000>;
5749                                         hysteresis = <2000>;
5750                                         type = "passive";
5751                                 };
5752
5753                                 cpu9_alert1: trip-point1 {
5754                                         temperature = <95000>;
5755                                         hysteresis = <2000>;
5756                                         type = "passive";
5757                                 };
5758
5759                                 cpu9_crit: cpu-crit {
5760                                         temperature = <110000>;
5761                                         hysteresis = <0>;
5762                                         type = "critical";
5763                                 };
5764                         };
5765
5766                         cooling-maps {
5767                                 map0 {
5768                                         trip = <&cpu9_alert0>;
5769                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5770                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5771                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5772                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5773                                 };
5774                                 map1 {
5775                                         trip = <&cpu9_alert1>;
5776                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5777                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5778                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5779                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5780                                 };
5781                         };
5782                 };
5783
5784                 cpu10-thermal {
5785                         polling-delay-passive = <250>;
5786                         polling-delay = <0>;
5787
5788                         thermal-sensors = <&tsens0 13>;
5789
5790                         trips {
5791                                 cpu10_alert0: trip-point0 {
5792                                         temperature = <90000>;
5793                                         hysteresis = <2000>;
5794                                         type = "passive";
5795                                 };
5796
5797                                 cpu10_alert1: trip-point1 {
5798                                         temperature = <95000>;
5799                                         hysteresis = <2000>;
5800                                         type = "passive";
5801                                 };
5802
5803                                 cpu10_crit: cpu-crit {
5804                                         temperature = <110000>;
5805                                         hysteresis = <0>;
5806                                         type = "critical";
5807                                 };
5808                         };
5809
5810                         cooling-maps {
5811                                 map0 {
5812                                         trip = <&cpu10_alert0>;
5813                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5814                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5815                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5816                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5817                                 };
5818                                 map1 {
5819                                         trip = <&cpu10_alert1>;
5820                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5821                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5822                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5823                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5824                                 };
5825                         };
5826                 };
5827
5828                 cpu11-thermal {
5829                         polling-delay-passive = <250>;
5830                         polling-delay = <0>;
5831
5832                         thermal-sensors = <&tsens0 14>;
5833
5834                         trips {
5835                                 cpu11_alert0: trip-point0 {
5836                                         temperature = <90000>;
5837                                         hysteresis = <2000>;
5838                                         type = "passive";
5839                                 };
5840
5841                                 cpu11_alert1: trip-point1 {
5842                                         temperature = <95000>;
5843                                         hysteresis = <2000>;
5844                                         type = "passive";
5845                                 };
5846
5847                                 cpu11_crit: cpu-crit {
5848                                         temperature = <110000>;
5849                                         hysteresis = <0>;
5850                                         type = "critical";
5851                                 };
5852                         };
5853
5854                         cooling-maps {
5855                                 map0 {
5856                                         trip = <&cpu11_alert0>;
5857                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5858                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5859                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5860                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5861                                 };
5862                                 map1 {
5863                                         trip = <&cpu11_alert1>;
5864                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5865                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5866                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5867                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5868                                 };
5869                         };
5870                 };
5871
5872                 aoss0-thermal {
5873                         polling-delay-passive = <0>;
5874                         polling-delay = <0>;
5875
5876                         thermal-sensors = <&tsens0 0>;
5877
5878                         trips {
5879                                 aoss0_alert0: trip-point0 {
5880                                         temperature = <90000>;
5881                                         hysteresis = <2000>;
5882                                         type = "hot";
5883                                 };
5884
5885                                 aoss0_crit: aoss0-crit {
5886                                         temperature = <110000>;
5887                                         hysteresis = <0>;
5888                                         type = "critical";
5889                                 };
5890                         };
5891                 };
5892
5893                 aoss1-thermal {
5894                         polling-delay-passive = <0>;
5895                         polling-delay = <0>;
5896
5897                         thermal-sensors = <&tsens1 0>;
5898
5899                         trips {
5900                                 aoss1_alert0: trip-point0 {
5901                                         temperature = <90000>;
5902                                         hysteresis = <2000>;
5903                                         type = "hot";
5904                                 };
5905
5906                                 aoss1_crit: aoss1-crit {
5907                                         temperature = <110000>;
5908                                         hysteresis = <0>;
5909                                         type = "critical";
5910                                 };
5911                         };
5912                 };
5913
5914                 cpuss0-thermal {
5915                         polling-delay-passive = <0>;
5916                         polling-delay = <0>;
5917
5918                         thermal-sensors = <&tsens0 5>;
5919
5920                         trips {
5921                                 cpuss0_alert0: trip-point0 {
5922                                         temperature = <90000>;
5923                                         hysteresis = <2000>;
5924                                         type = "hot";
5925                                 };
5926                                 cpuss0_crit: cluster0-crit {
5927                                         temperature = <110000>;
5928                                         hysteresis = <0>;
5929                                         type = "critical";
5930                                 };
5931                         };
5932                 };
5933
5934                 cpuss1-thermal {
5935                         polling-delay-passive = <0>;
5936                         polling-delay = <0>;
5937
5938                         thermal-sensors = <&tsens0 6>;
5939
5940                         trips {
5941                                 cpuss1_alert0: trip-point0 {
5942                                         temperature = <90000>;
5943                                         hysteresis = <2000>;
5944                                         type = "hot";
5945                                 };
5946                                 cpuss1_crit: cluster0-crit {
5947                                         temperature = <110000>;
5948                                         hysteresis = <0>;
5949                                         type = "critical";
5950                                 };
5951                         };
5952                 };
5953
5954                 gpuss0-thermal {
5955                         polling-delay-passive = <100>;
5956                         polling-delay = <0>;
5957
5958                         thermal-sensors = <&tsens1 1>;
5959
5960                         trips {
5961                                 gpuss0_alert0: trip-point0 {
5962                                         temperature = <95000>;
5963                                         hysteresis = <2000>;
5964                                         type = "passive";
5965                                 };
5966
5967                                 gpuss0_crit: gpuss0-crit {
5968                                         temperature = <110000>;
5969                                         hysteresis = <0>;
5970                                         type = "critical";
5971                                 };
5972                         };
5973
5974                         cooling-maps {
5975                                 map0 {
5976                                         trip = <&gpuss0_alert0>;
5977                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5978                                 };
5979                         };
5980                 };
5981
5982                 gpuss1-thermal {
5983                         polling-delay-passive = <100>;
5984                         polling-delay = <0>;
5985
5986                         thermal-sensors = <&tsens1 2>;
5987
5988                         trips {
5989                                 gpuss1_alert0: trip-point0 {
5990                                         temperature = <95000>;
5991                                         hysteresis = <2000>;
5992                                         type = "passive";
5993                                 };
5994
5995                                 gpuss1_crit: gpuss1-crit {
5996                                         temperature = <110000>;
5997                                         hysteresis = <0>;
5998                                         type = "critical";
5999                                 };
6000                         };
6001
6002                         cooling-maps {
6003                                 map0 {
6004                                         trip = <&gpuss1_alert0>;
6005                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6006                                 };
6007                         };
6008                 };
6009
6010                 nspss0-thermal {
6011                         polling-delay-passive = <0>;
6012                         polling-delay = <0>;
6013
6014                         thermal-sensors = <&tsens1 3>;
6015
6016                         trips {
6017                                 nspss0_alert0: trip-point0 {
6018                                         temperature = <90000>;
6019                                         hysteresis = <2000>;
6020                                         type = "hot";
6021                                 };
6022
6023                                 nspss0_crit: nspss0-crit {
6024                                         temperature = <110000>;
6025                                         hysteresis = <0>;
6026                                         type = "critical";
6027                                 };
6028                         };
6029                 };
6030
6031                 nspss1-thermal {
6032                         polling-delay-passive = <0>;
6033                         polling-delay = <0>;
6034
6035                         thermal-sensors = <&tsens1 4>;
6036
6037                         trips {
6038                                 nspss1_alert0: trip-point0 {
6039                                         temperature = <90000>;
6040                                         hysteresis = <2000>;
6041                                         type = "hot";
6042                                 };
6043
6044                                 nspss1_crit: nspss1-crit {
6045                                         temperature = <110000>;
6046                                         hysteresis = <0>;
6047                                         type = "critical";
6048                                 };
6049                         };
6050                 };
6051
6052                 video-thermal {
6053                         polling-delay-passive = <0>;
6054                         polling-delay = <0>;
6055
6056                         thermal-sensors = <&tsens1 5>;
6057
6058                         trips {
6059                                 video_alert0: trip-point0 {
6060                                         temperature = <90000>;
6061                                         hysteresis = <2000>;
6062                                         type = "hot";
6063                                 };
6064
6065                                 video_crit: video-crit {
6066                                         temperature = <110000>;
6067                                         hysteresis = <0>;
6068                                         type = "critical";
6069                                 };
6070                         };
6071                 };
6072
6073                 ddr-thermal {
6074                         polling-delay-passive = <0>;
6075                         polling-delay = <0>;
6076
6077                         thermal-sensors = <&tsens1 6>;
6078
6079                         trips {
6080                                 ddr_alert0: trip-point0 {
6081                                         temperature = <90000>;
6082                                         hysteresis = <2000>;
6083                                         type = "hot";
6084                                 };
6085
6086                                 ddr_crit: ddr-crit {
6087                                         temperature = <110000>;
6088                                         hysteresis = <0>;
6089                                         type = "critical";
6090                                 };
6091                         };
6092                 };
6093
6094                 mdmss0-thermal {
6095                         polling-delay-passive = <0>;
6096                         polling-delay = <0>;
6097
6098                         thermal-sensors = <&tsens1 7>;
6099
6100                         trips {
6101                                 mdmss0_alert0: trip-point0 {
6102                                         temperature = <90000>;
6103                                         hysteresis = <2000>;
6104                                         type = "hot";
6105                                 };
6106
6107                                 mdmss0_crit: mdmss0-crit {
6108                                         temperature = <110000>;
6109                                         hysteresis = <0>;
6110                                         type = "critical";
6111                                 };
6112                         };
6113                 };
6114
6115                 mdmss1-thermal {
6116                         polling-delay-passive = <0>;
6117                         polling-delay = <0>;
6118
6119                         thermal-sensors = <&tsens1 8>;
6120
6121                         trips {
6122                                 mdmss1_alert0: trip-point0 {
6123                                         temperature = <90000>;
6124                                         hysteresis = <2000>;
6125                                         type = "hot";
6126                                 };
6127
6128                                 mdmss1_crit: mdmss1-crit {
6129                                         temperature = <110000>;
6130                                         hysteresis = <0>;
6131                                         type = "critical";
6132                                 };
6133                         };
6134                 };
6135
6136                 mdmss2-thermal {
6137                         polling-delay-passive = <0>;
6138                         polling-delay = <0>;
6139
6140                         thermal-sensors = <&tsens1 9>;
6141
6142                         trips {
6143                                 mdmss2_alert0: trip-point0 {
6144                                         temperature = <90000>;
6145                                         hysteresis = <2000>;
6146                                         type = "hot";
6147                                 };
6148
6149                                 mdmss2_crit: mdmss2-crit {
6150                                         temperature = <110000>;
6151                                         hysteresis = <0>;
6152                                         type = "critical";
6153                                 };
6154                         };
6155                 };
6156
6157                 mdmss3-thermal {
6158                         polling-delay-passive = <0>;
6159                         polling-delay = <0>;
6160
6161                         thermal-sensors = <&tsens1 10>;
6162
6163                         trips {
6164                                 mdmss3_alert0: trip-point0 {
6165                                         temperature = <90000>;
6166                                         hysteresis = <2000>;
6167                                         type = "hot";
6168                                 };
6169
6170                                 mdmss3_crit: mdmss3-crit {
6171                                         temperature = <110000>;
6172                                         hysteresis = <0>;
6173                                         type = "critical";
6174                                 };
6175                         };
6176                 };
6177
6178                 camera0-thermal {
6179                         polling-delay-passive = <0>;
6180                         polling-delay = <0>;
6181
6182                         thermal-sensors = <&tsens1 11>;
6183
6184                         trips {
6185                                 camera0_alert0: trip-point0 {
6186                                         temperature = <90000>;
6187                                         hysteresis = <2000>;
6188                                         type = "hot";
6189                                 };
6190
6191                                 camera0_crit: camera0-crit {
6192                                         temperature = <110000>;
6193                                         hysteresis = <0>;
6194                                         type = "critical";
6195                                 };
6196                         };
6197                 };
6198         };
6199
6200         timer {
6201                 compatible = "arm,armv8-timer";
6202                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6203                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6204                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6205                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
6206         };
6207 };