arch/arm64/boot/dts/qcom/msm8998.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
   6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/power/qcom-rpmpd.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 / {
  13         interrupt-parent = <&intc>;
  14
  15         qcom,msm-id = <292 0x0>;
  16
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         chosen { };
  21
  22         memory@80000000 {
  23                 device_type = "memory";
  24                 /* We expect the bootloader to fill in the reg */
  25                 reg = <0x0 0x80000000 0x0 0x0>;
  26         };
  27
  28         reserved-memory {
  29                 #address-cells = <2>;
  30                 #size-cells = <2>;
  31                 ranges;
  32
  33                 hyp_mem: memory@85800000 {
  34                         reg = <0x0 0x85800000 0x0 0x600000>;
  35                         no-map;
  36                 };
  37
  38                 xbl_mem: memory@85e00000 {
  39                         reg = <0x0 0x85e00000 0x0 0x100000>;
  40                         no-map;
  41                 };
  42
  43                 smem_mem: smem-mem@86000000 {
  44                         reg = <0x0 0x86000000 0x0 0x200000>;
  45                         no-map;
  46                 };
  47
  48                 tz_mem: memory@86200000 {
  49                         reg = <0x0 0x86200000 0x0 0x2d00000>;
  50                         no-map;
  51                 };
  52
  53                 rmtfs_mem: memory@88f00000 {
  54                         compatible = "qcom,rmtfs-mem";
  55                         reg = <0x0 0x88f00000 0x0 0x200000>;
  56                         no-map;
  57
  58                         qcom,client-id = <1>;
  59                         qcom,vmid = <15>;
  60                 };
  61
  62                 spss_mem: memory@8ab00000 {
  63                         reg = <0x0 0x8ab00000 0x0 0x700000>;
  64                         no-map;
  65                 };
  66
  67                 adsp_mem: memory@8b200000 {
  68                         reg = <0x0 0x8b200000 0x0 0x1a00000>;
  69                         no-map;
  70                 };
  71
  72                 mpss_mem: memory@8cc00000 {
  73                         reg = <0x0 0x8cc00000 0x0 0x7000000>;
  74                         no-map;
  75                 };
  76
  77                 venus_mem: memory@93c00000 {
  78                         reg = <0x0 0x93c00000 0x0 0x500000>;
  79                         no-map;
  80                 };
  81
  82                 mba_mem: memory@94100000 {
  83                         reg = <0x0 0x94100000 0x0 0x200000>;
  84                         no-map;
  85                 };
  86
  87                 slpi_mem: memory@94300000 {
  88                         reg = <0x0 0x94300000 0x0 0xf00000>;
  89                         no-map;
  90                 };
  91
  92                 ipa_fw_mem: memory@95200000 {
  93                         reg = <0x0 0x95200000 0x0 0x10000>;
  94                         no-map;
  95                 };
  96
  97                 ipa_gsi_mem: memory@95210000 {
  98                         reg = <0x0 0x95210000 0x0 0x5000>;
  99                         no-map;
 100                 };
 101
 102                 gpu_mem: memory@95600000 {
 103                         reg = <0x0 0x95600000 0x0 0x100000>;
 104                         no-map;
 105                 };
 106
 107                 wlan_msa_mem: memory@95700000 {
 108                         reg = <0x0 0x95700000 0x0 0x100000>;
 109                         no-map;
 110                 };
 111         };
 112
 113         clocks {
 114                 xo: xo-board {
 115                         compatible = "fixed-clock";
 116                         #clock-cells = <0>;
 117                         clock-frequency = <19200000>;
 118                         clock-output-names = "xo_board";
 119                 };
 120
 121                 sleep_clk: sleep-clk {
 122                         compatible = "fixed-clock";
 123                         #clock-cells = <0>;
 124                         clock-frequency = <32764>;
 125                 };
 126         };
 127
 128         cpus {
 129                 #address-cells = <2>;
 130                 #size-cells = <0>;
 131
 132                 CPU0: cpu@0 {
 133                         device_type = "cpu";
 134                         compatible = "qcom,kryo280";
 135                         reg = <0x0 0x0>;
 136                         enable-method = "psci";
 137                         capacity-dmips-mhz = <1024>;
 138                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 139                         next-level-cache = <&L2_0>;
 140                         L2_0: l2-cache {
 141                                 compatible = "cache";
 142                                 cache-level = <2>;
 143                         };
 144                 };
 145
 146                 CPU1: cpu@1 {
 147                         device_type = "cpu";
 148                         compatible = "qcom,kryo280";
 149                         reg = <0x0 0x1>;
 150                         enable-method = "psci";
 151                         capacity-dmips-mhz = <1024>;
 152                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 153                         next-level-cache = <&L2_0>;
 154                 };
 155
 156                 CPU2: cpu@2 {
 157                         device_type = "cpu";
 158                         compatible = "qcom,kryo280";
 159                         reg = <0x0 0x2>;
 160                         enable-method = "psci";
 161                         capacity-dmips-mhz = <1024>;
 162                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 163                         next-level-cache = <&L2_0>;
 164                 };
 165
 166                 CPU3: cpu@3 {
 167                         device_type = "cpu";
 168                         compatible = "qcom,kryo280";
 169                         reg = <0x0 0x3>;
 170                         enable-method = "psci";
 171                         capacity-dmips-mhz = <1024>;
 172                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 173                         next-level-cache = <&L2_0>;
 174                 };
 175
 176                 CPU4: cpu@100 {
 177                         device_type = "cpu";
 178                         compatible = "qcom,kryo280";
 179                         reg = <0x0 0x100>;
 180                         enable-method = "psci";
 181                         capacity-dmips-mhz = <1536>;
 182                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 183                         next-level-cache = <&L2_1>;
 184                         L2_1: l2-cache {
 185                                 compatible = "cache";
 186                                 cache-level = <2>;
 187                         };
 188                 };
 189
 190                 CPU5: cpu@101 {
 191                         device_type = "cpu";
 192                         compatible = "qcom,kryo280";
 193                         reg = <0x0 0x101>;
 194                         enable-method = "psci";
 195                         capacity-dmips-mhz = <1536>;
 196                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 197                         next-level-cache = <&L2_1>;
 198                 };
 199
 200                 CPU6: cpu@102 {
 201                         device_type = "cpu";
 202                         compatible = "qcom,kryo280";
 203                         reg = <0x0 0x102>;
 204                         enable-method = "psci";
 205                         capacity-dmips-mhz = <1536>;
 206                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 207                         next-level-cache = <&L2_1>;
 208                 };
 209
 210                 CPU7: cpu@103 {
 211                         device_type = "cpu";
 212                         compatible = "qcom,kryo280";
 213                         reg = <0x0 0x103>;
 214                         enable-method = "psci";
 215                         capacity-dmips-mhz = <1536>;
 216                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 217                         next-level-cache = <&L2_1>;
 218                 };
 219
 220                 cpu-map {
 221                         cluster0 {
 222                                 core0 {
 223                                         cpu = <&CPU0>;
 224                                 };
 225
 226                                 core1 {
 227                                         cpu = <&CPU1>;
 228                                 };
 229
 230                                 core2 {
 231                                         cpu = <&CPU2>;
 232                                 };
 233
 234                                 core3 {
 235                                         cpu = <&CPU3>;
 236                                 };
 237                         };
 238
 239                         cluster1 {
 240                                 core0 {
 241                                         cpu = <&CPU4>;
 242                                 };
 243
 244                                 core1 {
 245                                         cpu = <&CPU5>;
 246                                 };
 247
 248                                 core2 {
 249                                         cpu = <&CPU6>;
 250                                 };
 251
 252                                 core3 {
 253                                         cpu = <&CPU7>;
 254                                 };
 255                         };
 256                 };
 257
 258                 idle-states {
 259                         entry-method = "psci";
 260
 261                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 262                                 compatible = "arm,idle-state";
 263                                 idle-state-name = "little-retention";
 264                                 /* CPU Retention (C2D), L2 Active */
 265                                 arm,psci-suspend-param = <0x00000002>;
 266                                 entry-latency-us = <81>;
 267                                 exit-latency-us = <86>;
 268                                 min-residency-us = <504>;
 269                         };
 270
 271                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 272                                 compatible = "arm,idle-state";
 273                                 idle-state-name = "little-power-collapse";
 274                                 /* CPU + L2 Power Collapse (C3, D4) */
 275                                 arm,psci-suspend-param = <0x40000003>;
 276                                 entry-latency-us = <814>;
 277                                 exit-latency-us = <4562>;
 278                                 min-residency-us = <9183>;
 279                                 local-timer-stop;
 280                         };
 281
 282                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 283                                 compatible = "arm,idle-state";
 284                                 idle-state-name = "big-retention";
 285                                 /* CPU Retention (C2D), L2 Active */
 286                                 arm,psci-suspend-param = <0x00000002>;
 287                                 entry-latency-us = <79>;
 288                                 exit-latency-us = <82>;
 289                                 min-residency-us = <1302>;
 290                         };
 291
 292                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 293                                 compatible = "arm,idle-state";
 294                                 idle-state-name = "big-power-collapse";
 295                                 /* CPU + L2 Power Collapse (C3, D4) */
 296                                 arm,psci-suspend-param = <0x40000003>;
 297                                 entry-latency-us = <724>;
 298                                 exit-latency-us = <2027>;
 299                                 min-residency-us = <9419>;
 300                                 local-timer-stop;
 301                         };
 302                 };
 303         };
 304
 305         firmware {
 306                 scm {
 307                         compatible = "qcom,scm-msm8998", "qcom,scm";
 308                 };
 309         };
 310
 311         tcsr_mutex: hwlock {
 312                 compatible = "qcom,tcsr-mutex";
 313                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 314                 #hwlock-cells = <1>;
 315         };
 316
 317         psci {
 318                 compatible = "arm,psci-1.0";
 319                 method = "smc";
 320         };
 321
 322         rpm-glink {
 323                 compatible = "qcom,glink-rpm";
 324
 325                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 326                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 327                 mboxes = <&apcs_glb 0>;
 328
 329                 rpm_requests: rpm-requests {
 330                         compatible = "qcom,rpm-msm8998";
 331                         qcom,glink-channels = "rpm_requests";
 332
 333                         rpmcc: clock-controller {
 334                                 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
 335                                 #clock-cells = <1>;
 336                         };
 337
 338                         rpmpd: power-controller {
 339                                 compatible = "qcom,msm8998-rpmpd";
 340                                 #power-domain-cells = <1>;
 341                                 operating-points-v2 = <&rpmpd_opp_table>;
 342
 343                                 rpmpd_opp_table: opp-table {
 344                                         compatible = "operating-points-v2";
 345
 346                                         rpmpd_opp_ret: opp1 {
 347                                                 opp-level = <RPM_SMD_LEVEL_RETENTION>;
 348                                         };
 349
 350                                         rpmpd_opp_ret_plus: opp2 {
 351                                                 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
 352                                         };
 353
 354                                         rpmpd_opp_min_svs: opp3 {
 355                                                 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
 356                                         };
 357
 358                                         rpmpd_opp_low_svs: opp4 {
 359                                                 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
 360                                         };
 361
 362                                         rpmpd_opp_svs: opp5 {
 363                                                 opp-level = <RPM_SMD_LEVEL_SVS>;
 364                                         };
 365
 366                                         rpmpd_opp_svs_plus: opp6 {
 367                                                 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
 368                                         };
 369
 370                                         rpmpd_opp_nom: opp7 {
 371                                                 opp-level = <RPM_SMD_LEVEL_NOM>;
 372                                         };
 373
 374                                         rpmpd_opp_nom_plus: opp8 {
 375                                                 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
 376                                         };
 377
 378                                         rpmpd_opp_turbo: opp9 {
 379                                                 opp-level = <RPM_SMD_LEVEL_TURBO>;
 380                                         };
 381
 382                                         rpmpd_opp_turbo_plus: opp10 {
 383                                                 opp-level = <RPM_SMD_LEVEL_BINNING>;
 384                                         };
 385                                 };
 386                         };
 387                 };
 388         };
 389
 390         smem {
 391                 compatible = "qcom,smem";
 392                 memory-region = <&smem_mem>;
 393                 hwlocks = <&tcsr_mutex 3>;
 394         };
 395
 396         smp2p-lpass {
 397                 compatible = "qcom,smp2p";
 398                 qcom,smem = <443>, <429>;
 399
 400                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 401
 402                 mboxes = <&apcs_glb 10>;
 403
 404                 qcom,local-pid = <0>;
 405                 qcom,remote-pid = <2>;
 406
 407                 adsp_smp2p_out: master-kernel {
 408                         qcom,entry-name = "master-kernel";
 409                         #qcom,smem-state-cells = <1>;
 410                 };
 411
 412                 adsp_smp2p_in: slave-kernel {
 413                         qcom,entry-name = "slave-kernel";
 414
 415                         interrupt-controller;
 416                         #interrupt-cells = <2>;
 417                 };
 418         };
 419
 420         smp2p-mpss {
 421                 compatible = "qcom,smp2p";
 422                 qcom,smem = <435>, <428>;
 423                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 424                 mboxes = <&apcs_glb 14>;
 425                 qcom,local-pid = <0>;
 426                 qcom,remote-pid = <1>;
 427
 428                 modem_smp2p_out: master-kernel {
 429                         qcom,entry-name = "master-kernel";
 430                         #qcom,smem-state-cells = <1>;
 431                 };
 432
 433                 modem_smp2p_in: slave-kernel {
 434                         qcom,entry-name = "slave-kernel";
 435                         interrupt-controller;
 436                         #interrupt-cells = <2>;
 437                 };
 438         };
 439
 440         smp2p-slpi {
 441                 compatible = "qcom,smp2p";
 442                 qcom,smem = <481>, <430>;
 443                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 444                 mboxes = <&apcs_glb 26>;
 445                 qcom,local-pid = <0>;
 446                 qcom,remote-pid = <3>;
 447
 448                 slpi_smp2p_out: master-kernel {
 449                         qcom,entry-name = "master-kernel";
 450                         #qcom,smem-state-cells = <1>;
 451                 };
 452
 453                 slpi_smp2p_in: slave-kernel {
 454                         qcom,entry-name = "slave-kernel";
 455                         interrupt-controller;
 456                         #interrupt-cells = <2>;
 457                 };
 458         };
 459
 460         thermal-zones {
 461                 cpu0-thermal {
 462                         polling-delay-passive = <250>;
 463                         polling-delay = <1000>;
 464
 465                         thermal-sensors = <&tsens0 1>;
 466
 467                         trips {
 468                                 cpu0_alert0: trip-point0 {
 469                                         temperature = <75000>;
 470                                         hysteresis = <2000>;
 471                                         type = "passive";
 472                                 };
 473
 474                                 cpu0_crit: cpu_crit {
 475                                         temperature = <110000>;
 476                                         hysteresis = <2000>;
 477                                         type = "critical";
 478                                 };
 479                         };
 480                 };
 481
 482                 cpu1-thermal {
 483                         polling-delay-passive = <250>;
 484                         polling-delay = <1000>;
 485
 486                         thermal-sensors = <&tsens0 2>;
 487
 488                         trips {
 489                                 cpu1_alert0: trip-point0 {
 490                                         temperature = <75000>;
 491                                         hysteresis = <2000>;
 492                                         type = "passive";
 493                                 };
 494
 495                                 cpu1_crit: cpu_crit {
 496                                         temperature = <110000>;
 497                                         hysteresis = <2000>;
 498                                         type = "critical";
 499                                 };
 500                         };
 501                 };
 502
 503                 cpu2-thermal {
 504                         polling-delay-passive = <250>;
 505                         polling-delay = <1000>;
 506
 507                         thermal-sensors = <&tsens0 3>;
 508
 509                         trips {
 510                                 cpu2_alert0: trip-point0 {
 511                                         temperature = <75000>;
 512                                         hysteresis = <2000>;
 513                                         type = "passive";
 514                                 };
 515
 516                                 cpu2_crit: cpu_crit {
 517                                         temperature = <110000>;
 518                                         hysteresis = <2000>;
 519                                         type = "critical";
 520                                 };
 521                         };
 522                 };
 523
 524                 cpu3-thermal {
 525                         polling-delay-passive = <250>;
 526                         polling-delay = <1000>;
 527
 528                         thermal-sensors = <&tsens0 4>;
 529
 530                         trips {
 531                                 cpu3_alert0: trip-point0 {
 532                                         temperature = <75000>;
 533                                         hysteresis = <2000>;
 534                                         type = "passive";
 535                                 };
 536
 537                                 cpu3_crit: cpu_crit {
 538                                         temperature = <110000>;
 539                                         hysteresis = <2000>;
 540                                         type = "critical";
 541                                 };
 542                         };
 543                 };
 544
 545                 cpu4-thermal {
 546                         polling-delay-passive = <250>;
 547                         polling-delay = <1000>;
 548
 549                         thermal-sensors = <&tsens0 7>;
 550
 551                         trips {
 552                                 cpu4_alert0: trip-point0 {
 553                                         temperature = <75000>;
 554                                         hysteresis = <2000>;
 555                                         type = "passive";
 556                                 };
 557
 558                                 cpu4_crit: cpu_crit {
 559                                         temperature = <110000>;
 560                                         hysteresis = <2000>;
 561                                         type = "critical";
 562                                 };
 563                         };
 564                 };
 565
 566                 cpu5-thermal {
 567                         polling-delay-passive = <250>;
 568                         polling-delay = <1000>;
 569
 570                         thermal-sensors = <&tsens0 8>;
 571
 572                         trips {
 573                                 cpu5_alert0: trip-point0 {
 574                                         temperature = <75000>;
 575                                         hysteresis = <2000>;
 576                                         type = "passive";
 577                                 };
 578
 579                                 cpu5_crit: cpu_crit {
 580                                         temperature = <110000>;
 581                                         hysteresis = <2000>;
 582                                         type = "critical";
 583                                 };
 584                         };
 585                 };
 586
 587                 cpu6-thermal {
 588                         polling-delay-passive = <250>;
 589                         polling-delay = <1000>;
 590
 591                         thermal-sensors = <&tsens0 9>;
 592
 593                         trips {
 594                                 cpu6_alert0: trip-point0 {
 595                                         temperature = <75000>;
 596                                         hysteresis = <2000>;
 597                                         type = "passive";
 598                                 };
 599
 600                                 cpu6_crit: cpu_crit {
 601                                         temperature = <110000>;
 602                                         hysteresis = <2000>;
 603                                         type = "critical";
 604                                 };
 605                         };
 606                 };
 607
 608                 cpu7-thermal {
 609                         polling-delay-passive = <250>;
 610                         polling-delay = <1000>;
 611
 612                         thermal-sensors = <&tsens0 10>;
 613
 614                         trips {
 615                                 cpu7_alert0: trip-point0 {
 616                                         temperature = <75000>;
 617                                         hysteresis = <2000>;
 618                                         type = "passive";
 619                                 };
 620
 621                                 cpu7_crit: cpu_crit {
 622                                         temperature = <110000>;
 623                                         hysteresis = <2000>;
 624                                         type = "critical";
 625                                 };
 626                         };
 627                 };
 628
 629                 gpu-bottom-thermal {
 630                         polling-delay-passive = <250>;
 631                         polling-delay = <1000>;
 632
 633                         thermal-sensors = <&tsens0 12>;
 634
 635                         trips {
 636                                 gpu1_alert0: trip-point0 {
 637                                         temperature = <90000>;
 638                                         hysteresis = <2000>;
 639                                         type = "hot";
 640                                 };
 641                         };
 642                 };
 643
 644                 gpu-top-thermal {
 645                         polling-delay-passive = <250>;
 646                         polling-delay = <1000>;
 647
 648                         thermal-sensors = <&tsens0 13>;
 649
 650                         trips {
 651                                 gpu2_alert0: trip-point0 {
 652                                         temperature = <90000>;
 653                                         hysteresis = <2000>;
 654                                         type = "hot";
 655                                 };
 656                         };
 657                 };
 658
 659                 clust0-mhm-thermal {
 660                         polling-delay-passive = <250>;
 661                         polling-delay = <1000>;
 662
 663                         thermal-sensors = <&tsens0 5>;
 664
 665                         trips {
 666                                 cluster0_mhm_alert0: trip-point0 {
 667                                         temperature = <90000>;
 668                                         hysteresis = <2000>;
 669                                         type = "hot";
 670                                 };
 671                         };
 672                 };
 673
 674                 clust1-mhm-thermal {
 675                         polling-delay-passive = <250>;
 676                         polling-delay = <1000>;
 677
 678                         thermal-sensors = <&tsens0 6>;
 679
 680                         trips {
 681                                 cluster1_mhm_alert0: trip-point0 {
 682                                         temperature = <90000>;
 683                                         hysteresis = <2000>;
 684                                         type = "hot";
 685                                 };
 686                         };
 687                 };
 688
 689                 cluster1-l2-thermal {
 690                         polling-delay-passive = <250>;
 691                         polling-delay = <1000>;
 692
 693                         thermal-sensors = <&tsens0 11>;
 694
 695                         trips {
 696                                 cluster1_l2_alert0: trip-point0 {
 697                                         temperature = <90000>;
 698                                         hysteresis = <2000>;
 699                                         type = "hot";
 700                                 };
 701                         };
 702                 };
 703
 704                 modem-thermal {
 705                         polling-delay-passive = <250>;
 706                         polling-delay = <1000>;
 707
 708                         thermal-sensors = <&tsens1 1>;
 709
 710                         trips {
 711                                 modem_alert0: trip-point0 {
 712                                         temperature = <90000>;
 713                                         hysteresis = <2000>;
 714                                         type = "hot";
 715                                 };
 716                         };
 717                 };
 718
 719                 mem-thermal {
 720                         polling-delay-passive = <250>;
 721                         polling-delay = <1000>;
 722
 723                         thermal-sensors = <&tsens1 2>;
 724
 725                         trips {
 726                                 mem_alert0: trip-point0 {
 727                                         temperature = <90000>;
 728                                         hysteresis = <2000>;
 729                                         type = "hot";
 730                                 };
 731                         };
 732                 };
 733
 734                 wlan-thermal {
 735                         polling-delay-passive = <250>;
 736                         polling-delay = <1000>;
 737
 738                         thermal-sensors = <&tsens1 3>;
 739
 740                         trips {
 741                                 wlan_alert0: trip-point0 {
 742                                         temperature = <90000>;
 743                                         hysteresis = <2000>;
 744                                         type = "hot";
 745                                 };
 746                         };
 747                 };
 748
 749                 q6-dsp-thermal {
 750                         polling-delay-passive = <250>;
 751                         polling-delay = <1000>;
 752
 753                         thermal-sensors = <&tsens1 4>;
 754
 755                         trips {
 756                                 q6_dsp_alert0: trip-point0 {
 757                                         temperature = <90000>;
 758                                         hysteresis = <2000>;
 759                                         type = "hot";
 760                                 };
 761                         };
 762                 };
 763
 764                 camera-thermal {
 765                         polling-delay-passive = <250>;
 766                         polling-delay = <1000>;
 767
 768                         thermal-sensors = <&tsens1 5>;
 769
 770                         trips {
 771                                 camera_alert0: trip-point0 {
 772                                         temperature = <90000>;
 773                                         hysteresis = <2000>;
 774                                         type = "hot";
 775                                 };
 776                         };
 777                 };
 778
 779                 multimedia-thermal {
 780                         polling-delay-passive = <250>;
 781                         polling-delay = <1000>;
 782
 783                         thermal-sensors = <&tsens1 6>;
 784
 785                         trips {
 786                                 multimedia_alert0: trip-point0 {
 787                                         temperature = <90000>;
 788                                         hysteresis = <2000>;
 789                                         type = "hot";
 790                                 };
 791                         };
 792                 };
 793         };
 794
 795         timer {
 796                 compatible = "arm,armv8-timer";
 797                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 798                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 799                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 800                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 801         };
 802
 803         soc: soc {
 804                 #address-cells = <1>;
 805                 #size-cells = <1>;
 806                 ranges = <0 0 0 0xffffffff>;
 807                 compatible = "simple-bus";
 808
 809                 gcc: clock-controller@100000 {
 810                         compatible = "qcom,gcc-msm8998";
 811                         #clock-cells = <1>;
 812                         #reset-cells = <1>;
 813                         #power-domain-cells = <1>;
 814                         reg = <0x00100000 0xb0000>;
 815
 816                         clock-names = "xo", "sleep_clk";
 817                         clocks = <&xo>, <&sleep_clk>;
 818
 819                         /*
 820                          * The hypervisor typically configures the memory region where these clocks
 821                          * reside as read-only for the HLOS. If the HLOS tried to enable or disable
 822                          * these clocks on a device with such configuration (e.g. because they are
 823                          * enabled but unused during boot-up), the device will most likely decide
 824                          * to reboot.
 825                          * In light of that, we are conservative here and we list all such clocks
 826                          * as protected. The board dts (or a user-supplied dts) can override the
 827                          * list of protected clocks if it differs from the norm, and it is in fact
 828                          * desired for the HLOS to manage these clocks
 829                          */
 830                         protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
 831                                            <SSC_XO>,
 832                                            <SSC_CNOC_AHBS_CLK>;
 833                 };
 834
 835                 rpm_msg_ram: sram@778000 {
 836                         compatible = "qcom,rpm-msg-ram";
 837                         reg = <0x00778000 0x7000>;
 838                 };
 839
 840                 qfprom: qfprom@784000 {
 841                         compatible = "qcom,qfprom";
 842                         reg = <0x00784000 0x621c>;
 843                         #address-cells = <1>;
 844                         #size-cells = <1>;
 845
 846                         qusb2_hstx_trim: hstx-trim@23a {
 847                                 reg = <0x23a 0x1>;
 848                                 bits = <0 4>;
 849                         };
 850                 };
 851
 852                 tsens0: thermal@10ab000 {
 853                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 854                         reg = <0x010ab000 0x1000>, /* TM */
 855                               <0x010aa000 0x1000>; /* SROT */
 856                         #qcom,sensors = <14>;
 857                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 858                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 859                         interrupt-names = "uplow", "critical";
 860                         #thermal-sensor-cells = <1>;
 861                 };
 862
 863                 tsens1: thermal@10ae000 {
 864                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 865                         reg = <0x010ae000 0x1000>, /* TM */
 866                               <0x010ad000 0x1000>; /* SROT */
 867                         #qcom,sensors = <8>;
 868                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 869                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 870                         interrupt-names = "uplow", "critical";
 871                         #thermal-sensor-cells = <1>;
 872                 };
 873
 874                 anoc1_smmu: iommu@1680000 {
 875                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 876                         reg = <0x01680000 0x10000>;
 877                         #iommu-cells = <1>;
 878
 879                         #global-interrupts = <0>;
 880                         interrupts =
 881                                 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
 882                                 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
 883                                 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
 884                                 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
 885                                 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
 886                                 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
 887                 };
 888
 889                 anoc2_smmu: iommu@16c0000 {
 890                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 891                         reg = <0x016c0000 0x40000>;
 892                         #iommu-cells = <1>;
 893
 894                         #global-interrupts = <0>;
 895                         interrupts =
 896                                 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
 897                                 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
 898                                 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
 899                                 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
 900                                 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
 901                                 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
 902                                 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
 903                                 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
 904                                 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
 905                                 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
 906                 };
 907
 908                 pcie0: pci@1c00000 {
 909                         compatible = "qcom,pcie-msm8996";
 910                         reg =   <0x01c00000 0x2000>,
 911                                 <0x1b000000 0xf1d>,
 912                                 <0x1b000f20 0xa8>,
 913                                 <0x1b100000 0x100000>;
 914                         reg-names = "parf", "dbi", "elbi", "config";
 915                         device_type = "pci";
 916                         linux,pci-domain = <0>;
 917                         bus-range = <0x00 0xff>;
 918                         #address-cells = <3>;
 919                         #size-cells = <2>;
 920                         num-lanes = <1>;
 921                         phys = <&pciephy>;
 922                         phy-names = "pciephy";
 923                         status = "disabled";
 924
 925                         ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
 926                                  <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
 927
 928                         #interrupt-cells = <1>;
 929                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 930                         interrupt-names = "msi";
 931                         interrupt-map-mask = <0 0 0 0x7>;
 932                         interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
 933                                         <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
 934                                         <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
 935                                         <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
 936
 937                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
 938                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 939                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
 940                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 941                                  <&gcc GCC_PCIE_0_AUX_CLK>;
 942                         clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
 943
 944                         power-domains = <&gcc PCIE_0_GDSC>;
 945                         iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
 946                         perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
 947                 };
 948
 949                 pcie_phy: phy@1c06000 {
 950                         compatible = "qcom,msm8998-qmp-pcie-phy";
 951                         reg = <0x01c06000 0x18c>;
 952                         #address-cells = <1>;
 953                         #size-cells = <1>;
 954                         status = "disabled";
 955                         ranges;
 956
 957                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 958                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 959                                  <&gcc GCC_PCIE_CLKREF_CLK>;
 960                         clock-names = "aux", "cfg_ahb", "ref";
 961
 962                         resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
 963                         reset-names = "phy", "common";
 964
 965                         vdda-phy-supply = <&vreg_l1a_0p875>;
 966                         vdda-pll-supply = <&vreg_l2a_1p2>;
 967
 968                         pciephy: phy@1c06800 {
 969                                 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
 970                                 #phy-cells = <0>;
 971
 972                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 973                                 clock-names = "pipe0";
 974                                 clock-output-names = "pcie_0_pipe_clk_src";
 975                                 #clock-cells = <0>;
 976                         };
 977                 };
 978
 979                 ufshc: ufshc@1da4000 {
 980                         compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
 981                         reg = <0x01da4000 0x2500>;
 982                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 983                         phys = <&ufsphy_lanes>;
 984                         phy-names = "ufsphy";
 985                         lanes-per-direction = <2>;
 986                         power-domains = <&gcc UFS_GDSC>;
 987                         status = "disabled";
 988                         #reset-cells = <1>;
 989
 990                         clock-names =
 991                                 "core_clk",
 992                                 "bus_aggr_clk",
 993                                 "iface_clk",
 994                                 "core_clk_unipro",
 995                                 "ref_clk",
 996                                 "tx_lane0_sync_clk",
 997                                 "rx_lane0_sync_clk",
 998                                 "rx_lane1_sync_clk";
 999                         clocks =
1000                                 <&gcc GCC_UFS_AXI_CLK>,
1001                                 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1002                                 <&gcc GCC_UFS_AHB_CLK>,
1003                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1004                                 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1005                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1006                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1007                                 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1008                         freq-table-hz =
1009                                 <50000000 200000000>,
1010                                 <0 0>,
1011                                 <0 0>,
1012                                 <37500000 150000000>,
1013                                 <0 0>,
1014                                 <0 0>,
1015                                 <0 0>,
1016                                 <0 0>;
1017
1018                         resets = <&gcc GCC_UFS_BCR>;
1019                         reset-names = "rst";
1020                 };
1021
1022                 ufsphy: phy@1da7000 {
1023                         compatible = "qcom,msm8998-qmp-ufs-phy";
1024                         reg = <0x01da7000 0x18c>;
1025                         #address-cells = <1>;
1026                         #size-cells = <1>;
1027                         status = "disabled";
1028                         ranges;
1029
1030                         clock-names =
1031                                 "ref",
1032                                 "ref_aux";
1033                         clocks =
1034                                 <&gcc GCC_UFS_CLKREF_CLK>,
1035                                 <&gcc GCC_UFS_PHY_AUX_CLK>;
1036
1037                         reset-names = "ufsphy";
1038                         resets = <&ufshc 0>;
1039
1040                         ufsphy_lanes: phy@1da7400 {
1041                                 reg = <0x01da7400 0x128>,
1042                                       <0x01da7600 0x1fc>,
1043                                       <0x01da7c00 0x1dc>,
1044                                       <0x01da7800 0x128>,
1045                                       <0x01da7a00 0x1fc>;
1046                                 #phy-cells = <0>;
1047                         };
1048                 };
1049
1050                 tcsr_mutex_regs: syscon@1f40000 {
1051                         compatible = "syscon";
1052                         reg = <0x01f40000 0x40000>;
1053                 };
1054
1055                 tlmm: pinctrl@3400000 {
1056                         compatible = "qcom,msm8998-pinctrl";
1057                         reg = <0x03400000 0xc00000>;
1058                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1059                         gpio-controller;
1060                         #gpio-cells = <0x2>;
1061                         interrupt-controller;
1062                         #interrupt-cells = <0x2>;
1063
1064                         sdc2_clk_on: sdc2_clk_on {
1065                                 config {
1066                                         pins = "sdc2_clk";
1067                                         bias-disable;
1068                                         drive-strength = <16>;
1069                                 };
1070                         };
1071
1072                         sdc2_clk_off: sdc2_clk_off {
1073                                 config {
1074                                         pins = "sdc2_clk";
1075                                         bias-disable;
1076                                         drive-strength = <2>;
1077                                 };
1078                         };
1079
1080                         sdc2_cmd_on: sdc2_cmd_on {
1081                                 config {
1082                                         pins = "sdc2_cmd";
1083                                         bias-pull-up;
1084                                         drive-strength = <10>;
1085                                 };
1086                         };
1087
1088                         sdc2_cmd_off: sdc2_cmd_off {
1089                                 config {
1090                                         pins = "sdc2_cmd";
1091                                         bias-pull-up;
1092                                         drive-strength = <2>;
1093                                 };
1094                         };
1095
1096                         sdc2_data_on: sdc2_data_on {
1097                                 config {
1098                                         pins = "sdc2_data";
1099                                         bias-pull-up;
1100                                         drive-strength = <10>;
1101                                 };
1102                         };
1103
1104                         sdc2_data_off: sdc2_data_off {
1105                                 config {
1106                                         pins = "sdc2_data";
1107                                         bias-pull-up;
1108                                         drive-strength = <2>;
1109                                 };
1110                         };
1111
1112                         sdc2_cd_on: sdc2_cd_on {
1113                                 mux {
1114                                         pins = "gpio95";
1115                                         function = "gpio";
1116                                 };
1117
1118                                 config {
1119                                         pins = "gpio95";
1120                                         bias-pull-up;
1121                                         drive-strength = <2>;
1122                                 };
1123                         };
1124
1125                         sdc2_cd_off: sdc2_cd_off {
1126                                 mux {
1127                                         pins = "gpio95";
1128                                         function = "gpio";
1129                                 };
1130
1131                                 config {
1132                                         pins = "gpio95";
1133                                         bias-pull-up;
1134                                         drive-strength = <2>;
1135                                 };
1136                         };
1137
1138                         blsp1_uart3_on: blsp1_uart3_on {
1139                                 tx {
1140                                         pins = "gpio45";
1141                                         function = "blsp_uart3_a";
1142                                         drive-strength = <2>;
1143                                         bias-disable;
1144                                 };
1145
1146                                 rx {
1147                                         pins = "gpio46";
1148                                         function = "blsp_uart3_a";
1149                                         drive-strength = <2>;
1150                                         bias-disable;
1151                                 };
1152
1153                                 cts {
1154                                         pins = "gpio47";
1155                                         function = "blsp_uart3_a";
1156                                         drive-strength = <2>;
1157                                         bias-disable;
1158                                 };
1159
1160                                 rfr {
1161                                         pins = "gpio48";
1162                                         function = "blsp_uart3_a";
1163                                         drive-strength = <2>;
1164                                         bias-disable;
1165                                 };
1166                         };
1167
1168                         blsp1_i2c1_default: blsp1-i2c1-default {
1169                                 pins = "gpio2", "gpio3";
1170                                 function = "blsp_i2c1";
1171                                 drive-strength = <2>;
1172                                 bias-disable;
1173                         };
1174
1175                         blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1176                                 pins = "gpio2", "gpio3";
1177                                 function = "blsp_i2c1";
1178                                 drive-strength = <2>;
1179                                 bias-pull-up;
1180                         };
1181
1182                         blsp1_i2c2_default: blsp1-i2c2-default {
1183                                 pins = "gpio32", "gpio33";
1184                                 function = "blsp_i2c2";
1185                                 drive-strength = <2>;
1186                                 bias-disable;
1187                         };
1188
1189                         blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1190                                 pins = "gpio32", "gpio33";
1191                                 function = "blsp_i2c2";
1192                                 drive-strength = <2>;
1193                                 bias-pull-up;
1194                         };
1195
1196                         blsp1_i2c3_default: blsp1-i2c3-default {
1197                                 pins = "gpio47", "gpio48";
1198                                 function = "blsp_i2c3";
1199                                 drive-strength = <2>;
1200                                 bias-disable;
1201                         };
1202
1203                         blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1204                                 pins = "gpio47", "gpio48";
1205                                 function = "blsp_i2c3";
1206                                 drive-strength = <2>;
1207                                 bias-pull-up;
1208                         };
1209
1210                         blsp1_i2c4_default: blsp1-i2c4-default {
1211                                 pins = "gpio10", "gpio11";
1212                                 function = "blsp_i2c4";
1213                                 drive-strength = <2>;
1214                                 bias-disable;
1215                         };
1216
1217                         blsp1_i2c4_sleep: blsp1-i2c4-sleep {
1218                                 pins = "gpio10", "gpio11";
1219                                 function = "blsp_i2c4";
1220                                 drive-strength = <2>;
1221                                 bias-pull-up;
1222                         };
1223
1224                         blsp1_i2c5_default: blsp1-i2c5-default {
1225                                 pins = "gpio87", "gpio88";
1226                                 function = "blsp_i2c5";
1227                                 drive-strength = <2>;
1228                                 bias-disable;
1229                         };
1230
1231                         blsp1_i2c5_sleep: blsp1-i2c5-sleep {
1232                                 pins = "gpio87", "gpio88";
1233                                 function = "blsp_i2c5";
1234                                 drive-strength = <2>;
1235                                 bias-pull-up;
1236                         };
1237
1238                         blsp1_i2c6_default: blsp1-i2c6-default {
1239                                 pins = "gpio43", "gpio44";
1240                                 function = "blsp_i2c6";
1241                                 drive-strength = <2>;
1242                                 bias-disable;
1243                         };
1244
1245                         blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1246                                 pins = "gpio43", "gpio44";
1247                                 function = "blsp_i2c6";
1248                                 drive-strength = <2>;
1249                                 bias-pull-up;
1250                         };
1251                         /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1252                         blsp2_i2c1_default: blsp2-i2c1-default {
1253                                 pins = "gpio55", "gpio56";
1254                                 function = "blsp_i2c7";
1255                                 drive-strength = <2>;
1256                                 bias-disable;
1257                         };
1258
1259                         blsp2_i2c1_sleep: blsp2-i2c1-sleep {
1260                                 pins = "gpio55", "gpio56";
1261                                 function = "blsp_i2c7";
1262                                 drive-strength = <2>;
1263                                 bias-pull-up;
1264                         };
1265
1266                         blsp2_i2c2_default: blsp2-i2c2-default {
1267                                 pins = "gpio6", "gpio7";
1268                                 function = "blsp_i2c8";
1269                                 drive-strength = <2>;
1270                                 bias-disable;
1271                         };
1272
1273                         blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1274                                 pins = "gpio6", "gpio7";
1275                                 function = "blsp_i2c8";
1276                                 drive-strength = <2>;
1277                                 bias-pull-up;
1278                         };
1279
1280                         blsp2_i2c3_default: blsp2-i2c3-default {
1281                                 pins = "gpio51", "gpio52";
1282                                 function = "blsp_i2c9";
1283                                 drive-strength = <2>;
1284                                 bias-disable;
1285                         };
1286
1287                         blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1288                                 pins = "gpio51", "gpio52";
1289                                 function = "blsp_i2c9";
1290                                 drive-strength = <2>;
1291                                 bias-pull-up;
1292                         };
1293
1294                         blsp2_i2c4_default: blsp2-i2c4-default {
1295                                 pins = "gpio67", "gpio68";
1296                                 function = "blsp_i2c10";
1297                                 drive-strength = <2>;
1298                                 bias-disable;
1299                         };
1300
1301                         blsp2_i2c4_sleep: blsp2-i2c4-sleep {
1302                                 pins = "gpio67", "gpio68";
1303                                 function = "blsp_i2c10";
1304                                 drive-strength = <2>;
1305                                 bias-pull-up;
1306                         };
1307
1308                         blsp2_i2c5_default: blsp2-i2c5-default {
1309                                 pins = "gpio60", "gpio61";
1310                                 function = "blsp_i2c11";
1311                                 drive-strength = <2>;
1312                                 bias-disable;
1313                         };
1314
1315                         blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1316                                 pins = "gpio60", "gpio61";
1317                                 function = "blsp_i2c11";
1318                                 drive-strength = <2>;
1319                                 bias-pull-up;
1320                         };
1321
1322                         blsp2_i2c6_default: blsp2-i2c6-default {
1323                                 pins = "gpio83", "gpio84";
1324                                 function = "blsp_i2c12";
1325                                 drive-strength = <2>;
1326                                 bias-disable;
1327                         };
1328
1329                         blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1330                                 pins = "gpio83", "gpio84";
1331                                 function = "blsp_i2c12";
1332                                 drive-strength = <2>;
1333                                 bias-pull-up;
1334                         };
1335                 };
1336
1337                 remoteproc_mss: remoteproc@4080000 {
1338                         compatible = "qcom,msm8998-mss-pil";
1339                         reg = <0x04080000 0x100>, <0x04180000 0x20>;
1340                         reg-names = "qdsp6", "rmb";
1341
1342                         interrupts-extended =
1343                                 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1344                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1345                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1346                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1347                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1348                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1349                         interrupt-names = "wdog", "fatal", "ready",
1350                                           "handover", "stop-ack",
1351                                           "shutdown-ack";
1352
1353                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1354                                  <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1355                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1356                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1357                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
1358                                  <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1359                                  <&rpmcc RPM_SMD_QDSS_CLK>,
1360                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1361                         clock-names = "iface", "bus", "mem", "gpll0_mss",
1362                                       "snoc_axi", "mnoc_axi", "qdss", "xo";
1363
1364                         qcom,smem-states = <&modem_smp2p_out 0>;
1365                         qcom,smem-state-names = "stop";
1366
1367                         resets = <&gcc GCC_MSS_RESTART>;
1368                         reset-names = "mss_restart";
1369
1370                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1371
1372                         power-domains = <&rpmpd MSM8998_VDDCX>,
1373                                         <&rpmpd MSM8998_VDDMX>;
1374                         power-domain-names = "cx", "mx";
1375
1376                         status = "disabled";
1377
1378                         mba {
1379                                 memory-region = <&mba_mem>;
1380                         };
1381
1382                         mpss {
1383                                 memory-region = <&mpss_mem>;
1384                         };
1385
1386                         glink-edge {
1387                                 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1388                                 label = "modem";
1389                                 qcom,remote-pid = <1>;
1390                                 mboxes = <&apcs_glb 15>;
1391                         };
1392                 };
1393
1394                 adreno_gpu: gpu@5000000 {
1395                         compatible = "qcom,adreno-540.1", "qcom,adreno";
1396                         reg = <0x05000000 0x40000>;
1397                         reg-names = "kgsl_3d0_reg_memory";
1398
1399                         clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1400                                 <&gpucc RBBMTIMER_CLK>,
1401                                 <&gcc GCC_BIMC_GFX_CLK>,
1402                                 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1403                                 <&gpucc RBCPR_CLK>,
1404                                 <&gpucc GFX3D_CLK>;
1405                         clock-names = "iface",
1406                                 "rbbmtimer",
1407                                 "mem",
1408                                 "mem_iface",
1409                                 "rbcpr",
1410                                 "core";
1411
1412                         interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1413                         iommus = <&adreno_smmu 0>;
1414                         operating-points-v2 = <&gpu_opp_table>;
1415                         power-domains = <&rpmpd MSM8998_VDDMX>;
1416                         status = "disabled";
1417
1418                         gpu_opp_table: opp-table {
1419                                 compatible  = "operating-points-v2";
1420                                 opp-710000097 {
1421                                         opp-hz = /bits/ 64 <710000097>;
1422                                         opp-level = <RPM_SMD_LEVEL_TURBO>;
1423                                         opp-supported-hw = <0xFF>;
1424                                 };
1425
1426                                 opp-670000048 {
1427                                         opp-hz = /bits/ 64 <670000048>;
1428                                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1429                                         opp-supported-hw = <0xFF>;
1430                                 };
1431
1432                                 opp-596000097 {
1433                                         opp-hz = /bits/ 64 <596000097>;
1434                                         opp-level = <RPM_SMD_LEVEL_NOM>;
1435                                         opp-supported-hw = <0xFF>;
1436                                 };
1437
1438                                 opp-515000097 {
1439                                         opp-hz = /bits/ 64 <515000097>;
1440                                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1441                                         opp-supported-hw = <0xFF>;
1442                                 };
1443
1444                                 opp-414000000 {
1445                                         opp-hz = /bits/ 64 <414000000>;
1446                                         opp-level = <RPM_SMD_LEVEL_SVS>;
1447                                         opp-supported-hw = <0xFF>;
1448                                 };
1449
1450                                 opp-342000000 {
1451                                         opp-hz = /bits/ 64 <342000000>;
1452                                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1453                                         opp-supported-hw = <0xFF>;
1454                                 };
1455
1456                                 opp-257000000 {
1457                                         opp-hz = /bits/ 64 <257000000>;
1458                                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1459                                         opp-supported-hw = <0xFF>;
1460                                 };
1461                         };
1462                 };
1463
1464                 adreno_smmu: iommu@5040000 {
1465                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1466                         reg = <0x05040000 0x10000>;
1467                         clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1468                                  <&gcc GCC_BIMC_GFX_CLK>,
1469                                  <&gcc GCC_GPU_BIMC_GFX_CLK>;
1470                         clock-names = "iface", "mem", "mem_iface";
1471
1472                         #global-interrupts = <0>;
1473                         #iommu-cells = <1>;
1474                         interrupts =
1475                                 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1476                                 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1477                                 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1478                         /*
1479                          * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1480                          * GPU-CX for SMMU but we need both of them up for Adreno.
1481                          * Contemporarily, we also need to manage the VDDMX rpmpd
1482                          * domain in the Adreno driver.
1483                          * Enable GPU CX/GX GDSCs here so that we can manage the
1484                          * SoC VDDMX RPM Power Domain in the Adreno driver.
1485                          */
1486                         power-domains = <&gpucc GPU_GX_GDSC>;
1487                         status = "disabled";
1488                 };
1489
1490                 gpucc: clock-controller@5065000 {
1491                         compatible = "qcom,msm8998-gpucc";
1492                         #clock-cells = <1>;
1493                         #reset-cells = <1>;
1494                         #power-domain-cells = <1>;
1495                         reg = <0x05065000 0x9000>;
1496
1497                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1498                                  <&gcc GPLL0_OUT_MAIN>;
1499                         clock-names = "xo",
1500                                       "gpll0";
1501                 };
1502
1503                 remoteproc_slpi: remoteproc@5800000 {
1504                         compatible = "qcom,msm8998-slpi-pas";
1505                         reg = <0x05800000 0x4040>;
1506
1507                         interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1508                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1509                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1510                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1511                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1512                         interrupt-names = "wdog", "fatal", "ready",
1513                                           "handover", "stop-ack";
1514
1515                         px-supply = <&vreg_lvs2a_1p8>;
1516
1517                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1518                                  <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1519                         clock-names = "xo", "aggre2";
1520
1521                         memory-region = <&slpi_mem>;
1522
1523                         qcom,smem-states = <&slpi_smp2p_out 0>;
1524                         qcom,smem-state-names = "stop";
1525
1526                         power-domains = <&rpmpd MSM8998_SSCCX>;
1527                         power-domain-names = "ssc_cx";
1528
1529                         status = "disabled";
1530
1531                         glink-edge {
1532                                 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1533                                 label = "dsps";
1534                                 qcom,remote-pid = <3>;
1535                                 mboxes = <&apcs_glb 27>;
1536                         };
1537                 };
1538
1539                 stm: stm@6002000 {
1540                         compatible = "arm,coresight-stm", "arm,primecell";
1541                         reg = <0x06002000 0x1000>,
1542                               <0x16280000 0x180000>;
1543                         reg-names = "stm-base", "stm-data-base";
1544                         status = "disabled";
1545
1546                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1547                         clock-names = "apb_pclk", "atclk";
1548
1549                         out-ports {
1550                                 port {
1551                                         stm_out: endpoint {
1552                                                 remote-endpoint = <&funnel0_in7>;
1553                                         };
1554                                 };
1555                         };
1556                 };
1557
1558                 funnel1: funnel@6041000 {
1559                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1560                         reg = <0x06041000 0x1000>;
1561                         status = "disabled";
1562
1563                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1564                         clock-names = "apb_pclk", "atclk";
1565
1566                         out-ports {
1567                                 port {
1568                                         funnel0_out: endpoint {
1569                                                 remote-endpoint =
1570                                                   <&merge_funnel_in0>;
1571                                         };
1572                                 };
1573                         };
1574
1575                         in-ports {
1576                                 #address-cells = <1>;
1577                                 #size-cells = <0>;
1578
1579                                 port@7 {
1580                                         reg = <7>;
1581                                         funnel0_in7: endpoint {
1582                                                 remote-endpoint = <&stm_out>;
1583                                         };
1584                                 };
1585                         };
1586                 };
1587
1588                 funnel2: funnel@6042000 {
1589                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1590                         reg = <0x06042000 0x1000>;
1591                         status = "disabled";
1592
1593                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1594                         clock-names = "apb_pclk", "atclk";
1595
1596                         out-ports {
1597                                 port {
1598                                         funnel1_out: endpoint {
1599                                                 remote-endpoint =
1600                                                   <&merge_funnel_in1>;
1601                                         };
1602                                 };
1603                         };
1604
1605                         in-ports {
1606                                 #address-cells = <1>;
1607                                 #size-cells = <0>;
1608
1609                                 port@6 {
1610                                         reg = <6>;
1611                                         funnel1_in6: endpoint {
1612                                                 remote-endpoint =
1613                                                   <&apss_merge_funnel_out>;
1614                                         };
1615                                 };
1616                         };
1617                 };
1618
1619                 funnel3: funnel@6045000 {
1620                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1621                         reg = <0x06045000 0x1000>;
1622                         status = "disabled";
1623
1624                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1625                         clock-names = "apb_pclk", "atclk";
1626
1627                         out-ports {
1628                                 port {
1629                                         merge_funnel_out: endpoint {
1630                                                 remote-endpoint =
1631                                                   <&etf_in>;
1632                                         };
1633                                 };
1634                         };
1635
1636                         in-ports {
1637                                 #address-cells = <1>;
1638                                 #size-cells = <0>;
1639
1640                                 port@0 {
1641                                         reg = <0>;
1642                                         merge_funnel_in0: endpoint {
1643                                                 remote-endpoint =
1644                                                   <&funnel0_out>;
1645                                         };
1646                                 };
1647
1648                                 port@1 {
1649                                         reg = <1>;
1650                                         merge_funnel_in1: endpoint {
1651                                                 remote-endpoint =
1652                                                   <&funnel1_out>;
1653                                         };
1654                                 };
1655                         };
1656                 };
1657
1658                 replicator1: replicator@6046000 {
1659                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1660                         reg = <0x06046000 0x1000>;
1661                         status = "disabled";
1662
1663                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1664                         clock-names = "apb_pclk", "atclk";
1665
1666                         out-ports {
1667                                 port {
1668                                         replicator_out: endpoint {
1669                                                 remote-endpoint = <&etr_in>;
1670                                         };
1671                                 };
1672                         };
1673
1674                         in-ports {
1675                                 port {
1676                                         replicator_in: endpoint {
1677                                                 remote-endpoint = <&etf_out>;
1678                                         };
1679                                 };
1680                         };
1681                 };
1682
1683                 etf: etf@6047000 {
1684                         compatible = "arm,coresight-tmc", "arm,primecell";
1685                         reg = <0x06047000 0x1000>;
1686                         status = "disabled";
1687
1688                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1689                         clock-names = "apb_pclk", "atclk";
1690
1691                         out-ports {
1692                                 port {
1693                                         etf_out: endpoint {
1694                                                 remote-endpoint =
1695                                                   <&replicator_in>;
1696                                         };
1697                                 };
1698                         };
1699
1700                         in-ports {
1701                                 port {
1702                                         etf_in: endpoint {
1703                                                 remote-endpoint =
1704                                                   <&merge_funnel_out>;
1705                                         };
1706                                 };
1707                         };
1708                 };
1709
1710                 etr: etr@6048000 {
1711                         compatible = "arm,coresight-tmc", "arm,primecell";
1712                         reg = <0x06048000 0x1000>;
1713                         status = "disabled";
1714
1715                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1716                         clock-names = "apb_pclk", "atclk";
1717                         arm,scatter-gather;
1718
1719                         in-ports {
1720                                 port {
1721                                         etr_in: endpoint {
1722                                                 remote-endpoint =
1723                                                   <&replicator_out>;
1724                                         };
1725                                 };
1726                         };
1727                 };
1728
1729                 etm1: etm@7840000 {
1730                         compatible = "arm,coresight-etm4x", "arm,primecell";
1731                         reg = <0x07840000 0x1000>;
1732                         status = "disabled";
1733
1734                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1735                         clock-names = "apb_pclk", "atclk";
1736
1737                         cpu = <&CPU0>;
1738
1739                         out-ports {
1740                                 port {
1741                                         etm0_out: endpoint {
1742                                                 remote-endpoint =
1743                                                   <&apss_funnel_in0>;
1744                                         };
1745                                 };
1746                         };
1747                 };
1748
1749                 etm2: etm@7940000 {
1750                         compatible = "arm,coresight-etm4x", "arm,primecell";
1751                         reg = <0x07940000 0x1000>;
1752                         status = "disabled";
1753
1754                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1755                         clock-names = "apb_pclk", "atclk";
1756
1757                         cpu = <&CPU1>;
1758
1759                         out-ports {
1760                                 port {
1761                                         etm1_out: endpoint {
1762                                                 remote-endpoint =
1763                                                   <&apss_funnel_in1>;
1764                                         };
1765                                 };
1766                         };
1767                 };
1768
1769                 etm3: etm@7a40000 {
1770                         compatible = "arm,coresight-etm4x", "arm,primecell";
1771                         reg = <0x07a40000 0x1000>;
1772                         status = "disabled";
1773
1774                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1775                         clock-names = "apb_pclk", "atclk";
1776
1777                         cpu = <&CPU2>;
1778
1779                         out-ports {
1780                                 port {
1781                                         etm2_out: endpoint {
1782                                                 remote-endpoint =
1783                                                   <&apss_funnel_in2>;
1784                                         };
1785                                 };
1786                         };
1787                 };
1788
1789                 etm4: etm@7b40000 {
1790                         compatible = "arm,coresight-etm4x", "arm,primecell";
1791                         reg = <0x07b40000 0x1000>;
1792                         status = "disabled";
1793
1794                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1795                         clock-names = "apb_pclk", "atclk";
1796
1797                         cpu = <&CPU3>;
1798
1799                         out-ports {
1800                                 port {
1801                                         etm3_out: endpoint {
1802                                                 remote-endpoint =
1803                                                   <&apss_funnel_in3>;
1804                                         };
1805                                 };
1806                         };
1807                 };
1808
1809                 funnel4: funnel@7b60000 { /* APSS Funnel */
1810                         compatible = "arm,coresight-etm4x", "arm,primecell";
1811                         reg = <0x07b60000 0x1000>;
1812                         status = "disabled";
1813
1814                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1815                         clock-names = "apb_pclk", "atclk";
1816
1817                         out-ports {
1818                                 port {
1819                                         apss_funnel_out: endpoint {
1820                                                 remote-endpoint =
1821                                                   <&apss_merge_funnel_in>;
1822                                         };
1823                                 };
1824                         };
1825
1826                         in-ports {
1827                                 #address-cells = <1>;
1828                                 #size-cells = <0>;
1829
1830                                 port@0 {
1831                                         reg = <0>;
1832                                         apss_funnel_in0: endpoint {
1833                                                 remote-endpoint =
1834                                                   <&etm0_out>;
1835                                         };
1836                                 };
1837
1838                                 port@1 {
1839                                         reg = <1>;
1840                                         apss_funnel_in1: endpoint {
1841                                                 remote-endpoint =
1842                                                   <&etm1_out>;
1843                                         };
1844                                 };
1845
1846                                 port@2 {
1847                                         reg = <2>;
1848                                         apss_funnel_in2: endpoint {
1849                                                 remote-endpoint =
1850                                                   <&etm2_out>;
1851                                         };
1852                                 };
1853
1854                                 port@3 {
1855                                         reg = <3>;
1856                                         apss_funnel_in3: endpoint {
1857                                                 remote-endpoint =
1858                                                   <&etm3_out>;
1859                                         };
1860                                 };
1861
1862                                 port@4 {
1863                                         reg = <4>;
1864                                         apss_funnel_in4: endpoint {
1865                                                 remote-endpoint =
1866                                                   <&etm4_out>;
1867                                         };
1868                                 };
1869
1870                                 port@5 {
1871                                         reg = <5>;
1872                                         apss_funnel_in5: endpoint {
1873                                                 remote-endpoint =
1874                                                   <&etm5_out>;
1875                                         };
1876                                 };
1877
1878                                 port@6 {
1879                                         reg = <6>;
1880                                         apss_funnel_in6: endpoint {
1881                                                 remote-endpoint =
1882                                                   <&etm6_out>;
1883                                         };
1884                                 };
1885
1886                                 port@7 {
1887                                         reg = <7>;
1888                                         apss_funnel_in7: endpoint {
1889                                                 remote-endpoint =
1890                                                   <&etm7_out>;
1891                                         };
1892                                 };
1893                         };
1894                 };
1895
1896                 funnel5: funnel@7b70000 {
1897                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1898                         reg = <0x07b70000 0x1000>;
1899                         status = "disabled";
1900
1901                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1902                         clock-names = "apb_pclk", "atclk";
1903
1904                         out-ports {
1905                                 port {
1906                                         apss_merge_funnel_out: endpoint {
1907                                                 remote-endpoint =
1908                                                   <&funnel1_in6>;
1909                                         };
1910                                 };
1911                         };
1912
1913                         in-ports {
1914                                 port {
1915                                         apss_merge_funnel_in: endpoint {
1916                                                 remote-endpoint =
1917                                                   <&apss_funnel_out>;
1918                                         };
1919                                 };
1920                         };
1921                 };
1922
1923                 etm5: etm@7c40000 {
1924                         compatible = "arm,coresight-etm4x", "arm,primecell";
1925                         reg = <0x07c40000 0x1000>;
1926                         status = "disabled";
1927
1928                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1929                         clock-names = "apb_pclk", "atclk";
1930
1931                         cpu = <&CPU4>;
1932
1933                         port{
1934                                 etm4_out: endpoint {
1935                                         remote-endpoint = <&apss_funnel_in4>;
1936                                 };
1937                         };
1938                 };
1939
1940                 etm6: etm@7d40000 {
1941                         compatible = "arm,coresight-etm4x", "arm,primecell";
1942                         reg = <0x07d40000 0x1000>;
1943                         status = "disabled";
1944
1945                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1946                         clock-names = "apb_pclk", "atclk";
1947
1948                         cpu = <&CPU5>;
1949
1950                         port{
1951                                 etm5_out: endpoint {
1952                                         remote-endpoint = <&apss_funnel_in5>;
1953                                 };
1954                         };
1955                 };
1956
1957                 etm7: etm@7e40000 {
1958                         compatible = "arm,coresight-etm4x", "arm,primecell";
1959                         reg = <0x07e40000 0x1000>;
1960                         status = "disabled";
1961
1962                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1963                         clock-names = "apb_pclk", "atclk";
1964
1965                         cpu = <&CPU6>;
1966
1967                         port{
1968                                 etm6_out: endpoint {
1969                                         remote-endpoint = <&apss_funnel_in6>;
1970                                 };
1971                         };
1972                 };
1973
1974                 etm8: etm@7f40000 {
1975                         compatible = "arm,coresight-etm4x", "arm,primecell";
1976                         reg = <0x07f40000 0x1000>;
1977                         status = "disabled";
1978
1979                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1980                         clock-names = "apb_pclk", "atclk";
1981
1982                         cpu = <&CPU7>;
1983
1984                         port{
1985                                 etm7_out: endpoint {
1986                                         remote-endpoint = <&apss_funnel_in7>;
1987                                 };
1988                         };
1989                 };
1990
1991                 sram@290000 {
1992                         compatible = "qcom,rpm-stats";
1993                         reg = <0x00290000 0x10000>;
1994                 };
1995
1996                 spmi_bus: spmi@800f000 {
1997                         compatible = "qcom,spmi-pmic-arb";
1998                         reg =   <0x0800f000 0x1000>,
1999                                 <0x08400000 0x1000000>,
2000                                 <0x09400000 0x1000000>,
2001                                 <0x0a400000 0x220000>,
2002                                 <0x0800a000 0x3000>;
2003                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2004                         interrupt-names = "periph_irq";
2005                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2006                         qcom,ee = <0>;
2007                         qcom,channel = <0>;
2008                         #address-cells = <2>;
2009                         #size-cells = <0>;
2010                         interrupt-controller;
2011                         #interrupt-cells = <4>;
2012                         cell-index = <0>;
2013                 };
2014
2015                 usb3: usb@a8f8800 {
2016                         compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2017                         reg = <0x0a8f8800 0x400>;
2018                         status = "disabled";
2019                         #address-cells = <1>;
2020                         #size-cells = <1>;
2021                         ranges;
2022
2023                         clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2024                                  <&gcc GCC_USB30_MASTER_CLK>,
2025                                  <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2026                                  <&gcc GCC_USB30_SLEEP_CLK>,
2027                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2028                         clock-names = "cfg_noc",
2029                                       "core",
2030                                       "iface",
2031                                       "sleep",
2032                                       "mock_utmi";
2033
2034                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2035                                           <&gcc GCC_USB30_MASTER_CLK>;
2036                         assigned-clock-rates = <19200000>, <120000000>;
2037
2038                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2039                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2040                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
2041
2042                         power-domains = <&gcc USB_30_GDSC>;
2043
2044                         resets = <&gcc GCC_USB_30_BCR>;
2045
2046                         usb3_dwc3: usb@a800000 {
2047                                 compatible = "snps,dwc3";
2048                                 reg = <0x0a800000 0xcd00>;
2049                                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2050                                 snps,dis_u2_susphy_quirk;
2051                                 snps,dis_enblslpm_quirk;
2052                                 phys = <&qusb2phy>, <&usb1_ssphy>;
2053                                 phy-names = "usb2-phy", "usb3-phy";
2054                                 snps,has-lpm-erratum;
2055                                 snps,hird-threshold = /bits/ 8 <0x10>;
2056                         };
2057                 };
2058
2059                 usb3phy: phy@c010000 {
2060                         compatible = "qcom,msm8998-qmp-usb3-phy";
2061                         reg = <0x0c010000 0x18c>;
2062                         status = "disabled";
2063                         #address-cells = <1>;
2064                         #size-cells = <1>;
2065                         ranges;
2066
2067                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2068                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2069                                  <&gcc GCC_USB3_CLKREF_CLK>;
2070                         clock-names = "aux", "cfg_ahb", "ref";
2071
2072                         resets = <&gcc GCC_USB3_PHY_BCR>,
2073                                  <&gcc GCC_USB3PHY_PHY_BCR>;
2074                         reset-names = "phy", "common";
2075
2076                         usb1_ssphy: phy@c010200 {
2077                                 reg = <0xc010200 0x128>,
2078                                       <0xc010400 0x200>,
2079                                       <0xc010c00 0x20c>,
2080                                       <0xc010600 0x128>,
2081                                       <0xc010800 0x200>;
2082                                 #phy-cells = <0>;
2083                                 #clock-cells = <1>;
2084                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2085                                 clock-names = "pipe0";
2086                                 clock-output-names = "usb3_phy_pipe_clk_src";
2087                         };
2088                 };
2089
2090                 qusb2phy: phy@c012000 {
2091                         compatible = "qcom,msm8998-qusb2-phy";
2092                         reg = <0x0c012000 0x2a8>;
2093                         status = "disabled";
2094                         #phy-cells = <0>;
2095
2096                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2097                                  <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2098                         clock-names = "cfg_ahb", "ref";
2099
2100                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2101
2102                         nvmem-cells = <&qusb2_hstx_trim>;
2103                 };
2104
2105                 sdhc2: sdhci@c0a4900 {
2106                         compatible = "qcom,sdhci-msm-v4";
2107                         reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2108                         reg-names = "hc_mem", "core_mem";
2109
2110                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2111                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2112                         interrupt-names = "hc_irq", "pwr_irq";
2113
2114                         clock-names = "iface", "core", "xo";
2115                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2116                                  <&gcc GCC_SDCC2_APPS_CLK>,
2117                                  <&xo>;
2118                         bus-width = <4>;
2119                         status = "disabled";
2120                 };
2121
2122                 blsp1_dma: dma-controller@c144000 {
2123                         compatible = "qcom,bam-v1.7.0";
2124                         reg = <0x0c144000 0x25000>;
2125                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2126                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2127                         clock-names = "bam_clk";
2128                         #dma-cells = <1>;
2129                         qcom,ee = <0>;
2130                         qcom,controlled-remotely;
2131                         num-channels = <18>;
2132                         qcom,num-ees = <4>;
2133                 };
2134
2135                 blsp1_uart3: serial@c171000 {
2136                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2137                         reg = <0x0c171000 0x1000>;
2138                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2139                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2140                                  <&gcc GCC_BLSP1_AHB_CLK>;
2141                         clock-names = "core", "iface";
2142                         dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2143                         dma-names = "tx", "rx";
2144                         pinctrl-names = "default";
2145                         pinctrl-0 = <&blsp1_uart3_on>;
2146                         status = "disabled";
2147                 };
2148
2149                 blsp1_i2c1: i2c@c175000 {
2150                         compatible = "qcom,i2c-qup-v2.2.1";
2151                         reg = <0x0c175000 0x600>;
2152                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2153
2154                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2155                                  <&gcc GCC_BLSP1_AHB_CLK>;
2156                         clock-names = "core", "iface";
2157                         dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2158                         dma-names = "tx", "rx";
2159                         pinctrl-names = "default", "sleep";
2160                         pinctrl-0 = <&blsp1_i2c1_default>;
2161                         pinctrl-1 = <&blsp1_i2c1_sleep>;
2162                         clock-frequency = <400000>;
2163
2164                         status = "disabled";
2165                         #address-cells = <1>;
2166                         #size-cells = <0>;
2167                 };
2168
2169                 blsp1_i2c2: i2c@c176000 {
2170                         compatible = "qcom,i2c-qup-v2.2.1";
2171                         reg = <0x0c176000 0x600>;
2172                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2173
2174                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2175                                  <&gcc GCC_BLSP1_AHB_CLK>;
2176                         clock-names = "core", "iface";
2177                         dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2178                         dma-names = "tx", "rx";
2179                         pinctrl-names = "default", "sleep";
2180                         pinctrl-0 = <&blsp1_i2c2_default>;
2181                         pinctrl-1 = <&blsp1_i2c2_sleep>;
2182                         clock-frequency = <400000>;
2183
2184                         status = "disabled";
2185                         #address-cells = <1>;
2186                         #size-cells = <0>;
2187                 };
2188
2189                 blsp1_i2c3: i2c@c177000 {
2190                         compatible = "qcom,i2c-qup-v2.2.1";
2191                         reg = <0x0c177000 0x600>;
2192                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2193
2194                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2195                                  <&gcc GCC_BLSP1_AHB_CLK>;
2196                         clock-names = "core", "iface";
2197                         dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2198                         dma-names = "tx", "rx";
2199                         pinctrl-names = "default", "sleep";
2200                         pinctrl-0 = <&blsp1_i2c3_default>;
2201                         pinctrl-1 = <&blsp1_i2c3_sleep>;
2202                         clock-frequency = <400000>;
2203
2204                         status = "disabled";
2205                         #address-cells = <1>;
2206                         #size-cells = <0>;
2207                 };
2208
2209                 blsp1_i2c4: i2c@c178000 {
2210                         compatible = "qcom,i2c-qup-v2.2.1";
2211                         reg = <0x0c178000 0x600>;
2212                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2213
2214                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2215                                  <&gcc GCC_BLSP1_AHB_CLK>;
2216                         clock-names = "core", "iface";
2217                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2218                         dma-names = "tx", "rx";
2219                         pinctrl-names = "default", "sleep";
2220                         pinctrl-0 = <&blsp1_i2c4_default>;
2221                         pinctrl-1 = <&blsp1_i2c4_sleep>;
2222                         clock-frequency = <400000>;
2223
2224                         status = "disabled";
2225                         #address-cells = <1>;
2226                         #size-cells = <0>;
2227                 };
2228
2229                 blsp1_i2c5: i2c@c179000 {
2230                         compatible = "qcom,i2c-qup-v2.2.1";
2231                         reg = <0x0c179000 0x600>;
2232                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2233
2234                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2235                                  <&gcc GCC_BLSP1_AHB_CLK>;
2236                         clock-names = "core", "iface";
2237                         dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2238                         dma-names = "tx", "rx";
2239                         pinctrl-names = "default", "sleep";
2240                         pinctrl-0 = <&blsp1_i2c5_default>;
2241                         pinctrl-1 = <&blsp1_i2c5_sleep>;
2242                         clock-frequency = <400000>;
2243
2244                         status = "disabled";
2245                         #address-cells = <1>;
2246                         #size-cells = <0>;
2247                 };
2248
2249                 blsp1_i2c6: i2c@c17a000 {
2250                         compatible = "qcom,i2c-qup-v2.2.1";
2251                         reg = <0x0c17a000 0x600>;
2252                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2253
2254                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2255                                  <&gcc GCC_BLSP1_AHB_CLK>;
2256                         clock-names = "core", "iface";
2257                         dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2258                         dma-names = "tx", "rx";
2259                         pinctrl-names = "default", "sleep";
2260                         pinctrl-0 = <&blsp1_i2c6_default>;
2261                         pinctrl-1 = <&blsp1_i2c6_sleep>;
2262                         clock-frequency = <400000>;
2263
2264                         status = "disabled";
2265                         #address-cells = <1>;
2266                         #size-cells = <0>;
2267                 };
2268
2269                 blsp2_dma: dma-controller@c184000 {
2270                         compatible = "qcom,bam-v1.7.0";
2271                         reg = <0x0c184000 0x25000>;
2272                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2273                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2274                         clock-names = "bam_clk";
2275                         #dma-cells = <1>;
2276                         qcom,ee = <0>;
2277                         qcom,controlled-remotely;
2278                         num-channels = <18>;
2279                         qcom,num-ees = <4>;
2280                 };
2281
2282                 blsp2_uart1: serial@c1b0000 {
2283                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2284                         reg = <0x0c1b0000 0x1000>;
2285                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2286                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2287                                  <&gcc GCC_BLSP2_AHB_CLK>;
2288                         clock-names = "core", "iface";
2289                         status = "disabled";
2290                 };
2291
2292                 blsp2_i2c1: i2c@c1b5000 {
2293                         compatible = "qcom,i2c-qup-v2.2.1";
2294                         reg = <0x0c1b5000 0x600>;
2295                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2296
2297                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2298                                  <&gcc GCC_BLSP2_AHB_CLK>;
2299                         clock-names = "core", "iface";
2300                         dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2301                         dma-names = "tx", "rx";
2302                         pinctrl-names = "default", "sleep";
2303                         pinctrl-0 = <&blsp2_i2c1_default>;
2304                         pinctrl-1 = <&blsp2_i2c1_sleep>;
2305                         clock-frequency = <400000>;
2306
2307                         status = "disabled";
2308                         #address-cells = <1>;
2309                         #size-cells = <0>;
2310                 };
2311
2312                 blsp2_i2c2: i2c@c1b6000 {
2313                         compatible = "qcom,i2c-qup-v2.2.1";
2314                         reg = <0x0c1b6000 0x600>;
2315                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2316
2317                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2318                                  <&gcc GCC_BLSP2_AHB_CLK>;
2319                         clock-names = "core", "iface";
2320                         dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2321                         dma-names = "tx", "rx";
2322                         pinctrl-names = "default", "sleep";
2323                         pinctrl-0 = <&blsp2_i2c2_default>;
2324                         pinctrl-1 = <&blsp2_i2c2_sleep>;
2325                         clock-frequency = <400000>;
2326
2327                         status = "disabled";
2328                         #address-cells = <1>;
2329                         #size-cells = <0>;
2330                 };
2331
2332                 blsp2_i2c3: i2c@c1b7000 {
2333                         compatible = "qcom,i2c-qup-v2.2.1";
2334                         reg = <0x0c1b7000 0x600>;
2335                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2336
2337                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2338                                  <&gcc GCC_BLSP2_AHB_CLK>;
2339                         clock-names = "core", "iface";
2340                         dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2341                         dma-names = "tx", "rx";
2342                         pinctrl-names = "default", "sleep";
2343                         pinctrl-0 = <&blsp2_i2c3_default>;
2344                         pinctrl-1 = <&blsp2_i2c3_sleep>;
2345                         clock-frequency = <400000>;
2346
2347                         status = "disabled";
2348                         #address-cells = <1>;
2349                         #size-cells = <0>;
2350                 };
2351
2352                 blsp2_i2c4: i2c@c1b8000 {
2353                         compatible = "qcom,i2c-qup-v2.2.1";
2354                         reg = <0x0c1b8000 0x600>;
2355                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2356
2357                         clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2358                                  <&gcc GCC_BLSP2_AHB_CLK>;
2359                         clock-names = "core", "iface";
2360                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2361                         dma-names = "tx", "rx";
2362                         pinctrl-names = "default", "sleep";
2363                         pinctrl-0 = <&blsp2_i2c4_default>;
2364                         pinctrl-1 = <&blsp2_i2c4_sleep>;
2365                         clock-frequency = <400000>;
2366
2367                         status = "disabled";
2368                         #address-cells = <1>;
2369                         #size-cells = <0>;
2370                 };
2371
2372                 blsp2_i2c5: i2c@c1b9000 {
2373                         compatible = "qcom,i2c-qup-v2.2.1";
2374                         reg = <0x0c1b9000 0x600>;
2375                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2376
2377                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2378                                  <&gcc GCC_BLSP2_AHB_CLK>;
2379                         clock-names = "core", "iface";
2380                         dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2381                         dma-names = "tx", "rx";
2382                         pinctrl-names = "default", "sleep";
2383                         pinctrl-0 = <&blsp2_i2c5_default>;
2384                         pinctrl-1 = <&blsp2_i2c5_sleep>;
2385                         clock-frequency = <400000>;
2386
2387                         status = "disabled";
2388                         #address-cells = <1>;
2389                         #size-cells = <0>;
2390                 };
2391
2392                 blsp2_i2c6: i2c@c1ba000 {
2393                         compatible = "qcom,i2c-qup-v2.2.1";
2394                         reg = <0x0c1ba000 0x600>;
2395                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2396
2397                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2398                                  <&gcc GCC_BLSP2_AHB_CLK>;
2399                         clock-names = "core", "iface";
2400                         dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2401                         dma-names = "tx", "rx";
2402                         pinctrl-names = "default", "sleep";
2403                         pinctrl-0 = <&blsp2_i2c6_default>;
2404                         pinctrl-1 = <&blsp2_i2c6_sleep>;
2405                         clock-frequency = <400000>;
2406
2407                         status = "disabled";
2408                         #address-cells = <1>;
2409                         #size-cells = <0>;
2410                 };
2411
2412                 mmcc: clock-controller@c8c0000 {
2413                         compatible = "qcom,mmcc-msm8998";
2414                         #clock-cells = <1>;
2415                         #reset-cells = <1>;
2416                         #power-domain-cells = <1>;
2417                         reg = <0xc8c0000 0x40000>;
2418                         status = "disabled";
2419
2420                         clock-names = "xo",
2421                                       "gpll0",
2422                                       "dsi0dsi",
2423                                       "dsi0byte",
2424                                       "dsi1dsi",
2425                                       "dsi1byte",
2426                                       "hdmipll",
2427                                       "dplink",
2428                                       "dpvco",
2429                                       "core_bi_pll_test_se";
2430                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2431                                  <&gcc GCC_MMSS_GPLL0_CLK>,
2432                                  <0>,
2433                                  <0>,
2434                                  <0>,
2435                                  <0>,
2436                                  <0>,
2437                                  <0>,
2438                                  <0>,
2439                                  <0>;
2440                 };
2441
2442                 mmss_smmu: iommu@cd00000 {
2443                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
2444                         reg = <0x0cd00000 0x40000>;
2445                         #iommu-cells = <1>;
2446
2447                         clocks = <&mmcc MNOC_AHB_CLK>,
2448                                  <&mmcc BIMC_SMMU_AHB_CLK>,
2449                                  <&rpmcc RPM_SMD_MMAXI_CLK>,
2450                                  <&mmcc BIMC_SMMU_AXI_CLK>;
2451                         clock-names = "iface-mm", "iface-smmu",
2452                                       "bus-mm", "bus-smmu";
2453                         status = "disabled";
2454
2455                         #global-interrupts = <0>;
2456                         interrupts =
2457                                 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2458                                 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2459                                 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2460                                 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2461                                 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2462                                 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2463                                 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2464                                 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2465                                 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2466                                 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2467                                 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2468                                 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2469                                 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2470                                 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2471                                 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2472                                 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2473                                 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2474                                 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2475                                 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2476                                 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2477                 };
2478
2479                 remoteproc_adsp: remoteproc@17300000 {
2480                         compatible = "qcom,msm8998-adsp-pas";
2481                         reg = <0x17300000 0x4040>;
2482
2483                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2484                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2485                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2486                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2487                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2488                         interrupt-names = "wdog", "fatal", "ready",
2489                                           "handover", "stop-ack";
2490
2491                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2492                         clock-names = "xo";
2493
2494                         memory-region = <&adsp_mem>;
2495
2496                         qcom,smem-states = <&adsp_smp2p_out 0>;
2497                         qcom,smem-state-names = "stop";
2498
2499                         power-domains = <&rpmpd MSM8998_VDDCX>;
2500                         power-domain-names = "cx";
2501
2502                         status = "disabled";
2503
2504                         glink-edge {
2505                                 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2506                                 label = "lpass";
2507                                 qcom,remote-pid = <2>;
2508                                 mboxes = <&apcs_glb 9>;
2509                         };
2510                 };
2511
2512                 apcs_glb: mailbox@17911000 {
2513                         compatible = "qcom,msm8998-apcs-hmss-global";
2514                         reg = <0x17911000 0x1000>;
2515
2516                         #mbox-cells = <1>;
2517                 };
2518
2519                 timer@17920000 {
2520                         #address-cells = <1>;
2521                         #size-cells = <1>;
2522                         ranges;
2523                         compatible = "arm,armv7-timer-mem";
2524                         reg = <0x17920000 0x1000>;
2525
2526                         frame@17921000 {
2527                                 frame-number = <0>;
2528                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2529                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2530                                 reg = <0x17921000 0x1000>,
2531                                       <0x17922000 0x1000>;
2532                         };
2533
2534                         frame@17923000 {
2535                                 frame-number = <1>;
2536                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2537                                 reg = <0x17923000 0x1000>;
2538                                 status = "disabled";
2539                         };
2540
2541                         frame@17924000 {
2542                                 frame-number = <2>;
2543                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2544                                 reg = <0x17924000 0x1000>;
2545                                 status = "disabled";
2546                         };
2547
2548                         frame@17925000 {
2549                                 frame-number = <3>;
2550                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2551                                 reg = <0x17925000 0x1000>;
2552                                 status = "disabled";
2553                         };
2554
2555                         frame@17926000 {
2556                                 frame-number = <4>;
2557                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2558                                 reg = <0x17926000 0x1000>;
2559                                 status = "disabled";
2560                         };
2561
2562                         frame@17927000 {
2563                                 frame-number = <5>;
2564                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2565                                 reg = <0x17927000 0x1000>;
2566                                 status = "disabled";
2567                         };
2568
2569                         frame@17928000 {
2570                                 frame-number = <6>;
2571                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2572                                 reg = <0x17928000 0x1000>;
2573                                 status = "disabled";
2574                         };
2575                 };
2576
2577                 intc: interrupt-controller@17a00000 {
2578                         compatible = "arm,gic-v3";
2579                         reg = <0x17a00000 0x10000>,       /* GICD */
2580                               <0x17b00000 0x100000>;      /* GICR * 8 */
2581                         #interrupt-cells = <3>;
2582                         #address-cells = <1>;
2583                         #size-cells = <1>;
2584                         ranges;
2585                         interrupt-controller;
2586                         #redistributor-regions = <1>;
2587                         redistributor-stride = <0x0 0x20000>;
2588                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2589                 };
2590
2591                 wifi: wifi@18800000 {
2592                         compatible = "qcom,wcn3990-wifi";
2593                         status = "disabled";
2594                         reg = <0x18800000 0x800000>;
2595                         reg-names = "membase";
2596                         memory-region = <&wlan_msa_mem>;
2597                         clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
2598                         clock-names = "cxo_ref_clk_pin";
2599                         interrupts =
2600                                 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2601                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2602                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2603                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2604                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2605                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2606                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2607                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2608                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2609                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2610                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2611                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2612                         iommus = <&anoc2_smmu 0x1900>,
2613                                  <&anoc2_smmu 0x1901>;
2614                         qcom,snoc-host-cap-8bit-quirk;
2615                 };
2616         };
2617 };