arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM8916";
  20         compatible = "qcom,msm8916";
  21
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         aliases { };
  28
  29         chosen { };
  30
  31         memory {
  32                 device_type = "memory";
  33                 /* We expect the bootloader to fill in the reg */
  34                 reg = <0 0 0 0>;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 CPU0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a53", "arm,armv8";
  44                         reg = <0x0>;
  45                 };
  46
  47                 CPU1: cpu@1 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53", "arm,armv8";
  50                         reg = <0x1>;
  51                 };
  52
  53                 CPU2: cpu@2 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a53", "arm,armv8";
  56                         reg = <0x2>;
  57                 };
  58
  59                 CPU3: cpu@3 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a53", "arm,armv8";
  62                         reg = <0x3>;
  63                 };
  64         };
  65
  66         timer {
  67                 compatible = "arm,armv8-timer";
  68                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  69                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  70                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  71                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  72         };
  73
  74         soc: soc {
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77                 ranges = <0 0 0 0xffffffff>;
  78                 compatible = "simple-bus";
  79
  80                 restart@4ab000 {
  81                         compatible = "qcom,pshold";
  82                         reg = <0x4ab000 0x4>;
  83                 };
  84
  85                 msmgpio: pinctrl@1000000 {
  86                         compatible = "qcom,msm8916-pinctrl";
  87                         reg = <0x1000000 0x300000>;
  88                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  89                         gpio-controller;
  90                         #gpio-cells = <2>;
  91                         interrupt-controller;
  92                         #interrupt-cells = <2>;
  93
  94                         blsp1_uart2_default: blsp1_uart2_default {
  95                                 pinmux {
  96                                         function = "blsp_uart2";
  97                                         pins = "gpio4", "gpio5";
  98                                 };
  99                                 pinconf {
 100                                         pins = "gpio4", "gpio5";
 101                                         drive-strength = <16>;
 102                                         bias-disable;
 103                                 };
 104                         };
 105
 106                         blsp1_uart2_sleep: blsp1_uart2_sleep {
 107                                 pinmux {
 108                                         function = "blsp_uart2";
 109                                         pins = "gpio4", "gpio5";
 110                                 };
 111                                 pinconf {
 112                                         pins = "gpio4", "gpio5";
 113                                         drive-strength = <2>;
 114                                         bias-pull-down;
 115                                 };
 116                         };
 117                 };
 118
 119                 gcc: qcom,gcc@1800000 {
 120                         compatible = "qcom,gcc-msm8916";
 121                         #clock-cells = <1>;
 122                         #reset-cells = <1>;
 123                         reg = <0x1800000 0x80000>;
 124                 };
 125
 126                 blsp1_uart2: serial@78b0000 {
 127                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 128                         reg = <0x78b0000 0x200>;
 129                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 130                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 131                         clock-names = "core", "iface";
 132                         status = "disabled";
 133                 };
 134
 135                 intc: interrupt-controller@b000000 {
 136                         compatible = "qcom,msm-qgic2";
 137                         interrupt-controller;
 138                         #interrupt-cells = <3>;
 139                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 140                 };
 141
 142                 timer@b020000 {
 143                         #address-cells = <1>;
 144                         #size-cells = <1>;
 145                         ranges;
 146                         compatible = "arm,armv7-timer-mem";
 147                         reg = <0xb020000 0x1000>;
 148                         clock-frequency = <19200000>;
 149
 150                         frame@b021000 {
 151                                 frame-number = <0>;
 152                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 153                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 154                                 reg = <0xb021000 0x1000>,
 155                                       <0xb022000 0x1000>;
 156                         };
 157
 158                         frame@b023000 {
 159                                 frame-number = <1>;
 160                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 161                                 reg = <0xb023000 0x1000>;
 162                                 status = "disabled";
 163                         };
 164
 165                         frame@b024000 {
 166                                 frame-number = <2>;
 167                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 168                                 reg = <0xb024000 0x1000>;
 169                                 status = "disabled";
 170                         };
 171
 172                         frame@b025000 {
 173                                 frame-number = <3>;
 174                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 175                                 reg = <0xb025000 0x1000>;
 176                                 status = "disabled";
 177                         };
 178
 179                         frame@b026000 {
 180                                 frame-number = <4>;
 181                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 182                                 reg = <0xb026000 0x1000>;
 183                                 status = "disabled";
 184                         };
 185
 186                         frame@b027000 {
 187                                 frame-number = <5>;
 188                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 189                                 reg = <0xb027000 0x1000>;
 190                                 status = "disabled";
 191                         };
 192
 193                         frame@b028000 {
 194                                 frame-number = <6>;
 195                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 196                                 reg = <0xb028000 0x1000>;
 197                                 status = "disabled";
 198                         };
 199                 };
 200
 201                 spmi_bus: spmi@200f000 {
 202                         compatible = "qcom,spmi-pmic-arb";
 203                         reg = <0x200f000 0x001000>,
 204                               <0x2400000 0x400000>,
 205                               <0x2c00000 0x400000>,
 206                               <0x3800000 0x200000>,
 207                               <0x200a000 0x002100>;
 208                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 209                         interrupt-names = "periph_irq";
 210                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 211                         qcom,ee = <0>;
 212                         qcom,channel = <0>;
 213                         #address-cells = <2>;
 214                         #size-cells = <0>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <4>;
 217                 };
 218         };
 219 };