arch/arm64/boot/dts/qcom/ipq8074.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
   8
   9 / {
  10         model = "Qualcomm Technologies, Inc. IPQ8074";
  11         compatible = "qcom,ipq8074";
  12
  13         clocks {
  14                 sleep_clk: sleep_clk {
  15                         compatible = "fixed-clock";
  16                         clock-frequency = <32000>;
  17                         #clock-cells = <0>;
  18                 };
  19
  20                 xo: xo {
  21                         compatible = "fixed-clock";
  22                         clock-frequency = <19200000>;
  23                         #clock-cells = <0>;
  24                 };
  25         };
  26
  27         cpus {
  28                 #address-cells = <0x1>;
  29                 #size-cells = <0x0>;
  30
  31                 CPU0: cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a53";
  34                         reg = <0x0>;
  35                         next-level-cache = <&L2_0>;
  36                         enable-method = "psci";
  37                 };
  38
  39                 CPU1: cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53";
  42                         enable-method = "psci";
  43                         reg = <0x1>;
  44                         next-level-cache = <&L2_0>;
  45                 };
  46
  47                 CPU2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         enable-method = "psci";
  51                         reg = <0x2>;
  52                         next-level-cache = <&L2_0>;
  53                 };
  54
  55                 CPU3: cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53";
  58                         enable-method = "psci";
  59                         reg = <0x3>;
  60                         next-level-cache = <&L2_0>;
  61                 };
  62
  63                 L2_0: l2-cache {
  64                         compatible = "cache";
  65                         cache-level = <0x2>;
  66                 };
  67         };
  68
  69         pmu {
  70                 compatible = "arm,cortex-a53-pmu";
  71                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         reserved-memory {
  80                 #address-cells = <2>;
  81                 #size-cells = <2>;
  82                 ranges;
  83
  84                 smem@4ab00000 {
  85                         compatible = "qcom,smem";
  86                         reg = <0x0 0x4ab00000 0x0 0x00100000>;
  87                         no-map;
  88
  89                         hwlocks = <&tcsr_mutex 0>;
  90                 };
  91
  92                 memory@4ac00000 {
  93                         no-map;
  94                         reg = <0x0 0x4ac00000 0x0 0x00400000>;
  95                 };
  96         };
  97
  98         firmware {
  99                 scm {
 100                         compatible = "qcom,scm-ipq8074", "qcom,scm";
 101                 };
 102         };
 103
 104         soc: soc {
 105                 #address-cells = <0x1>;
 106                 #size-cells = <0x1>;
 107                 ranges = <0 0 0 0xffffffff>;
 108                 compatible = "simple-bus";
 109
 110                 ssphy_1: phy@58000 {
 111                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 112                         reg = <0x00058000 0x1c4>;
 113                         #address-cells = <1>;
 114                         #size-cells = <1>;
 115                         ranges;
 116
 117                         clocks = <&gcc GCC_USB1_AUX_CLK>,
 118                                 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 119                                 <&xo>;
 120                         clock-names = "aux", "cfg_ahb", "ref";
 121
 122                         resets =  <&gcc GCC_USB1_PHY_BCR>,
 123                                 <&gcc GCC_USB3PHY_1_PHY_BCR>;
 124                         reset-names = "phy","common";
 125                         status = "disabled";
 126
 127                         usb1_ssphy: phy@58200 {
 128                                 reg = <0x00058200 0x130>,       /* Tx */
 129                                       <0x00058400 0x200>,     /* Rx */
 130                                       <0x00058800 0x1f8>,     /* PCS  */
 131                                       <0x00058600 0x044>;     /* PCS misc*/
 132                                 #phy-cells = <0>;
 133                                 #clock-cells = <1>;
 134                                 clocks = <&gcc GCC_USB1_PIPE_CLK>;
 135                                 clock-names = "pipe0";
 136                                 clock-output-names = "gcc_usb1_pipe_clk_src";
 137                         };
 138                 };
 139
 140                 qusb_phy_1: phy@59000 {
 141                         compatible = "qcom,ipq8074-qusb2-phy";
 142                         reg = <0x00059000 0x180>;
 143                         #phy-cells = <0>;
 144
 145                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 146                                  <&xo>;
 147                         clock-names = "cfg_ahb", "ref";
 148
 149                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
 150                         status = "disabled";
 151                 };
 152
 153                 ssphy_0: phy@78000 {
 154                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 155                         reg = <0x00078000 0x1c4>;
 156                         #address-cells = <1>;
 157                         #size-cells = <1>;
 158                         ranges;
 159
 160                         clocks = <&gcc GCC_USB0_AUX_CLK>,
 161                                 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 162                                 <&xo>;
 163                         clock-names = "aux", "cfg_ahb", "ref";
 164
 165                         resets =  <&gcc GCC_USB0_PHY_BCR>,
 166                                 <&gcc GCC_USB3PHY_0_PHY_BCR>;
 167                         reset-names = "phy","common";
 168                         status = "disabled";
 169
 170                         usb0_ssphy: phy@78200 {
 171                                 reg = <0x00078200 0x130>,       /* Tx */
 172                                       <0x00078400 0x200>,     /* Rx */
 173                                       <0x00078800 0x1f8>,     /* PCS  */
 174                                       <0x00078600 0x044>;     /* PCS misc*/
 175                                 #phy-cells = <0>;
 176                                 #clock-cells = <1>;
 177                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
 178                                 clock-names = "pipe0";
 179                                 clock-output-names = "gcc_usb0_pipe_clk_src";
 180                         };
 181                 };
 182
 183                 qusb_phy_0: phy@79000 {
 184                         compatible = "qcom,ipq8074-qusb2-phy";
 185                         reg = <0x00079000 0x180>;
 186                         #phy-cells = <0>;
 187
 188                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 189                                  <&xo>;
 190                         clock-names = "cfg_ahb", "ref";
 191
 192                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
 193                         status = "disabled";
 194                 };
 195
 196                 pcie_qmp0: phy@86000 {
 197                         compatible = "qcom,ipq8074-qmp-pcie-phy";
 198                         reg = <0x00086000 0x1000>;
 199                         #address-cells = <1>;
 200                         #size-cells = <1>;
 201                         ranges;
 202
 203                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
 204                                 <&gcc GCC_PCIE0_AHB_CLK>;
 205                         clock-names = "aux", "cfg_ahb";
 206                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
 207                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
 208                         reset-names = "phy",
 209                                       "common";
 210                         status = "disabled";
 211
 212                         pcie_phy0: phy@86200 {
 213                                 reg = <0x86200 0x16c>,
 214                                       <0x86400 0x200>,
 215                                       <0x86800 0x4f4>;
 216                                 #phy-cells = <0>;
 217                                 #clock-cells = <0>;
 218                                 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
 219                                 clock-names = "pipe0";
 220                                 clock-output-names = "pcie_0_pipe_clk";
 221                         };
 222                 };
 223
 224                 pcie_qmp1: phy@8e000 {
 225                         compatible = "qcom,ipq8074-qmp-pcie-phy";
 226                         reg = <0x0008e000 0x1000>;
 227                         #address-cells = <1>;
 228                         #size-cells = <1>;
 229                         ranges;
 230
 231                         clocks = <&gcc GCC_PCIE1_AUX_CLK>,
 232                                 <&gcc GCC_PCIE1_AHB_CLK>;
 233                         clock-names = "aux", "cfg_ahb";
 234                         resets = <&gcc GCC_PCIE1_PHY_BCR>,
 235                                 <&gcc GCC_PCIE1PHY_PHY_BCR>;
 236                         reset-names = "phy",
 237                                       "common";
 238                         status = "disabled";
 239
 240                         pcie_phy1: phy@8e200 {
 241                                 reg = <0x8e200 0x16c>,
 242                                       <0x8e400 0x200>,
 243                                       <0x8e800 0x4f4>;
 244                                 #phy-cells = <0>;
 245                                 #clock-cells = <0>;
 246                                 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
 247                                 clock-names = "pipe0";
 248                                 clock-output-names = "pcie_1_pipe_clk";
 249                         };
 250                 };
 251
 252                 mdio: mdio@90000 {
 253                         compatible = "qcom,ipq4019-mdio";
 254                         reg = <0x00090000 0x64>;
 255                         #address-cells = <1>;
 256                         #size-cells = <0>;
 257
 258                         clocks = <&gcc GCC_MDIO_AHB_CLK>;
 259                         clock-names = "gcc_mdio_ahb_clk";
 260
 261                         status = "disabled";
 262                 };
 263
 264                 prng: rng@e3000 {
 265                         compatible = "qcom,prng-ee";
 266                         reg = <0x000e3000 0x1000>;
 267                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 268                         clock-names = "core";
 269                         status = "disabled";
 270                 };
 271
 272                 cryptobam: dma-controller@704000 {
 273                         compatible = "qcom,bam-v1.7.0";
 274                         reg = <0x00704000 0x20000>;
 275                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 276                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 277                         clock-names = "bam_clk";
 278                         #dma-cells = <1>;
 279                         qcom,ee = <1>;
 280                         qcom,controlled-remotely;
 281                         status = "disabled";
 282                 };
 283
 284                 crypto: crypto@73a000 {
 285                         compatible = "qcom,crypto-v5.1";
 286                         reg = <0x0073a000 0x6000>;
 287                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 288                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 289                                  <&gcc GCC_CRYPTO_CLK>;
 290                         clock-names = "iface", "bus", "core";
 291                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 292                         dma-names = "rx", "tx";
 293                         status = "disabled";
 294                 };
 295
 296                 tlmm: pinctrl@1000000 {
 297                         compatible = "qcom,ipq8074-pinctrl";
 298                         reg = <0x01000000 0x300000>;
 299                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 300                         gpio-controller;
 301                         gpio-ranges = <&tlmm 0 0 70>;
 302                         #gpio-cells = <0x2>;
 303                         interrupt-controller;
 304                         #interrupt-cells = <0x2>;
 305
 306                         serial_4_pins: serial4-pinmux {
 307                                 pins = "gpio23", "gpio24";
 308                                 function = "blsp4_uart1";
 309                                 drive-strength = <8>;
 310                                 bias-disable;
 311                         };
 312
 313                         i2c_0_pins: i2c-0-pinmux {
 314                                 pins = "gpio42", "gpio43";
 315                                 function = "blsp1_i2c";
 316                                 drive-strength = <8>;
 317                                 bias-disable;
 318                         };
 319
 320                         spi_0_pins: spi-0-pins {
 321                                 pins = "gpio38", "gpio39", "gpio40", "gpio41";
 322                                 function = "blsp0_spi";
 323                                 drive-strength = <8>;
 324                                 bias-disable;
 325                         };
 326
 327                         hsuart_pins: hsuart-pins {
 328                                 pins = "gpio46", "gpio47", "gpio48", "gpio49";
 329                                 function = "blsp2_uart";
 330                                 drive-strength = <8>;
 331                                 bias-disable;
 332                         };
 333
 334                         qpic_pins: qpic-pins {
 335                                 pins = "gpio1", "gpio3", "gpio4",
 336                                        "gpio5", "gpio6", "gpio7",
 337                                        "gpio8", "gpio10", "gpio11",
 338                                        "gpio12", "gpio13", "gpio14",
 339                                        "gpio15", "gpio16", "gpio17";
 340                                 function = "qpic";
 341                                 drive-strength = <8>;
 342                                 bias-disable;
 343                         };
 344                 };
 345
 346                 gcc: gcc@1800000 {
 347                         compatible = "qcom,gcc-ipq8074";
 348                         reg = <0x01800000 0x80000>;
 349                         #clock-cells = <0x1>;
 350                         #reset-cells = <0x1>;
 351                 };
 352
 353                 tcsr_mutex: hwlock@1905000 {
 354                         compatible = "qcom,tcsr-mutex";
 355                         reg = <0x01905000 0x20000>;
 356                         #hwlock-cells = <1>;
 357                 };
 358
 359                 spmi_bus: spmi@200f000 {
 360                         compatible = "qcom,spmi-pmic-arb";
 361                         reg = <0x0200f000 0x001000>,
 362                               <0x02400000 0x800000>,
 363                               <0x02c00000 0x800000>,
 364                               <0x03800000 0x200000>,
 365                               <0x0200a000 0x000700>;
 366                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 367                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 368                         interrupt-names = "periph_irq";
 369                         qcom,ee = <0>;
 370                         qcom,channel = <0>;
 371                         #address-cells = <2>;
 372                         #size-cells = <0>;
 373                         interrupt-controller;
 374                         #interrupt-cells = <4>;
 375                         cell-index = <0>;
 376                 };
 377
 378                 sdhc_1: sdhci@7824900 {
 379                         compatible = "qcom,sdhci-msm-v4";
 380                         reg = <0x7824900 0x500>, <0x7824000 0x800>;
 381                         reg-names = "hc_mem", "core_mem";
 382
 383                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 384                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 385                         interrupt-names = "hc_irq", "pwr_irq";
 386
 387                         clocks = <&xo>,
 388                                  <&gcc GCC_SDCC1_AHB_CLK>,
 389                                  <&gcc GCC_SDCC1_APPS_CLK>;
 390                         clock-names = "xo", "iface", "core";
 391                         max-frequency = <384000000>;
 392                         mmc-ddr-1_8v;
 393                         mmc-hs200-1_8v;
 394                         mmc-hs400-1_8v;
 395                         bus-width = <8>;
 396
 397                         status = "disabled";
 398                 };
 399
 400                 blsp_dma: dma-controller@7884000 {
 401                         compatible = "qcom,bam-v1.7.0";
 402                         reg = <0x07884000 0x2b000>;
 403                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 404                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 405                         clock-names = "bam_clk";
 406                         #dma-cells = <1>;
 407                         qcom,ee = <0>;
 408                 };
 409
 410                 blsp1_uart1: serial@78af000 {
 411                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 412                         reg = <0x078af000 0x200>;
 413                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 414                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 415                                  <&gcc GCC_BLSP1_AHB_CLK>;
 416                         clock-names = "core", "iface";
 417                         status = "disabled";
 418                 };
 419
 420                 blsp1_uart3: serial@78b1000 {
 421                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 422                         reg = <0x078b1000 0x200>;
 423                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 424                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 425                                 <&gcc GCC_BLSP1_AHB_CLK>;
 426                         clock-names = "core", "iface";
 427                         dmas = <&blsp_dma 4>,
 428                                 <&blsp_dma 5>;
 429                         dma-names = "tx", "rx";
 430                         pinctrl-0 = <&hsuart_pins>;
 431                         pinctrl-names = "default";
 432                         status = "disabled";
 433                 };
 434
 435                 blsp1_uart5: serial@78b3000 {
 436                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 437                         reg = <0x078b3000 0x200>;
 438                         interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
 439                         clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 440                                  <&gcc GCC_BLSP1_AHB_CLK>;
 441                         clock-names = "core", "iface";
 442                         pinctrl-0 = <&serial_4_pins>;
 443                         pinctrl-names = "default";
 444                         status = "disabled";
 445                 };
 446
 447                 blsp1_spi1: spi@78b5000 {
 448                         compatible = "qcom,spi-qup-v2.2.1";
 449                         #address-cells = <1>;
 450                         #size-cells = <0>;
 451                         reg = <0x078b5000 0x600>;
 452                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 453                         spi-max-frequency = <50000000>;
 454                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 455                                 <&gcc GCC_BLSP1_AHB_CLK>;
 456                         clock-names = "core", "iface";
 457                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 458                         dma-names = "tx", "rx";
 459                         pinctrl-0 = <&spi_0_pins>;
 460                         pinctrl-names = "default";
 461                         status = "disabled";
 462                 };
 463
 464                 blsp1_i2c2: i2c@78b6000 {
 465                         compatible = "qcom,i2c-qup-v2.2.1";
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                         reg = <0x078b6000 0x600>;
 469                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 470                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 471                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 472                         clock-names = "iface", "core";
 473                         clock-frequency = <400000>;
 474                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 475                         dma-names = "rx", "tx";
 476                         pinctrl-0 = <&i2c_0_pins>;
 477                         pinctrl-names = "default";
 478                         status = "disabled";
 479                 };
 480
 481                 blsp1_i2c3: i2c@78b7000 {
 482                         compatible = "qcom,i2c-qup-v2.2.1";
 483                         #address-cells = <1>;
 484                         #size-cells = <0>;
 485                         reg = <0x078b7000 0x600>;
 486                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 487                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 488                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 489                         clock-names = "iface", "core";
 490                         clock-frequency = <100000>;
 491                         dmas = <&blsp_dma 17>, <&blsp_dma 16>;
 492                         dma-names = "rx", "tx";
 493                         status = "disabled";
 494                 };
 495
 496                 blsp1_i2c5: i2c@78b9000 {
 497                         compatible = "qcom,i2c-qup-v2.2.1";
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                         reg = <0x78b9000 0x600>;
 501                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 502                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 503                                  <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
 504                         clock-names = "iface", "core";
 505                         clock-frequency = <400000>;
 506                         dmas = <&blsp_dma 21>, <&blsp_dma 20>;
 507                         dma-names = "rx", "tx";
 508                         status = "disabled";
 509                 };
 510
 511                 blsp1_i2c6: i2c@78ba000 {
 512                         compatible = "qcom,i2c-qup-v2.2.1";
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         reg = <0x078ba000 0x600>;
 516                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 517                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 518                                  <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 519                         clock-names = "iface", "core";
 520                         clock-frequency = <100000>;
 521                         dmas = <&blsp_dma 23>, <&blsp_dma 22>;
 522                         dma-names = "rx", "tx";
 523                         status = "disabled";
 524                 };
 525
 526                 qpic_bam: dma-controller@7984000 {
 527                         compatible = "qcom,bam-v1.7.0";
 528                         reg = <0x07984000 0x1a000>;
 529                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 530                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
 531                         clock-names = "bam_clk";
 532                         #dma-cells = <1>;
 533                         qcom,ee = <0>;
 534                         status = "disabled";
 535                 };
 536
 537                 qpic_nand: nand@79b0000 {
 538                         compatible = "qcom,ipq8074-nand";
 539                         reg = <0x079b0000 0x10000>;
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         clocks = <&gcc GCC_QPIC_CLK>,
 543                                  <&gcc GCC_QPIC_AHB_CLK>;
 544                         clock-names = "core", "aon";
 545
 546                         dmas = <&qpic_bam 0>,
 547                                <&qpic_bam 1>,
 548                                <&qpic_bam 2>;
 549                         dma-names = "tx", "rx", "cmd";
 550                         pinctrl-0 = <&qpic_pins>;
 551                         pinctrl-names = "default";
 552                         status = "disabled";
 553                 };
 554
 555                 usb_0: usb@8af8800 {
 556                         compatible = "qcom,dwc3";
 557                         reg = <0x08af8800 0x400>;
 558                         #address-cells = <1>;
 559                         #size-cells = <1>;
 560                         ranges;
 561
 562                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 563                                 <&gcc GCC_USB0_MASTER_CLK>,
 564                                 <&gcc GCC_USB0_SLEEP_CLK>,
 565                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 566                         clock-names = "sys_noc_axi",
 567                                 "master",
 568                                 "sleep",
 569                                 "mock_utmi";
 570
 571                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 572                                           <&gcc GCC_USB0_MASTER_CLK>,
 573                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 574                         assigned-clock-rates = <133330000>,
 575                                                 <133330000>,
 576                                                 <19200000>;
 577
 578                         resets = <&gcc GCC_USB0_BCR>;
 579                         status = "disabled";
 580
 581                         dwc_0: dwc3@8a00000 {
 582                                 compatible = "snps,dwc3";
 583                                 reg = <0x8a00000 0xcd00>;
 584                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 585                                 phys = <&qusb_phy_0>, <&usb0_ssphy>;
 586                                 phy-names = "usb2-phy", "usb3-phy";
 587                                 snps,is-utmi-l1-suspend;
 588                                 snps,hird-threshold = /bits/ 8 <0x0>;
 589                                 snps,dis_u2_susphy_quirk;
 590                                 snps,dis_u3_susphy_quirk;
 591                                 dr_mode = "host";
 592                         };
 593                 };
 594
 595                 usb_1: usb@8cf8800 {
 596                         compatible = "qcom,dwc3";
 597                         reg = <0x08cf8800 0x400>;
 598                         #address-cells = <1>;
 599                         #size-cells = <1>;
 600                         ranges;
 601
 602                         clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 603                                 <&gcc GCC_USB1_MASTER_CLK>,
 604                                 <&gcc GCC_USB1_SLEEP_CLK>,
 605                                 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 606                         clock-names = "sys_noc_axi",
 607                                 "master",
 608                                 "sleep",
 609                                 "mock_utmi";
 610
 611                         assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 612                                           <&gcc GCC_USB1_MASTER_CLK>,
 613                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 614                         assigned-clock-rates = <133330000>,
 615                                                 <133330000>,
 616                                                 <19200000>;
 617
 618                         resets = <&gcc GCC_USB1_BCR>;
 619                         status = "disabled";
 620
 621                         dwc_1: dwc3@8c00000 {
 622                                 compatible = "snps,dwc3";
 623                                 reg = <0x8c00000 0xcd00>;
 624                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 625                                 phys = <&qusb_phy_1>, <&usb1_ssphy>;
 626                                 phy-names = "usb2-phy", "usb3-phy";
 627                                 snps,is-utmi-l1-suspend;
 628                                 snps,hird-threshold = /bits/ 8 <0x0>;
 629                                 snps,dis_u2_susphy_quirk;
 630                                 snps,dis_u3_susphy_quirk;
 631                                 dr_mode = "host";
 632                         };
 633                 };
 634
 635                 intc: interrupt-controller@b000000 {
 636                         compatible = "qcom,msm-qgic2";
 637                         #address-cells = <1>;
 638                         #size-cells = <1>;
 639                         interrupt-controller;
 640                         #interrupt-cells = <0x3>;
 641                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 642                         ranges = <0 0xb00a000 0xffd>;
 643
 644                         v2m@0 {
 645                                 compatible = "arm,gic-v2m-frame";
 646                                 msi-controller;
 647                                 reg = <0x0 0xffd>;
 648                         };
 649                 };
 650
 651                 timer {
 652                         compatible = "arm,armv8-timer";
 653                         interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 654                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 655                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 656                                      <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 657                 };
 658
 659                 watchdog: watchdog@b017000 {
 660                         compatible = "qcom,kpss-wdt";
 661                         reg = <0xb017000 0x1000>;
 662                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 663                         clocks = <&sleep_clk>;
 664                         timeout-sec = <30>;
 665                 };
 666
 667                 timer@b120000 {
 668                         #address-cells = <1>;
 669                         #size-cells = <1>;
 670                         ranges;
 671                         compatible = "arm,armv7-timer-mem";
 672                         reg = <0x0b120000 0x1000>;
 673                         clock-frequency = <19200000>;
 674
 675                         frame@b120000 {
 676                                 frame-number = <0>;
 677                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 678                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 679                                 reg = <0x0b121000 0x1000>,
 680                                       <0x0b122000 0x1000>;
 681                         };
 682
 683                         frame@b123000 {
 684                                 frame-number = <1>;
 685                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 686                                 reg = <0x0b123000 0x1000>;
 687                                 status = "disabled";
 688                         };
 689
 690                         frame@b124000 {
 691                                 frame-number = <2>;
 692                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 693                                 reg = <0x0b124000 0x1000>;
 694                                 status = "disabled";
 695                         };
 696
 697                         frame@b125000 {
 698                                 frame-number = <3>;
 699                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 700                                 reg = <0x0b125000 0x1000>;
 701                                 status = "disabled";
 702                         };
 703
 704                         frame@b126000 {
 705                                 frame-number = <4>;
 706                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 707                                 reg = <0x0b126000 0x1000>;
 708                                 status = "disabled";
 709                         };
 710
 711                         frame@b127000 {
 712                                 frame-number = <5>;
 713                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 714                                 reg = <0x0b127000 0x1000>;
 715                                 status = "disabled";
 716                         };
 717
 718                         frame@b128000 {
 719                                 frame-number = <6>;
 720                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 721                                 reg = <0x0b128000 0x1000>;
 722                                 status = "disabled";
 723                         };
 724                 };
 725
 726                 pcie1: pci@10000000 {
 727                         compatible = "qcom,pcie-ipq8074";
 728                         reg =  <0x10000000 0xf1d>,
 729                                <0x10000f20 0xa8>,
 730                                <0x00088000 0x2000>,
 731                                <0x10100000 0x1000>;
 732                         reg-names = "dbi", "elbi", "parf", "config";
 733                         device_type = "pci";
 734                         linux,pci-domain = <1>;
 735                         bus-range = <0x00 0xff>;
 736                         num-lanes = <1>;
 737                         #address-cells = <3>;
 738                         #size-cells = <2>;
 739
 740                         phys = <&pcie_phy1>;
 741                         phy-names = "pciephy";
 742
 743                         ranges = <0x81000000 0 0x10200000 0x10200000
 744                                   0 0x100000   /* downstream I/O */
 745                                   0x82000000 0 0x10300000 0x10300000
 746                                   0 0xd00000>; /* non-prefetchable memory */
 747
 748                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 749                         interrupt-names = "msi";
 750                         #interrupt-cells = <1>;
 751                         interrupt-map-mask = <0 0 0 0x7>;
 752                         interrupt-map = <0 0 0 1 &intc 0 142
 753                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 754                                         <0 0 0 2 &intc 0 143
 755                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 756                                         <0 0 0 3 &intc 0 144
 757                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 758                                         <0 0 0 4 &intc 0 145
 759                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 760
 761                         clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
 762                                  <&gcc GCC_PCIE1_AXI_M_CLK>,
 763                                  <&gcc GCC_PCIE1_AXI_S_CLK>,
 764                                  <&gcc GCC_PCIE1_AHB_CLK>,
 765                                  <&gcc GCC_PCIE1_AUX_CLK>;
 766                         clock-names = "iface",
 767                                       "axi_m",
 768                                       "axi_s",
 769                                       "ahb",
 770                                       "aux";
 771                         resets = <&gcc GCC_PCIE1_PIPE_ARES>,
 772                                  <&gcc GCC_PCIE1_SLEEP_ARES>,
 773                                  <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
 774                                  <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
 775                                  <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
 776                                  <&gcc GCC_PCIE1_AHB_ARES>,
 777                                  <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
 778                         reset-names = "pipe",
 779                                       "sleep",
 780                                       "sticky",
 781                                       "axi_m",
 782                                       "axi_s",
 783                                       "ahb",
 784                                       "axi_m_sticky";
 785                         status = "disabled";
 786                 };
 787
 788                 pcie0: pci@20000000 {
 789                         compatible = "qcom,pcie-ipq8074";
 790                         reg = <0x20000000 0xf1d>,
 791                               <0x20000f20 0xa8>,
 792                               <0x00080000 0x2000>,
 793                               <0x20100000 0x1000>;
 794                         reg-names = "dbi", "elbi", "parf", "config";
 795                         device_type = "pci";
 796                         linux,pci-domain = <0>;
 797                         bus-range = <0x00 0xff>;
 798                         num-lanes = <1>;
 799                         #address-cells = <3>;
 800                         #size-cells = <2>;
 801
 802                         phys = <&pcie_phy0>;
 803                         phy-names = "pciephy";
 804
 805                         ranges = <0x81000000 0 0x20200000 0x20200000
 806                                   0 0x100000   /* downstream I/O */
 807                                   0x82000000 0 0x20300000 0x20300000
 808                                   0 0xd00000>; /* non-prefetchable memory */
 809
 810                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 811                         interrupt-names = "msi";
 812                         #interrupt-cells = <1>;
 813                         interrupt-map-mask = <0 0 0 0x7>;
 814                         interrupt-map = <0 0 0 1 &intc 0 75
 815                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 816                                         <0 0 0 2 &intc 0 78
 817                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 818                                         <0 0 0 3 &intc 0 79
 819                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 820                                         <0 0 0 4 &intc 0 83
 821                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 822
 823                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 824                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 825                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 826                                  <&gcc GCC_PCIE0_AHB_CLK>,
 827                                  <&gcc GCC_PCIE0_AUX_CLK>;
 828
 829                         clock-names = "iface",
 830                                       "axi_m",
 831                                       "axi_s",
 832                                       "ahb",
 833                                       "aux";
 834                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 835                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 836                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 837                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 838                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 839                                  <&gcc GCC_PCIE0_AHB_ARES>,
 840                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
 841                         reset-names = "pipe",
 842                                       "sleep",
 843                                       "sticky",
 844                                       "axi_m",
 845                                       "axi_s",
 846                                       "ahb",
 847                                       "axi_m_sticky";
 848                         status = "disabled";
 849                 };
 850         };
 851 };