1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
10 model = "Qualcomm Technologies, Inc. IPQ8074";
11 compatible = "qcom,ipq8074";
14 sleep_clk: sleep_clk {
15 compatible = "fixed-clock";
16 clock-frequency = <32000>;
21 compatible = "fixed-clock";
22 clock-frequency = <19200000>;
28 #address-cells = <0x1>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&L2_0>;
36 enable-method = "psci";
41 compatible = "arm,cortex-a53";
42 enable-method = "psci";
44 next-level-cache = <&L2_0>;
49 compatible = "arm,cortex-a53";
50 enable-method = "psci";
52 next-level-cache = <&L2_0>;
57 compatible = "arm,cortex-a53";
58 enable-method = "psci";
60 next-level-cache = <&L2_0>;
70 compatible = "arm,cortex-a53-pmu";
71 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
75 compatible = "arm,psci-1.0";
85 compatible = "qcom,smem";
86 reg = <0x0 0x4ab00000 0x0 0x00100000>;
89 hwlocks = <&tcsr_mutex 0>;
94 reg = <0x0 0x4ac00000 0x0 0x00400000>;
100 compatible = "qcom,scm-ipq8074", "qcom,scm";
105 #address-cells = <0x1>;
107 ranges = <0 0 0 0xffffffff>;
108 compatible = "simple-bus";
111 compatible = "qcom,ipq8074-qmp-usb3-phy";
112 reg = <0x00058000 0x1c4>;
113 #address-cells = <1>;
117 clocks = <&gcc GCC_USB1_AUX_CLK>,
118 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
120 clock-names = "aux", "cfg_ahb", "ref";
122 resets = <&gcc GCC_USB1_PHY_BCR>,
123 <&gcc GCC_USB3PHY_1_PHY_BCR>;
124 reset-names = "phy","common";
127 usb1_ssphy: phy@58200 {
128 reg = <0x00058200 0x130>, /* Tx */
129 <0x00058400 0x200>, /* Rx */
130 <0x00058800 0x1f8>, /* PCS */
131 <0x00058600 0x044>; /* PCS misc*/
134 clocks = <&gcc GCC_USB1_PIPE_CLK>;
135 clock-names = "pipe0";
136 clock-output-names = "gcc_usb1_pipe_clk_src";
140 qusb_phy_1: phy@59000 {
141 compatible = "qcom,ipq8074-qusb2-phy";
142 reg = <0x00059000 0x180>;
145 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
147 clock-names = "cfg_ahb", "ref";
149 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
154 compatible = "qcom,ipq8074-qmp-usb3-phy";
155 reg = <0x00078000 0x1c4>;
156 #address-cells = <1>;
160 clocks = <&gcc GCC_USB0_AUX_CLK>,
161 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
163 clock-names = "aux", "cfg_ahb", "ref";
165 resets = <&gcc GCC_USB0_PHY_BCR>,
166 <&gcc GCC_USB3PHY_0_PHY_BCR>;
167 reset-names = "phy","common";
170 usb0_ssphy: phy@78200 {
171 reg = <0x00078200 0x130>, /* Tx */
172 <0x00078400 0x200>, /* Rx */
173 <0x00078800 0x1f8>, /* PCS */
174 <0x00078600 0x044>; /* PCS misc*/
177 clocks = <&gcc GCC_USB0_PIPE_CLK>;
178 clock-names = "pipe0";
179 clock-output-names = "gcc_usb0_pipe_clk_src";
183 qusb_phy_0: phy@79000 {
184 compatible = "qcom,ipq8074-qusb2-phy";
185 reg = <0x00079000 0x180>;
188 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
190 clock-names = "cfg_ahb", "ref";
192 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
196 pcie_qmp0: phy@86000 {
197 compatible = "qcom,ipq8074-qmp-pcie-phy";
198 reg = <0x00086000 0x1000>;
199 #address-cells = <1>;
203 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
204 <&gcc GCC_PCIE0_AHB_CLK>;
205 clock-names = "aux", "cfg_ahb";
206 resets = <&gcc GCC_PCIE0_PHY_BCR>,
207 <&gcc GCC_PCIE0PHY_PHY_BCR>;
212 pcie_phy0: phy@86200 {
213 reg = <0x86200 0x16c>,
218 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
219 clock-names = "pipe0";
220 clock-output-names = "pcie_0_pipe_clk";
224 pcie_qmp1: phy@8e000 {
225 compatible = "qcom,ipq8074-qmp-pcie-phy";
226 reg = <0x0008e000 0x1000>;
227 #address-cells = <1>;
231 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
232 <&gcc GCC_PCIE1_AHB_CLK>;
233 clock-names = "aux", "cfg_ahb";
234 resets = <&gcc GCC_PCIE1_PHY_BCR>,
235 <&gcc GCC_PCIE1PHY_PHY_BCR>;
240 pcie_phy1: phy@8e200 {
241 reg = <0x8e200 0x16c>,
246 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
247 clock-names = "pipe0";
248 clock-output-names = "pcie_1_pipe_clk";
253 compatible = "qcom,ipq4019-mdio";
254 reg = <0x00090000 0x64>;
255 #address-cells = <1>;
258 clocks = <&gcc GCC_MDIO_AHB_CLK>;
259 clock-names = "gcc_mdio_ahb_clk";
265 compatible = "qcom,prng-ee";
266 reg = <0x000e3000 0x1000>;
267 clocks = <&gcc GCC_PRNG_AHB_CLK>;
268 clock-names = "core";
272 cryptobam: dma-controller@704000 {
273 compatible = "qcom,bam-v1.7.0";
274 reg = <0x00704000 0x20000>;
275 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
277 clock-names = "bam_clk";
280 qcom,controlled-remotely;
284 crypto: crypto@73a000 {
285 compatible = "qcom,crypto-v5.1";
286 reg = <0x0073a000 0x6000>;
287 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
288 <&gcc GCC_CRYPTO_AXI_CLK>,
289 <&gcc GCC_CRYPTO_CLK>;
290 clock-names = "iface", "bus", "core";
291 dmas = <&cryptobam 2>, <&cryptobam 3>;
292 dma-names = "rx", "tx";
296 tlmm: pinctrl@1000000 {
297 compatible = "qcom,ipq8074-pinctrl";
298 reg = <0x01000000 0x300000>;
299 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
301 gpio-ranges = <&tlmm 0 0 70>;
303 interrupt-controller;
304 #interrupt-cells = <0x2>;
306 serial_4_pins: serial4-pinmux {
307 pins = "gpio23", "gpio24";
308 function = "blsp4_uart1";
309 drive-strength = <8>;
313 i2c_0_pins: i2c-0-pinmux {
314 pins = "gpio42", "gpio43";
315 function = "blsp1_i2c";
316 drive-strength = <8>;
320 spi_0_pins: spi-0-pins {
321 pins = "gpio38", "gpio39", "gpio40", "gpio41";
322 function = "blsp0_spi";
323 drive-strength = <8>;
327 hsuart_pins: hsuart-pins {
328 pins = "gpio46", "gpio47", "gpio48", "gpio49";
329 function = "blsp2_uart";
330 drive-strength = <8>;
334 qpic_pins: qpic-pins {
335 pins = "gpio1", "gpio3", "gpio4",
336 "gpio5", "gpio6", "gpio7",
337 "gpio8", "gpio10", "gpio11",
338 "gpio12", "gpio13", "gpio14",
339 "gpio15", "gpio16", "gpio17";
341 drive-strength = <8>;
347 compatible = "qcom,gcc-ipq8074";
348 reg = <0x01800000 0x80000>;
349 #clock-cells = <0x1>;
350 #reset-cells = <0x1>;
353 tcsr_mutex: hwlock@1905000 {
354 compatible = "qcom,tcsr-mutex";
355 reg = <0x01905000 0x20000>;
359 spmi_bus: spmi@200f000 {
360 compatible = "qcom,spmi-pmic-arb";
361 reg = <0x0200f000 0x001000>,
362 <0x02400000 0x800000>,
363 <0x02c00000 0x800000>,
364 <0x03800000 0x200000>,
365 <0x0200a000 0x000700>;
366 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
367 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "periph_irq";
371 #address-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <4>;
378 sdhc_1: sdhci@7824900 {
379 compatible = "qcom,sdhci-msm-v4";
380 reg = <0x7824900 0x500>, <0x7824000 0x800>;
381 reg-names = "hc_mem", "core_mem";
383 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
385 interrupt-names = "hc_irq", "pwr_irq";
388 <&gcc GCC_SDCC1_AHB_CLK>,
389 <&gcc GCC_SDCC1_APPS_CLK>;
390 clock-names = "xo", "iface", "core";
391 max-frequency = <384000000>;
400 blsp_dma: dma-controller@7884000 {
401 compatible = "qcom,bam-v1.7.0";
402 reg = <0x07884000 0x2b000>;
403 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
405 clock-names = "bam_clk";
410 blsp1_uart1: serial@78af000 {
411 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
412 reg = <0x078af000 0x200>;
413 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
415 <&gcc GCC_BLSP1_AHB_CLK>;
416 clock-names = "core", "iface";
420 blsp1_uart3: serial@78b1000 {
421 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
422 reg = <0x078b1000 0x200>;
423 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
425 <&gcc GCC_BLSP1_AHB_CLK>;
426 clock-names = "core", "iface";
427 dmas = <&blsp_dma 4>,
429 dma-names = "tx", "rx";
430 pinctrl-0 = <&hsuart_pins>;
431 pinctrl-names = "default";
435 blsp1_uart5: serial@78b3000 {
436 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
437 reg = <0x078b3000 0x200>;
438 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
440 <&gcc GCC_BLSP1_AHB_CLK>;
441 clock-names = "core", "iface";
442 pinctrl-0 = <&serial_4_pins>;
443 pinctrl-names = "default";
447 blsp1_spi1: spi@78b5000 {
448 compatible = "qcom,spi-qup-v2.2.1";
449 #address-cells = <1>;
451 reg = <0x078b5000 0x600>;
452 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
453 spi-max-frequency = <50000000>;
454 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
455 <&gcc GCC_BLSP1_AHB_CLK>;
456 clock-names = "core", "iface";
457 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
458 dma-names = "tx", "rx";
459 pinctrl-0 = <&spi_0_pins>;
460 pinctrl-names = "default";
464 blsp1_i2c2: i2c@78b6000 {
465 compatible = "qcom,i2c-qup-v2.2.1";
466 #address-cells = <1>;
468 reg = <0x078b6000 0x600>;
469 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
471 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
472 clock-names = "iface", "core";
473 clock-frequency = <400000>;
474 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
475 dma-names = "rx", "tx";
476 pinctrl-0 = <&i2c_0_pins>;
477 pinctrl-names = "default";
481 blsp1_i2c3: i2c@78b7000 {
482 compatible = "qcom,i2c-qup-v2.2.1";
483 #address-cells = <1>;
485 reg = <0x078b7000 0x600>;
486 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
488 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
489 clock-names = "iface", "core";
490 clock-frequency = <100000>;
491 dmas = <&blsp_dma 17>, <&blsp_dma 16>;
492 dma-names = "rx", "tx";
496 blsp1_i2c5: i2c@78b9000 {
497 compatible = "qcom,i2c-qup-v2.2.1";
498 #address-cells = <1>;
500 reg = <0x78b9000 0x600>;
501 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
503 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
504 clock-names = "iface", "core";
505 clock-frequency = <400000>;
506 dmas = <&blsp_dma 21>, <&blsp_dma 20>;
507 dma-names = "rx", "tx";
511 blsp1_i2c6: i2c@78ba000 {
512 compatible = "qcom,i2c-qup-v2.2.1";
513 #address-cells = <1>;
515 reg = <0x078ba000 0x600>;
516 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
518 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
519 clock-names = "iface", "core";
520 clock-frequency = <100000>;
521 dmas = <&blsp_dma 23>, <&blsp_dma 22>;
522 dma-names = "rx", "tx";
526 qpic_bam: dma-controller@7984000 {
527 compatible = "qcom,bam-v1.7.0";
528 reg = <0x07984000 0x1a000>;
529 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&gcc GCC_QPIC_AHB_CLK>;
531 clock-names = "bam_clk";
537 qpic_nand: nand@79b0000 {
538 compatible = "qcom,ipq8074-nand";
539 reg = <0x079b0000 0x10000>;
540 #address-cells = <1>;
542 clocks = <&gcc GCC_QPIC_CLK>,
543 <&gcc GCC_QPIC_AHB_CLK>;
544 clock-names = "core", "aon";
546 dmas = <&qpic_bam 0>,
549 dma-names = "tx", "rx", "cmd";
550 pinctrl-0 = <&qpic_pins>;
551 pinctrl-names = "default";
556 compatible = "qcom,dwc3";
557 reg = <0x08af8800 0x400>;
558 #address-cells = <1>;
562 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
563 <&gcc GCC_USB0_MASTER_CLK>,
564 <&gcc GCC_USB0_SLEEP_CLK>,
565 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
566 clock-names = "sys_noc_axi",
571 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
572 <&gcc GCC_USB0_MASTER_CLK>,
573 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
574 assigned-clock-rates = <133330000>,
578 resets = <&gcc GCC_USB0_BCR>;
581 dwc_0: dwc3@8a00000 {
582 compatible = "snps,dwc3";
583 reg = <0x8a00000 0xcd00>;
584 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
585 phys = <&qusb_phy_0>, <&usb0_ssphy>;
586 phy-names = "usb2-phy", "usb3-phy";
587 snps,is-utmi-l1-suspend;
588 snps,hird-threshold = /bits/ 8 <0x0>;
589 snps,dis_u2_susphy_quirk;
590 snps,dis_u3_susphy_quirk;
596 compatible = "qcom,dwc3";
597 reg = <0x08cf8800 0x400>;
598 #address-cells = <1>;
602 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
603 <&gcc GCC_USB1_MASTER_CLK>,
604 <&gcc GCC_USB1_SLEEP_CLK>,
605 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
606 clock-names = "sys_noc_axi",
611 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
612 <&gcc GCC_USB1_MASTER_CLK>,
613 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
614 assigned-clock-rates = <133330000>,
618 resets = <&gcc GCC_USB1_BCR>;
621 dwc_1: dwc3@8c00000 {
622 compatible = "snps,dwc3";
623 reg = <0x8c00000 0xcd00>;
624 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
625 phys = <&qusb_phy_1>, <&usb1_ssphy>;
626 phy-names = "usb2-phy", "usb3-phy";
627 snps,is-utmi-l1-suspend;
628 snps,hird-threshold = /bits/ 8 <0x0>;
629 snps,dis_u2_susphy_quirk;
630 snps,dis_u3_susphy_quirk;
635 intc: interrupt-controller@b000000 {
636 compatible = "qcom,msm-qgic2";
637 #address-cells = <1>;
639 interrupt-controller;
640 #interrupt-cells = <0x3>;
641 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
642 ranges = <0 0xb00a000 0xffd>;
645 compatible = "arm,gic-v2m-frame";
652 compatible = "arm,armv8-timer";
653 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
654 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
655 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
656 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
659 watchdog: watchdog@b017000 {
660 compatible = "qcom,kpss-wdt";
661 reg = <0xb017000 0x1000>;
662 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
663 clocks = <&sleep_clk>;
668 #address-cells = <1>;
671 compatible = "arm,armv7-timer-mem";
672 reg = <0x0b120000 0x1000>;
673 clock-frequency = <19200000>;
677 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
679 reg = <0x0b121000 0x1000>,
685 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
686 reg = <0x0b123000 0x1000>;
692 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
693 reg = <0x0b124000 0x1000>;
699 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
700 reg = <0x0b125000 0x1000>;
706 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
707 reg = <0x0b126000 0x1000>;
713 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
714 reg = <0x0b127000 0x1000>;
720 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
721 reg = <0x0b128000 0x1000>;
726 pcie1: pci@10000000 {
727 compatible = "qcom,pcie-ipq8074";
728 reg = <0x10000000 0xf1d>,
732 reg-names = "dbi", "elbi", "parf", "config";
734 linux,pci-domain = <1>;
735 bus-range = <0x00 0xff>;
737 #address-cells = <3>;
741 phy-names = "pciephy";
743 ranges = <0x81000000 0 0x10200000 0x10200000
744 0 0x100000 /* downstream I/O */
745 0x82000000 0 0x10300000 0x10300000
746 0 0xd00000>; /* non-prefetchable memory */
748 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
749 interrupt-names = "msi";
750 #interrupt-cells = <1>;
751 interrupt-map-mask = <0 0 0 0x7>;
752 interrupt-map = <0 0 0 1 &intc 0 142
753 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
755 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
757 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
759 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
761 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
762 <&gcc GCC_PCIE1_AXI_M_CLK>,
763 <&gcc GCC_PCIE1_AXI_S_CLK>,
764 <&gcc GCC_PCIE1_AHB_CLK>,
765 <&gcc GCC_PCIE1_AUX_CLK>;
766 clock-names = "iface",
771 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
772 <&gcc GCC_PCIE1_SLEEP_ARES>,
773 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
774 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
775 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
776 <&gcc GCC_PCIE1_AHB_ARES>,
777 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
778 reset-names = "pipe",
788 pcie0: pci@20000000 {
789 compatible = "qcom,pcie-ipq8074";
790 reg = <0x20000000 0xf1d>,
794 reg-names = "dbi", "elbi", "parf", "config";
796 linux,pci-domain = <0>;
797 bus-range = <0x00 0xff>;
799 #address-cells = <3>;
803 phy-names = "pciephy";
805 ranges = <0x81000000 0 0x20200000 0x20200000
806 0 0x100000 /* downstream I/O */
807 0x82000000 0 0x20300000 0x20300000
808 0 0xd00000>; /* non-prefetchable memory */
810 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
811 interrupt-names = "msi";
812 #interrupt-cells = <1>;
813 interrupt-map-mask = <0 0 0 0x7>;
814 interrupt-map = <0 0 0 1 &intc 0 75
815 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
817 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
819 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
821 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
823 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
824 <&gcc GCC_PCIE0_AXI_M_CLK>,
825 <&gcc GCC_PCIE0_AXI_S_CLK>,
826 <&gcc GCC_PCIE0_AHB_CLK>,
827 <&gcc GCC_PCIE0_AUX_CLK>;
829 clock-names = "iface",
834 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
835 <&gcc GCC_PCIE0_SLEEP_ARES>,
836 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
837 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
838 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
839 <&gcc GCC_PCIE0_AHB_ARES>,
840 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
841 reset-names = "pipe",