arch/arm64/boot/dts/qcom/ipq5332.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * IPQ5332 device tree source
   4  *
   5  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,apss-ipq.h>
   9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         interrupt-parent = <&intc>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         clocks {
  18                 sleep_clk: sleep-clk {
  19                         compatible = "fixed-clock";
  20                         #clock-cells = <0>;
  21                 };
  22
  23                 xo_board: xo-board-clk {
  24                         compatible = "fixed-clock";
  25                         #clock-cells = <0>;
  26                 };
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 CPU0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53";
  36                         reg = <0x0>;
  37                         enable-method = "psci";
  38                         next-level-cache = <&L2_0>;
  39                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  40                         operating-points-v2 = <&cpu_opp_table>;
  41                 };
  42
  43                 CPU1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a53";
  46                         reg = <0x1>;
  47                         enable-method = "psci";
  48                         next-level-cache = <&L2_0>;
  49                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  50                         operating-points-v2 = <&cpu_opp_table>;
  51                 };
  52
  53                 CPU2: cpu@2 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a53";
  56                         reg = <0x2>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&L2_0>;
  59                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  60                         operating-points-v2 = <&cpu_opp_table>;
  61                 };
  62
  63                 CPU3: cpu@3 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a53";
  66                         reg = <0x3>;
  67                         enable-method = "psci";
  68                         next-level-cache = <&L2_0>;
  69                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  70                         operating-points-v2 = <&cpu_opp_table>;
  71                 };
  72
  73                 L2_0: l2-cache {
  74                         compatible = "cache";
  75                         cache-level = <2>;
  76                 };
  77         };
  78
  79         firmware {
  80                 scm {
  81                         compatible = "qcom,scm-ipq5332", "qcom,scm";
  82                         qcom,dload-mode = <&tcsr 0x6100>;
  83                 };
  84         };
  85
  86         memory@40000000 {
  87                 device_type = "memory";
  88                 /* We expect the bootloader to fill in the size */
  89                 reg = <0x0 0x40000000 0x0 0x0>;
  90         };
  91
  92         cpu_opp_table: opp-table-cpu {
  93                 compatible = "operating-points-v2";
  94                 opp-shared;
  95
  96                 opp-1488000000 {
  97                         opp-hz = /bits/ 64 <1488000000>;
  98                         clock-latency-ns = <200000>;
  99                 };
 100         };
 101
 102         pmu {
 103                 compatible = "arm,cortex-a53-pmu";
 104                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 105         };
 106
 107         psci {
 108                 compatible = "arm,psci-1.0";
 109                 method = "smc";
 110         };
 111
 112         reserved-memory {
 113                 #address-cells = <2>;
 114                 #size-cells = <2>;
 115                 ranges;
 116
 117                 tz_mem: tz@4a600000 {
 118                         reg = <0x0 0x4a600000 0x0 0x200000>;
 119                         no-map;
 120                 };
 121
 122                 smem@4a800000 {
 123                         compatible = "qcom,smem";
 124                         reg = <0x0 0x4a800000 0x0 0x00100000>;
 125                         no-map;
 126
 127                         hwlocks = <&tcsr_mutex 0>;
 128                 };
 129         };
 130
 131         soc@0 {
 132                 compatible = "simple-bus";
 133                 #address-cells = <1>;
 134                 #size-cells = <1>;
 135                 ranges = <0 0 0 0xffffffff>;
 136
 137                 qfprom: efuse@a4000 {
 138                         compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
 139                         reg = <0x000a4000 0x721>;
 140                         #address-cells = <1>;
 141                         #size-cells = <1>;
 142                 };
 143
 144                 rng: rng@e3000 {
 145                         compatible = "qcom,prng-ee";
 146                         reg = <0x000e3000 0x1000>;
 147                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 148                         clock-names = "core";
 149                 };
 150
 151                 tlmm: pinctrl@1000000 {
 152                         compatible = "qcom,ipq5332-tlmm";
 153                         reg = <0x01000000 0x300000>;
 154                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 155                         gpio-controller;
 156                         #gpio-cells = <2>;
 157                         gpio-ranges = <&tlmm 0 0 53>;
 158                         interrupt-controller;
 159                         #interrupt-cells = <2>;
 160
 161                         serial_0_pins: serial0-state {
 162                                 pins = "gpio18", "gpio19";
 163                                 function = "blsp0_uart0";
 164                                 drive-strength = <8>;
 165                                 bias-pull-up;
 166                         };
 167                 };
 168
 169                 gcc: clock-controller@1800000 {
 170                         compatible = "qcom,ipq5332-gcc";
 171                         reg = <0x01800000 0x80000>;
 172                         #clock-cells = <1>;
 173                         #reset-cells = <1>;
 174                         #power-domain-cells = <1>;
 175                         clocks = <&xo_board>,
 176                                  <&sleep_clk>,
 177                                  <0>,
 178                                  <0>,
 179                                  <0>;
 180                 };
 181
 182                 tcsr_mutex: hwlock@1905000 {
 183                         compatible = "qcom,tcsr-mutex";
 184                         reg = <0x01905000 0x20000>;
 185                         #hwlock-cells = <1>;
 186                 };
 187
 188                 tcsr: syscon@1937000 {
 189                         compatible = "qcom,tcsr-ipq5332", "syscon";
 190                         reg = <0x01937000 0x21000>;
 191                 };
 192
 193                 sdhc: mmc@7804000 {
 194                         compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
 195                         reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
 196
 197                         interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
 199                         interrupt-names = "hc_irq", "pwr_irq";
 200
 201                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 202                                  <&gcc GCC_SDCC1_APPS_CLK>,
 203                                  <&xo_board>;
 204                         clock-names = "iface", "core", "xo";
 205                         status = "disabled";
 206                 };
 207
 208                 blsp_dma: dma-controller@7884000 {
 209                         compatible = "qcom,bam-v1.7.0";
 210                         reg = <0x07884000 0x1d000>;
 211                         interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
 212                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 213                         clock-names = "bam_clk";
 214                         #dma-cells = <1>;
 215                         qcom,ee = <0>;
 216                 };
 217
 218                 blsp1_uart0: serial@78af000 {
 219                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 220                         reg = <0x078af000 0x200>;
 221                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 222                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 223                                  <&gcc GCC_BLSP1_AHB_CLK>;
 224                         clock-names = "core", "iface";
 225                         status = "disabled";
 226                 };
 227
 228                 blsp1_spi0: spi@78b5000 {
 229                         compatible = "qcom,spi-qup-v2.2.1";
 230                         reg = <0x078b5000 0x600>;
 231                         #address-cells = <1>;
 232                         #size-cells = <0>;
 233                         interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
 234                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 235                                  <&gcc GCC_BLSP1_AHB_CLK>;
 236                         clock-names = "core", "iface";
 237                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
 238                         dma-names = "tx", "rx";
 239                         status = "disabled";
 240                 };
 241
 242                 blsp1_i2c1: i2c@78b6000 {
 243                         compatible = "qcom,i2c-qup-v2.2.1";
 244                         reg = <0x078b6000 0x600>;
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
 248                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 249                                  <&gcc GCC_BLSP1_AHB_CLK>;
 250                         clock-names = "core", "iface";
 251                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
 252                         dma-names = "tx", "rx";
 253                         status = "disabled";
 254                 };
 255
 256                 blsp1_spi2: spi@78b7000 {
 257                         compatible = "qcom,spi-qup-v2.2.1";
 258                         reg = <0x078b7000 0x600>;
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                         interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
 262                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 263                                  <&gcc GCC_BLSP1_AHB_CLK>;
 264                         clock-names = "core", "iface";
 265                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
 266                         dma-names = "tx", "rx";
 267                         status = "disabled";
 268                 };
 269
 270                 intc: interrupt-controller@b000000 {
 271                         compatible = "qcom,msm-qgic2";
 272                         reg = <0x0b000000 0x1000>,      /* GICD */
 273                               <0x0b002000 0x1000>,      /* GICC */
 274                               <0x0b001000 0x1000>,      /* GICH */
 275                               <0x0b004000 0x1000>;      /* GICV */
 276                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 277                         interrupt-controller;
 278                         #interrupt-cells = <3>;
 279                         #address-cells = <1>;
 280                         #size-cells = <1>;
 281                         ranges = <0 0x0b00c000 0x3000>;
 282
 283                         v2m0: v2m@0 {
 284                                 compatible = "arm,gic-v2m-frame";
 285                                 reg = <0x00000000 0xffd>;
 286                                 msi-controller;
 287                         };
 288
 289                         v2m1: v2m@1000 {
 290                                 compatible = "arm,gic-v2m-frame";
 291                                 reg = <0x00001000 0xffd>;
 292                                 msi-controller;
 293                         };
 294
 295                         v2m2: v2m@2000 {
 296                                 compatible = "arm,gic-v2m-frame";
 297                                 reg = <0x00002000 0xffd>;
 298                                 msi-controller;
 299                         };
 300                 };
 301
 302                 watchdog: watchdog@b017000 {
 303                         compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
 304                         reg = <0x0b017000 0x1000>;
 305                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 306                         clocks = <&sleep_clk>;
 307                         timeout-sec = <30>;
 308                 };
 309
 310                 apcs_glb: mailbox@b111000 {
 311                         compatible = "qcom,ipq5332-apcs-apps-global",
 312                                      "qcom,ipq6018-apcs-apps-global";
 313                         reg = <0x0b111000 0x1000>;
 314                         #clock-cells = <1>;
 315                         clocks = <&a53pll>, <&xo_board>;
 316                         clock-names = "pll", "xo";
 317                         #mbox-cells = <1>;
 318                 };
 319
 320                 a53pll: clock@b116000 {
 321                         compatible = "qcom,ipq5332-a53pll";
 322                         reg = <0x0b116000 0x40>;
 323                         #clock-cells = <0>;
 324                         clocks = <&xo_board>;
 325                         clock-names = "xo";
 326                 };
 327
 328                 timer@b120000 {
 329                         compatible = "arm,armv7-timer-mem";
 330                         reg = <0x0b120000 0x1000>;
 331                         #address-cells = <1>;
 332                         #size-cells = <1>;
 333                         ranges;
 334
 335                         frame@b120000 {
 336                                 reg = <0x0b121000 0x1000>,
 337                                       <0x0b122000 0x1000>;
 338                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 339                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 340                                 frame-number = <0>;
 341                         };
 342
 343                         frame@b123000 {
 344                                 reg = <0x0b123000 0x1000>;
 345                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 346                                 frame-number = <1>;
 347                                 status = "disabled";
 348                         };
 349
 350                         frame@b124000 {
 351                                 reg = <0x0b124000 0x1000>;
 352                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 353                                 frame-number = <2>;
 354                                 status = "disabled";
 355                         };
 356
 357                         frame@b125000 {
 358                                 reg = <0x0b125000 0x1000>;
 359                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 360                                 frame-number = <3>;
 361                                 status = "disabled";
 362                         };
 363
 364                         frame@b126000 {
 365                                 reg = <0x0b126000 0x1000>;
 366                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 367                                 frame-number = <4>;
 368                                 status = "disabled";
 369                         };
 370
 371                         frame@b127000 {
 372                                 reg = <0x0b127000 0x1000>;
 373                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 374                                 frame-number = <5>;
 375                                 status = "disabled";
 376                         };
 377
 378                         frame@b128000 {
 379                                 reg = <0x0b128000 0x1000>;
 380                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 381                                 frame-number = <6>;
 382                                 status = "disabled";
 383                         };
 384                 };
 385         };
 386
 387         timer {
 388                 compatible = "arm,armv8-timer";
 389                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 390                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 391                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 392                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 393         };
 394 };