arch/arm64/boot/dts/qcom/ipq5332.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * IPQ5332 device tree source
   4  *
   5  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,apss-ipq.h>
   9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         interrupt-parent = <&intc>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         clocks {
  18                 sleep_clk: sleep-clk {
  19                         compatible = "fixed-clock";
  20                         #clock-cells = <0>;
  21                 };
  22
  23                 xo_board: xo-board-clk {
  24                         compatible = "fixed-clock";
  25                         #clock-cells = <0>;
  26                 };
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 CPU0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53";
  36                         reg = <0x0>;
  37                         enable-method = "psci";
  38                         next-level-cache = <&L2_0>;
  39                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  40                         operating-points-v2 = <&cpu_opp_table>;
  41                 };
  42
  43                 CPU1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a53";
  46                         reg = <0x1>;
  47                         enable-method = "psci";
  48                         next-level-cache = <&L2_0>;
  49                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  50                         operating-points-v2 = <&cpu_opp_table>;
  51                 };
  52
  53                 CPU2: cpu@2 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a53";
  56                         reg = <0x2>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&L2_0>;
  59                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  60                         operating-points-v2 = <&cpu_opp_table>;
  61                 };
  62
  63                 CPU3: cpu@3 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a53";
  66                         reg = <0x3>;
  67                         enable-method = "psci";
  68                         next-level-cache = <&L2_0>;
  69                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  70                         operating-points-v2 = <&cpu_opp_table>;
  71                 };
  72
  73                 L2_0: l2-cache {
  74                         compatible = "cache";
  75                         cache-level = <2>;
  76                         cache-unified;
  77                 };
  78         };
  79
  80         firmware {
  81                 scm {
  82                         compatible = "qcom,scm-ipq5332", "qcom,scm";
  83                         qcom,dload-mode = <&tcsr 0x6100>;
  84                 };
  85         };
  86
  87         memory@40000000 {
  88                 device_type = "memory";
  89                 /* We expect the bootloader to fill in the size */
  90                 reg = <0x0 0x40000000 0x0 0x0>;
  91         };
  92
  93         cpu_opp_table: opp-table-cpu {
  94                 compatible = "operating-points-v2-kryo-cpu";
  95                 opp-shared;
  96                 nvmem-cells = <&cpu_speed_bin>;
  97
  98                 opp-1100000000 {
  99                         opp-hz = /bits/ 64 <1100000000>;
 100                         opp-supported-hw = <0x7>;
 101                         clock-latency-ns = <200000>;
 102                 };
 103
 104                 opp-1500000000 {
 105                         opp-hz = /bits/ 64 <1500000000>;
 106                         opp-supported-hw = <0x3>;
 107                         clock-latency-ns = <200000>;
 108                 };
 109         };
 110
 111         pmu {
 112                 compatible = "arm,cortex-a53-pmu";
 113                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 114         };
 115
 116         psci {
 117                 compatible = "arm,psci-1.0";
 118                 method = "smc";
 119         };
 120
 121         reserved-memory {
 122                 #address-cells = <2>;
 123                 #size-cells = <2>;
 124                 ranges;
 125
 126                 bootloader@4a100000 {
 127                         reg = <0x0 0x4a100000 0x0 0x400000>;
 128                         no-map;
 129                 };
 130
 131                 sbl@4a500000 {
 132                         reg = <0x0 0x4a500000 0x0 0x100000>;
 133                         no-map;
 134                 };
 135
 136                 tz_mem: tz@4a600000 {
 137                         reg = <0x0 0x4a600000 0x0 0x200000>;
 138                         no-map;
 139                 };
 140
 141                 smem@4a800000 {
 142                         compatible = "qcom,smem";
 143                         reg = <0x0 0x4a800000 0x0 0x100000>;
 144                         no-map;
 145
 146                         hwlocks = <&tcsr_mutex 3>;
 147                 };
 148         };
 149
 150         soc@0 {
 151                 compatible = "simple-bus";
 152                 #address-cells = <1>;
 153                 #size-cells = <1>;
 154                 ranges = <0 0 0 0xffffffff>;
 155
 156                 usbphy0: phy@7b000 {
 157                         compatible = "qcom,ipq5332-usb-hsphy";
 158                         reg = <0x0007b000 0x12c>;
 159
 160                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
 161
 162                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
 163
 164                         #phy-cells = <0>;
 165
 166                         status = "disabled";
 167                 };
 168
 169                 qfprom: efuse@a4000 {
 170                         compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
 171                         reg = <0x000a4000 0x721>;
 172                         #address-cells = <1>;
 173                         #size-cells = <1>;
 174
 175                         cpu_speed_bin: cpu-speed-bin@1d {
 176                                 reg = <0x1d 0x2>;
 177                                 bits = <7 2>;
 178                         };
 179                 };
 180
 181                 rng: rng@e3000 {
 182                         compatible = "qcom,prng-ee";
 183                         reg = <0x000e3000 0x1000>;
 184                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 185                         clock-names = "core";
 186                 };
 187
 188                 tlmm: pinctrl@1000000 {
 189                         compatible = "qcom,ipq5332-tlmm";
 190                         reg = <0x01000000 0x300000>;
 191                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 192                         gpio-controller;
 193                         #gpio-cells = <2>;
 194                         gpio-ranges = <&tlmm 0 0 53>;
 195                         interrupt-controller;
 196                         #interrupt-cells = <2>;
 197
 198                         serial_0_pins: serial0-state {
 199                                 pins = "gpio18", "gpio19";
 200                                 function = "blsp0_uart0";
 201                                 drive-strength = <8>;
 202                                 bias-pull-up;
 203                         };
 204                 };
 205
 206                 gcc: clock-controller@1800000 {
 207                         compatible = "qcom,ipq5332-gcc";
 208                         reg = <0x01800000 0x80000>;
 209                         #clock-cells = <1>;
 210                         #reset-cells = <1>;
 211                         #power-domain-cells = <1>;
 212                         clocks = <&xo_board>,
 213                                  <&sleep_clk>,
 214                                  <0>,
 215                                  <0>,
 216                                  <0>;
 217                 };
 218
 219                 tcsr_mutex: hwlock@1905000 {
 220                         compatible = "qcom,tcsr-mutex";
 221                         reg = <0x01905000 0x20000>;
 222                         #hwlock-cells = <1>;
 223                 };
 224
 225                 tcsr: syscon@1937000 {
 226                         compatible = "qcom,tcsr-ipq5332", "syscon";
 227                         reg = <0x01937000 0x21000>;
 228                 };
 229
 230                 sdhc: mmc@7804000 {
 231                         compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
 232                         reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
 233
 234                         interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
 236                         interrupt-names = "hc_irq", "pwr_irq";
 237
 238                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 239                                  <&gcc GCC_SDCC1_APPS_CLK>,
 240                                  <&xo_board>;
 241                         clock-names = "iface", "core", "xo";
 242                         status = "disabled";
 243                 };
 244
 245                 blsp_dma: dma-controller@7884000 {
 246                         compatible = "qcom,bam-v1.7.0";
 247                         reg = <0x07884000 0x1d000>;
 248                         interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
 249                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 250                         clock-names = "bam_clk";
 251                         #dma-cells = <1>;
 252                         qcom,ee = <0>;
 253                 };
 254
 255                 blsp1_uart0: serial@78af000 {
 256                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 257                         reg = <0x078af000 0x200>;
 258                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 259                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 260                                  <&gcc GCC_BLSP1_AHB_CLK>;
 261                         clock-names = "core", "iface";
 262                         status = "disabled";
 263                 };
 264
 265                 blsp1_uart1: serial@78b0000 {
 266                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 267                         reg = <0x078b0000 0x200>;
 268                         interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
 269                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 270                                  <&gcc GCC_BLSP1_AHB_CLK>;
 271                         clock-names = "core", "iface";
 272                         dmas = <&blsp_dma 2>, <&blsp_dma 3>;
 273                         dma-names = "tx", "rx";
 274                         status = "disabled";
 275                 };
 276
 277                 blsp1_spi0: spi@78b5000 {
 278                         compatible = "qcom,spi-qup-v2.2.1";
 279                         reg = <0x078b5000 0x600>;
 280                         #address-cells = <1>;
 281                         #size-cells = <0>;
 282                         interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
 283                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 284                                  <&gcc GCC_BLSP1_AHB_CLK>;
 285                         clock-names = "core", "iface";
 286                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
 287                         dma-names = "tx", "rx";
 288                         status = "disabled";
 289                 };
 290
 291                 blsp1_i2c1: i2c@78b6000 {
 292                         compatible = "qcom,i2c-qup-v2.2.1";
 293                         reg = <0x078b6000 0x600>;
 294                         #address-cells = <1>;
 295                         #size-cells = <0>;
 296                         interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
 297                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 298                                  <&gcc GCC_BLSP1_AHB_CLK>;
 299                         clock-names = "core", "iface";
 300                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
 301                         dma-names = "tx", "rx";
 302                         status = "disabled";
 303                 };
 304
 305                 blsp1_spi2: spi@78b7000 {
 306                         compatible = "qcom,spi-qup-v2.2.1";
 307                         reg = <0x078b7000 0x600>;
 308                         #address-cells = <1>;
 309                         #size-cells = <0>;
 310                         interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
 311                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 312                                  <&gcc GCC_BLSP1_AHB_CLK>;
 313                         clock-names = "core", "iface";
 314                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
 315                         dma-names = "tx", "rx";
 316                         status = "disabled";
 317                 };
 318
 319                 usb: usb@8af8800 {
 320                         compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
 321                         reg = <0x08af8800 0x400>;
 322
 323                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 324                         interrupt-names = "hs_phy_irq";
 325
 326                         clocks = <&gcc GCC_USB0_MASTER_CLK>,
 327                                  <&gcc GCC_SNOC_USB_CLK>,
 328                                  <&gcc GCC_USB0_SLEEP_CLK>,
 329                                  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 330                         clock-names = "core",
 331                                       "iface",
 332                                       "sleep",
 333                                       "mock_utmi";
 334
 335                         resets = <&gcc GCC_USB_BCR>;
 336
 337                         qcom,select-utmi-as-pipe-clk;
 338
 339                         #address-cells = <1>;
 340                         #size-cells = <1>;
 341                         ranges;
 342
 343                         status = "disabled";
 344
 345                         usb_dwc: usb@8a00000 {
 346                                 compatible = "snps,dwc3";
 347                                 reg = <0x08a00000 0xe000>;
 348                                 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 349                                 clock-names = "ref";
 350                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 351                                 phy-names = "usb2-phy";
 352                                 phys = <&usbphy0>;
 353                                 tx-fifo-resize;
 354                                 snps,is-utmi-l1-suspend;
 355                                 snps,hird-threshold = /bits/ 8 <0x0>;
 356                                 snps,dis_u2_susphy_quirk;
 357                                 snps,dis_u3_susphy_quirk;
 358                         };
 359                 };
 360
 361                 intc: interrupt-controller@b000000 {
 362                         compatible = "qcom,msm-qgic2";
 363                         reg = <0x0b000000 0x1000>,      /* GICD */
 364                               <0x0b002000 0x1000>,      /* GICC */
 365                               <0x0b001000 0x1000>,      /* GICH */
 366                               <0x0b004000 0x1000>;      /* GICV */
 367                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 368                         interrupt-controller;
 369                         #interrupt-cells = <3>;
 370                         #address-cells = <1>;
 371                         #size-cells = <1>;
 372                         ranges = <0 0x0b00c000 0x3000>;
 373
 374                         v2m0: v2m@0 {
 375                                 compatible = "arm,gic-v2m-frame";
 376                                 reg = <0x00000000 0xffd>;
 377                                 msi-controller;
 378                         };
 379
 380                         v2m1: v2m@1000 {
 381                                 compatible = "arm,gic-v2m-frame";
 382                                 reg = <0x00001000 0xffd>;
 383                                 msi-controller;
 384                         };
 385
 386                         v2m2: v2m@2000 {
 387                                 compatible = "arm,gic-v2m-frame";
 388                                 reg = <0x00002000 0xffd>;
 389                                 msi-controller;
 390                         };
 391                 };
 392
 393                 watchdog: watchdog@b017000 {
 394                         compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
 395                         reg = <0x0b017000 0x1000>;
 396                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 397                         clocks = <&sleep_clk>;
 398                         timeout-sec = <30>;
 399                 };
 400
 401                 apcs_glb: mailbox@b111000 {
 402                         compatible = "qcom,ipq5332-apcs-apps-global",
 403                                      "qcom,ipq6018-apcs-apps-global";
 404                         reg = <0x0b111000 0x1000>;
 405                         #clock-cells = <1>;
 406                         clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>;
 407                         clock-names = "pll", "xo", "gpll0";
 408                         #mbox-cells = <1>;
 409                 };
 410
 411                 a53pll: clock@b116000 {
 412                         compatible = "qcom,ipq5332-a53pll";
 413                         reg = <0x0b116000 0x40>;
 414                         #clock-cells = <0>;
 415                         clocks = <&xo_board>;
 416                         clock-names = "xo";
 417                 };
 418
 419                 timer@b120000 {
 420                         compatible = "arm,armv7-timer-mem";
 421                         reg = <0x0b120000 0x1000>;
 422                         #address-cells = <1>;
 423                         #size-cells = <1>;
 424                         ranges;
 425
 426                         frame@b120000 {
 427                                 reg = <0x0b121000 0x1000>,
 428                                       <0x0b122000 0x1000>;
 429                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 430                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 431                                 frame-number = <0>;
 432                         };
 433
 434                         frame@b123000 {
 435                                 reg = <0x0b123000 0x1000>;
 436                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 437                                 frame-number = <1>;
 438                                 status = "disabled";
 439                         };
 440
 441                         frame@b124000 {
 442                                 reg = <0x0b124000 0x1000>;
 443                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 444                                 frame-number = <2>;
 445                                 status = "disabled";
 446                         };
 447
 448                         frame@b125000 {
 449                                 reg = <0x0b125000 0x1000>;
 450                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 451                                 frame-number = <3>;
 452                                 status = "disabled";
 453                         };
 454
 455                         frame@b126000 {
 456                                 reg = <0x0b126000 0x1000>;
 457                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 458                                 frame-number = <4>;
 459                                 status = "disabled";
 460                         };
 461
 462                         frame@b127000 {
 463                                 reg = <0x0b127000 0x1000>;
 464                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 465                                 frame-number = <5>;
 466                                 status = "disabled";
 467                         };
 468
 469                         frame@b128000 {
 470                                 reg = <0x0b128000 0x1000>;
 471                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 472                                 frame-number = <6>;
 473                                 status = "disabled";
 474                         };
 475                 };
 476         };
 477
 478         timer {
 479                 compatible = "arm,armv8-timer";
 480                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 481                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 482                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 483                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 484         };
 485 };