arch/arm64/boot/dts/nvidia/tegra234.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 #include <dt-bindings/clock/tegra234-clock.h>
   4 #include <dt-bindings/gpio/tegra234-gpio.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/mailbox/tegra186-hsp.h>
   7 #include <dt-bindings/memory/tegra234-mc.h>
   8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
   9 #include <dt-bindings/power/tegra234-powergate.h>
  10 #include <dt-bindings/reset/tegra234-reset.h>
  11
  12 / {
  13         compatible = "nvidia,tegra234";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         bus@0 {
  19                 compatible = "simple-bus";
  20
  21                 #address-cells = <2>;
  22                 #size-cells = <2>;
  23                 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
  24
  25                 misc@100000 {
  26                         compatible = "nvidia,tegra234-misc";
  27                         reg = <0x0 0x00100000 0x0 0xf000>,
  28                               <0x0 0x0010f000 0x0 0x1000>;
  29                         status = "okay";
  30                 };
  31
  32                 timer@2080000 {
  33                         compatible = "nvidia,tegra234-timer";
  34                         reg = <0x0 0x02080000 0x0 0x00121000>;
  35                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  36                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  37                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  38                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  39                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  40                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  41                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  42                                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  43                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  44                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  45                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  46                                      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  47                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  48                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  49                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  50                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  51                         status = "okay";
  52                 };
  53
  54                 gpio: gpio@2200000 {
  55                         compatible = "nvidia,tegra234-gpio";
  56                         reg-names = "security", "gpio";
  57                         reg = <0x0 0x02200000 0x0 0x10000>,
  58                               <0x0 0x02210000 0x0 0x10000>;
  59                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
  60                                      <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
  61                                      <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
  62                                      <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
  63                                      <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
  64                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
  65                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
  66                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
  67                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
  68                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
  69                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
  70                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
  71                                      <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
  72                                      <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
  73                                      <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
  74                                      <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
  75                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  76                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
  77                                      <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
  78                                      <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
  79                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
  80                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
  81                                      <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
  83                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  84                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
  86                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
  87                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
  88                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
  89                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
  90                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
  91                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
  94                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
  95                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
  96                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
  97                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
  98                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
  99                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
 100                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
 101                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 102                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
 103                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
 104                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
 105                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 106                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
 107                         #interrupt-cells = <2>;
 108                         interrupt-controller;
 109                         #gpio-cells = <2>;
 110                         gpio-controller;
 111                 };
 112
 113                 gpcdma: dma-controller@2600000 {
 114                         compatible = "nvidia,tegra234-gpcdma",
 115                                      "nvidia,tegra186-gpcdma";
 116                         reg = <0x0 0x2600000 0x0 0x210000>;
 117                         resets = <&bpmp TEGRA234_RESET_GPCDMA>;
 118                         reset-names = "gpcdma";
 119                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 120                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 121                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 122                                      <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 123                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 124                                      <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 125                                      <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
 126                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
 127                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 128                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 129                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 130                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 131                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 132                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 133                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 134                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 135                                      <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 136                                      <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 137                                      <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 139                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 140                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 141                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 142                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 143                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 144                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 145                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 147                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 148                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 149                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 150                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 151                         #dma-cells = <1>;
 152                         iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
 153                         dma-channel-mask = <0xfffffffe>;
 154                         dma-coherent;
 155                 };
 156
 157                 aconnect@2900000 {
 158                         compatible = "nvidia,tegra234-aconnect",
 159                                      "nvidia,tegra210-aconnect";
 160                         clocks = <&bpmp TEGRA234_CLK_APE>,
 161                                  <&bpmp TEGRA234_CLK_APB2APE>;
 162                         clock-names = "ape", "apb2ape";
 163                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
 164                         status = "disabled";
 165
 166                         #address-cells = <2>;
 167                         #size-cells = <2>;
 168                         ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
 169
 170                         tegra_ahub: ahub@2900800 {
 171                                 compatible = "nvidia,tegra234-ahub";
 172                                 reg = <0x0 0x02900800 0x0 0x800>;
 173                                 clocks = <&bpmp TEGRA234_CLK_AHUB>;
 174                                 clock-names = "ahub";
 175                                 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
 176                                 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 177                                 status = "disabled";
 178
 179                                 #address-cells = <2>;
 180                                 #size-cells = <2>;
 181                                 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
 182
 183                                 tegra_i2s1: i2s@2901000 {
 184                                         compatible = "nvidia,tegra234-i2s",
 185                                                      "nvidia,tegra210-i2s";
 186                                         reg = <0x0 0x2901000 0x0 0x100>;
 187                                         clocks = <&bpmp TEGRA234_CLK_I2S1>,
 188                                                  <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
 189                                         clock-names = "i2s", "sync_input";
 190                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
 191                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 192                                         assigned-clock-rates = <1536000>;
 193                                         sound-name-prefix = "I2S1";
 194                                         status = "disabled";
 195                                 };
 196
 197                                 tegra_i2s2: i2s@2901100 {
 198                                         compatible = "nvidia,tegra234-i2s",
 199                                                      "nvidia,tegra210-i2s";
 200                                         reg = <0x0 0x2901100 0x0 0x100>;
 201                                         clocks = <&bpmp TEGRA234_CLK_I2S2>,
 202                                                  <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
 203                                         clock-names = "i2s", "sync_input";
 204                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
 205                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 206                                         assigned-clock-rates = <1536000>;
 207                                         sound-name-prefix = "I2S2";
 208                                         status = "disabled";
 209                                 };
 210
 211                                 tegra_i2s3: i2s@2901200 {
 212                                         compatible = "nvidia,tegra234-i2s",
 213                                                      "nvidia,tegra210-i2s";
 214                                         reg = <0x0 0x2901200 0x0 0x100>;
 215                                         clocks = <&bpmp TEGRA234_CLK_I2S3>,
 216                                                  <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
 217                                         clock-names = "i2s", "sync_input";
 218                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
 219                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 220                                         assigned-clock-rates = <1536000>;
 221                                         sound-name-prefix = "I2S3";
 222                                         status = "disabled";
 223                                 };
 224
 225                                 tegra_i2s4: i2s@2901300 {
 226                                         compatible = "nvidia,tegra234-i2s",
 227                                                      "nvidia,tegra210-i2s";
 228                                         reg = <0x0 0x2901300 0x0 0x100>;
 229                                         clocks = <&bpmp TEGRA234_CLK_I2S4>,
 230                                                  <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
 231                                         clock-names = "i2s", "sync_input";
 232                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
 233                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 234                                         assigned-clock-rates = <1536000>;
 235                                         sound-name-prefix = "I2S4";
 236                                         status = "disabled";
 237                                 };
 238
 239                                 tegra_i2s5: i2s@2901400 {
 240                                         compatible = "nvidia,tegra234-i2s",
 241                                                      "nvidia,tegra210-i2s";
 242                                         reg = <0x0 0x2901400 0x0 0x100>;
 243                                         clocks = <&bpmp TEGRA234_CLK_I2S5>,
 244                                                  <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
 245                                         clock-names = "i2s", "sync_input";
 246                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
 247                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 248                                         assigned-clock-rates = <1536000>;
 249                                         sound-name-prefix = "I2S5";
 250                                         status = "disabled";
 251                                 };
 252
 253                                 tegra_i2s6: i2s@2901500 {
 254                                         compatible = "nvidia,tegra234-i2s",
 255                                                      "nvidia,tegra210-i2s";
 256                                         reg = <0x0 0x2901500 0x0 0x100>;
 257                                         clocks = <&bpmp TEGRA234_CLK_I2S6>,
 258                                                  <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
 259                                         clock-names = "i2s", "sync_input";
 260                                         assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
 261                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 262                                         assigned-clock-rates = <1536000>;
 263                                         sound-name-prefix = "I2S6";
 264                                         status = "disabled";
 265                                 };
 266
 267                                 tegra_sfc1: sfc@2902000 {
 268                                         compatible = "nvidia,tegra234-sfc",
 269                                                      "nvidia,tegra210-sfc";
 270                                         reg = <0x0 0x2902000 0x0 0x200>;
 271                                         sound-name-prefix = "SFC1";
 272                                         status = "disabled";
 273                                 };
 274
 275                                 tegra_sfc2: sfc@2902200 {
 276                                         compatible = "nvidia,tegra234-sfc",
 277                                                      "nvidia,tegra210-sfc";
 278                                         reg = <0x0 0x2902200 0x0 0x200>;
 279                                         sound-name-prefix = "SFC2";
 280                                         status = "disabled";
 281                                 };
 282
 283                                 tegra_sfc3: sfc@2902400 {
 284                                         compatible = "nvidia,tegra234-sfc",
 285                                                      "nvidia,tegra210-sfc";
 286                                         reg = <0x0 0x2902400 0x0 0x200>;
 287                                         sound-name-prefix = "SFC3";
 288                                         status = "disabled";
 289                                 };
 290
 291                                 tegra_sfc4: sfc@2902600 {
 292                                         compatible = "nvidia,tegra234-sfc",
 293                                                      "nvidia,tegra210-sfc";
 294                                         reg = <0x0 0x2902600 0x0 0x200>;
 295                                         sound-name-prefix = "SFC4";
 296                                         status = "disabled";
 297                                 };
 298
 299                                 tegra_amx1: amx@2903000 {
 300                                         compatible = "nvidia,tegra234-amx",
 301                                                      "nvidia,tegra194-amx";
 302                                         reg = <0x0 0x2903000 0x0 0x100>;
 303                                         sound-name-prefix = "AMX1";
 304                                         status = "disabled";
 305                                 };
 306
 307                                 tegra_amx2: amx@2903100 {
 308                                         compatible = "nvidia,tegra234-amx",
 309                                                      "nvidia,tegra194-amx";
 310                                         reg = <0x0 0x2903100 0x0 0x100>;
 311                                         sound-name-prefix = "AMX2";
 312                                         status = "disabled";
 313                                 };
 314
 315                                 tegra_amx3: amx@2903200 {
 316                                         compatible = "nvidia,tegra234-amx",
 317                                                      "nvidia,tegra194-amx";
 318                                         reg = <0x0 0x2903200 0x0 0x100>;
 319                                         sound-name-prefix = "AMX3";
 320                                         status = "disabled";
 321                                 };
 322
 323                                 tegra_amx4: amx@2903300 {
 324                                         compatible = "nvidia,tegra234-amx",
 325                                                      "nvidia,tegra194-amx";
 326                                         reg = <0x0 0x2903300 0x0 0x100>;
 327                                         sound-name-prefix = "AMX4";
 328                                         status = "disabled";
 329                                 };
 330
 331                                 tegra_adx1: adx@2903800 {
 332                                         compatible = "nvidia,tegra234-adx",
 333                                                      "nvidia,tegra210-adx";
 334                                         reg = <0x0 0x2903800 0x0 0x100>;
 335                                         sound-name-prefix = "ADX1";
 336                                         status = "disabled";
 337                                 };
 338
 339                                 tegra_adx2: adx@2903900 {
 340                                         compatible = "nvidia,tegra234-adx",
 341                                                      "nvidia,tegra210-adx";
 342                                         reg = <0x0 0x2903900 0x0 0x100>;
 343                                         sound-name-prefix = "ADX2";
 344                                         status = "disabled";
 345                                 };
 346
 347                                 tegra_adx3: adx@2903a00 {
 348                                         compatible = "nvidia,tegra234-adx",
 349                                                      "nvidia,tegra210-adx";
 350                                         reg = <0x0 0x2903a00 0x0 0x100>;
 351                                         sound-name-prefix = "ADX3";
 352                                         status = "disabled";
 353                                 };
 354
 355                                 tegra_adx4: adx@2903b00 {
 356                                         compatible = "nvidia,tegra234-adx",
 357                                                      "nvidia,tegra210-adx";
 358                                         reg = <0x0 0x2903b00 0x0 0x100>;
 359                                         sound-name-prefix = "ADX4";
 360                                         status = "disabled";
 361                                 };
 362
 363
 364                                 tegra_dmic1: dmic@2904000 {
 365                                         compatible = "nvidia,tegra234-dmic",
 366                                                      "nvidia,tegra210-dmic";
 367                                         reg = <0x0 0x2904000 0x0 0x100>;
 368                                         clocks = <&bpmp TEGRA234_CLK_DMIC1>;
 369                                         clock-names = "dmic";
 370                                         assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
 371                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 372                                         assigned-clock-rates = <3072000>;
 373                                         sound-name-prefix = "DMIC1";
 374                                         status = "disabled";
 375                                 };
 376
 377                                 tegra_dmic2: dmic@2904100 {
 378                                         compatible = "nvidia,tegra234-dmic",
 379                                                      "nvidia,tegra210-dmic";
 380                                         reg = <0x0 0x2904100 0x0 0x100>;
 381                                         clocks = <&bpmp TEGRA234_CLK_DMIC2>;
 382                                         clock-names = "dmic";
 383                                         assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
 384                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 385                                         assigned-clock-rates = <3072000>;
 386                                         sound-name-prefix = "DMIC2";
 387                                         status = "disabled";
 388                                 };
 389
 390                                 tegra_dmic3: dmic@2904200 {
 391                                         compatible = "nvidia,tegra234-dmic",
 392                                                      "nvidia,tegra210-dmic";
 393                                         reg = <0x0 0x2904200 0x0 0x100>;
 394                                         clocks = <&bpmp TEGRA234_CLK_DMIC3>;
 395                                         clock-names = "dmic";
 396                                         assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
 397                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 398                                         assigned-clock-rates = <3072000>;
 399                                         sound-name-prefix = "DMIC3";
 400                                         status = "disabled";
 401                                 };
 402
 403                                 tegra_dmic4: dmic@2904300 {
 404                                         compatible = "nvidia,tegra234-dmic",
 405                                                      "nvidia,tegra210-dmic";
 406                                         reg = <0x0 0x2904300 0x0 0x100>;
 407                                         clocks = <&bpmp TEGRA234_CLK_DMIC4>;
 408                                         clock-names = "dmic";
 409                                         assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
 410                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 411                                         assigned-clock-rates = <3072000>;
 412                                         sound-name-prefix = "DMIC4";
 413                                         status = "disabled";
 414                                 };
 415
 416                                 tegra_dspk1: dspk@2905000 {
 417                                         compatible = "nvidia,tegra234-dspk",
 418                                                      "nvidia,tegra186-dspk";
 419                                         reg = <0x0 0x2905000 0x0 0x100>;
 420                                         clocks = <&bpmp TEGRA234_CLK_DSPK1>;
 421                                         clock-names = "dspk";
 422                                         assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
 423                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 424                                         assigned-clock-rates = <12288000>;
 425                                         sound-name-prefix = "DSPK1";
 426                                         status = "disabled";
 427                                 };
 428
 429                                 tegra_dspk2: dspk@2905100 {
 430                                         compatible = "nvidia,tegra234-dspk",
 431                                                      "nvidia,tegra186-dspk";
 432                                         reg = <0x0 0x2905100 0x0 0x100>;
 433                                         clocks = <&bpmp TEGRA234_CLK_DSPK2>;
 434                                         clock-names = "dspk";
 435                                         assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
 436                                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
 437                                         assigned-clock-rates = <12288000>;
 438                                         sound-name-prefix = "DSPK2";
 439                                         status = "disabled";
 440                                 };
 441
 442                                 tegra_ope1: processing-engine@2908000 {
 443                                         compatible = "nvidia,tegra234-ope",
 444                                                      "nvidia,tegra210-ope";
 445                                         reg = <0x0 0x2908000 0x0 0x100>;
 446                                         sound-name-prefix = "OPE1";
 447                                         status = "disabled";
 448
 449                                         #address-cells = <2>;
 450                                         #size-cells = <2>;
 451                                         ranges;
 452
 453                                         equalizer@2908100 {
 454                                                 compatible = "nvidia,tegra234-peq",
 455                                                              "nvidia,tegra210-peq";
 456                                                 reg = <0x0 0x2908100 0x0 0x100>;
 457                                         };
 458
 459                                         dynamic-range-compressor@2908200 {
 460                                                 compatible = "nvidia,tegra234-mbdrc",
 461                                                              "nvidia,tegra210-mbdrc";
 462                                                 reg = <0x0 0x2908200 0x0 0x200>;
 463                                         };
 464                                 };
 465
 466                                 tegra_mvc1: mvc@290a000 {
 467                                         compatible = "nvidia,tegra234-mvc",
 468                                                      "nvidia,tegra210-mvc";
 469                                         reg = <0x0 0x290a000 0x0 0x200>;
 470                                         sound-name-prefix = "MVC1";
 471                                         status = "disabled";
 472                                 };
 473
 474                                 tegra_mvc2: mvc@290a200 {
 475                                         compatible = "nvidia,tegra234-mvc",
 476                                                      "nvidia,tegra210-mvc";
 477                                         reg = <0x0 0x290a200 0x0 0x200>;
 478                                         sound-name-prefix = "MVC2";
 479                                         status = "disabled";
 480                                 };
 481
 482                                 tegra_amixer: amixer@290bb00 {
 483                                         compatible = "nvidia,tegra234-amixer",
 484                                                      "nvidia,tegra210-amixer";
 485                                         reg = <0x0 0x290bb00 0x0 0x800>;
 486                                         sound-name-prefix = "MIXER1";
 487                                         status = "disabled";
 488                                 };
 489
 490                                 tegra_admaif: admaif@290f000 {
 491                                         compatible = "nvidia,tegra234-admaif",
 492                                                      "nvidia,tegra186-admaif";
 493                                         reg = <0x0 0x0290f000 0x0 0x1000>;
 494                                         dmas = <&adma 1>, <&adma 1>,
 495                                                <&adma 2>, <&adma 2>,
 496                                                <&adma 3>, <&adma 3>,
 497                                                <&adma 4>, <&adma 4>,
 498                                                <&adma 5>, <&adma 5>,
 499                                                <&adma 6>, <&adma 6>,
 500                                                <&adma 7>, <&adma 7>,
 501                                                <&adma 8>, <&adma 8>,
 502                                                <&adma 9>, <&adma 9>,
 503                                                <&adma 10>, <&adma 10>,
 504                                                <&adma 11>, <&adma 11>,
 505                                                <&adma 12>, <&adma 12>,
 506                                                <&adma 13>, <&adma 13>,
 507                                                <&adma 14>, <&adma 14>,
 508                                                <&adma 15>, <&adma 15>,
 509                                                <&adma 16>, <&adma 16>,
 510                                                <&adma 17>, <&adma 17>,
 511                                                <&adma 18>, <&adma 18>,
 512                                                <&adma 19>, <&adma 19>,
 513                                                <&adma 20>, <&adma 20>;
 514                                         dma-names = "rx1", "tx1",
 515                                                     "rx2", "tx2",
 516                                                     "rx3", "tx3",
 517                                                     "rx4", "tx4",
 518                                                     "rx5", "tx5",
 519                                                     "rx6", "tx6",
 520                                                     "rx7", "tx7",
 521                                                     "rx8", "tx8",
 522                                                     "rx9", "tx9",
 523                                                     "rx10", "tx10",
 524                                                     "rx11", "tx11",
 525                                                     "rx12", "tx12",
 526                                                     "rx13", "tx13",
 527                                                     "rx14", "tx14",
 528                                                     "rx15", "tx15",
 529                                                     "rx16", "tx16",
 530                                                     "rx17", "tx17",
 531                                                     "rx18", "tx18",
 532                                                     "rx19", "tx19",
 533                                                     "rx20", "tx20";
 534                                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>,
 535                                                         <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
 536                                         interconnect-names = "dma-mem", "write";
 537                                         iommus = <&smmu_niso0 TEGRA234_SID_APE>;
 538                                         status = "disabled";
 539                                 };
 540
 541                                 tegra_asrc: asrc@2910000 {
 542                                         compatible = "nvidia,tegra234-asrc",
 543                                                      "nvidia,tegra186-asrc";
 544                                         reg = <0x0 0x2910000 0x0 0x2000>;
 545                                         sound-name-prefix = "ASRC1";
 546                                         status = "disabled";
 547                                 };
 548                         };
 549
 550                         adma: dma-controller@2930000 {
 551                                 compatible = "nvidia,tegra234-adma",
 552                                              "nvidia,tegra186-adma";
 553                                 reg = <0x0 0x02930000 0x0 0x20000>;
 554                                 interrupt-parent = <&agic>;
 555                                 interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 556                                               <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 557                                               <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 558                                               <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 559                                               <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 560                                               <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 561                                               <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 562                                               <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 563                                               <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 564                                               <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 565                                               <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 566                                               <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 567                                               <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 568                                               <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 569                                               <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 570                                               <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 571                                               <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 572                                               <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 573                                               <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 574                                               <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 575                                               <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 576                                               <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 577                                               <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 578                                               <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 579                                               <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 580                                               <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 581                                               <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 582                                               <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 583                                               <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 584                                               <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 585                                               <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 586                                               <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 587                                 #dma-cells = <1>;
 588                                 clocks = <&bpmp TEGRA234_CLK_AHUB>;
 589                                 clock-names = "d_audio";
 590                                 status = "disabled";
 591                         };
 592
 593                         agic: interrupt-controller@2a40000 {
 594                                 compatible = "nvidia,tegra234-agic",
 595                                              "nvidia,tegra210-agic";
 596                                 #interrupt-cells = <3>;
 597                                 interrupt-controller;
 598                                 reg = <0x0 0x02a41000 0x0 0x1000>,
 599                                       <0x0 0x02a42000 0x0 0x2000>;
 600                                 interrupts = <GIC_SPI 145
 601                                               (GIC_CPU_MASK_SIMPLE(4) |
 602                                                IRQ_TYPE_LEVEL_HIGH)>;
 603                                 clocks = <&bpmp TEGRA234_CLK_APE>;
 604                                 clock-names = "clk";
 605                                 status = "disabled";
 606                         };
 607                 };
 608
 609                 mc: memory-controller@2c00000 {
 610                         compatible = "nvidia,tegra234-mc";
 611                         reg = <0x0 0x02c00000 0x0 0x10000>,   /* MC-SID */
 612                               <0x0 0x02c10000 0x0 0x10000>,   /* MC Broadcast*/
 613                               <0x0 0x02c20000 0x0 0x10000>,   /* MC0 */
 614                               <0x0 0x02c30000 0x0 0x10000>,   /* MC1 */
 615                               <0x0 0x02c40000 0x0 0x10000>,   /* MC2 */
 616                               <0x0 0x02c50000 0x0 0x10000>,   /* MC3 */
 617                               <0x0 0x02b80000 0x0 0x10000>,   /* MC4 */
 618                               <0x0 0x02b90000 0x0 0x10000>,   /* MC5 */
 619                               <0x0 0x02ba0000 0x0 0x10000>,   /* MC6 */
 620                               <0x0 0x02bb0000 0x0 0x10000>,   /* MC7 */
 621                               <0x0 0x01700000 0x0 0x10000>,   /* MC8 */
 622                               <0x0 0x01710000 0x0 0x10000>,   /* MC9 */
 623                               <0x0 0x01720000 0x0 0x10000>,   /* MC10 */
 624                               <0x0 0x01730000 0x0 0x10000>,   /* MC11 */
 625                               <0x0 0x01740000 0x0 0x10000>,   /* MC12 */
 626                               <0x0 0x01750000 0x0 0x10000>,   /* MC13 */
 627                               <0x0 0x01760000 0x0 0x10000>,   /* MC14 */
 628                               <0x0 0x01770000 0x0 0x10000>;   /* MC15 */
 629                         reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
 630                                     "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
 631                                     "ch11", "ch12", "ch13", "ch14", "ch15";
 632                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 633                         #interconnect-cells = <1>;
 634                         status = "okay";
 635
 636                         #address-cells = <2>;
 637                         #size-cells = <2>;
 638                         ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
 639                                  <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
 640                                  <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
 641
 642                         /*
 643                          * Bit 39 of addresses passing through the memory
 644                          * controller selects the XBAR format used when memory
 645                          * is accessed. This is used to transparently access
 646                          * memory in the XBAR format used by the discrete GPU
 647                          * (bit 39 set) or Tegra (bit 39 clear).
 648                          *
 649                          * As a consequence, the operating system must ensure
 650                          * that bit 39 is never used implicitly, for example
 651                          * via an I/O virtual address mapping of an IOMMU. If
 652                          * devices require access to the XBAR switch, their
 653                          * drivers must set this bit explicitly.
 654                          *
 655                          * Limit the DMA range for memory clients to [38:0].
 656                          */
 657                         dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
 658
 659                         emc: external-memory-controller@2c60000 {
 660                                 compatible = "nvidia,tegra234-emc";
 661                                 reg = <0x0 0x02c60000 0x0 0x90000>,
 662                                       <0x0 0x01780000 0x0 0x80000>;
 663                                 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 664                                 clocks = <&bpmp TEGRA234_CLK_EMC>;
 665                                 clock-names = "emc";
 666                                 status = "okay";
 667
 668                                 #interconnect-cells = <0>;
 669
 670                                 nvidia,bpmp = <&bpmp>;
 671                         };
 672                 };
 673
 674                 uarta: serial@3100000 {
 675                         compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
 676                         reg = <0x0 0x03100000 0x0 0x10000>;
 677                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 678                         clocks = <&bpmp TEGRA234_CLK_UARTA>;
 679                         resets = <&bpmp TEGRA234_RESET_UARTA>;
 680                         status = "disabled";
 681                 };
 682
 683                 gen1_i2c: i2c@3160000 {
 684                         compatible = "nvidia,tegra194-i2c";
 685                         reg = <0x0 0x3160000 0x0 0x100>;
 686                         status = "disabled";
 687                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 688                         #address-cells = <1>;
 689                         #size-cells = <0>;
 690                         clock-frequency = <400000>;
 691                         clocks = <&bpmp TEGRA234_CLK_I2C1
 692                                   &bpmp TEGRA234_CLK_PLLP_OUT0>;
 693                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
 694                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
 695                         clock-names = "div-clk", "parent";
 696                         resets = <&bpmp TEGRA234_RESET_I2C1>;
 697                         reset-names = "i2c";
 698                         dmas = <&gpcdma 21>, <&gpcdma 21>;
 699                         dma-names = "rx", "tx";
 700                 };
 701
 702                 cam_i2c: i2c@3180000 {
 703                         compatible = "nvidia,tegra194-i2c";
 704                         reg = <0x0 0x3180000 0x0 0x100>;
 705                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 706                         #address-cells = <1>;
 707                         #size-cells = <0>;
 708                         status = "disabled";
 709                         clock-frequency = <400000>;
 710                         clocks = <&bpmp TEGRA234_CLK_I2C3
 711                                 &bpmp TEGRA234_CLK_PLLP_OUT0>;
 712                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
 713                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
 714                         clock-names = "div-clk", "parent";
 715                         resets = <&bpmp TEGRA234_RESET_I2C3>;
 716                         reset-names = "i2c";
 717                         dmas = <&gpcdma 23>, <&gpcdma 23>;
 718                         dma-names = "rx", "tx";
 719                 };
 720
 721                 dp_aux_ch1_i2c: i2c@3190000 {
 722                         compatible = "nvidia,tegra194-i2c";
 723                         reg = <0x0 0x3190000 0x0 0x100>;
 724                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 725                         #address-cells = <1>;
 726                         #size-cells = <0>;
 727                         status = "disabled";
 728                         clock-frequency = <100000>;
 729                         clocks = <&bpmp TEGRA234_CLK_I2C4
 730                                 &bpmp TEGRA234_CLK_PLLP_OUT0>;
 731                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
 732                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
 733                         clock-names = "div-clk", "parent";
 734                         resets = <&bpmp TEGRA234_RESET_I2C4>;
 735                         reset-names = "i2c";
 736                         dmas = <&gpcdma 26>, <&gpcdma 26>;
 737                         dma-names = "rx", "tx";
 738                 };
 739
 740                 dp_aux_ch0_i2c: i2c@31b0000 {
 741                         compatible = "nvidia,tegra194-i2c";
 742                         reg = <0x0 0x31b0000 0x0 0x100>;
 743                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 744                         #address-cells = <1>;
 745                         #size-cells = <0>;
 746                         status = "disabled";
 747                         clock-frequency = <100000>;
 748                         clocks = <&bpmp TEGRA234_CLK_I2C6
 749                                 &bpmp TEGRA234_CLK_PLLP_OUT0>;
 750                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
 751                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
 752                         clock-names = "div-clk", "parent";
 753                         resets = <&bpmp TEGRA234_RESET_I2C6>;
 754                         reset-names = "i2c";
 755                         dmas = <&gpcdma 30>, <&gpcdma 30>;
 756                         dma-names = "rx", "tx";
 757                 };
 758
 759                 dp_aux_ch2_i2c: i2c@31c0000 {
 760                         compatible = "nvidia,tegra194-i2c";
 761                         reg = <0x0 0x31c0000 0x0 0x100>;
 762                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 763                         #address-cells = <1>;
 764                         #size-cells = <0>;
 765                         status = "disabled";
 766                         clock-frequency = <100000>;
 767                         clocks = <&bpmp TEGRA234_CLK_I2C7
 768                                 &bpmp TEGRA234_CLK_PLLP_OUT0>;
 769                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
 770                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
 771                         clock-names = "div-clk", "parent";
 772                         resets = <&bpmp TEGRA234_RESET_I2C7>;
 773                         reset-names = "i2c";
 774                         dmas = <&gpcdma 27>, <&gpcdma 27>;
 775                         dma-names = "rx", "tx";
 776                 };
 777
 778                 uarti: serial@31d0000 {
 779                         compatible = "arm,sbsa-uart";
 780                         reg = <0x0 0x31d0000 0x0 0x10000>;
 781                         interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
 782                         status = "disabled";
 783                 };
 784
 785                 dp_aux_ch3_i2c: i2c@31e0000 {
 786                         compatible = "nvidia,tegra194-i2c";
 787                         reg = <0x0 0x31e0000 0x0 0x100>;
 788                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 789                         #address-cells = <1>;
 790                         #size-cells = <0>;
 791                         status = "disabled";
 792                         clock-frequency = <100000>;
 793                         clocks = <&bpmp TEGRA234_CLK_I2C9
 794                                 &bpmp TEGRA234_CLK_PLLP_OUT0>;
 795                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
 796                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
 797                         clock-names = "div-clk", "parent";
 798                         resets = <&bpmp TEGRA234_RESET_I2C9>;
 799                         reset-names = "i2c";
 800                         dmas = <&gpcdma 31>, <&gpcdma 31>;
 801                         dma-names = "rx", "tx";
 802                 };
 803
 804                 spi@3270000 {
 805                         compatible = "nvidia,tegra234-qspi";
 806                         reg = <0x0 0x3270000 0x0 0x1000>;
 807                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 808                         #address-cells = <1>;
 809                         #size-cells = <0>;
 810                         clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
 811                                  <&bpmp TEGRA234_CLK_QSPI0_PM>;
 812                         clock-names = "qspi", "qspi_out";
 813                         resets = <&bpmp TEGRA234_RESET_QSPI0>;
 814                         status = "disabled";
 815                 };
 816
 817                 pwm1: pwm@3280000 {
 818                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
 819                         reg = <0x0 0x3280000 0x0 0x10000>;
 820                         clocks = <&bpmp TEGRA234_CLK_PWM1>;
 821                         resets = <&bpmp TEGRA234_RESET_PWM1>;
 822                         reset-names = "pwm";
 823                         status = "disabled";
 824                         #pwm-cells = <2>;
 825                 };
 826
 827                 pwm2: pwm@3290000 {
 828                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
 829                         reg = <0x0 0x3290000 0x0 0x10000>;
 830                         clocks = <&bpmp TEGRA234_CLK_PWM2>;
 831                         resets = <&bpmp TEGRA234_RESET_PWM2>;
 832                         reset-names = "pwm";
 833                         status = "disabled";
 834                         #pwm-cells = <2>;
 835                 };
 836
 837                 pwm3: pwm@32a0000 {
 838                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
 839                         reg = <0x0 0x32a0000 0x0 0x10000>;
 840                         clocks = <&bpmp TEGRA234_CLK_PWM3>;
 841                         resets = <&bpmp TEGRA234_RESET_PWM3>;
 842                         reset-names = "pwm";
 843                         status = "disabled";
 844                         #pwm-cells = <2>;
 845                 };
 846
 847                 pwm5: pwm@32c0000 {
 848                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
 849                         reg = <0x0 0x32c0000 0x0 0x10000>;
 850                         clocks = <&bpmp TEGRA234_CLK_PWM5>;
 851                         resets = <&bpmp TEGRA234_RESET_PWM5>;
 852                         reset-names = "pwm";
 853                         status = "disabled";
 854                         #pwm-cells = <2>;
 855                 };
 856
 857                 pwm6: pwm@32d0000 {
 858                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
 859                         reg = <0x0 0x32d0000 0x0 0x10000>;
 860                         clocks = <&bpmp TEGRA234_CLK_PWM6>;
 861                         resets = <&bpmp TEGRA234_RESET_PWM6>;
 862                         reset-names = "pwm";
 863                         status = "disabled";
 864                         #pwm-cells = <2>;
 865                 };
 866
 867                 pwm7: pwm@32e0000 {
 868                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
 869                         reg = <0x0 0x32e0000 0x0 0x10000>;
 870                         clocks = <&bpmp TEGRA234_CLK_PWM7>;
 871                         resets = <&bpmp TEGRA234_RESET_PWM7>;
 872                         reset-names = "pwm";
 873                         status = "disabled";
 874                         #pwm-cells = <2>;
 875                 };
 876
 877                 pwm8: pwm@32f0000 {
 878                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
 879                         reg = <0x0 0x32f0000 0x0 0x10000>;
 880                         clocks = <&bpmp TEGRA234_CLK_PWM8>;
 881                         resets = <&bpmp TEGRA234_RESET_PWM8>;
 882                         reset-names = "pwm";
 883                         status = "disabled";
 884                         #pwm-cells = <2>;
 885                 };
 886
 887                 spi@3300000 {
 888                         compatible = "nvidia,tegra234-qspi";
 889                         reg = <0x0 0x3300000 0x0 0x1000>;
 890                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 891                         #address-cells = <1>;
 892                         #size-cells = <0>;
 893                         clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
 894                                  <&bpmp TEGRA234_CLK_QSPI1_PM>;
 895                         clock-names = "qspi", "qspi_out";
 896                         resets = <&bpmp TEGRA234_RESET_QSPI1>;
 897                         status = "disabled";
 898                 };
 899
 900                 mmc@3400000 {
 901                         compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
 902                         reg = <0x0 0x03400000 0x0 0x20000>;
 903                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 904                         clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
 905                                  <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
 906                         clock-names = "sdhci", "tmclk";
 907                         assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
 908                                           <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
 909                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
 910                                                  <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
 911                         resets = <&bpmp TEGRA234_RESET_SDMMC1>;
 912                         reset-names = "sdhci";
 913                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
 914                                         <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
 915                         interconnect-names = "dma-mem", "write";
 916                         iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
 917                         pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 918                         pinctrl-0 = <&sdmmc1_3v3>;
 919                         pinctrl-1 = <&sdmmc1_1v8>;
 920                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 921                         nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
 922                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 923                         nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 924                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 925                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 926                         nvidia,default-tap = <14>;
 927                         nvidia,default-trim = <0x8>;
 928                         sd-uhs-sdr25;
 929                         sd-uhs-sdr50;
 930                         sd-uhs-ddr50;
 931                         sd-uhs-sdr104;
 932                         status = "disabled";
 933                 };
 934
 935                 mmc@3460000 {
 936                         compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
 937                         reg = <0x0 0x03460000 0x0 0x20000>;
 938                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 939                         clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
 940                                  <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
 941                         clock-names = "sdhci", "tmclk";
 942                         assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
 943                                           <&bpmp TEGRA234_CLK_PLLC4>;
 944                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
 945                         resets = <&bpmp TEGRA234_RESET_SDMMC4>;
 946                         reset-names = "sdhci";
 947                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
 948                                         <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
 949                         interconnect-names = "dma-mem", "write";
 950                         iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>;
 951                         nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
 952                         nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
 953                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
 954                         nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
 955                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
 956                         nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
 957                         nvidia,default-tap = <0x8>;
 958                         nvidia,default-trim = <0x14>;
 959                         nvidia,dqs-trim = <40>;
 960                         supports-cqe;
 961                         status = "disabled";
 962                 };
 963
 964                 hda@3510000 {
 965                         compatible = "nvidia,tegra234-hda";
 966                         reg = <0x0 0x3510000 0x0 0x10000>;
 967                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 968                         clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
 969                                  <&bpmp TEGRA234_CLK_AZA_2XBIT>;
 970                         clock-names = "hda", "hda2codec_2x";
 971                         resets = <&bpmp TEGRA234_RESET_HDA>,
 972                                  <&bpmp TEGRA234_RESET_HDACODEC>;
 973                         reset-names = "hda", "hda2codec_2x";
 974                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
 975                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>,
 976                                         <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>;
 977                         interconnect-names = "dma-mem", "write";
 978                         iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
 979                         status = "disabled";
 980                 };
 981
 982                 xusb_padctl: padctl@3520000 {
 983                         compatible = "nvidia,tegra234-xusb-padctl";
 984                         reg = <0x0 0x03520000 0x0 0x20000>,
 985                               <0x0 0x03540000 0x0 0x10000>;
 986                         reg-names = "padctl", "ao";
 987                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 988
 989                         resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>;
 990                         reset-names = "padctl";
 991
 992                         status = "disabled";
 993
 994                         pads {
 995                                 usb2 {
 996                                         clocks = <&bpmp TEGRA234_CLK_USB2_TRK>;
 997                                         clock-names = "trk";
 998
 999                                         lanes {
1000                                                 usb2-0 {
1001                                                         nvidia,function = "xusb";
1002                                                         status = "disabled";
1003                                                         #phy-cells = <0>;
1004                                                 };
1005
1006                                                 usb2-1 {
1007                                                         nvidia,function = "xusb";
1008                                                         status = "disabled";
1009                                                         #phy-cells = <0>;
1010                                                 };
1011
1012                                                 usb2-2 {
1013                                                         nvidia,function = "xusb";
1014                                                         status = "disabled";
1015                                                         #phy-cells = <0>;
1016                                                 };
1017
1018                                                 usb2-3 {
1019                                                         nvidia,function = "xusb";
1020                                                         status = "disabled";
1021                                                         #phy-cells = <0>;
1022                                                 };
1023                                         };
1024                                 };
1025
1026                                 usb3 {
1027                                         lanes {
1028                                                 usb3-0 {
1029                                                         nvidia,function = "xusb";
1030                                                         status = "disabled";
1031                                                         #phy-cells = <0>;
1032                                                 };
1033
1034                                                 usb3-1 {
1035                                                         nvidia,function = "xusb";
1036                                                         status = "disabled";
1037                                                         #phy-cells = <0>;
1038                                                 };
1039
1040                                                 usb3-2 {
1041                                                         nvidia,function = "xusb";
1042                                                         status = "disabled";
1043                                                         #phy-cells = <0>;
1044                                                 };
1045
1046                                                 usb3-3 {
1047                                                         nvidia,function = "xusb";
1048                                                         status = "disabled";
1049                                                         #phy-cells = <0>;
1050                                                 };
1051                                         };
1052                                 };
1053                         };
1054
1055                         ports {
1056                                 usb2-0 {
1057                                         status = "disabled";
1058                                 };
1059
1060                                 usb2-1 {
1061                                         status = "disabled";
1062                                 };
1063
1064                                 usb2-2 {
1065                                         status = "disabled";
1066                                 };
1067
1068                                 usb2-3 {
1069                                         status = "disabled";
1070                                 };
1071
1072                                 usb3-0 {
1073                                         status = "disabled";
1074                                 };
1075
1076                                 usb3-1 {
1077                                         status = "disabled";
1078                                 };
1079
1080                                 usb3-2 {
1081                                         status = "disabled";
1082                                 };
1083
1084                                 usb3-3 {
1085                                         status = "disabled";
1086                                 };
1087                         };
1088                 };
1089
1090                 usb@3550000 {
1091                         compatible = "nvidia,tegra234-xudc";
1092                         reg = <0x0 0x03550000 0x0 0x8000>,
1093                               <0x0 0x03558000 0x0 0x8000>;
1094                         reg-names = "base", "fpci";
1095                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1096                         clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>,
1097                                  <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
1098                                  <&bpmp TEGRA234_CLK_XUSB_SS>,
1099                                  <&bpmp TEGRA234_CLK_XUSB_FS>;
1100                         clock-names = "dev", "ss", "ss_src", "fs_src";
1101                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>,
1102                                         <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>;
1103                         interconnect-names = "dma-mem", "write";
1104                         iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>;
1105                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
1106                                         <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
1107                         power-domain-names = "dev", "ss";
1108                         nvidia,xusb-padctl = <&xusb_padctl>;
1109                         dma-coherent;
1110                         status = "disabled";
1111                 };
1112
1113                 usb@3610000 {
1114                         compatible = "nvidia,tegra234-xusb";
1115                         reg = <0x0 0x03610000 0x0 0x40000>,
1116                               <0x0 0x03600000 0x0 0x10000>,
1117                               <0x0 0x03650000 0x0 0x10000>;
1118                         reg-names = "hcd", "fpci", "bar2";
1119
1120                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1121                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1122
1123                         clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
1124                                  <&bpmp TEGRA234_CLK_XUSB_FALCON>,
1125                                  <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
1126                                  <&bpmp TEGRA234_CLK_XUSB_SS>,
1127                                  <&bpmp TEGRA234_CLK_CLK_M>,
1128                                  <&bpmp TEGRA234_CLK_XUSB_FS>,
1129                                  <&bpmp TEGRA234_CLK_UTMIP_PLL>,
1130                                  <&bpmp TEGRA234_CLK_CLK_M>,
1131                                  <&bpmp TEGRA234_CLK_PLLE>;
1132                         clock-names = "xusb_host", "xusb_falcon_src",
1133                                       "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1134                                       "xusb_fs_src", "pll_u_480m", "clk_m",
1135                                       "pll_e";
1136                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1137                                         <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1138                         interconnect-names = "dma-mem", "write";
1139                         iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>;
1140
1141                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
1142                                         <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
1143                         power-domain-names = "xusb_host", "xusb_ss";
1144
1145                         nvidia,xusb-padctl = <&xusb_padctl>;
1146                         dma-coherent;
1147                         status = "disabled";
1148                 };
1149
1150                 fuse@3810000 {
1151                         compatible = "nvidia,tegra234-efuse";
1152                         reg = <0x0 0x03810000 0x0 0x10000>;
1153                         clocks = <&bpmp TEGRA234_CLK_FUSE>;
1154                         clock-names = "fuse";
1155                 };
1156
1157                 hsp_top0: hsp@3c00000 {
1158                         compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
1159                         reg = <0x0 0x03c00000 0x0 0xa0000>;
1160                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1161                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1162                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1163                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1164                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1165                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1166                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1167                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1168                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1169                         interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1170                                           "shared3", "shared4", "shared5", "shared6",
1171                                           "shared7";
1172                         #mbox-cells = <2>;
1173                 };
1174
1175                 p2u_hsio_0: phy@3e00000 {
1176                         compatible = "nvidia,tegra234-p2u";
1177                         reg = <0x0 0x03e00000 0x0 0x10000>;
1178                         reg-names = "ctl";
1179
1180                         #phy-cells = <0>;
1181                 };
1182
1183                 p2u_hsio_1: phy@3e10000 {
1184                         compatible = "nvidia,tegra234-p2u";
1185                         reg = <0x0 0x03e10000 0x0 0x10000>;
1186                         reg-names = "ctl";
1187
1188                         #phy-cells = <0>;
1189                 };
1190
1191                 p2u_hsio_2: phy@3e20000 {
1192                         compatible = "nvidia,tegra234-p2u";
1193                         reg = <0x0 0x03e20000 0x0 0x10000>;
1194                         reg-names = "ctl";
1195
1196                         #phy-cells = <0>;
1197                 };
1198
1199                 p2u_hsio_3: phy@3e30000 {
1200                         compatible = "nvidia,tegra234-p2u";
1201                         reg = <0x0 0x03e30000 0x0 0x10000>;
1202                         reg-names = "ctl";
1203
1204                         #phy-cells = <0>;
1205                 };
1206
1207                 p2u_hsio_4: phy@3e40000 {
1208                         compatible = "nvidia,tegra234-p2u";
1209                         reg = <0x0 0x03e40000 0x0 0x10000>;
1210                         reg-names = "ctl";
1211
1212                         #phy-cells = <0>;
1213                 };
1214
1215                 p2u_hsio_5: phy@3e50000 {
1216                         compatible = "nvidia,tegra234-p2u";
1217                         reg = <0x0 0x03e50000 0x0 0x10000>;
1218                         reg-names = "ctl";
1219
1220                         #phy-cells = <0>;
1221                 };
1222
1223                 p2u_hsio_6: phy@3e60000 {
1224                         compatible = "nvidia,tegra234-p2u";
1225                         reg = <0x0 0x03e60000 0x0 0x10000>;
1226                         reg-names = "ctl";
1227
1228                         #phy-cells = <0>;
1229                 };
1230
1231                 p2u_hsio_7: phy@3e70000 {
1232                         compatible = "nvidia,tegra234-p2u";
1233                         reg = <0x0 0x03e70000 0x0 0x10000>;
1234                         reg-names = "ctl";
1235
1236                         #phy-cells = <0>;
1237                 };
1238
1239                 p2u_nvhs_0: phy@3e90000 {
1240                         compatible = "nvidia,tegra234-p2u";
1241                         reg = <0x0 0x03e90000 0x0 0x10000>;
1242                         reg-names = "ctl";
1243
1244                         #phy-cells = <0>;
1245                 };
1246
1247                 p2u_nvhs_1: phy@3ea0000 {
1248                         compatible = "nvidia,tegra234-p2u";
1249                         reg = <0x0 0x03ea0000 0x0 0x10000>;
1250                         reg-names = "ctl";
1251
1252                         #phy-cells = <0>;
1253                 };
1254
1255                 p2u_nvhs_2: phy@3eb0000 {
1256                         compatible = "nvidia,tegra234-p2u";
1257                         reg = <0x0 0x03eb0000 0x0 0x10000>;
1258                         reg-names = "ctl";
1259
1260                         #phy-cells = <0>;
1261                 };
1262
1263                 p2u_nvhs_3: phy@3ec0000 {
1264                         compatible = "nvidia,tegra234-p2u";
1265                         reg = <0x0 0x03ec0000 0x0 0x10000>;
1266                         reg-names = "ctl";
1267
1268                         #phy-cells = <0>;
1269                 };
1270
1271                 p2u_nvhs_4: phy@3ed0000 {
1272                         compatible = "nvidia,tegra234-p2u";
1273                         reg = <0x0 0x03ed0000 0x0 0x10000>;
1274                         reg-names = "ctl";
1275
1276                         #phy-cells = <0>;
1277                 };
1278
1279                 p2u_nvhs_5: phy@3ee0000 {
1280                         compatible = "nvidia,tegra234-p2u";
1281                         reg = <0x0 0x03ee0000 0x0 0x10000>;
1282                         reg-names = "ctl";
1283
1284                         #phy-cells = <0>;
1285                 };
1286
1287                 p2u_nvhs_6: phy@3ef0000 {
1288                         compatible = "nvidia,tegra234-p2u";
1289                         reg = <0x0 0x03ef0000 0x0 0x10000>;
1290                         reg-names = "ctl";
1291
1292                         #phy-cells = <0>;
1293                 };
1294
1295                 p2u_nvhs_7: phy@3f00000 {
1296                         compatible = "nvidia,tegra234-p2u";
1297                         reg = <0x0 0x03f00000 0x0 0x10000>;
1298                         reg-names = "ctl";
1299
1300                         #phy-cells = <0>;
1301                 };
1302
1303                 p2u_gbe_0: phy@3f20000 {
1304                         compatible = "nvidia,tegra234-p2u";
1305                         reg = <0x0 0x03f20000 0x0 0x10000>;
1306                         reg-names = "ctl";
1307
1308                         #phy-cells = <0>;
1309                 };
1310
1311                 p2u_gbe_1: phy@3f30000 {
1312                         compatible = "nvidia,tegra234-p2u";
1313                         reg = <0x0 0x03f30000 0x0 0x10000>;
1314                         reg-names = "ctl";
1315
1316                         #phy-cells = <0>;
1317                 };
1318
1319                 p2u_gbe_2: phy@3f40000 {
1320                         compatible = "nvidia,tegra234-p2u";
1321                         reg = <0x0 0x03f40000 0x0 0x10000>;
1322                         reg-names = "ctl";
1323
1324                         #phy-cells = <0>;
1325                 };
1326
1327                 p2u_gbe_3: phy@3f50000 {
1328                         compatible = "nvidia,tegra234-p2u";
1329                         reg = <0x0 0x03f50000 0x0 0x10000>;
1330                         reg-names = "ctl";
1331
1332                         #phy-cells = <0>;
1333                 };
1334
1335                 p2u_gbe_4: phy@3f60000 {
1336                         compatible = "nvidia,tegra234-p2u";
1337                         reg = <0x0 0x03f60000 0x0 0x10000>;
1338                         reg-names = "ctl";
1339
1340                         #phy-cells = <0>;
1341                 };
1342
1343                 p2u_gbe_5: phy@3f70000 {
1344                         compatible = "nvidia,tegra234-p2u";
1345                         reg = <0x0 0x03f70000 0x0 0x10000>;
1346                         reg-names = "ctl";
1347
1348                         #phy-cells = <0>;
1349                 };
1350
1351                 p2u_gbe_6: phy@3f80000 {
1352                         compatible = "nvidia,tegra234-p2u";
1353                         reg = <0x0 0x03f80000 0x0 0x10000>;
1354                         reg-names = "ctl";
1355
1356                         #phy-cells = <0>;
1357                 };
1358
1359                 p2u_gbe_7: phy@3f90000 {
1360                         compatible = "nvidia,tegra234-p2u";
1361                         reg = <0x0 0x03f90000 0x0 0x10000>;
1362                         reg-names = "ctl";
1363
1364                         #phy-cells = <0>;
1365                 };
1366
1367                 ethernet@6800000 {
1368                         compatible = "nvidia,tegra234-mgbe";
1369                         reg = <0x0 0x06800000 0x0 0x10000>,
1370                               <0x0 0x06810000 0x0 0x10000>,
1371                               <0x0 0x068a0000 0x0 0x10000>;
1372                         reg-names = "hypervisor", "mac", "xpcs";
1373                         interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
1374                         interrupt-names = "common";
1375                         clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
1376                                  <&bpmp TEGRA234_CLK_MGBE0_MAC>,
1377                                  <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
1378                                  <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
1379                                  <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
1380                                  <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
1381                                  <&bpmp TEGRA234_CLK_MGBE0_TX>,
1382                                  <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
1383                                  <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
1384                                  <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
1385                                  <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
1386                                  <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
1387                         clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1388                                       "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1389                                       "rx-pcs", "tx-pcs";
1390                         resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
1391                                  <&bpmp TEGRA234_RESET_MGBE0_PCS>;
1392                         reset-names = "mac", "pcs";
1393                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
1394                                         <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
1395                         interconnect-names = "dma-mem", "write";
1396                         iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
1397                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
1398                         status = "disabled";
1399                 };
1400
1401                 ethernet@6900000 {
1402                         compatible = "nvidia,tegra234-mgbe";
1403                         reg = <0x0 0x06900000 0x0 0x10000>,
1404                               <0x0 0x06910000 0x0 0x10000>,
1405                               <0x0 0x069a0000 0x0 0x10000>;
1406                         reg-names = "hypervisor", "mac", "xpcs";
1407                         interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
1408                         interrupt-names = "common";
1409                         clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
1410                                  <&bpmp TEGRA234_CLK_MGBE1_MAC>,
1411                                  <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
1412                                  <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
1413                                  <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
1414                                  <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
1415                                  <&bpmp TEGRA234_CLK_MGBE1_TX>,
1416                                  <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
1417                                  <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
1418                                  <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
1419                                  <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
1420                                  <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
1421                         clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1422                                       "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1423                                       "rx-pcs", "tx-pcs";
1424                         resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
1425                                  <&bpmp TEGRA234_RESET_MGBE1_PCS>;
1426                         reset-names = "mac", "pcs";
1427                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
1428                                         <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
1429                         interconnect-names = "dma-mem", "write";
1430                         iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
1431                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
1432                         status = "disabled";
1433                 };
1434
1435                 ethernet@6a00000 {
1436                         compatible = "nvidia,tegra234-mgbe";
1437                         reg = <0x0 0x06a00000 0x0 0x10000>,
1438                               <0x0 0x06a10000 0x0 0x10000>,
1439                               <0x0 0x06aa0000 0x0 0x10000>;
1440                         reg-names = "hypervisor", "mac", "xpcs";
1441                         interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
1442                         interrupt-names = "common";
1443                         clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
1444                                  <&bpmp TEGRA234_CLK_MGBE2_MAC>,
1445                                  <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
1446                                  <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
1447                                  <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
1448                                  <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
1449                                  <&bpmp TEGRA234_CLK_MGBE2_TX>,
1450                                  <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
1451                                  <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
1452                                  <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
1453                                  <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
1454                                  <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
1455                         clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1456                                       "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1457                                       "rx-pcs", "tx-pcs";
1458                         resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
1459                                  <&bpmp TEGRA234_RESET_MGBE2_PCS>;
1460                         reset-names = "mac", "pcs";
1461                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
1462                                         <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
1463                         interconnect-names = "dma-mem", "write";
1464                         iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
1465                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
1466                         status = "disabled";
1467                 };
1468
1469                 ethernet@6b00000 {
1470                         compatible = "nvidia,tegra234-mgbe";
1471                         reg = <0x0 0x06b00000 0x0 0x10000>,
1472                               <0x0 0x06b10000 0x0 0x10000>,
1473                               <0x0 0x06ba0000 0x0 0x10000>;
1474                         reg-names = "hypervisor", "mac", "xpcs";
1475                         interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1476                         interrupt-names = "common";
1477                         clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
1478                                  <&bpmp TEGRA234_CLK_MGBE3_MAC>,
1479                                  <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
1480                                  <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
1481                                  <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
1482                                  <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
1483                                  <&bpmp TEGRA234_CLK_MGBE3_TX>,
1484                                  <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
1485                                  <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
1486                                  <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
1487                                  <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
1488                                  <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
1489                         clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1490                                       "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1491                                       "rx-pcs", "tx-pcs";
1492                         resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
1493                                  <&bpmp TEGRA234_RESET_MGBE3_PCS>;
1494                         reset-names = "mac", "pcs";
1495                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
1496                                         <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
1497                         interconnect-names = "dma-mem", "write";
1498                         iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
1499                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1500                         status = "disabled";
1501                 };
1502
1503                 smmu_niso1: iommu@8000000 {
1504                         compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1505                         reg = <0x0 0x8000000 0x0 0x1000000>,
1506                               <0x0 0x7000000 0x0 0x1000000>;
1507                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1508                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
1509                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1510                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
1511                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1512                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1513                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1514                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1515                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1516                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1517                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1518                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1519                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1520                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1521                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1522                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1523                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1524                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1525                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1526                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1527                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1528                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1529                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1530                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1531                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1532                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1533                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1534                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1535                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1536                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1537                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1538                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1539                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1540                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1541                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1542                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1543                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1544                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1545                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1546                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1547                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1548                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1549                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1550                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1551                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1552                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1553                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1554                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1555                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1556                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1557                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1558                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1559                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1560                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1561                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1562                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1563                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1564                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1565                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1566                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1567                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1568                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1569                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1570                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1571                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1572                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1573                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1574                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1575                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1576                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1577                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1578                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1579                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1580                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1581                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1582                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1583                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1584                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1585                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1586                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1587                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1588                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1589                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1590                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1591                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1592                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1593                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1594                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1595                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1596                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1597                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1598                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1599                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1600                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1601                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1602                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1603                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1604                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1605                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1606                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1607                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1608                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1609                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1610                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1611                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1612                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1613                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1614                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1615                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1616                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1617                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1618                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1619                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1620                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1621                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1622                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1623                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1624                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1625                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1626                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1627                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1628                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1629                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1630                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1631                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1632                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1633                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1634                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1635                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1636                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1637                         stream-match-mask = <0x7f80>;
1638                         #global-interrupts = <2>;
1639                         #iommu-cells = <1>;
1640
1641                         nvidia,memory-controller = <&mc>;
1642                         status = "okay";
1643                 };
1644
1645                 sce-fabric@b600000 {
1646                         compatible = "nvidia,tegra234-sce-fabric";
1647                         reg = <0x0 0xb600000 0x0 0x40000>;
1648                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
1649                         status = "okay";
1650                 };
1651
1652                 rce-fabric@be00000 {
1653                         compatible = "nvidia,tegra234-rce-fabric";
1654                         reg = <0x0 0xbe00000 0x0 0x40000>;
1655                         interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1656                         status = "okay";
1657                 };
1658
1659                 hsp_aon: hsp@c150000 {
1660                         compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
1661                         reg = <0x0 0x0c150000 0x0 0x90000>;
1662                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1663                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1664                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1665                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1666                         /*
1667                          * Shared interrupt 0 is routed only to AON/SPE, so
1668                          * we only have 4 shared interrupts for the CCPLEX.
1669                          */
1670                         interrupt-names = "shared1", "shared2", "shared3", "shared4";
1671                         #mbox-cells = <2>;
1672                 };
1673
1674                 gen2_i2c: i2c@c240000 {
1675                         compatible = "nvidia,tegra194-i2c";
1676                         reg = <0x0 0xc240000 0x0 0x100>;
1677                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1678                         #address-cells = <1>;
1679                         #size-cells = <0>;
1680                         status = "disabled";
1681                         clock-frequency = <100000>;
1682                         clocks = <&bpmp TEGRA234_CLK_I2C2
1683                                 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1684                         clock-names = "div-clk", "parent";
1685                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
1686                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1687                         resets = <&bpmp TEGRA234_RESET_I2C2>;
1688                         reset-names = "i2c";
1689                         dmas = <&gpcdma 22>, <&gpcdma 22>;
1690                         dma-names = "rx", "tx";
1691                 };
1692
1693                 gen8_i2c: i2c@c250000 {
1694                         compatible = "nvidia,tegra194-i2c";
1695                         reg = <0x0 0xc250000 0x0 0x100>;
1696                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1697                         #address-cells = <1>;
1698                         #size-cells = <0>;
1699                         status = "disabled";
1700                         clock-frequency = <400000>;
1701                         clocks = <&bpmp TEGRA234_CLK_I2C8
1702                                 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1703                         clock-names = "div-clk", "parent";
1704                         assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
1705                         assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1706                         resets = <&bpmp TEGRA234_RESET_I2C8>;
1707                         reset-names = "i2c";
1708                         dmas = <&gpcdma 0>, <&gpcdma 0>;
1709                         dma-names = "rx", "tx";
1710                 };
1711
1712                 rtc@c2a0000 {
1713                         compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
1714                         reg = <0x0 0x0c2a0000 0x0 0x10000>;
1715                         interrupt-parent = <&pmc>;
1716                         interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1717                         clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
1718                         clock-names = "rtc";
1719                         status = "disabled";
1720                 };
1721
1722                 gpio_aon: gpio@c2f0000 {
1723                         compatible = "nvidia,tegra234-gpio-aon";
1724                         reg-names = "security", "gpio";
1725                         reg = <0x0 0x0c2f0000 0x0 0x1000>,
1726                               <0x0 0x0c2f1000 0x0 0x1000>;
1727                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1728                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1729                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1730                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1731                         #interrupt-cells = <2>;
1732                         interrupt-controller;
1733                         #gpio-cells = <2>;
1734                         gpio-controller;
1735                 };
1736
1737                 pwm4: pwm@c340000 {
1738                         compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
1739                         reg = <0x0 0xc340000 0x0 0x10000>;
1740                         clocks = <&bpmp TEGRA234_CLK_PWM4>;
1741                         resets = <&bpmp TEGRA234_RESET_PWM4>;
1742                         reset-names = "pwm";
1743                         status = "disabled";
1744                         #pwm-cells = <2>;
1745                 };
1746
1747                 pmc: pmc@c360000 {
1748                         compatible = "nvidia,tegra234-pmc";
1749                         reg = <0x0 0x0c360000 0x0 0x10000>,
1750                               <0x0 0x0c370000 0x0 0x10000>,
1751                               <0x0 0x0c380000 0x0 0x10000>,
1752                               <0x0 0x0c390000 0x0 0x10000>,
1753                               <0x0 0x0c3a0000 0x0 0x10000>;
1754                         reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1755
1756                         #interrupt-cells = <2>;
1757                         interrupt-controller;
1758
1759                         sdmmc1_1v8: sdmmc1-1v8 {
1760                                 pins = "sdmmc1-hv";
1761                                 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1762                         };
1763
1764                         sdmmc1_3v3: sdmmc1-3v3 {
1765                                 pins = "sdmmc1-hv";
1766                                 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1767                         };
1768
1769                         sdmmc3_1v8: sdmmc3-1v8 {
1770                                 pins = "sdmmc3-hv";
1771                                 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1772                         };
1773
1774                         sdmmc3_3v3: sdmmc3-3v3 {
1775                                 pins = "sdmmc3-hv";
1776                                 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1777                         };
1778                 };
1779
1780                 aon-fabric@c600000 {
1781                         compatible = "nvidia,tegra234-aon-fabric";
1782                         reg = <0x0 0xc600000 0x0 0x40000>;
1783                         interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1784                         status = "okay";
1785                 };
1786
1787                 bpmp-fabric@d600000 {
1788                         compatible = "nvidia,tegra234-bpmp-fabric";
1789                         reg = <0x0 0xd600000 0x0 0x40000>;
1790                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1791                         status = "okay";
1792                 };
1793
1794                 dce-fabric@de00000 {
1795                         compatible = "nvidia,tegra234-sce-fabric";
1796                         reg = <0x0 0xde00000 0x0 0x40000>;
1797                         interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
1798                         status = "okay";
1799                 };
1800
1801                 ccplex@e000000 {
1802                         compatible = "nvidia,tegra234-ccplex-cluster";
1803                         reg = <0x0 0x0e000000 0x0 0x5ffff>;
1804                         nvidia,bpmp = <&bpmp>;
1805                         status = "okay";
1806                 };
1807
1808                 gic: interrupt-controller@f400000 {
1809                         compatible = "arm,gic-v3";
1810                         reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
1811                               <0x0 0x0f440000 0x0 0x200000>; /* GICR */
1812                         interrupt-parent = <&gic>;
1813                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1814
1815                         #redistributor-regions = <1>;
1816                         #interrupt-cells = <3>;
1817                         interrupt-controller;
1818                 };
1819
1820                 smmu_iso: iommu@10000000 {
1821                         compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1822                         reg = <0x0 0x10000000 0x0 0x1000000>;
1823                         interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1824                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1825                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1826                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1827                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1828                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1829                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1830                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1831                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1832                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1833                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1834                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1835                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1836                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1837                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1838                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1839                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1840                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1841                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1842                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1843                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1844                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1845                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1846                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1847                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1848                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1849                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1850                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1851                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1852                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1853                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1854                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1855                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1856                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1857                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1858                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1859                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1860                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1861                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1862                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1863                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1864                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1865                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1866                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1867                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1868                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1869                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1870                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1871                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1872                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1873                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1874                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1875                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1876                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1877                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1878                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1879                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1880                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1881                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1882                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1883                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1884                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1885                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1886                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1887                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1888                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1889                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1890                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1891                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1892                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1893                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1894                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1895                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1896                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1897                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1898                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1899                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1900                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1901                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1902                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1903                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1904                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1905                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1906                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1907                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1908                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1909                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1910                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1911                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1912                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1913                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1914                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1915                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1916                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1917                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1918                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1919                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1920                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1921                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1922                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1923                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1924                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1925                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1926                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1927                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1928                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1929                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1930                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1931                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1932                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1933                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1934                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1935                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1936                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1937                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1938                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1939                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1940                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1941                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1942                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1943                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1944                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1945                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1946                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1947                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1948                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1949                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1950                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1951                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1952                         stream-match-mask = <0x7f80>;
1953                         #global-interrupts = <1>;
1954                         #iommu-cells = <1>;
1955
1956                         nvidia,memory-controller = <&mc>;
1957                         status = "okay";
1958                 };
1959
1960                 smmu_niso0: iommu@12000000 {
1961                         compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1962                         reg = <0x0 0x12000000 0x0 0x1000000>,
1963                               <0x0 0x11000000 0x0 0x1000000>;
1964                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1965                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1966                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1967                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1968                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1969                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1970                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1971                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1972                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1973                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1974                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1975                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1976                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1977                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1978                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1979                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1980                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1981                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1982                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1983                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1984                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1985                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1986                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1987                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1988                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1989                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1990                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1991                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1992                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1993                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1994                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1995                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1996                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1997                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1998                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1999                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2000                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2001                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2002                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2003                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2004                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2005                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2006                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2007                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2008                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2009                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2010                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2011                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2012                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2013                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2014                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2015                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2016                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2017                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2018                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2019                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2020                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2021                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2022                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2023                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2024                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2025                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2026                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2027                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2028                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2029                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2030                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2031                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2032                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2033                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2034                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2035                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2036                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2037                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2038                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2039                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2040                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2041                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2042                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2043                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2044                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2045                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2046                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2047                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2048                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2049                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2050                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2051                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2052                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2053                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2054                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2055                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2056                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2057                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2058                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2059                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2060                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2061                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2062                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2063                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2064                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2065                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2066                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2067                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2068                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2069                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2070                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2071                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2072                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2073                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2074                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2075                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2076                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2077                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2078                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2079                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2080                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2081                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2082                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2083                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2084                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2085                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2086                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2087                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2088                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2089                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2090                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2091                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2092                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2093                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2094                         stream-match-mask = <0x7f80>;
2095                         #global-interrupts = <2>;
2096                         #iommu-cells = <1>;
2097
2098                         nvidia,memory-controller = <&mc>;
2099                         status = "okay";
2100                 };
2101
2102                 cbb-fabric@13a00000 {
2103                         compatible = "nvidia,tegra234-cbb-fabric";
2104                         reg = <0x0 0x13a00000 0x0 0x400000>;
2105                         interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
2106                         status = "okay";
2107                 };
2108
2109                 host1x@13e00000 {
2110                         compatible = "nvidia,tegra234-host1x";
2111                         reg = <0x0 0x13e00000 0x0 0x10000>,
2112                               <0x0 0x13e10000 0x0 0x10000>,
2113                               <0x0 0x13e40000 0x0 0x10000>;
2114                         reg-names = "common", "hypervisor", "vm";
2115                         interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
2116                                      <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
2117                                      <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
2118                                      <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
2119                                      <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
2120                                      <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
2121                                      <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
2122                                      <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
2123                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2124                         interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
2125                                           "syncpt5", "syncpt6", "syncpt7", "host1x";
2126                         clocks = <&bpmp TEGRA234_CLK_HOST1X>;
2127                         clock-names = "host1x";
2128
2129                         #address-cells = <2>;
2130                         #size-cells = <2>;
2131                         ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>;
2132
2133                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>;
2134                         interconnect-names = "dma-mem";
2135                         iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
2136                         dma-coherent;
2137
2138                         /* Context isolation domains */
2139                         iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
2140                                     <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
2141                                     <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
2142                                     <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
2143                                     <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
2144                                     <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
2145                                     <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
2146                                     <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
2147                                     <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
2148                                     <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
2149                                     <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
2150                                     <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
2151                                     <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
2152                                     <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
2153                                     <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
2154                                     <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
2155
2156                         vic@15340000 {
2157                                 compatible = "nvidia,tegra234-vic";
2158                                 reg = <0x0 0x15340000 0x0 0x00040000>;
2159                                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2160                                 clocks = <&bpmp TEGRA234_CLK_VIC>;
2161                                 clock-names = "vic";
2162                                 resets = <&bpmp TEGRA234_RESET_VIC>;
2163                                 reset-names = "vic";
2164
2165                                 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
2166                                 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>,
2167                                                 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>;
2168                                 interconnect-names = "dma-mem", "write";
2169                                 iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
2170                                 dma-coherent;
2171                         };
2172
2173                         nvdec@15480000 {
2174                                 compatible = "nvidia,tegra234-nvdec";
2175                                 reg = <0x0 0x15480000 0x0 0x00040000>;
2176                                 clocks = <&bpmp TEGRA234_CLK_NVDEC>,
2177                                          <&bpmp TEGRA234_CLK_FUSE>,
2178                                          <&bpmp TEGRA234_CLK_TSEC_PKA>;
2179                                 clock-names = "nvdec", "fuse", "tsec_pka";
2180                                 resets = <&bpmp TEGRA234_RESET_NVDEC>;
2181                                 reset-names = "nvdec";
2182                                 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
2183                                 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
2184                                                 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
2185                                 interconnect-names = "dma-mem", "write";
2186                                 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
2187                                 dma-coherent;
2188
2189                                 nvidia,memory-controller = <&mc>;
2190
2191                                 /*
2192                                  * Placeholder values that firmware needs to update with the real
2193                                  * offsets parsed from the microcode headers.
2194                                  */
2195                                 nvidia,bl-manifest-offset = <0>;
2196                                 nvidia,bl-data-offset = <0>;
2197                                 nvidia,bl-code-offset = <0>;
2198                                 nvidia,os-manifest-offset = <0>;
2199                                 nvidia,os-data-offset = <0>;
2200                                 nvidia,os-code-offset = <0>;
2201
2202                                 /*
2203                                  * Firmware needs to set this to "okay" once the above values have
2204                                  * been updated.
2205                                  */
2206                                 status = "disabled";
2207                         };
2208                 };
2209
2210                 pcie@140a0000 {
2211                         compatible = "nvidia,tegra234-pcie";
2212                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
2213                         reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K)      */
2214                               <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
2215                               <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2216                               <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2217                               <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2218                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2219
2220                         #address-cells = <3>;
2221                         #size-cells = <2>;
2222                         device_type = "pci";
2223                         num-lanes = <4>;
2224                         num-viewport = <8>;
2225                         linux,pci-domain = <8>;
2226
2227                         clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
2228                         clock-names = "core";
2229
2230                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
2231                                  <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
2232                         reset-names = "apb", "core";
2233
2234                         interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2235                                      <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2236                         interrupt-names = "intr", "msi";
2237
2238                         #interrupt-cells = <1>;
2239                         interrupt-map-mask = <0 0 0 0>;
2240                         interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
2241
2242                         nvidia,bpmp = <&bpmp 8>;
2243
2244                         nvidia,aspm-cmrt-us = <60>;
2245                         nvidia,aspm-pwr-on-t-us = <20>;
2246                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2247
2248                         bus-range = <0x0 0xff>;
2249
2250                         ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2251                                  <0x02000000 0x0  0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2252                                  <0x01000000 0x0  0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2253
2254                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>,
2255                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>;
2256                         interconnect-names = "dma-mem", "write";
2257                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
2258                         iommu-map-mask = <0x0>;
2259                         dma-coherent;
2260
2261                         status = "disabled";
2262                 };
2263
2264                 pcie@140c0000 {
2265                         compatible = "nvidia,tegra234-pcie";
2266                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
2267                         reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K)      */
2268                               <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
2269                               <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2270                               <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2271                               <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2272                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2273
2274                         #address-cells = <3>;
2275                         #size-cells = <2>;
2276                         device_type = "pci";
2277                         num-lanes = <4>;
2278                         num-viewport = <8>;
2279                         linux,pci-domain = <9>;
2280
2281                         clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
2282                         clock-names = "core";
2283
2284                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
2285                                  <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
2286                         reset-names = "apb", "core";
2287
2288                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2289                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2290                         interrupt-names = "intr", "msi";
2291
2292                         #interrupt-cells = <1>;
2293                         interrupt-map-mask = <0 0 0 0>;
2294                         interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2295
2296                         nvidia,bpmp = <&bpmp 9>;
2297
2298                         nvidia,aspm-cmrt-us = <60>;
2299                         nvidia,aspm-pwr-on-t-us = <20>;
2300                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2301
2302                         bus-range = <0x0 0xff>;
2303
2304                         ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */
2305                                  <0x02000000 0x0  0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2306                                  <0x01000000 0x0  0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2307
2308                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>,
2309                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>;
2310                         interconnect-names = "dma-mem", "write";
2311                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
2312                         iommu-map-mask = <0x0>;
2313                         dma-coherent;
2314
2315                         status = "disabled";
2316                 };
2317
2318                 pcie@140e0000 {
2319                         compatible = "nvidia,tegra234-pcie";
2320                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2321                         reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K)      */
2322                               <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
2323                               <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2324                               <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2325                               <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2326                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2327
2328                         #address-cells = <3>;
2329                         #size-cells = <2>;
2330                         device_type = "pci";
2331                         num-lanes = <4>;
2332                         num-viewport = <8>;
2333                         linux,pci-domain = <10>;
2334
2335                         clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2336                         clock-names = "core";
2337
2338                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2339                                  <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2340                         reset-names = "apb", "core";
2341
2342                         interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2343                                      <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2344                         interrupt-names = "intr", "msi";
2345
2346                         #interrupt-cells = <1>;
2347                         interrupt-map-mask = <0 0 0 0>;
2348                         interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2349
2350                         nvidia,bpmp = <&bpmp 10>;
2351
2352                         nvidia,aspm-cmrt-us = <60>;
2353                         nvidia,aspm-pwr-on-t-us = <20>;
2354                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2355
2356                         bus-range = <0x0 0xff>;
2357
2358                         ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2359                                  <0x02000000 0x0  0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2360                                  <0x01000000 0x0  0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2361
2362                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2363                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2364                         interconnect-names = "dma-mem", "write";
2365                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2366                         iommu-map-mask = <0x0>;
2367                         dma-coherent;
2368
2369                         status = "disabled";
2370                 };
2371
2372                 pcie-ep@140e0000 {
2373                         compatible = "nvidia,tegra234-pcie-ep";
2374                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2375                         reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K)      */
2376                               <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2377                               <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K)           */
2378                               <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G)        */
2379                         reg-names = "appl", "atu_dma", "dbi", "addr_space";
2380
2381                         num-lanes = <4>;
2382
2383                         clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2384                         clock-names = "core";
2385
2386                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2387                                  <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2388                         reset-names = "apb", "core";
2389
2390                         interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2391                         interrupt-names = "intr";
2392
2393                         nvidia,bpmp = <&bpmp 10>;
2394
2395                         nvidia,enable-ext-refclk;
2396                         nvidia,aspm-cmrt-us = <60>;
2397                         nvidia,aspm-pwr-on-t-us = <20>;
2398                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2399
2400                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2401                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2402                         interconnect-names = "dma-mem", "write";
2403                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2404                         iommu-map-mask = <0x0>;
2405                         dma-coherent;
2406
2407                         status = "disabled";
2408                 };
2409
2410                 pcie@14100000 {
2411                         compatible = "nvidia,tegra234-pcie";
2412                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2413                         reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K)      */
2414                               <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2415                               <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2416                               <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2417                               <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB)               */
2418                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2419
2420                         #address-cells = <3>;
2421                         #size-cells = <2>;
2422                         device_type = "pci";
2423                         num-lanes = <1>;
2424                         num-viewport = <8>;
2425                         linux,pci-domain = <1>;
2426
2427                         clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
2428                         clock-names = "core";
2429
2430                         resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
2431                                  <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
2432                         reset-names = "apb", "core";
2433
2434                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2435                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2436                         interrupt-names = "intr", "msi";
2437
2438                         #interrupt-cells = <1>;
2439                         interrupt-map-mask = <0 0 0 0>;
2440                         interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2441
2442                         nvidia,bpmp = <&bpmp 1>;
2443
2444                         nvidia,aspm-cmrt-us = <60>;
2445                         nvidia,aspm-pwr-on-t-us = <20>;
2446                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2447
2448                         bus-range = <0x0 0xff>;
2449
2450                         ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2451                                  <0x02000000 0x0  0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2452                                  <0x01000000 0x0  0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2453
2454                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>,
2455                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>;
2456                         interconnect-names = "dma-mem", "write";
2457                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2458                         iommu-map-mask = <0x0>;
2459                         dma-coherent;
2460
2461                         status = "disabled";
2462                 };
2463
2464                 pcie@14120000 {
2465                         compatible = "nvidia,tegra234-pcie";
2466                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2467                         reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K)      */
2468                               <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2469                               <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2470                               <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2471                               <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB)               */
2472                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2473
2474                         #address-cells = <3>;
2475                         #size-cells = <2>;
2476                         device_type = "pci";
2477                         num-lanes = <1>;
2478                         num-viewport = <8>;
2479                         linux,pci-domain = <2>;
2480
2481                         clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
2482                         clock-names = "core";
2483
2484                         resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
2485                                  <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
2486                         reset-names = "apb", "core";
2487
2488                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2489                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2490                         interrupt-names = "intr", "msi";
2491
2492                         #interrupt-cells = <1>;
2493                         interrupt-map-mask = <0 0 0 0>;
2494                         interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2495
2496                         nvidia,bpmp = <&bpmp 2>;
2497
2498                         nvidia,aspm-cmrt-us = <60>;
2499                         nvidia,aspm-pwr-on-t-us = <20>;
2500                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2501
2502                         bus-range = <0x0 0xff>;
2503
2504                         ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2505                                  <0x02000000 0x0  0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2506                                  <0x01000000 0x0  0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2507
2508                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>,
2509                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>;
2510                         interconnect-names = "dma-mem", "write";
2511                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2512                         iommu-map-mask = <0x0>;
2513                         dma-coherent;
2514
2515                         status = "disabled";
2516                 };
2517
2518                 pcie@14140000 {
2519                         compatible = "nvidia,tegra234-pcie";
2520                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2521                         reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K)      */
2522                               <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2523                               <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2524                               <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2525                               <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2526                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2527
2528                         #address-cells = <3>;
2529                         #size-cells = <2>;
2530                         device_type = "pci";
2531                         num-lanes = <1>;
2532                         num-viewport = <8>;
2533                         linux,pci-domain = <3>;
2534
2535                         clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
2536                         clock-names = "core";
2537
2538                         resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
2539                                  <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
2540                         reset-names = "apb", "core";
2541
2542                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2543                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2544                         interrupt-names = "intr", "msi";
2545
2546                         #interrupt-cells = <1>;
2547                         interrupt-map-mask = <0 0 0 0>;
2548                         interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2549
2550                         nvidia,bpmp = <&bpmp 3>;
2551
2552                         nvidia,aspm-cmrt-us = <60>;
2553                         nvidia,aspm-pwr-on-t-us = <20>;
2554                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2555
2556                         bus-range = <0x0 0xff>;
2557
2558                         ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2559                                  <0x02000000 0x0  0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2560                                  <0x01000000 0x0  0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2561
2562                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
2563                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>;
2564                         interconnect-names = "dma-mem", "write";
2565                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2566                         iommu-map-mask = <0x0>;
2567                         dma-coherent;
2568
2569                         status = "disabled";
2570                 };
2571
2572                 pcie@14160000 {
2573                         compatible = "nvidia,tegra234-pcie";
2574                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
2575                         reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
2576                               <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2577                               <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2578                               <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2579                               <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2580                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2581
2582                         #address-cells = <3>;
2583                         #size-cells = <2>;
2584                         device_type = "pci";
2585                         num-lanes = <4>;
2586                         num-viewport = <8>;
2587                         linux,pci-domain = <4>;
2588
2589                         clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
2590                         clock-names = "core";
2591
2592                         resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
2593                                  <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
2594                         reset-names = "apb", "core";
2595
2596                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2597                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2598                         interrupt-names = "intr", "msi";
2599
2600                         #interrupt-cells = <1>;
2601                         interrupt-map-mask = <0 0 0 0>;
2602                         interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2603
2604                         nvidia,bpmp = <&bpmp 4>;
2605
2606                         nvidia,aspm-cmrt-us = <60>;
2607                         nvidia,aspm-pwr-on-t-us = <20>;
2608                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2609
2610                         bus-range = <0x0 0xff>;
2611
2612                         ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2613                                  <0x02000000 0x0  0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2614                                  <0x01000000 0x0  0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2615
2616                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
2617                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
2618                         interconnect-names = "dma-mem", "write";
2619                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2620                         iommu-map-mask = <0x0>;
2621                         dma-coherent;
2622
2623                         status = "disabled";
2624                 };
2625
2626                 pcie@14180000 {
2627                         compatible = "nvidia,tegra234-pcie";
2628                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
2629                         reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2630                               <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2631                               <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2632                               <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2633                               <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2634                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2635
2636                         #address-cells = <3>;
2637                         #size-cells = <2>;
2638                         device_type = "pci";
2639                         num-lanes = <4>;
2640                         num-viewport = <8>;
2641                         linux,pci-domain = <0>;
2642
2643                         clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
2644                         clock-names = "core";
2645
2646                         resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
2647                                  <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
2648                         reset-names = "apb", "core";
2649
2650                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2651                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2652                         interrupt-names = "intr", "msi";
2653
2654                         #interrupt-cells = <1>;
2655                         interrupt-map-mask = <0 0 0 0>;
2656                         interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2657
2658                         nvidia,bpmp = <&bpmp 0>;
2659
2660                         nvidia,aspm-cmrt-us = <60>;
2661                         nvidia,aspm-pwr-on-t-us = <20>;
2662                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2663
2664                         bus-range = <0x0 0xff>;
2665
2666                         ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2667                                  <0x02000000 0x0  0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2668                                  <0x01000000 0x0  0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2669
2670                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>,
2671                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>;
2672                         interconnect-names = "dma-mem", "write";
2673                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2674                         iommu-map-mask = <0x0>;
2675                         dma-coherent;
2676
2677                         status = "disabled";
2678                 };
2679
2680                 pcie@141a0000 {
2681                         compatible = "nvidia,tegra234-pcie";
2682                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2683                         reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2684                               <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2685                               <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2686                               <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2687                               <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2688                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2689
2690                         #address-cells = <3>;
2691                         #size-cells = <2>;
2692                         device_type = "pci";
2693                         num-lanes = <8>;
2694                         num-viewport = <8>;
2695                         linux,pci-domain = <5>;
2696
2697                         clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2698                         clock-names = "core";
2699
2700                         resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2701                                  <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2702                         reset-names = "apb", "core";
2703
2704                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2705                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2706                         interrupt-names = "intr", "msi";
2707
2708                         #interrupt-cells = <1>;
2709                         interrupt-map-mask = <0 0 0 0>;
2710                         interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2711
2712                         nvidia,bpmp = <&bpmp 5>;
2713
2714                         nvidia,aspm-cmrt-us = <60>;
2715                         nvidia,aspm-pwr-on-t-us = <20>;
2716                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2717
2718                         bus-range = <0x0 0xff>;
2719
2720                         ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
2721                                  <0x02000000 0x0  0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2722                                  <0x01000000 0x0  0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2723
2724                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2725                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2726                         interconnect-names = "dma-mem", "write";
2727                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2728                         iommu-map-mask = <0x0>;
2729                         dma-coherent;
2730
2731                         status = "disabled";
2732                 };
2733
2734                 pcie-ep@141a0000 {
2735                         compatible = "nvidia,tegra234-pcie-ep";
2736                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2737                         reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2738                               <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2739                               <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2740                               <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G)        */
2741                         reg-names = "appl", "atu_dma", "dbi", "addr_space";
2742
2743                         num-lanes = <8>;
2744
2745                         clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2746                         clock-names = "core";
2747
2748                         resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2749                                  <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2750                         reset-names = "apb", "core";
2751
2752                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
2753                         interrupt-names = "intr";
2754
2755                         nvidia,bpmp = <&bpmp 5>;
2756
2757                         nvidia,enable-ext-refclk;
2758                         nvidia,aspm-cmrt-us = <60>;
2759                         nvidia,aspm-pwr-on-t-us = <20>;
2760                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2761
2762                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2763                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2764                         interconnect-names = "dma-mem", "write";
2765                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2766                         iommu-map-mask = <0x0>;
2767                         dma-coherent;
2768
2769                         status = "disabled";
2770                 };
2771
2772                 pcie@141c0000 {
2773                         compatible = "nvidia,tegra234-pcie";
2774                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2775                         reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K)      */
2776                               <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
2777                               <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2778                               <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2779                               <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2780                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2781
2782                         #address-cells = <3>;
2783                         #size-cells = <2>;
2784                         device_type = "pci";
2785                         num-lanes = <4>;
2786                         num-viewport = <8>;
2787                         linux,pci-domain = <6>;
2788
2789                         clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2790                         clock-names = "core";
2791
2792                         resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2793                                  <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2794                         reset-names = "apb", "core";
2795
2796                         interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2797                                      <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2798                         interrupt-names = "intr", "msi";
2799
2800                         #interrupt-cells = <1>;
2801                         interrupt-map-mask = <0 0 0 0>;
2802                         interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
2803
2804                         nvidia,bpmp = <&bpmp 6>;
2805
2806                         nvidia,aspm-cmrt-us = <60>;
2807                         nvidia,aspm-pwr-on-t-us = <20>;
2808                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2809
2810                         bus-range = <0x0 0xff>;
2811
2812                         ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2813                                  <0x02000000 0x0  0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2814                                  <0x01000000 0x0  0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2815
2816                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2817                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2818                         interconnect-names = "dma-mem", "write";
2819                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2820                         iommu-map-mask = <0x0>;
2821                         dma-coherent;
2822
2823                         status = "disabled";
2824                 };
2825
2826                 pcie-ep@141c0000 {
2827                         compatible = "nvidia,tegra234-pcie-ep";
2828                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2829                         reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K)      */
2830                               <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2831                               <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K)           */
2832                               <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G)        */
2833                         reg-names = "appl", "atu_dma", "dbi", "addr_space";
2834
2835                         num-lanes = <4>;
2836
2837                         clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2838                         clock-names = "core";
2839
2840                         resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2841                                  <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2842                         reset-names = "apb", "core";
2843
2844                         interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2845                         interrupt-names = "intr";
2846
2847                         nvidia,bpmp = <&bpmp 6>;
2848
2849                         nvidia,enable-ext-refclk;
2850                         nvidia,aspm-cmrt-us = <60>;
2851                         nvidia,aspm-pwr-on-t-us = <20>;
2852                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2853
2854                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2855                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2856                         interconnect-names = "dma-mem", "write";
2857                         iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2858                         iommu-map-mask = <0x0>;
2859                         dma-coherent;
2860
2861                         status = "disabled";
2862                 };
2863
2864                 pcie@141e0000 {
2865                         compatible = "nvidia,tegra234-pcie";
2866                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2867                         reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K)      */
2868                               <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
2869                               <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2870                               <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2871                               <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
2872                         reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
2873
2874                         #address-cells = <3>;
2875                         #size-cells = <2>;
2876                         device_type = "pci";
2877                         num-lanes = <8>;
2878                         num-viewport = <8>;
2879                         linux,pci-domain = <7>;
2880
2881                         clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2882                         clock-names = "core";
2883
2884                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2885                                  <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2886                         reset-names = "apb", "core";
2887
2888                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2889                                      <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2890                         interrupt-names = "intr", "msi";
2891
2892                         #interrupt-cells = <1>;
2893                         interrupt-map-mask = <0 0 0 0>;
2894                         interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
2895
2896                         nvidia,bpmp = <&bpmp 7>;
2897
2898                         nvidia,aspm-cmrt-us = <60>;
2899                         nvidia,aspm-pwr-on-t-us = <20>;
2900                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2901
2902                         bus-range = <0x0 0xff>;
2903
2904                         ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */
2905                                  <0x02000000 0x0  0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2906                                  <0x01000000 0x0  0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2907
2908                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2909                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2910                         interconnect-names = "dma-mem", "write";
2911                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2912                         iommu-map-mask = <0x0>;
2913                         dma-coherent;
2914
2915                         status = "disabled";
2916                 };
2917
2918                 pcie-ep@141e0000 {
2919                         compatible = "nvidia,tegra234-pcie-ep";
2920                         power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2921                         reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K)      */
2922                               <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2923                               <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K)           */
2924                               <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G)        */
2925                         reg-names = "appl", "atu_dma", "dbi", "addr_space";
2926
2927                         num-lanes = <8>;
2928
2929                         clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2930                         clock-names = "core";
2931
2932                         resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2933                                  <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2934                         reset-names = "apb", "core";
2935
2936                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2937                         interrupt-names = "intr";
2938
2939                         nvidia,bpmp = <&bpmp 7>;
2940
2941                         nvidia,enable-ext-refclk;
2942                         nvidia,aspm-cmrt-us = <60>;
2943                         nvidia,aspm-pwr-on-t-us = <20>;
2944                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2945
2946                         interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2947                                         <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2948                         interconnect-names = "dma-mem", "write";
2949                         iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2950                         iommu-map-mask = <0x0>;
2951                         dma-coherent;
2952
2953                         status = "disabled";
2954                 };
2955         };
2956
2957         sram@40000000 {
2958                 compatible = "nvidia,tegra234-sysram", "mmio-sram";
2959                 reg = <0x0 0x40000000 0x0 0x80000>;
2960
2961                 #address-cells = <1>;
2962                 #size-cells = <1>;
2963                 ranges = <0x0 0x0 0x40000000 0x80000>;
2964
2965                 no-memory-wc;
2966
2967                 cpu_bpmp_tx: sram@70000 {
2968                         reg = <0x70000 0x1000>;
2969                         label = "cpu-bpmp-tx";
2970                         pool;
2971                 };
2972
2973                 cpu_bpmp_rx: sram@71000 {
2974                         reg = <0x71000 0x1000>;
2975                         label = "cpu-bpmp-rx";
2976                         pool;
2977                 };
2978         };
2979
2980         bpmp: bpmp {
2981                 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
2982                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2983                                     TEGRA_HSP_DB_MASTER_BPMP>;
2984                 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
2985                 #clock-cells = <1>;
2986                 #reset-cells = <1>;
2987                 #power-domain-cells = <1>;
2988                 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
2989                                 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
2990                                 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
2991                                 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
2992                 interconnect-names = "read", "write", "dma-mem", "dma-write";
2993                 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>;
2994
2995                 bpmp_i2c: i2c {
2996                         compatible = "nvidia,tegra186-bpmp-i2c";
2997                         nvidia,bpmp-bus-id = <5>;
2998                         #address-cells = <1>;
2999                         #size-cells = <0>;
3000                 };
3001         };
3002
3003         cpus {
3004                 #address-cells = <1>;
3005                 #size-cells = <0>;
3006
3007                 cpu0_0: cpu@0 {
3008                         compatible = "arm,cortex-a78";
3009                         device_type = "cpu";
3010                         reg = <0x00000>;
3011
3012                         enable-method = "psci";
3013
3014                         i-cache-size = <65536>;
3015                         i-cache-line-size = <64>;
3016                         i-cache-sets = <256>;
3017                         d-cache-size = <65536>;
3018                         d-cache-line-size = <64>;
3019                         d-cache-sets = <256>;
3020                         next-level-cache = <&l2c0_0>;
3021                 };
3022
3023                 cpu0_1: cpu@100 {
3024                         compatible = "arm,cortex-a78";
3025                         device_type = "cpu";
3026                         reg = <0x00100>;
3027
3028                         enable-method = "psci";
3029
3030                         i-cache-size = <65536>;
3031                         i-cache-line-size = <64>;
3032                         i-cache-sets = <256>;
3033                         d-cache-size = <65536>;
3034                         d-cache-line-size = <64>;
3035                         d-cache-sets = <256>;
3036                         next-level-cache = <&l2c0_1>;
3037                 };
3038
3039                 cpu0_2: cpu@200 {
3040                         compatible = "arm,cortex-a78";
3041                         device_type = "cpu";
3042                         reg = <0x00200>;
3043
3044                         enable-method = "psci";
3045
3046                         i-cache-size = <65536>;
3047                         i-cache-line-size = <64>;
3048                         i-cache-sets = <256>;
3049                         d-cache-size = <65536>;
3050                         d-cache-line-size = <64>;
3051                         d-cache-sets = <256>;
3052                         next-level-cache = <&l2c0_2>;
3053                 };
3054
3055                 cpu0_3: cpu@300 {
3056                         compatible = "arm,cortex-a78";
3057                         device_type = "cpu";
3058                         reg = <0x00300>;
3059
3060                         enable-method = "psci";
3061
3062                         i-cache-size = <65536>;
3063                         i-cache-line-size = <64>;
3064                         i-cache-sets = <256>;
3065                         d-cache-size = <65536>;
3066                         d-cache-line-size = <64>;
3067                         d-cache-sets = <256>;
3068                         next-level-cache = <&l2c0_3>;
3069                 };
3070
3071                 cpu1_0: cpu@10000 {
3072                         compatible = "arm,cortex-a78";
3073                         device_type = "cpu";
3074                         reg = <0x10000>;
3075
3076                         enable-method = "psci";
3077
3078                         i-cache-size = <65536>;
3079                         i-cache-line-size = <64>;
3080                         i-cache-sets = <256>;
3081                         d-cache-size = <65536>;
3082                         d-cache-line-size = <64>;
3083                         d-cache-sets = <256>;
3084                         next-level-cache = <&l2c1_0>;
3085                 };
3086
3087                 cpu1_1: cpu@10100 {
3088                         compatible = "arm,cortex-a78";
3089                         device_type = "cpu";
3090                         reg = <0x10100>;
3091
3092                         enable-method = "psci";
3093
3094                         i-cache-size = <65536>;
3095                         i-cache-line-size = <64>;
3096                         i-cache-sets = <256>;
3097                         d-cache-size = <65536>;
3098                         d-cache-line-size = <64>;
3099                         d-cache-sets = <256>;
3100                         next-level-cache = <&l2c1_1>;
3101                 };
3102
3103                 cpu1_2: cpu@10200 {
3104                         compatible = "arm,cortex-a78";
3105                         device_type = "cpu";
3106                         reg = <0x10200>;
3107
3108                         enable-method = "psci";
3109
3110                         i-cache-size = <65536>;
3111                         i-cache-line-size = <64>;
3112                         i-cache-sets = <256>;
3113                         d-cache-size = <65536>;
3114                         d-cache-line-size = <64>;
3115                         d-cache-sets = <256>;
3116                         next-level-cache = <&l2c1_2>;
3117                 };
3118
3119                 cpu1_3: cpu@10300 {
3120                         compatible = "arm,cortex-a78";
3121                         device_type = "cpu";
3122                         reg = <0x10300>;
3123
3124                         enable-method = "psci";
3125
3126                         i-cache-size = <65536>;
3127                         i-cache-line-size = <64>;
3128                         i-cache-sets = <256>;
3129                         d-cache-size = <65536>;
3130                         d-cache-line-size = <64>;
3131                         d-cache-sets = <256>;
3132                         next-level-cache = <&l2c1_3>;
3133                 };
3134
3135                 cpu2_0: cpu@20000 {
3136                         compatible = "arm,cortex-a78";
3137                         device_type = "cpu";
3138                         reg = <0x20000>;
3139
3140                         enable-method = "psci";
3141
3142                         i-cache-size = <65536>;
3143                         i-cache-line-size = <64>;
3144                         i-cache-sets = <256>;
3145                         d-cache-size = <65536>;
3146                         d-cache-line-size = <64>;
3147                         d-cache-sets = <256>;
3148                         next-level-cache = <&l2c2_0>;
3149                 };
3150
3151                 cpu2_1: cpu@20100 {
3152                         compatible = "arm,cortex-a78";
3153                         device_type = "cpu";
3154                         reg = <0x20100>;
3155
3156                         enable-method = "psci";
3157
3158                         i-cache-size = <65536>;
3159                         i-cache-line-size = <64>;
3160                         i-cache-sets = <256>;
3161                         d-cache-size = <65536>;
3162                         d-cache-line-size = <64>;
3163                         d-cache-sets = <256>;
3164                         next-level-cache = <&l2c2_1>;
3165                 };
3166
3167                 cpu2_2: cpu@20200 {
3168                         compatible = "arm,cortex-a78";
3169                         device_type = "cpu";
3170                         reg = <0x20200>;
3171
3172                         enable-method = "psci";
3173
3174                         i-cache-size = <65536>;
3175                         i-cache-line-size = <64>;
3176                         i-cache-sets = <256>;
3177                         d-cache-size = <65536>;
3178                         d-cache-line-size = <64>;
3179                         d-cache-sets = <256>;
3180                         next-level-cache = <&l2c2_2>;
3181                 };
3182
3183                 cpu2_3: cpu@20300 {
3184                         compatible = "arm,cortex-a78";
3185                         device_type = "cpu";
3186                         reg = <0x20300>;
3187
3188                         enable-method = "psci";
3189
3190                         i-cache-size = <65536>;
3191                         i-cache-line-size = <64>;
3192                         i-cache-sets = <256>;
3193                         d-cache-size = <65536>;
3194                         d-cache-line-size = <64>;
3195                         d-cache-sets = <256>;
3196                         next-level-cache = <&l2c2_3>;
3197                 };
3198
3199                 cpu-map {
3200                         cluster0 {
3201                                 core0 {
3202                                         cpu = <&cpu0_0>;
3203                                 };
3204
3205                                 core1 {
3206                                         cpu = <&cpu0_1>;
3207                                 };
3208
3209                                 core2 {
3210                                         cpu = <&cpu0_2>;
3211                                 };
3212
3213                                 core3 {
3214                                         cpu = <&cpu0_3>;
3215                                 };
3216                         };
3217
3218                         cluster1 {
3219                                 core0 {
3220                                         cpu = <&cpu1_0>;
3221                                 };
3222
3223                                 core1 {
3224                                         cpu = <&cpu1_1>;
3225                                 };
3226
3227                                 core2 {
3228                                         cpu = <&cpu1_2>;
3229                                 };
3230
3231                                 core3 {
3232                                         cpu = <&cpu1_3>;
3233                                 };
3234                         };
3235
3236                         cluster2 {
3237                                 core0 {
3238                                         cpu = <&cpu2_0>;
3239                                 };
3240
3241                                 core1 {
3242                                         cpu = <&cpu2_1>;
3243                                 };
3244
3245                                 core2 {
3246                                         cpu = <&cpu2_2>;
3247                                 };
3248
3249                                 core3 {
3250                                         cpu = <&cpu2_3>;
3251                                 };
3252                         };
3253                 };
3254
3255                 l2c0_0: l2-cache00 {
3256                         compatible = "cache";
3257                         cache-size = <262144>;
3258                         cache-line-size = <64>;
3259                         cache-sets = <512>;
3260                         cache-unified;
3261                         cache-level = <2>;
3262                         next-level-cache = <&l3c0>;
3263                 };
3264
3265                 l2c0_1: l2-cache01 {
3266                         compatible = "cache";
3267                         cache-size = <262144>;
3268                         cache-line-size = <64>;
3269                         cache-sets = <512>;
3270                         cache-unified;
3271                         cache-level = <2>;
3272                         next-level-cache = <&l3c0>;
3273                 };
3274
3275                 l2c0_2: l2-cache02 {
3276                         compatible = "cache";
3277                         cache-size = <262144>;
3278                         cache-line-size = <64>;
3279                         cache-sets = <512>;
3280                         cache-unified;
3281                         cache-level = <2>;
3282                         next-level-cache = <&l3c0>;
3283                 };
3284
3285                 l2c0_3: l2-cache03 {
3286                         compatible = "cache";
3287                         cache-size = <262144>;
3288                         cache-line-size = <64>;
3289                         cache-sets = <512>;
3290                         cache-unified;
3291                         cache-level = <2>;
3292                         next-level-cache = <&l3c0>;
3293                 };
3294
3295                 l2c1_0: l2-cache10 {
3296                         compatible = "cache";
3297                         cache-size = <262144>;
3298                         cache-line-size = <64>;
3299                         cache-sets = <512>;
3300                         cache-unified;
3301                         cache-level = <2>;
3302                         next-level-cache = <&l3c1>;
3303                 };
3304
3305                 l2c1_1: l2-cache11 {
3306                         compatible = "cache";
3307                         cache-size = <262144>;
3308                         cache-line-size = <64>;
3309                         cache-sets = <512>;
3310                         cache-unified;
3311                         cache-level = <2>;
3312                         next-level-cache = <&l3c1>;
3313                 };
3314
3315                 l2c1_2: l2-cache12 {
3316                         compatible = "cache";
3317                         cache-size = <262144>;
3318                         cache-line-size = <64>;
3319                         cache-sets = <512>;
3320                         cache-unified;
3321                         cache-level = <2>;
3322                         next-level-cache = <&l3c1>;
3323                 };
3324
3325                 l2c1_3: l2-cache13 {
3326                         compatible = "cache";
3327                         cache-size = <262144>;
3328                         cache-line-size = <64>;
3329                         cache-sets = <512>;
3330                         cache-unified;
3331                         cache-level = <2>;
3332                         next-level-cache = <&l3c1>;
3333                 };
3334
3335                 l2c2_0: l2-cache20 {
3336                         compatible = "cache";
3337                         cache-size = <262144>;
3338                         cache-line-size = <64>;
3339                         cache-sets = <512>;
3340                         cache-unified;
3341                         cache-level = <2>;
3342                         next-level-cache = <&l3c2>;
3343                 };
3344
3345                 l2c2_1: l2-cache21 {
3346                         compatible = "cache";
3347                         cache-size = <262144>;
3348                         cache-line-size = <64>;
3349                         cache-sets = <512>;
3350                         cache-unified;
3351                         cache-level = <2>;
3352                         next-level-cache = <&l3c2>;
3353                 };
3354
3355                 l2c2_2: l2-cache22 {
3356                         compatible = "cache";
3357                         cache-size = <262144>;
3358                         cache-line-size = <64>;
3359                         cache-sets = <512>;
3360                         cache-unified;
3361                         cache-level = <2>;
3362                         next-level-cache = <&l3c2>;
3363                 };
3364
3365                 l2c2_3: l2-cache23 {
3366                         compatible = "cache";
3367                         cache-size = <262144>;
3368                         cache-line-size = <64>;
3369                         cache-sets = <512>;
3370                         cache-unified;
3371                         cache-level = <2>;
3372                         next-level-cache = <&l3c2>;
3373                 };
3374
3375                 l3c0: l3-cache0 {
3376                         compatible = "cache";
3377                         cache-unified;
3378                         cache-size = <2097152>;
3379                         cache-line-size = <64>;
3380                         cache-sets = <2048>;
3381                         cache-level = <3>;
3382                 };
3383
3384                 l3c1: l3-cache1 {
3385                         compatible = "cache";
3386                         cache-unified;
3387                         cache-size = <2097152>;
3388                         cache-line-size = <64>;
3389                         cache-sets = <2048>;
3390                         cache-level = <3>;
3391                 };
3392
3393                 l3c2: l3-cache2 {
3394                         compatible = "cache";
3395                         cache-unified;
3396                         cache-size = <2097152>;
3397                         cache-line-size = <64>;
3398                         cache-sets = <2048>;
3399                         cache-level = <3>;
3400                 };
3401         };
3402
3403         dsu-pmu0 {
3404                 compatible = "arm,dsu-pmu";
3405                 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
3406                 cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>;
3407         };
3408
3409         dsu-pmu1 {
3410                 compatible = "arm,dsu-pmu";
3411                 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
3412                 cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>;
3413         };
3414
3415         dsu-pmu2 {
3416                 compatible = "arm,dsu-pmu";
3417                 interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
3418                 cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>;
3419         };
3420
3421         pmu {
3422                 compatible = "arm,cortex-a78-pmu";
3423                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
3424                 status = "okay";
3425         };
3426
3427         psci {
3428                 compatible = "arm,psci-1.0";
3429                 status = "okay";
3430                 method = "smc";
3431         };
3432
3433         tcu: serial {
3434                 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
3435                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3436                          <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
3437                 mbox-names = "rx", "tx";
3438                 status = "disabled";
3439         };
3440
3441         sound {
3442                 status = "disabled";
3443
3444                 clocks = <&bpmp TEGRA234_CLK_PLLA>,
3445                          <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3446                 clock-names = "pll_a", "plla_out0";
3447                 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
3448                                   <&bpmp TEGRA234_CLK_PLLA_OUT0>,
3449                                   <&bpmp TEGRA234_CLK_AUD_MCLK>;
3450                 assigned-clock-parents = <0>,
3451                                          <&bpmp TEGRA234_CLK_PLLA>,
3452                                          <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3453         };
3454
3455         timer {
3456                 compatible = "arm,armv8-timer";
3457                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3458                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3459                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3460                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3461                 interrupt-parent = <&gic>;
3462                 always-on;
3463         };
3464 };