1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/power/tegra186-powergate.h>
7 #include <dt-bindings/reset/tegra186-reset.h>
10 compatible = "nvidia,tegra186";
11 interrupt-parent = <&gic>;
16 compatible = "nvidia,tegra186-gpio";
17 reg-names = "security", "gpio";
18 reg = <0x0 0x2200000 0x0 0x10000>,
19 <0x0 0x2210000 0x0 0x10000>;
20 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
21 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
22 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
23 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
24 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
25 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
26 #interrupt-cells = <2>;
33 compatible = "nvidia,tegra186-eqos",
34 "snps,dwc-qos-ethernet-4.10";
35 reg = <0x0 0x02490000 0x0 0x10000>;
36 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
37 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
38 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
39 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
40 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
41 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
42 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
43 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
44 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
45 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
46 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
47 <&bpmp TEGRA186_CLK_EQOS_AXI>,
48 <&bpmp TEGRA186_CLK_EQOS_RX>,
49 <&bpmp TEGRA186_CLK_EQOS_TX>,
50 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
51 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
52 resets = <&bpmp TEGRA186_RESET_EQOS>;
56 snps,write-requests = <1>;
57 snps,read-requests = <3>;
58 snps,burst-map = <0x7>;
63 uarta: serial@3100000 {
64 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
65 reg = <0x0 0x03100000 0x0 0x40>;
67 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&bpmp TEGRA186_CLK_UARTA>;
69 clock-names = "serial";
70 resets = <&bpmp TEGRA186_RESET_UARTA>;
71 reset-names = "serial";
75 uartb: serial@3110000 {
76 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
77 reg = <0x0 0x03110000 0x0 0x40>;
79 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&bpmp TEGRA186_CLK_UARTB>;
81 clock-names = "serial";
82 resets = <&bpmp TEGRA186_RESET_UARTB>;
83 reset-names = "serial";
87 uartd: serial@3130000 {
88 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
89 reg = <0x0 0x03130000 0x0 0x40>;
91 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&bpmp TEGRA186_CLK_UARTD>;
93 clock-names = "serial";
94 resets = <&bpmp TEGRA186_RESET_UARTD>;
95 reset-names = "serial";
99 uarte: serial@3140000 {
100 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
101 reg = <0x0 0x03140000 0x0 0x40>;
103 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
104 clocks = <&bpmp TEGRA186_CLK_UARTE>;
105 clock-names = "serial";
106 resets = <&bpmp TEGRA186_RESET_UARTE>;
107 reset-names = "serial";
111 uartf: serial@3150000 {
112 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
113 reg = <0x0 0x03150000 0x0 0x40>;
115 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&bpmp TEGRA186_CLK_UARTF>;
117 clock-names = "serial";
118 resets = <&bpmp TEGRA186_RESET_UARTF>;
119 reset-names = "serial";
123 gen1_i2c: i2c@3160000 {
124 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
125 reg = <0x0 0x03160000 0x0 0x10000>;
126 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
127 #address-cells = <1>;
129 clocks = <&bpmp TEGRA186_CLK_I2C1>;
130 clock-names = "div-clk";
131 resets = <&bpmp TEGRA186_RESET_I2C1>;
136 cam_i2c: i2c@3180000 {
137 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
138 reg = <0x0 0x03180000 0x0 0x10000>;
139 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
140 #address-cells = <1>;
142 clocks = <&bpmp TEGRA186_CLK_I2C3>;
143 clock-names = "div-clk";
144 resets = <&bpmp TEGRA186_RESET_I2C3>;
149 /* shares pads with dpaux1 */
150 dp_aux_ch1_i2c: i2c@3190000 {
151 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
152 reg = <0x0 0x03190000 0x0 0x10000>;
153 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
154 #address-cells = <1>;
156 clocks = <&bpmp TEGRA186_CLK_I2C4>;
157 clock-names = "div-clk";
158 resets = <&bpmp TEGRA186_RESET_I2C4>;
163 /* controlled by BPMP, should not be enabled */
164 pwr_i2c: i2c@31a0000 {
165 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
166 reg = <0x0 0x031a0000 0x0 0x10000>;
167 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
168 #address-cells = <1>;
170 clocks = <&bpmp TEGRA186_CLK_I2C5>;
171 clock-names = "div-clk";
172 resets = <&bpmp TEGRA186_RESET_I2C5>;
177 /* shares pads with dpaux0 */
178 dp_aux_ch0_i2c: i2c@31b0000 {
179 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
180 reg = <0x0 0x031b0000 0x0 0x10000>;
181 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
182 #address-cells = <1>;
184 clocks = <&bpmp TEGRA186_CLK_I2C6>;
185 clock-names = "div-clk";
186 resets = <&bpmp TEGRA186_RESET_I2C6>;
191 gen7_i2c: i2c@31c0000 {
192 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
193 reg = <0x0 0x031c0000 0x0 0x10000>;
194 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
195 #address-cells = <1>;
197 clocks = <&bpmp TEGRA186_CLK_I2C7>;
198 clock-names = "div-clk";
199 resets = <&bpmp TEGRA186_RESET_I2C7>;
204 gen9_i2c: i2c@31e0000 {
205 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
206 reg = <0x0 0x031e0000 0x0 0x10000>;
207 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
208 #address-cells = <1>;
210 clocks = <&bpmp TEGRA186_CLK_I2C9>;
211 clock-names = "div-clk";
212 resets = <&bpmp TEGRA186_RESET_I2C9>;
217 sdmmc1: sdhci@3400000 {
218 compatible = "nvidia,tegra186-sdhci";
219 reg = <0x0 0x03400000 0x0 0x10000>;
220 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
222 clock-names = "sdhci";
223 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
224 reset-names = "sdhci";
228 sdmmc2: sdhci@3420000 {
229 compatible = "nvidia,tegra186-sdhci";
230 reg = <0x0 0x03420000 0x0 0x10000>;
231 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
233 clock-names = "sdhci";
234 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
235 reset-names = "sdhci";
239 sdmmc3: sdhci@3440000 {
240 compatible = "nvidia,tegra186-sdhci";
241 reg = <0x0 0x03440000 0x0 0x10000>;
242 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
244 clock-names = "sdhci";
245 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
246 reset-names = "sdhci";
250 sdmmc4: sdhci@3460000 {
251 compatible = "nvidia,tegra186-sdhci";
252 reg = <0x0 0x03460000 0x0 0x10000>;
253 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
255 clock-names = "sdhci";
256 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
257 reset-names = "sdhci";
261 gic: interrupt-controller@3881000 {
262 compatible = "arm,gic-400";
263 #interrupt-cells = <3>;
264 interrupt-controller;
265 reg = <0x0 0x03881000 0x0 0x1000>,
266 <0x0 0x03882000 0x0 0x2000>;
267 interrupts = <GIC_PPI 9
268 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
269 interrupt-parent = <&gic>;
272 hsp_top0: hsp@3c00000 {
273 compatible = "nvidia,tegra186-hsp";
274 reg = <0x0 0x03c00000 0x0 0xa0000>;
275 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "doorbell";
281 gen2_i2c: i2c@c240000 {
282 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
283 reg = <0x0 0x0c240000 0x0 0x10000>;
284 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
285 #address-cells = <1>;
287 clocks = <&bpmp TEGRA186_CLK_I2C2>;
288 clock-names = "div-clk";
289 resets = <&bpmp TEGRA186_RESET_I2C2>;
294 gen8_i2c: i2c@c250000 {
295 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
296 reg = <0x0 0x0c250000 0x0 0x10000>;
297 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
298 #address-cells = <1>;
300 clocks = <&bpmp TEGRA186_CLK_I2C8>;
301 clock-names = "div-clk";
302 resets = <&bpmp TEGRA186_RESET_I2C8>;
307 uartc: serial@c280000 {
308 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
309 reg = <0x0 0x0c280000 0x0 0x40>;
311 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&bpmp TEGRA186_CLK_UARTC>;
313 clock-names = "serial";
314 resets = <&bpmp TEGRA186_RESET_UARTC>;
315 reset-names = "serial";
319 uartg: serial@c290000 {
320 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
321 reg = <0x0 0x0c290000 0x0 0x40>;
323 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&bpmp TEGRA186_CLK_UARTG>;
325 clock-names = "serial";
326 resets = <&bpmp TEGRA186_RESET_UARTG>;
327 reset-names = "serial";
331 gpio_aon: gpio@c2f0000 {
332 compatible = "nvidia,tegra186-gpio-aon";
333 reg-names = "security", "gpio";
334 reg = <0x0 0xc2f0000 0x0 0x1000>,
335 <0x0 0xc2f1000 0x0 0x1000>;
336 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
339 interrupt-controller;
340 #interrupt-cells = <2>;
344 compatible = "nvidia,tegra186-pmc";
345 reg = <0 0x0c360000 0 0x10000>,
346 <0 0x0c370000 0 0x10000>,
347 <0 0x0c380000 0 0x10000>,
348 <0 0x0c390000 0 0x10000>;
349 reg-names = "pmc", "wake", "aotag", "scratch";
353 compatible = "nvidia,tegra186-ccplex-cluster";
354 reg = <0x0 0x0e000000 0x0 0x3fffff>;
356 nvidia,bpmp = <&bpmp>;
360 compatible = "nvidia,gp10b";
361 reg = <0x0 0x17000000 0x0 0x1000000>,
362 <0x0 0x18000000 0x0 0x1000000>;
363 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-names = "stall", "nonstall";
367 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
368 <&bpmp TEGRA186_CLK_GPU>;
369 clock-names = "gpu", "pwr";
370 resets = <&bpmp TEGRA186_RESET_GPU>;
374 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
378 compatible = "nvidia,tegra186-sysram", "mmio-sram";
379 reg = <0x0 0x30000000 0x0 0x50000>;
380 #address-cells = <2>;
382 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
384 cpu_bpmp_tx: shmem@4e000 {
385 compatible = "nvidia,tegra186-bpmp-shmem";
386 reg = <0x0 0x4e000 0x0 0x1000>;
387 label = "cpu-bpmp-tx";
391 cpu_bpmp_rx: shmem@4f000 {
392 compatible = "nvidia,tegra186-bpmp-shmem";
393 reg = <0x0 0x4f000 0x0 0x1000>;
394 label = "cpu-bpmp-rx";
400 #address-cells = <1>;
404 compatible = "nvidia,tegra186-denver", "arm,armv8";
410 compatible = "nvidia,tegra186-denver", "arm,armv8";
416 compatible = "arm,cortex-a57", "arm,armv8";
422 compatible = "arm,cortex-a57", "arm,armv8";
428 compatible = "arm,cortex-a57", "arm,armv8";
434 compatible = "arm,cortex-a57", "arm,armv8";
441 compatible = "nvidia,tegra186-bpmp";
442 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
443 TEGRA_HSP_DB_MASTER_BPMP>;
444 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
449 compatible = "nvidia,tegra186-bpmp-i2c";
450 nvidia,bpmp-bus-id = <5>;
451 #address-cells = <1>;
458 compatible = "arm,armv8-timer";
459 interrupts = <GIC_PPI 13
460 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
462 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
464 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
466 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
467 interrupt-parent = <&gic>;