arch/arm64/boot/dts/mediatek/mt8195.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2021 MediaTek Inc.
   4  * Author: Seiya Wang <seiya.wang@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/mt8195-clk.h>
   9 #include <dt-bindings/gce/mt8195-gce.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/memory/mt8195-memory-port.h>
  13 #include <dt-bindings/phy/phy.h>
  14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
  15 #include <dt-bindings/power/mt8195-power.h>
  16 #include <dt-bindings/reset/mt8195-resets.h>
  17 #include <dt-bindings/thermal/thermal.h>
  18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
  19
  20 / {
  21         compatible = "mediatek,mt8195";
  22         interrupt-parent = <&gic>;
  23         #address-cells = <2>;
  24         #size-cells = <2>;
  25
  26         aliases {
  27                 dp-intf0 = &dp_intf0;
  28                 dp-intf1 = &dp_intf1;
  29                 gce0 = &gce0;
  30                 gce1 = &gce1;
  31                 ethdr0 = &ethdr0;
  32                 mutex0 = &mutex;
  33                 mutex1 = &mutex1;
  34                 merge1 = &merge1;
  35                 merge2 = &merge2;
  36                 merge3 = &merge3;
  37                 merge4 = &merge4;
  38                 merge5 = &merge5;
  39                 vdo1-rdma0 = &vdo1_rdma0;
  40                 vdo1-rdma1 = &vdo1_rdma1;
  41                 vdo1-rdma2 = &vdo1_rdma2;
  42                 vdo1-rdma3 = &vdo1_rdma3;
  43                 vdo1-rdma4 = &vdo1_rdma4;
  44                 vdo1-rdma5 = &vdo1_rdma5;
  45                 vdo1-rdma6 = &vdo1_rdma6;
  46                 vdo1-rdma7 = &vdo1_rdma7;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu0: cpu@0 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a55";
  56                         reg = <0x000>;
  57                         enable-method = "psci";
  58                         performance-domains = <&performance 0>;
  59                         clock-frequency = <1701000000>;
  60                         capacity-dmips-mhz = <308>;
  61                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
  62                         i-cache-size = <32768>;
  63                         i-cache-line-size = <64>;
  64                         i-cache-sets = <128>;
  65                         d-cache-size = <32768>;
  66                         d-cache-line-size = <64>;
  67                         d-cache-sets = <128>;
  68                         next-level-cache = <&l2_0>;
  69                         #cooling-cells = <2>;
  70                 };
  71
  72                 cpu1: cpu@100 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a55";
  75                         reg = <0x100>;
  76                         enable-method = "psci";
  77                         performance-domains = <&performance 0>;
  78                         clock-frequency = <1701000000>;
  79                         capacity-dmips-mhz = <308>;
  80                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
  81                         i-cache-size = <32768>;
  82                         i-cache-line-size = <64>;
  83                         i-cache-sets = <128>;
  84                         d-cache-size = <32768>;
  85                         d-cache-line-size = <64>;
  86                         d-cache-sets = <128>;
  87                         next-level-cache = <&l2_0>;
  88                         #cooling-cells = <2>;
  89                 };
  90
  91                 cpu2: cpu@200 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a55";
  94                         reg = <0x200>;
  95                         enable-method = "psci";
  96                         performance-domains = <&performance 0>;
  97                         clock-frequency = <1701000000>;
  98                         capacity-dmips-mhz = <308>;
  99                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 100                         i-cache-size = <32768>;
 101                         i-cache-line-size = <64>;
 102                         i-cache-sets = <128>;
 103                         d-cache-size = <32768>;
 104                         d-cache-line-size = <64>;
 105                         d-cache-sets = <128>;
 106                         next-level-cache = <&l2_0>;
 107                         #cooling-cells = <2>;
 108                 };
 109
 110                 cpu3: cpu@300 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a55";
 113                         reg = <0x300>;
 114                         enable-method = "psci";
 115                         performance-domains = <&performance 0>;
 116                         clock-frequency = <1701000000>;
 117                         capacity-dmips-mhz = <308>;
 118                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 119                         i-cache-size = <32768>;
 120                         i-cache-line-size = <64>;
 121                         i-cache-sets = <128>;
 122                         d-cache-size = <32768>;
 123                         d-cache-line-size = <64>;
 124                         d-cache-sets = <128>;
 125                         next-level-cache = <&l2_0>;
 126                         #cooling-cells = <2>;
 127                 };
 128
 129                 cpu4: cpu@400 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a78";
 132                         reg = <0x400>;
 133                         enable-method = "psci";
 134                         performance-domains = <&performance 1>;
 135                         clock-frequency = <2171000000>;
 136                         capacity-dmips-mhz = <1024>;
 137                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 138                         i-cache-size = <65536>;
 139                         i-cache-line-size = <64>;
 140                         i-cache-sets = <256>;
 141                         d-cache-size = <65536>;
 142                         d-cache-line-size = <64>;
 143                         d-cache-sets = <256>;
 144                         next-level-cache = <&l2_1>;
 145                         #cooling-cells = <2>;
 146                 };
 147
 148                 cpu5: cpu@500 {
 149                         device_type = "cpu";
 150                         compatible = "arm,cortex-a78";
 151                         reg = <0x500>;
 152                         enable-method = "psci";
 153                         performance-domains = <&performance 1>;
 154                         clock-frequency = <2171000000>;
 155                         capacity-dmips-mhz = <1024>;
 156                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 157                         i-cache-size = <65536>;
 158                         i-cache-line-size = <64>;
 159                         i-cache-sets = <256>;
 160                         d-cache-size = <65536>;
 161                         d-cache-line-size = <64>;
 162                         d-cache-sets = <256>;
 163                         next-level-cache = <&l2_1>;
 164                         #cooling-cells = <2>;
 165                 };
 166
 167                 cpu6: cpu@600 {
 168                         device_type = "cpu";
 169                         compatible = "arm,cortex-a78";
 170                         reg = <0x600>;
 171                         enable-method = "psci";
 172                         performance-domains = <&performance 1>;
 173                         clock-frequency = <2171000000>;
 174                         capacity-dmips-mhz = <1024>;
 175                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 176                         i-cache-size = <65536>;
 177                         i-cache-line-size = <64>;
 178                         i-cache-sets = <256>;
 179                         d-cache-size = <65536>;
 180                         d-cache-line-size = <64>;
 181                         d-cache-sets = <256>;
 182                         next-level-cache = <&l2_1>;
 183                         #cooling-cells = <2>;
 184                 };
 185
 186                 cpu7: cpu@700 {
 187                         device_type = "cpu";
 188                         compatible = "arm,cortex-a78";
 189                         reg = <0x700>;
 190                         enable-method = "psci";
 191                         performance-domains = <&performance 1>;
 192                         clock-frequency = <2171000000>;
 193                         capacity-dmips-mhz = <1024>;
 194                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 195                         i-cache-size = <65536>;
 196                         i-cache-line-size = <64>;
 197                         i-cache-sets = <256>;
 198                         d-cache-size = <65536>;
 199                         d-cache-line-size = <64>;
 200                         d-cache-sets = <256>;
 201                         next-level-cache = <&l2_1>;
 202                         #cooling-cells = <2>;
 203                 };
 204
 205                 cpu-map {
 206                         cluster0 {
 207                                 core0 {
 208                                         cpu = <&cpu0>;
 209                                 };
 210
 211                                 core1 {
 212                                         cpu = <&cpu1>;
 213                                 };
 214
 215                                 core2 {
 216                                         cpu = <&cpu2>;
 217                                 };
 218
 219                                 core3 {
 220                                         cpu = <&cpu3>;
 221                                 };
 222
 223                                 core4 {
 224                                         cpu = <&cpu4>;
 225                                 };
 226
 227                                 core5 {
 228                                         cpu = <&cpu5>;
 229                                 };
 230
 231                                 core6 {
 232                                         cpu = <&cpu6>;
 233                                 };
 234
 235                                 core7 {
 236                                         cpu = <&cpu7>;
 237                                 };
 238                         };
 239                 };
 240
 241                 idle-states {
 242                         entry-method = "psci";
 243
 244                         cpu_ret_l: cpu-retention-l {
 245                                 compatible = "arm,idle-state";
 246                                 arm,psci-suspend-param = <0x00010001>;
 247                                 local-timer-stop;
 248                                 entry-latency-us = <50>;
 249                                 exit-latency-us = <95>;
 250                                 min-residency-us = <580>;
 251                         };
 252
 253                         cpu_ret_b: cpu-retention-b {
 254                                 compatible = "arm,idle-state";
 255                                 arm,psci-suspend-param = <0x00010001>;
 256                                 local-timer-stop;
 257                                 entry-latency-us = <45>;
 258                                 exit-latency-us = <140>;
 259                                 min-residency-us = <740>;
 260                         };
 261
 262                         cpu_off_l: cpu-off-l {
 263                                 compatible = "arm,idle-state";
 264                                 arm,psci-suspend-param = <0x01010002>;
 265                                 local-timer-stop;
 266                                 entry-latency-us = <55>;
 267                                 exit-latency-us = <155>;
 268                                 min-residency-us = <840>;
 269                         };
 270
 271                         cpu_off_b: cpu-off-b {
 272                                 compatible = "arm,idle-state";
 273                                 arm,psci-suspend-param = <0x01010002>;
 274                                 local-timer-stop;
 275                                 entry-latency-us = <50>;
 276                                 exit-latency-us = <200>;
 277                                 min-residency-us = <1000>;
 278                         };
 279                 };
 280
 281                 l2_0: l2-cache0 {
 282                         compatible = "cache";
 283                         cache-level = <2>;
 284                         cache-size = <131072>;
 285                         cache-line-size = <64>;
 286                         cache-sets = <512>;
 287                         next-level-cache = <&l3_0>;
 288                         cache-unified;
 289                 };
 290
 291                 l2_1: l2-cache1 {
 292                         compatible = "cache";
 293                         cache-level = <2>;
 294                         cache-size = <262144>;
 295                         cache-line-size = <64>;
 296                         cache-sets = <512>;
 297                         next-level-cache = <&l3_0>;
 298                         cache-unified;
 299                 };
 300
 301                 l3_0: l3-cache {
 302                         compatible = "cache";
 303                         cache-level = <3>;
 304                         cache-size = <2097152>;
 305                         cache-line-size = <64>;
 306                         cache-sets = <2048>;
 307                         cache-unified;
 308                 };
 309         };
 310
 311         dsu-pmu {
 312                 compatible = "arm,dsu-pmu";
 313                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
 315                        <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
 316                 status = "fail";
 317         };
 318
 319         dmic_codec: dmic-codec {
 320                 compatible = "dmic-codec";
 321                 num-channels = <2>;
 322                 wakeup-delay-ms = <50>;
 323         };
 324
 325         sound: mt8195-sound {
 326                 mediatek,platform = <&afe>;
 327                 status = "disabled";
 328         };
 329
 330         clk13m: fixed-factor-clock-13m {
 331                 compatible = "fixed-factor-clock";
 332                 #clock-cells = <0>;
 333                 clocks = <&clk26m>;
 334                 clock-div = <2>;
 335                 clock-mult = <1>;
 336                 clock-output-names = "clk13m";
 337         };
 338
 339         clk26m: oscillator-26m {
 340                 compatible = "fixed-clock";
 341                 #clock-cells = <0>;
 342                 clock-frequency = <26000000>;
 343                 clock-output-names = "clk26m";
 344         };
 345
 346         clk32k: oscillator-32k {
 347                 compatible = "fixed-clock";
 348                 #clock-cells = <0>;
 349                 clock-frequency = <32768>;
 350                 clock-output-names = "clk32k";
 351         };
 352
 353         performance: performance-controller@11bc10 {
 354                 compatible = "mediatek,cpufreq-hw";
 355                 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
 356                 #performance-domain-cells = <1>;
 357         };
 358
 359         gpu_opp_table: opp-table-gpu {
 360                 compatible = "operating-points-v2";
 361                 opp-shared;
 362
 363                 opp-390000000 {
 364                         opp-hz = /bits/ 64 <390000000>;
 365                         opp-microvolt = <625000>;
 366                 };
 367                 opp-410000000 {
 368                         opp-hz = /bits/ 64 <410000000>;
 369                         opp-microvolt = <631250>;
 370                 };
 371                 opp-431000000 {
 372                         opp-hz = /bits/ 64 <431000000>;
 373                         opp-microvolt = <631250>;
 374                 };
 375                 opp-473000000 {
 376                         opp-hz = /bits/ 64 <473000000>;
 377                         opp-microvolt = <637500>;
 378                 };
 379                 opp-515000000 {
 380                         opp-hz = /bits/ 64 <515000000>;
 381                         opp-microvolt = <637500>;
 382                 };
 383                 opp-556000000 {
 384                         opp-hz = /bits/ 64 <556000000>;
 385                         opp-microvolt = <643750>;
 386                 };
 387                 opp-598000000 {
 388                         opp-hz = /bits/ 64 <598000000>;
 389                         opp-microvolt = <650000>;
 390                 };
 391                 opp-640000000 {
 392                         opp-hz = /bits/ 64 <640000000>;
 393                         opp-microvolt = <650000>;
 394                 };
 395                 opp-670000000 {
 396                         opp-hz = /bits/ 64 <670000000>;
 397                         opp-microvolt = <662500>;
 398                 };
 399                 opp-700000000 {
 400                         opp-hz = /bits/ 64 <700000000>;
 401                         opp-microvolt = <675000>;
 402                 };
 403                 opp-730000000 {
 404                         opp-hz = /bits/ 64 <730000000>;
 405                         opp-microvolt = <687500>;
 406                 };
 407                 opp-760000000 {
 408                         opp-hz = /bits/ 64 <760000000>;
 409                         opp-microvolt = <700000>;
 410                 };
 411                 opp-790000000 {
 412                         opp-hz = /bits/ 64 <790000000>;
 413                         opp-microvolt = <712500>;
 414                 };
 415                 opp-820000000 {
 416                         opp-hz = /bits/ 64 <820000000>;
 417                         opp-microvolt = <725000>;
 418                 };
 419                 opp-850000000 {
 420                         opp-hz = /bits/ 64 <850000000>;
 421                         opp-microvolt = <737500>;
 422                 };
 423                 opp-880000000 {
 424                         opp-hz = /bits/ 64 <880000000>;
 425                         opp-microvolt = <750000>;
 426                 };
 427         };
 428
 429         pmu-a55 {
 430                 compatible = "arm,cortex-a55-pmu";
 431                 interrupt-parent = <&gic>;
 432                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
 433         };
 434
 435         pmu-a78 {
 436                 compatible = "arm,cortex-a78-pmu";
 437                 interrupt-parent = <&gic>;
 438                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 439         };
 440
 441         psci {
 442                 compatible = "arm,psci-1.0";
 443                 method = "smc";
 444         };
 445
 446         timer: timer {
 447                 compatible = "arm,armv8-timer";
 448                 interrupt-parent = <&gic>;
 449                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
 450                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
 451                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
 452                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
 453         };
 454
 455         soc {
 456                 #address-cells = <2>;
 457                 #size-cells = <2>;
 458                 compatible = "simple-bus";
 459                 ranges;
 460                 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
 461
 462                 gic: interrupt-controller@c000000 {
 463                         compatible = "arm,gic-v3";
 464                         #interrupt-cells = <4>;
 465                         #redistributor-regions = <1>;
 466                         interrupt-parent = <&gic>;
 467                         interrupt-controller;
 468                         reg = <0 0x0c000000 0 0x40000>,
 469                               <0 0x0c040000 0 0x200000>;
 470                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 471
 472                         ppi-partitions {
 473                                 ppi_cluster0: interrupt-partition-0 {
 474                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 475                                 };
 476
 477                                 ppi_cluster1: interrupt-partition-1 {
 478                                         affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
 479                                 };
 480                         };
 481                 };
 482
 483                 topckgen: syscon@10000000 {
 484                         compatible = "mediatek,mt8195-topckgen", "syscon";
 485                         reg = <0 0x10000000 0 0x1000>;
 486                         #clock-cells = <1>;
 487                 };
 488
 489                 infracfg_ao: syscon@10001000 {
 490                         compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
 491                         reg = <0 0x10001000 0 0x1000>;
 492                         #clock-cells = <1>;
 493                         #reset-cells = <1>;
 494                 };
 495
 496                 pericfg: syscon@10003000 {
 497                         compatible = "mediatek,mt8195-pericfg", "syscon";
 498                         reg = <0 0x10003000 0 0x1000>;
 499                         #clock-cells = <1>;
 500                 };
 501
 502                 pio: pinctrl@10005000 {
 503                         compatible = "mediatek,mt8195-pinctrl";
 504                         reg = <0 0x10005000 0 0x1000>,
 505                               <0 0x11d10000 0 0x1000>,
 506                               <0 0x11d30000 0 0x1000>,
 507                               <0 0x11d40000 0 0x1000>,
 508                               <0 0x11e20000 0 0x1000>,
 509                               <0 0x11eb0000 0 0x1000>,
 510                               <0 0x11f40000 0 0x1000>,
 511                               <0 0x1000b000 0 0x1000>;
 512                         reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
 513                                     "iocfg_br", "iocfg_lm", "iocfg_rb",
 514                                     "iocfg_tl", "eint";
 515                         gpio-controller;
 516                         #gpio-cells = <2>;
 517                         gpio-ranges = <&pio 0 0 144>;
 518                         interrupt-controller;
 519                         interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
 520                         #interrupt-cells = <2>;
 521                 };
 522
 523                 scpsys: syscon@10006000 {
 524                         compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
 525                         reg = <0 0x10006000 0 0x1000>;
 526
 527                         /* System Power Manager */
 528                         spm: power-controller {
 529                                 compatible = "mediatek,mt8195-power-controller";
 530                                 #address-cells = <1>;
 531                                 #size-cells = <0>;
 532                                 #power-domain-cells = <1>;
 533
 534                                 /* power domain of the SoC */
 535                                 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
 536                                         reg = <MT8195_POWER_DOMAIN_MFG0>;
 537                                         #address-cells = <1>;
 538                                         #size-cells = <0>;
 539                                         #power-domain-cells = <1>;
 540
 541                                         mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
 542                                                 reg = <MT8195_POWER_DOMAIN_MFG1>;
 543                                                 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
 544                                                          <&topckgen CLK_TOP_MFG_CORE_TMP>;
 545                                                 clock-names = "mfg", "alt";
 546                                                 mediatek,infracfg = <&infracfg_ao>;
 547                                                 #address-cells = <1>;
 548                                                 #size-cells = <0>;
 549                                                 #power-domain-cells = <1>;
 550
 551                                                 power-domain@MT8195_POWER_DOMAIN_MFG2 {
 552                                                         reg = <MT8195_POWER_DOMAIN_MFG2>;
 553                                                         #power-domain-cells = <0>;
 554                                                 };
 555
 556                                                 power-domain@MT8195_POWER_DOMAIN_MFG3 {
 557                                                         reg = <MT8195_POWER_DOMAIN_MFG3>;
 558                                                         #power-domain-cells = <0>;
 559                                                 };
 560
 561                                                 power-domain@MT8195_POWER_DOMAIN_MFG4 {
 562                                                         reg = <MT8195_POWER_DOMAIN_MFG4>;
 563                                                         #power-domain-cells = <0>;
 564                                                 };
 565
 566                                                 power-domain@MT8195_POWER_DOMAIN_MFG5 {
 567                                                         reg = <MT8195_POWER_DOMAIN_MFG5>;
 568                                                         #power-domain-cells = <0>;
 569                                                 };
 570
 571                                                 power-domain@MT8195_POWER_DOMAIN_MFG6 {
 572                                                         reg = <MT8195_POWER_DOMAIN_MFG6>;
 573                                                         #power-domain-cells = <0>;
 574                                                 };
 575                                         };
 576                                 };
 577
 578                                 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
 579                                         reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
 580                                         clocks = <&topckgen CLK_TOP_VPP>,
 581                                                  <&topckgen CLK_TOP_CAM>,
 582                                                  <&topckgen CLK_TOP_CCU>,
 583                                                  <&topckgen CLK_TOP_IMG>,
 584                                                  <&topckgen CLK_TOP_VENC>,
 585                                                  <&topckgen CLK_TOP_VDEC>,
 586                                                  <&topckgen CLK_TOP_WPE_VPP>,
 587                                                  <&topckgen CLK_TOP_CFG_VPP0>,
 588                                                  <&vppsys0 CLK_VPP0_SMI_COMMON>,
 589                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
 590                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
 591                                                  <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
 592                                                  <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
 593                                                  <&vppsys0 CLK_VPP0_GALS_INFRA>,
 594                                                  <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
 595                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
 596                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
 597                                                  <&vppsys0 CLK_VPP0_SMI_REORDER>,
 598                                                  <&vppsys0 CLK_VPP0_SMI_IOMMU>,
 599                                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
 600                                                  <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
 601                                                  <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
 602                                                  <&vppsys0 CLK_VPP0_SMI_RSI>,
 603                                                  <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
 604                                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
 605                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
 606                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
 607                                         clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
 608                                                       "vppsys4", "vppsys5", "vppsys6", "vppsys7",
 609                                                       "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
 610                                                       "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
 611                                                       "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
 612                                                       "vppsys0-12", "vppsys0-13", "vppsys0-14",
 613                                                       "vppsys0-15", "vppsys0-16", "vppsys0-17",
 614                                                       "vppsys0-18";
 615                                         mediatek,infracfg = <&infracfg_ao>;
 616                                         #address-cells = <1>;
 617                                         #size-cells = <0>;
 618                                         #power-domain-cells = <1>;
 619
 620                                         power-domain@MT8195_POWER_DOMAIN_VDEC1 {
 621                                                 reg = <MT8195_POWER_DOMAIN_VDEC1>;
 622                                                 clocks = <&vdecsys CLK_VDEC_LARB1>;
 623                                                 clock-names = "vdec1-0";
 624                                                 mediatek,infracfg = <&infracfg_ao>;
 625                                                 #power-domain-cells = <0>;
 626                                         };
 627
 628                                         power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
 629                                                 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
 630                                                 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
 631                                                 clock-names = "venc1-larb";
 632                                                 mediatek,infracfg = <&infracfg_ao>;
 633                                                 #power-domain-cells = <0>;
 634                                         };
 635
 636                                         power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
 637                                                 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
 638                                                 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
 639                                                          <&vdosys0 CLK_VDO0_SMI_GALS>,
 640                                                          <&vdosys0 CLK_VDO0_SMI_COMMON>,
 641                                                          <&vdosys0 CLK_VDO0_SMI_EMI>,
 642                                                          <&vdosys0 CLK_VDO0_SMI_IOMMU>,
 643                                                          <&vdosys0 CLK_VDO0_SMI_LARB>,
 644                                                          <&vdosys0 CLK_VDO0_SMI_RSI>;
 645                                                 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
 646                                                               "vdosys0-2", "vdosys0-3",
 647                                                               "vdosys0-4", "vdosys0-5";
 648                                                 mediatek,infracfg = <&infracfg_ao>;
 649                                                 #address-cells = <1>;
 650                                                 #size-cells = <0>;
 651                                                 #power-domain-cells = <1>;
 652
 653                                                 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
 654                                                         reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
 655                                                         clocks = <&topckgen CLK_TOP_CFG_VPP1>,
 656                                                                  <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
 657                                                                  <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
 658                                                         clock-names = "vppsys1", "vppsys1-0",
 659                                                                       "vppsys1-1";
 660                                                         mediatek,infracfg = <&infracfg_ao>;
 661                                                         #power-domain-cells = <0>;
 662                                                 };
 663
 664                                                 power-domain@MT8195_POWER_DOMAIN_WPESYS {
 665                                                         reg = <MT8195_POWER_DOMAIN_WPESYS>;
 666                                                         clocks = <&wpesys CLK_WPE_SMI_LARB7>,
 667                                                                  <&wpesys CLK_WPE_SMI_LARB8>,
 668                                                                  <&wpesys CLK_WPE_SMI_LARB7_P>,
 669                                                                  <&wpesys CLK_WPE_SMI_LARB8_P>;
 670                                                         clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
 671                                                                       "wepsys-3";
 672                                                         mediatek,infracfg = <&infracfg_ao>;
 673                                                         #power-domain-cells = <0>;
 674                                                 };
 675
 676                                                 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
 677                                                         reg = <MT8195_POWER_DOMAIN_VDEC0>;
 678                                                         clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
 679                                                         clock-names = "vdec0-0";
 680                                                         mediatek,infracfg = <&infracfg_ao>;
 681                                                         #power-domain-cells = <0>;
 682                                                 };
 683
 684                                                 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
 685                                                         reg = <MT8195_POWER_DOMAIN_VDEC2>;
 686                                                         clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
 687                                                         clock-names = "vdec2-0";
 688                                                         mediatek,infracfg = <&infracfg_ao>;
 689                                                         #power-domain-cells = <0>;
 690                                                 };
 691
 692                                                 power-domain@MT8195_POWER_DOMAIN_VENC {
 693                                                         reg = <MT8195_POWER_DOMAIN_VENC>;
 694                                                         clocks = <&vencsys CLK_VENC_LARB>;
 695                                                         clock-names = "venc0-larb";
 696                                                         mediatek,infracfg = <&infracfg_ao>;
 697                                                         #power-domain-cells = <0>;
 698                                                 };
 699
 700                                                 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
 701                                                         reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
 702                                                         clocks = <&topckgen CLK_TOP_CFG_VDO1>,
 703                                                                  <&vdosys1 CLK_VDO1_SMI_LARB2>,
 704                                                                  <&vdosys1 CLK_VDO1_SMI_LARB3>,
 705                                                                  <&vdosys1 CLK_VDO1_GALS>;
 706                                                         clock-names = "vdosys1", "vdosys1-0",
 707                                                                       "vdosys1-1", "vdosys1-2";
 708                                                         mediatek,infracfg = <&infracfg_ao>;
 709                                                         #address-cells = <1>;
 710                                                         #size-cells = <0>;
 711                                                         #power-domain-cells = <1>;
 712
 713                                                         power-domain@MT8195_POWER_DOMAIN_DP_TX {
 714                                                                 reg = <MT8195_POWER_DOMAIN_DP_TX>;
 715                                                                 mediatek,infracfg = <&infracfg_ao>;
 716                                                                 #power-domain-cells = <0>;
 717                                                         };
 718
 719                                                         power-domain@MT8195_POWER_DOMAIN_EPD_TX {
 720                                                                 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
 721                                                                 mediatek,infracfg = <&infracfg_ao>;
 722                                                                 #power-domain-cells = <0>;
 723                                                         };
 724
 725                                                         power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
 726                                                                 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
 727                                                                 clocks = <&topckgen CLK_TOP_HDMI_APB>;
 728                                                                 clock-names = "hdmi_tx";
 729                                                                 #power-domain-cells = <0>;
 730                                                         };
 731                                                 };
 732
 733                                                 power-domain@MT8195_POWER_DOMAIN_IMG {
 734                                                         reg = <MT8195_POWER_DOMAIN_IMG>;
 735                                                         clocks = <&imgsys CLK_IMG_LARB9>,
 736                                                                  <&imgsys CLK_IMG_GALS>;
 737                                                         clock-names = "img-0", "img-1";
 738                                                         mediatek,infracfg = <&infracfg_ao>;
 739                                                         #address-cells = <1>;
 740                                                         #size-cells = <0>;
 741                                                         #power-domain-cells = <1>;
 742
 743                                                         power-domain@MT8195_POWER_DOMAIN_DIP {
 744                                                                 reg = <MT8195_POWER_DOMAIN_DIP>;
 745                                                                 #power-domain-cells = <0>;
 746                                                         };
 747
 748                                                         power-domain@MT8195_POWER_DOMAIN_IPE {
 749                                                                 reg = <MT8195_POWER_DOMAIN_IPE>;
 750                                                                 clocks = <&topckgen CLK_TOP_IPE>,
 751                                                                          <&imgsys CLK_IMG_IPE>,
 752                                                                          <&ipesys CLK_IPE_SMI_LARB12>;
 753                                                                 clock-names = "ipe", "ipe-0", "ipe-1";
 754                                                                 mediatek,infracfg = <&infracfg_ao>;
 755                                                                 #power-domain-cells = <0>;
 756                                                         };
 757                                                 };
 758
 759                                                 power-domain@MT8195_POWER_DOMAIN_CAM {
 760                                                         reg = <MT8195_POWER_DOMAIN_CAM>;
 761                                                         clocks = <&camsys CLK_CAM_LARB13>,
 762                                                                  <&camsys CLK_CAM_LARB14>,
 763                                                                  <&camsys CLK_CAM_CAM2MM0_GALS>,
 764                                                                  <&camsys CLK_CAM_CAM2MM1_GALS>,
 765                                                                  <&camsys CLK_CAM_CAM2SYS_GALS>;
 766                                                         clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
 767                                                                       "cam-4";
 768                                                         mediatek,infracfg = <&infracfg_ao>;
 769                                                         #address-cells = <1>;
 770                                                         #size-cells = <0>;
 771                                                         #power-domain-cells = <1>;
 772
 773                                                         power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
 774                                                                 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
 775                                                                 #power-domain-cells = <0>;
 776                                                         };
 777
 778                                                         power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
 779                                                                 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
 780                                                                 #power-domain-cells = <0>;
 781                                                         };
 782
 783                                                         power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
 784                                                                 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
 785                                                                 #power-domain-cells = <0>;
 786                                                         };
 787                                                 };
 788                                         };
 789                                 };
 790
 791                                 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
 792                                         reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
 793                                         mediatek,infracfg = <&infracfg_ao>;
 794                                         #power-domain-cells = <0>;
 795                                 };
 796
 797                                 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
 798                                         reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
 799                                         mediatek,infracfg = <&infracfg_ao>;
 800                                         #power-domain-cells = <0>;
 801                                 };
 802
 803                                 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
 804                                         reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
 805                                         #power-domain-cells = <0>;
 806                                 };
 807
 808                                 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
 809                                         reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
 810                                         #power-domain-cells = <0>;
 811                                 };
 812
 813                                 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
 814                                         reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
 815                                         clocks = <&topckgen CLK_TOP_SENINF>,
 816                                                  <&topckgen CLK_TOP_SENINF2>;
 817                                         clock-names = "csi_rx_top", "csi_rx_top1";
 818                                         #power-domain-cells = <0>;
 819                                 };
 820
 821                                 power-domain@MT8195_POWER_DOMAIN_ETHER {
 822                                         reg = <MT8195_POWER_DOMAIN_ETHER>;
 823                                         clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
 824                                         clock-names = "ether";
 825                                         #power-domain-cells = <0>;
 826                                 };
 827
 828                                 power-domain@MT8195_POWER_DOMAIN_ADSP {
 829                                         reg = <MT8195_POWER_DOMAIN_ADSP>;
 830                                         clocks = <&topckgen CLK_TOP_ADSP>,
 831                                                  <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
 832                                         clock-names = "adsp", "adsp1";
 833                                         #address-cells = <1>;
 834                                         #size-cells = <0>;
 835                                         mediatek,infracfg = <&infracfg_ao>;
 836                                         #power-domain-cells = <1>;
 837
 838                                         power-domain@MT8195_POWER_DOMAIN_AUDIO {
 839                                                 reg = <MT8195_POWER_DOMAIN_AUDIO>;
 840                                                 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
 841                                                          <&topckgen CLK_TOP_AUD_INTBUS>,
 842                                                          <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
 843                                                          <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
 844                                                 clock-names = "audio", "audio1", "audio2",
 845                                                               "audio3";
 846                                                 mediatek,infracfg = <&infracfg_ao>;
 847                                                 #power-domain-cells = <0>;
 848                                         };
 849                                 };
 850                         };
 851                 };
 852
 853                 watchdog: watchdog@10007000 {
 854                         compatible = "mediatek,mt8195-wdt";
 855                         mediatek,disable-extrst;
 856                         reg = <0 0x10007000 0 0x100>;
 857                         #reset-cells = <1>;
 858                 };
 859
 860                 apmixedsys: syscon@1000c000 {
 861                         compatible = "mediatek,mt8195-apmixedsys", "syscon";
 862                         reg = <0 0x1000c000 0 0x1000>;
 863                         #clock-cells = <1>;
 864                 };
 865
 866                 systimer: timer@10017000 {
 867                         compatible = "mediatek,mt8195-timer",
 868                                      "mediatek,mt6765-timer";
 869                         reg = <0 0x10017000 0 0x1000>;
 870                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
 871                         clocks = <&clk13m>;
 872                 };
 873
 874                 pwrap: pwrap@10024000 {
 875                         compatible = "mediatek,mt8195-pwrap", "syscon";
 876                         reg = <0 0x10024000 0 0x1000>;
 877                         reg-names = "pwrap";
 878                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
 879                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
 880                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
 881                         clock-names = "spi", "wrap";
 882                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
 883                         assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
 884                 };
 885
 886                 spmi: spmi@10027000 {
 887                         compatible = "mediatek,mt8195-spmi";
 888                         reg = <0 0x10027000 0 0x000e00>,
 889                               <0 0x10029000 0 0x000100>;
 890                         reg-names = "pmif", "spmimst";
 891                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
 892                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
 893                                  <&topckgen CLK_TOP_SPMI_M_MST>;
 894                         clock-names = "pmif_sys_ck",
 895                                       "pmif_tmr_ck",
 896                                       "spmimst_clk_mux";
 897                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
 898                         assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
 899                 };
 900
 901                 iommu_infra: infra-iommu@10315000 {
 902                         compatible = "mediatek,mt8195-iommu-infra";
 903                         reg = <0 0x10315000 0 0x5000>;
 904                         interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
 905                                      <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
 906                                      <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
 907                                      <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
 908                                      <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
 909                         #iommu-cells = <1>;
 910                 };
 911
 912                 gce0: mailbox@10320000 {
 913                         compatible = "mediatek,mt8195-gce";
 914                         reg = <0 0x10320000 0 0x4000>;
 915                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
 916                         #mbox-cells = <2>;
 917                         clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
 918                 };
 919
 920                 gce1: mailbox@10330000 {
 921                         compatible = "mediatek,mt8195-gce";
 922                         reg = <0 0x10330000 0 0x4000>;
 923                         interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
 924                         #mbox-cells = <2>;
 925                         clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
 926                 };
 927
 928                 scp: scp@10500000 {
 929                         compatible = "mediatek,mt8195-scp";
 930                         reg = <0 0x10500000 0 0x100000>,
 931                               <0 0x10720000 0 0xe0000>,
 932                               <0 0x10700000 0 0x8000>;
 933                         reg-names = "sram", "cfg", "l1tcm";
 934                         interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
 935                         status = "disabled";
 936                 };
 937
 938                 scp_adsp: clock-controller@10720000 {
 939                         compatible = "mediatek,mt8195-scp_adsp";
 940                         reg = <0 0x10720000 0 0x1000>;
 941                         #clock-cells = <1>;
 942                 };
 943
 944                 adsp: dsp@10803000 {
 945                         compatible = "mediatek,mt8195-dsp";
 946                         reg = <0 0x10803000 0 0x1000>,
 947                               <0 0x10840000 0 0x40000>;
 948                         reg-names = "cfg", "sram";
 949                         clocks = <&topckgen CLK_TOP_ADSP>,
 950                                  <&clk26m>,
 951                                  <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
 952                                  <&topckgen CLK_TOP_MAINPLL_D7_D2>,
 953                                  <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
 954                                  <&topckgen CLK_TOP_AUDIO_H>;
 955                         clock-names = "adsp_sel",
 956                                  "clk26m_ck",
 957                                  "audio_local_bus",
 958                                  "mainpll_d7_d2",
 959                                  "scp_adsp_audiodsp",
 960                                  "audio_h";
 961                         power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
 962                         mbox-names = "rx", "tx";
 963                         mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
 964                         status = "disabled";
 965                 };
 966
 967                 adsp_mailbox0: mailbox@10816000 {
 968                         compatible = "mediatek,mt8195-adsp-mbox";
 969                         #mbox-cells = <0>;
 970                         reg = <0 0x10816000 0 0x1000>;
 971                         interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
 972                 };
 973
 974                 adsp_mailbox1: mailbox@10817000 {
 975                         compatible = "mediatek,mt8195-adsp-mbox";
 976                         #mbox-cells = <0>;
 977                         reg = <0 0x10817000 0 0x1000>;
 978                         interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
 979                 };
 980
 981                 afe: mt8195-afe-pcm@10890000 {
 982                         compatible = "mediatek,mt8195-audio";
 983                         reg = <0 0x10890000 0 0x10000>;
 984                         mediatek,topckgen = <&topckgen>;
 985                         power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
 986                         interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
 987                         resets = <&watchdog 14>;
 988                         reset-names = "audiosys";
 989                         clocks = <&clk26m>,
 990                                 <&apmixedsys CLK_APMIXED_APLL1>,
 991                                 <&apmixedsys CLK_APMIXED_APLL2>,
 992                                 <&topckgen CLK_TOP_APLL12_DIV0>,
 993                                 <&topckgen CLK_TOP_APLL12_DIV1>,
 994                                 <&topckgen CLK_TOP_APLL12_DIV2>,
 995                                 <&topckgen CLK_TOP_APLL12_DIV3>,
 996                                 <&topckgen CLK_TOP_APLL12_DIV9>,
 997                                 <&topckgen CLK_TOP_A1SYS_HP>,
 998                                 <&topckgen CLK_TOP_AUD_INTBUS>,
 999                                 <&topckgen CLK_TOP_AUDIO_H>,
1000                                 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
1001                                 <&topckgen CLK_TOP_DPTX_MCK>,
1002                                 <&topckgen CLK_TOP_I2SO1_MCK>,
1003                                 <&topckgen CLK_TOP_I2SO2_MCK>,
1004                                 <&topckgen CLK_TOP_I2SI1_MCK>,
1005                                 <&topckgen CLK_TOP_I2SI2_MCK>,
1006                                 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
1007                                 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
1008                         clock-names = "clk26m",
1009                                 "apll1_ck",
1010                                 "apll2_ck",
1011                                 "apll12_div0",
1012                                 "apll12_div1",
1013                                 "apll12_div2",
1014                                 "apll12_div3",
1015                                 "apll12_div9",
1016                                 "a1sys_hp_sel",
1017                                 "aud_intbus_sel",
1018                                 "audio_h_sel",
1019                                 "audio_local_bus_sel",
1020                                 "dptx_m_sel",
1021                                 "i2so1_m_sel",
1022                                 "i2so2_m_sel",
1023                                 "i2si1_m_sel",
1024                                 "i2si2_m_sel",
1025                                 "infra_ao_audio_26m_b",
1026                                 "scp_adsp_audiodsp";
1027                         status = "disabled";
1028                 };
1029
1030                 uart0: serial@11001100 {
1031                         compatible = "mediatek,mt8195-uart",
1032                                      "mediatek,mt6577-uart";
1033                         reg = <0 0x11001100 0 0x100>;
1034                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
1035                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1036                         clock-names = "baud", "bus";
1037                         status = "disabled";
1038                 };
1039
1040                 uart1: serial@11001200 {
1041                         compatible = "mediatek,mt8195-uart",
1042                                      "mediatek,mt6577-uart";
1043                         reg = <0 0x11001200 0 0x100>;
1044                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
1045                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1046                         clock-names = "baud", "bus";
1047                         status = "disabled";
1048                 };
1049
1050                 uart2: serial@11001300 {
1051                         compatible = "mediatek,mt8195-uart",
1052                                      "mediatek,mt6577-uart";
1053                         reg = <0 0x11001300 0 0x100>;
1054                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1055                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1056                         clock-names = "baud", "bus";
1057                         status = "disabled";
1058                 };
1059
1060                 uart3: serial@11001400 {
1061                         compatible = "mediatek,mt8195-uart",
1062                                      "mediatek,mt6577-uart";
1063                         reg = <0 0x11001400 0 0x100>;
1064                         interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
1065                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1066                         clock-names = "baud", "bus";
1067                         status = "disabled";
1068                 };
1069
1070                 uart4: serial@11001500 {
1071                         compatible = "mediatek,mt8195-uart",
1072                                      "mediatek,mt6577-uart";
1073                         reg = <0 0x11001500 0 0x100>;
1074                         interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
1075                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
1076                         clock-names = "baud", "bus";
1077                         status = "disabled";
1078                 };
1079
1080                 uart5: serial@11001600 {
1081                         compatible = "mediatek,mt8195-uart",
1082                                      "mediatek,mt6577-uart";
1083                         reg = <0 0x11001600 0 0x100>;
1084                         interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
1085                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
1086                         clock-names = "baud", "bus";
1087                         status = "disabled";
1088                 };
1089
1090                 auxadc: auxadc@11002000 {
1091                         compatible = "mediatek,mt8195-auxadc",
1092                                      "mediatek,mt8173-auxadc";
1093                         reg = <0 0x11002000 0 0x1000>;
1094                         clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1095                         clock-names = "main";
1096                         #io-channel-cells = <1>;
1097                         status = "disabled";
1098                 };
1099
1100                 pericfg_ao: syscon@11003000 {
1101                         compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1102                         reg = <0 0x11003000 0 0x1000>;
1103                         #clock-cells = <1>;
1104                 };
1105
1106                 spi0: spi@1100a000 {
1107                         compatible = "mediatek,mt8195-spi",
1108                                      "mediatek,mt6765-spi";
1109                         #address-cells = <1>;
1110                         #size-cells = <0>;
1111                         reg = <0 0x1100a000 0 0x1000>;
1112                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
1113                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1114                                  <&topckgen CLK_TOP_SPI>,
1115                                  <&infracfg_ao CLK_INFRA_AO_SPI0>;
1116                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1117                         status = "disabled";
1118                 };
1119
1120                 lvts_ap: thermal-sensor@1100b000 {
1121                         compatible = "mediatek,mt8195-lvts-ap";
1122                         reg = <0 0x1100b000 0 0xc00>;
1123                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1124                         clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1125                         resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
1126                         nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1127                         nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1128                         #thermal-sensor-cells = <1>;
1129                 };
1130
1131                 svs: svs@1100bc00 {
1132                         compatible = "mediatek,mt8195-svs";
1133                         reg = <0 0x1100bc00 0 0x400>;
1134                         interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>;
1135                         clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1136                         clock-names = "main";
1137                         nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
1138                         nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
1139                         resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>;
1140                         reset-names = "svs_rst";
1141                 };
1142
1143                 disp_pwm0: pwm@1100e000 {
1144                         compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1145                         reg = <0 0x1100e000 0 0x1000>;
1146                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
1147                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1148                         #pwm-cells = <2>;
1149                         clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1150                                  <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1151                         clock-names = "main", "mm";
1152                         status = "disabled";
1153                 };
1154
1155                 disp_pwm1: pwm@1100f000 {
1156                         compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1157                         reg = <0 0x1100f000 0 0x1000>;
1158                         interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
1159                         #pwm-cells = <2>;
1160                         clocks = <&topckgen CLK_TOP_DISP_PWM1>,
1161                                  <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
1162                         clock-names = "main", "mm";
1163                         status = "disabled";
1164                 };
1165
1166                 spi1: spi@11010000 {
1167                         compatible = "mediatek,mt8195-spi",
1168                                      "mediatek,mt6765-spi";
1169                         #address-cells = <1>;
1170                         #size-cells = <0>;
1171                         reg = <0 0x11010000 0 0x1000>;
1172                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
1173                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1174                                  <&topckgen CLK_TOP_SPI>,
1175                                  <&infracfg_ao CLK_INFRA_AO_SPI1>;
1176                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1177                         status = "disabled";
1178                 };
1179
1180                 spi2: spi@11012000 {
1181                         compatible = "mediatek,mt8195-spi",
1182                                      "mediatek,mt6765-spi";
1183                         #address-cells = <1>;
1184                         #size-cells = <0>;
1185                         reg = <0 0x11012000 0 0x1000>;
1186                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
1187                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1188                                  <&topckgen CLK_TOP_SPI>,
1189                                  <&infracfg_ao CLK_INFRA_AO_SPI2>;
1190                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1191                         status = "disabled";
1192                 };
1193
1194                 spi3: spi@11013000 {
1195                         compatible = "mediatek,mt8195-spi",
1196                                      "mediatek,mt6765-spi";
1197                         #address-cells = <1>;
1198                         #size-cells = <0>;
1199                         reg = <0 0x11013000 0 0x1000>;
1200                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1201                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1202                                  <&topckgen CLK_TOP_SPI>,
1203                                  <&infracfg_ao CLK_INFRA_AO_SPI3>;
1204                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1205                         status = "disabled";
1206                 };
1207
1208                 spi4: spi@11018000 {
1209                         compatible = "mediatek,mt8195-spi",
1210                                      "mediatek,mt6765-spi";
1211                         #address-cells = <1>;
1212                         #size-cells = <0>;
1213                         reg = <0 0x11018000 0 0x1000>;
1214                         interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1215                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1216                                  <&topckgen CLK_TOP_SPI>,
1217                                  <&infracfg_ao CLK_INFRA_AO_SPI4>;
1218                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1219                         status = "disabled";
1220                 };
1221
1222                 spi5: spi@11019000 {
1223                         compatible = "mediatek,mt8195-spi",
1224                                      "mediatek,mt6765-spi";
1225                         #address-cells = <1>;
1226                         #size-cells = <0>;
1227                         reg = <0 0x11019000 0 0x1000>;
1228                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1229                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1230                                  <&topckgen CLK_TOP_SPI>,
1231                                  <&infracfg_ao CLK_INFRA_AO_SPI5>;
1232                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1233                         status = "disabled";
1234                 };
1235
1236                 spis0: spi@1101d000 {
1237                         compatible = "mediatek,mt8195-spi-slave";
1238                         reg = <0 0x1101d000 0 0x1000>;
1239                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
1240                         clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1241                         clock-names = "spi";
1242                         assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1243                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1244                         status = "disabled";
1245                 };
1246
1247                 spis1: spi@1101e000 {
1248                         compatible = "mediatek,mt8195-spi-slave";
1249                         reg = <0 0x1101e000 0 0x1000>;
1250                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1251                         clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1252                         clock-names = "spi";
1253                         assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1254                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1255                         status = "disabled";
1256                 };
1257
1258                 eth: ethernet@11021000 {
1259                         compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1260                         reg = <0 0x11021000 0 0x4000>;
1261                         interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
1262                         interrupt-names = "macirq";
1263                         clock-names = "axi",
1264                                       "apb",
1265                                       "mac_main",
1266                                       "ptp_ref",
1267                                       "rmii_internal",
1268                                       "mac_cg";
1269                         clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
1270                                  <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
1271                                  <&topckgen CLK_TOP_SNPS_ETH_250M>,
1272                                  <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1273                                  <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1274                                  <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1275                         assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1276                                           <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1277                                           <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1278                         assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1279                                                  <&topckgen CLK_TOP_ETHPLL_D8>,
1280                                                  <&topckgen CLK_TOP_ETHPLL_D10>;
1281                         power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1282                         mediatek,pericfg = <&infracfg_ao>;
1283                         snps,axi-config = <&stmmac_axi_setup>;
1284                         snps,mtl-rx-config = <&mtl_rx_setup>;
1285                         snps,mtl-tx-config = <&mtl_tx_setup>;
1286                         snps,txpbl = <16>;
1287                         snps,rxpbl = <16>;
1288                         snps,clk-csr = <0>;
1289                         status = "disabled";
1290
1291                         mdio {
1292                                 compatible = "snps,dwmac-mdio";
1293                                 #address-cells = <1>;
1294                                 #size-cells = <0>;
1295                         };
1296
1297                         stmmac_axi_setup: stmmac-axi-config {
1298                                 snps,wr_osr_lmt = <0x7>;
1299                                 snps,rd_osr_lmt = <0x7>;
1300                                 snps,blen = <0 0 0 0 16 8 4>;
1301                         };
1302
1303                         mtl_rx_setup: rx-queues-config {
1304                                 snps,rx-queues-to-use = <4>;
1305                                 snps,rx-sched-sp;
1306                                 queue0 {
1307                                         snps,dcb-algorithm;
1308                                         snps,map-to-dma-channel = <0x0>;
1309                                 };
1310                                 queue1 {
1311                                         snps,dcb-algorithm;
1312                                         snps,map-to-dma-channel = <0x0>;
1313                                 };
1314                                 queue2 {
1315                                         snps,dcb-algorithm;
1316                                         snps,map-to-dma-channel = <0x0>;
1317                                 };
1318                                 queue3 {
1319                                         snps,dcb-algorithm;
1320                                         snps,map-to-dma-channel = <0x0>;
1321                                 };
1322                         };
1323
1324                         mtl_tx_setup: tx-queues-config {
1325                                 snps,tx-queues-to-use = <4>;
1326                                 snps,tx-sched-wrr;
1327                                 queue0 {
1328                                         snps,weight = <0x10>;
1329                                         snps,dcb-algorithm;
1330                                         snps,priority = <0x0>;
1331                                 };
1332                                 queue1 {
1333                                         snps,weight = <0x11>;
1334                                         snps,dcb-algorithm;
1335                                         snps,priority = <0x1>;
1336                                 };
1337                                 queue2 {
1338                                         snps,weight = <0x12>;
1339                                         snps,dcb-algorithm;
1340                                         snps,priority = <0x2>;
1341                                 };
1342                                 queue3 {
1343                                         snps,weight = <0x13>;
1344                                         snps,dcb-algorithm;
1345                                         snps,priority = <0x3>;
1346                                 };
1347                         };
1348                 };
1349
1350                 xhci0: usb@11200000 {
1351                         compatible = "mediatek,mt8195-xhci",
1352                                      "mediatek,mtk-xhci";
1353                         reg = <0 0x11200000 0 0x1000>,
1354                               <0 0x11203e00 0 0x0100>;
1355                         reg-names = "mac", "ippc";
1356                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1357                         phys = <&u2port0 PHY_TYPE_USB2>,
1358                                <&u3port0 PHY_TYPE_USB3>;
1359                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1360                                           <&topckgen CLK_TOP_SSUSB_XHCI>;
1361                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1362                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1363                         clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1364                                  <&topckgen CLK_TOP_SSUSB_REF>,
1365                                  <&apmixedsys CLK_APMIXED_USB1PLL>,
1366                                  <&clk26m>,
1367                                  <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1368                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1369                                       "xhci_ck";
1370                         mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1371                         wakeup-source;
1372                         status = "disabled";
1373                 };
1374
1375                 mmc0: mmc@11230000 {
1376                         compatible = "mediatek,mt8195-mmc",
1377                                      "mediatek,mt8183-mmc";
1378                         reg = <0 0x11230000 0 0x10000>,
1379                               <0 0x11f50000 0 0x1000>;
1380                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1381                         clocks = <&topckgen CLK_TOP_MSDC50_0>,
1382                                  <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1383                                  <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1384                         clock-names = "source", "hclk", "source_cg";
1385                         status = "disabled";
1386                 };
1387
1388                 mmc1: mmc@11240000 {
1389                         compatible = "mediatek,mt8195-mmc",
1390                                      "mediatek,mt8183-mmc";
1391                         reg = <0 0x11240000 0 0x1000>,
1392                               <0 0x11c70000 0 0x1000>;
1393                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1394                         clocks = <&topckgen CLK_TOP_MSDC30_1>,
1395                                  <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1396                                  <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1397                         clock-names = "source", "hclk", "source_cg";
1398                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1399                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1400                         status = "disabled";
1401                 };
1402
1403                 mmc2: mmc@11250000 {
1404                         compatible = "mediatek,mt8195-mmc",
1405                                      "mediatek,mt8183-mmc";
1406                         reg = <0 0x11250000 0 0x1000>,
1407                               <0 0x11e60000 0 0x1000>;
1408                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
1409                         clocks = <&topckgen CLK_TOP_MSDC30_2>,
1410                                  <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1411                                  <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1412                         clock-names = "source", "hclk", "source_cg";
1413                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1414                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1415                         status = "disabled";
1416                 };
1417
1418                 lvts_mcu: thermal-sensor@11278000 {
1419                         compatible = "mediatek,mt8195-lvts-mcu";
1420                         reg = <0 0x11278000 0 0x1000>;
1421                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1422                         clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1423                         resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
1424                         nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1425                         nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1426                         #thermal-sensor-cells = <1>;
1427                 };
1428
1429                 xhci1: usb@11290000 {
1430                         compatible = "mediatek,mt8195-xhci",
1431                                      "mediatek,mtk-xhci";
1432                         reg = <0 0x11290000 0 0x1000>,
1433                               <0 0x11293e00 0 0x0100>;
1434                         reg-names = "mac", "ippc";
1435                         interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1436                         phys = <&u2port1 PHY_TYPE_USB2>;
1437                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1438                                           <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1439                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1440                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1441                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1442                                  <&topckgen CLK_TOP_SSUSB_P1_REF>,
1443                                  <&apmixedsys CLK_APMIXED_USB1PLL>,
1444                                  <&clk26m>,
1445                                  <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
1446                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1447                                       "xhci_ck";
1448                         mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1449                         wakeup-source;
1450                         status = "disabled";
1451                 };
1452
1453                 xhci2: usb@112a0000 {
1454                         compatible = "mediatek,mt8195-xhci",
1455                                      "mediatek,mtk-xhci";
1456                         reg = <0 0x112a0000 0 0x1000>,
1457                               <0 0x112a3e00 0 0x0100>;
1458                         reg-names = "mac", "ippc";
1459                         interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1460                         phys = <&u2port2 PHY_TYPE_USB2>;
1461                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1462                                           <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1463                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1464                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1465                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1466                                  <&topckgen CLK_TOP_SSUSB_P2_REF>,
1467                                  <&clk26m>,
1468                                  <&clk26m>,
1469                                  <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1470                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1471                                       "xhci_ck";
1472                         mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1473                         wakeup-source;
1474                         status = "disabled";
1475                 };
1476
1477                 xhci3: usb@112b0000 {
1478                         compatible = "mediatek,mt8195-xhci",
1479                                      "mediatek,mtk-xhci";
1480                         reg = <0 0x112b0000 0 0x1000>,
1481                               <0 0x112b3e00 0 0x0100>;
1482                         reg-names = "mac", "ippc";
1483                         interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1484                         phys = <&u2port3 PHY_TYPE_USB2>;
1485                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1486                                           <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1487                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1488                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1489                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1490                                  <&topckgen CLK_TOP_SSUSB_P3_REF>,
1491                                  <&clk26m>,
1492                                  <&clk26m>,
1493                                  <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1494                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1495                                       "xhci_ck";
1496                         mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1497                         wakeup-source;
1498                         status = "disabled";
1499                 };
1500
1501                 pcie0: pcie@112f0000 {
1502                         compatible = "mediatek,mt8195-pcie",
1503                                      "mediatek,mt8192-pcie";
1504                         device_type = "pci";
1505                         #address-cells = <3>;
1506                         #size-cells = <2>;
1507                         reg = <0 0x112f0000 0 0x4000>;
1508                         reg-names = "pcie-mac";
1509                         interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
1510                         bus-range = <0x00 0xff>;
1511                         ranges = <0x81000000 0 0x20000000
1512                                   0x0 0x20000000 0 0x200000>,
1513                                  <0x82000000 0 0x20200000
1514                                   0x0 0x20200000 0 0x3e00000>;
1515
1516                         iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1517                         iommu-map-mask = <0x0>;
1518
1519                         clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
1520                                  <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
1521                                  <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1522                                  <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
1523                                  <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1524                                  <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1525                         clock-names = "pl_250m", "tl_26m", "tl_96m",
1526                                       "tl_32k", "peri_26m", "peri_mem";
1527                         assigned-clocks = <&topckgen CLK_TOP_TL>;
1528                         assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1529
1530                         phys = <&pciephy>;
1531                         phy-names = "pcie-phy";
1532
1533                         power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1534
1535                         resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
1536                         reset-names = "mac";
1537
1538                         #interrupt-cells = <1>;
1539                         interrupt-map-mask = <0 0 0 7>;
1540                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1541                                         <0 0 0 2 &pcie_intc0 1>,
1542                                         <0 0 0 3 &pcie_intc0 2>,
1543                                         <0 0 0 4 &pcie_intc0 3>;
1544                         status = "disabled";
1545
1546                         pcie_intc0: interrupt-controller {
1547                                 interrupt-controller;
1548                                 #address-cells = <0>;
1549                                 #interrupt-cells = <1>;
1550                         };
1551                 };
1552
1553                 pcie1: pcie@112f8000 {
1554                         compatible = "mediatek,mt8195-pcie",
1555                                      "mediatek,mt8192-pcie";
1556                         device_type = "pci";
1557                         #address-cells = <3>;
1558                         #size-cells = <2>;
1559                         reg = <0 0x112f8000 0 0x4000>;
1560                         reg-names = "pcie-mac";
1561                         interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
1562                         bus-range = <0x00 0xff>;
1563                         ranges = <0x81000000 0 0x24000000
1564                                   0x0 0x24000000 0 0x200000>,
1565                                  <0x82000000 0 0x24200000
1566                                   0x0 0x24200000 0 0x3e00000>;
1567
1568                         iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1569                         iommu-map-mask = <0x0>;
1570
1571                         clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1572                                  <&clk26m>,
1573                                  <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
1574                                  <&clk26m>,
1575                                  <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
1576                                  /* Designer has connect pcie1 with peri_mem_p0 clock */
1577                                  <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1578                         clock-names = "pl_250m", "tl_26m", "tl_96m",
1579                                       "tl_32k", "peri_26m", "peri_mem";
1580                         assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1581                         assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1582
1583                         phys = <&u3port1 PHY_TYPE_PCIE>;
1584                         phy-names = "pcie-phy";
1585                         power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1586
1587                         resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
1588                         reset-names = "mac";
1589
1590                         #interrupt-cells = <1>;
1591                         interrupt-map-mask = <0 0 0 7>;
1592                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1593                                         <0 0 0 2 &pcie_intc1 1>,
1594                                         <0 0 0 3 &pcie_intc1 2>,
1595                                         <0 0 0 4 &pcie_intc1 3>;
1596                         status = "disabled";
1597
1598                         pcie_intc1: interrupt-controller {
1599                                 interrupt-controller;
1600                                 #address-cells = <0>;
1601                                 #interrupt-cells = <1>;
1602                         };
1603                 };
1604
1605                 nor_flash: spi@1132c000 {
1606                         compatible = "mediatek,mt8195-nor",
1607                                      "mediatek,mt8173-nor";
1608                         reg = <0 0x1132c000 0 0x1000>;
1609                         interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1610                         clocks = <&topckgen CLK_TOP_SPINOR>,
1611                                  <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1612                                  <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1613                         clock-names = "spi", "sf", "axi";
1614                         #address-cells = <1>;
1615                         #size-cells = <0>;
1616                         status = "disabled";
1617                 };
1618
1619                 efuse: efuse@11c10000 {
1620                         compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1621                         reg = <0 0x11c10000 0 0x1000>;
1622                         #address-cells = <1>;
1623                         #size-cells = <1>;
1624                         u3_tx_imp_p0: usb3-tx-imp@184,1 {
1625                                 reg = <0x184 0x1>;
1626                                 bits = <0 5>;
1627                         };
1628                         u3_rx_imp_p0: usb3-rx-imp@184,2 {
1629                                 reg = <0x184 0x2>;
1630                                 bits = <5 5>;
1631                         };
1632                         u3_intr_p0: usb3-intr@185 {
1633                                 reg = <0x185 0x1>;
1634                                 bits = <2 6>;
1635                         };
1636                         comb_tx_imp_p1: usb3-tx-imp@186,1 {
1637                                 reg = <0x186 0x1>;
1638                                 bits = <0 5>;
1639                         };
1640                         comb_rx_imp_p1: usb3-rx-imp@186,2 {
1641                                 reg = <0x186 0x2>;
1642                                 bits = <5 5>;
1643                         };
1644                         comb_intr_p1: usb3-intr@187 {
1645                                 reg = <0x187 0x1>;
1646                                 bits = <2 6>;
1647                         };
1648                         u2_intr_p0: usb2-intr-p0@188,1 {
1649                                 reg = <0x188 0x1>;
1650                                 bits = <0 5>;
1651                         };
1652                         u2_intr_p1: usb2-intr-p1@188,2 {
1653                                 reg = <0x188 0x2>;
1654                                 bits = <5 5>;
1655                         };
1656                         u2_intr_p2: usb2-intr-p2@189,1 {
1657                                 reg = <0x189 0x1>;
1658                                 bits = <2 5>;
1659                         };
1660                         u2_intr_p3: usb2-intr-p3@189,2 {
1661                                 reg = <0x189 0x2>;
1662                                 bits = <7 5>;
1663                         };
1664                         pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1665                                 reg = <0x190 0x1>;
1666                                 bits = <0 4>;
1667                         };
1668                         pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1669                                 reg = <0x190 0x1>;
1670                                 bits = <4 4>;
1671                         };
1672                         pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1673                                 reg = <0x191 0x1>;
1674                                 bits = <0 4>;
1675                         };
1676                         pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1677                                 reg = <0x191 0x1>;
1678                                 bits = <4 4>;
1679                         };
1680                         pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1681                                 reg = <0x192 0x1>;
1682                                 bits = <0 4>;
1683                         };
1684                         pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1685                                 reg = <0x192 0x1>;
1686                                 bits = <4 4>;
1687                         };
1688                         pciephy_glb_intr: pciephy-glb-intr@193 {
1689                                 reg = <0x193 0x1>;
1690                                 bits = <0 4>;
1691                         };
1692                         dp_calibration: dp-data@1ac {
1693                                 reg = <0x1ac 0x10>;
1694                         };
1695                         lvts_efuse_data1: lvts1-calib@1bc {
1696                                 reg = <0x1bc 0x14>;
1697                         };
1698                         lvts_efuse_data2: lvts2-calib@1d0 {
1699                                 reg = <0x1d0 0x38>;
1700                         };
1701                         svs_calib_data: svs-calib@580 {
1702                                 reg = <0x580 0x64>;
1703                         };
1704                 };
1705
1706                 u3phy2: t-phy@11c40000 {
1707                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1708                         #address-cells = <1>;
1709                         #size-cells = <1>;
1710                         ranges = <0 0 0x11c40000 0x700>;
1711                         status = "disabled";
1712
1713                         u2port2: usb-phy@0 {
1714                                 reg = <0x0 0x700>;
1715                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1716                                 clock-names = "ref";
1717                                 #phy-cells = <1>;
1718                         };
1719                 };
1720
1721                 u3phy3: t-phy@11c50000 {
1722                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1723                         #address-cells = <1>;
1724                         #size-cells = <1>;
1725                         ranges = <0 0 0x11c50000 0x700>;
1726                         status = "disabled";
1727
1728                         u2port3: usb-phy@0 {
1729                                 reg = <0x0 0x700>;
1730                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1731                                 clock-names = "ref";
1732                                 #phy-cells = <1>;
1733                         };
1734                 };
1735
1736                 mipi_tx0: dsi-phy@11c80000 {
1737                         compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1738                         reg = <0 0x11c80000 0 0x1000>;
1739                         clocks = <&clk26m>;
1740                         clock-output-names = "mipi_tx0_pll";
1741                         #clock-cells = <0>;
1742                         #phy-cells = <0>;
1743                         status = "disabled";
1744                 };
1745
1746                 mipi_tx1: dsi-phy@11c90000 {
1747                         compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
1748                         reg = <0 0x11c90000 0 0x1000>;
1749                         clocks = <&clk26m>;
1750                         clock-output-names = "mipi_tx1_pll";
1751                         #clock-cells = <0>;
1752                         #phy-cells = <0>;
1753                         status = "disabled";
1754                 };
1755
1756                 i2c5: i2c@11d00000 {
1757                         compatible = "mediatek,mt8195-i2c",
1758                                      "mediatek,mt8192-i2c";
1759                         reg = <0 0x11d00000 0 0x1000>,
1760                               <0 0x10220580 0 0x80>;
1761                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
1762                         clock-div = <1>;
1763                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
1764                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1765                         clock-names = "main", "dma";
1766                         #address-cells = <1>;
1767                         #size-cells = <0>;
1768                         status = "disabled";
1769                 };
1770
1771                 i2c6: i2c@11d01000 {
1772                         compatible = "mediatek,mt8195-i2c",
1773                                      "mediatek,mt8192-i2c";
1774                         reg = <0 0x11d01000 0 0x1000>,
1775                               <0 0x10220600 0 0x80>;
1776                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
1777                         clock-div = <1>;
1778                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
1779                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1780                         clock-names = "main", "dma";
1781                         #address-cells = <1>;
1782                         #size-cells = <0>;
1783                         status = "disabled";
1784                 };
1785
1786                 i2c7: i2c@11d02000 {
1787                         compatible = "mediatek,mt8195-i2c",
1788                                      "mediatek,mt8192-i2c";
1789                         reg = <0 0x11d02000 0 0x1000>,
1790                               <0 0x10220680 0 0x80>;
1791                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1792                         clock-div = <1>;
1793                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1794                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1795                         clock-names = "main", "dma";
1796                         #address-cells = <1>;
1797                         #size-cells = <0>;
1798                         status = "disabled";
1799                 };
1800
1801                 imp_iic_wrap_s: clock-controller@11d03000 {
1802                         compatible = "mediatek,mt8195-imp_iic_wrap_s";
1803                         reg = <0 0x11d03000 0 0x1000>;
1804                         #clock-cells = <1>;
1805                 };
1806
1807                 i2c0: i2c@11e00000 {
1808                         compatible = "mediatek,mt8195-i2c",
1809                                      "mediatek,mt8192-i2c";
1810                         reg = <0 0x11e00000 0 0x1000>,
1811                               <0 0x10220080 0 0x80>;
1812                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
1813                         clock-div = <1>;
1814                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
1815                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1816                         clock-names = "main", "dma";
1817                         #address-cells = <1>;
1818                         #size-cells = <0>;
1819                         status = "disabled";
1820                 };
1821
1822                 i2c1: i2c@11e01000 {
1823                         compatible = "mediatek,mt8195-i2c",
1824                                      "mediatek,mt8192-i2c";
1825                         reg = <0 0x11e01000 0 0x1000>,
1826                               <0 0x10220200 0 0x80>;
1827                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1828                         clock-div = <1>;
1829                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
1830                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1831                         clock-names = "main", "dma";
1832                         #address-cells = <1>;
1833                         #size-cells = <0>;
1834                         status = "disabled";
1835                 };
1836
1837                 i2c2: i2c@11e02000 {
1838                         compatible = "mediatek,mt8195-i2c",
1839                                      "mediatek,mt8192-i2c";
1840                         reg = <0 0x11e02000 0 0x1000>,
1841                               <0 0x10220380 0 0x80>;
1842                         interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1843                         clock-div = <1>;
1844                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
1845                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1846                         clock-names = "main", "dma";
1847                         #address-cells = <1>;
1848                         #size-cells = <0>;
1849                         status = "disabled";
1850                 };
1851
1852                 i2c3: i2c@11e03000 {
1853                         compatible = "mediatek,mt8195-i2c",
1854                                      "mediatek,mt8192-i2c";
1855                         reg = <0 0x11e03000 0 0x1000>,
1856                               <0 0x10220480 0 0x80>;
1857                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1858                         clock-div = <1>;
1859                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
1860                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1861                         clock-names = "main", "dma";
1862                         #address-cells = <1>;
1863                         #size-cells = <0>;
1864                         status = "disabled";
1865                 };
1866
1867                 i2c4: i2c@11e04000 {
1868                         compatible = "mediatek,mt8195-i2c",
1869                                      "mediatek,mt8192-i2c";
1870                         reg = <0 0x11e04000 0 0x1000>,
1871                               <0 0x10220500 0 0x80>;
1872                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
1873                         clock-div = <1>;
1874                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
1875                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1876                         clock-names = "main", "dma";
1877                         #address-cells = <1>;
1878                         #size-cells = <0>;
1879                         status = "disabled";
1880                 };
1881
1882                 imp_iic_wrap_w: clock-controller@11e05000 {
1883                         compatible = "mediatek,mt8195-imp_iic_wrap_w";
1884                         reg = <0 0x11e05000 0 0x1000>;
1885                         #clock-cells = <1>;
1886                 };
1887
1888                 u3phy1: t-phy@11e30000 {
1889                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1890                         #address-cells = <1>;
1891                         #size-cells = <1>;
1892                         ranges = <0 0 0x11e30000 0xe00>;
1893                         power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1894                         status = "disabled";
1895
1896                         u2port1: usb-phy@0 {
1897                                 reg = <0x0 0x700>;
1898                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1899                                          <&clk26m>;
1900                                 clock-names = "ref", "da_ref";
1901                                 #phy-cells = <1>;
1902                         };
1903
1904                         u3port1: usb-phy@700 {
1905                                 reg = <0x700 0x700>;
1906                                 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1907                                          <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1908                                 clock-names = "ref", "da_ref";
1909                                 nvmem-cells = <&comb_intr_p1>,
1910                                               <&comb_rx_imp_p1>,
1911                                               <&comb_tx_imp_p1>;
1912                                 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1913                                 #phy-cells = <1>;
1914                         };
1915                 };
1916
1917                 u3phy0: t-phy@11e40000 {
1918                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1919                         #address-cells = <1>;
1920                         #size-cells = <1>;
1921                         ranges = <0 0 0x11e40000 0xe00>;
1922                         status = "disabled";
1923
1924                         u2port0: usb-phy@0 {
1925                                 reg = <0x0 0x700>;
1926                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1927                                          <&clk26m>;
1928                                 clock-names = "ref", "da_ref";
1929                                 #phy-cells = <1>;
1930                         };
1931
1932                         u3port0: usb-phy@700 {
1933                                 reg = <0x700 0x700>;
1934                                 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1935                                          <&topckgen CLK_TOP_SSUSB_PHY_REF>;
1936                                 clock-names = "ref", "da_ref";
1937                                 nvmem-cells = <&u3_intr_p0>,
1938                                               <&u3_rx_imp_p0>,
1939                                               <&u3_tx_imp_p0>;
1940                                 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1941                                 #phy-cells = <1>;
1942                         };
1943                 };
1944
1945                 pciephy: phy@11e80000 {
1946                         compatible = "mediatek,mt8195-pcie-phy";
1947                         reg = <0 0x11e80000 0 0x10000>;
1948                         reg-names = "sif";
1949                         nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1950                                       <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
1951                                       <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
1952                                       <&pciephy_rx_ln1>;
1953                         nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1954                                            "tx_ln0_nmos", "rx_ln0",
1955                                            "tx_ln1_pmos", "tx_ln1_nmos",
1956                                            "rx_ln1";
1957                         power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1958                         #phy-cells = <0>;
1959                         status = "disabled";
1960                 };
1961
1962                 ufsphy: ufs-phy@11fa0000 {
1963                         compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1964                         reg = <0 0x11fa0000 0 0xc000>;
1965                         clocks = <&clk26m>, <&clk26m>;
1966                         clock-names = "unipro", "mp";
1967                         #phy-cells = <0>;
1968                         status = "disabled";
1969                 };
1970
1971                 gpu: gpu@13000000 {
1972                         compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
1973                                      "arm,mali-valhall-jm";
1974                         reg = <0 0x13000000 0 0x4000>;
1975
1976                         clocks = <&mfgcfg CLK_MFG_BG3D>;
1977                         interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
1978                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
1979                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>;
1980                         interrupt-names = "job", "mmu", "gpu";
1981                         operating-points-v2 = <&gpu_opp_table>;
1982                         power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
1983                                         <&spm MT8195_POWER_DOMAIN_MFG3>,
1984                                         <&spm MT8195_POWER_DOMAIN_MFG4>,
1985                                         <&spm MT8195_POWER_DOMAIN_MFG5>,
1986                                         <&spm MT8195_POWER_DOMAIN_MFG6>;
1987                         power-domain-names = "core0", "core1", "core2", "core3", "core4";
1988                         status = "disabled";
1989                 };
1990
1991                 mfgcfg: clock-controller@13fbf000 {
1992                         compatible = "mediatek,mt8195-mfgcfg";
1993                         reg = <0 0x13fbf000 0 0x1000>;
1994                         #clock-cells = <1>;
1995                 };
1996
1997                 vppsys0: syscon@14000000 {
1998                         compatible = "mediatek,mt8195-vppsys0", "syscon";
1999                         reg = <0 0x14000000 0 0x1000>;
2000                         #clock-cells = <1>;
2001                 };
2002
2003                 dma-controller@14001000 {
2004                         compatible = "mediatek,mt8195-mdp3-rdma";
2005                         reg = <0 0x14001000 0 0x1000>;
2006                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
2007                         mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
2008                                               <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
2009                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2010                         iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>;
2011                         clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
2012                         mboxes = <&gce1 12 CMDQ_THR_PRIO_1>,
2013                                  <&gce1 13 CMDQ_THR_PRIO_1>,
2014                                  <&gce1 14 CMDQ_THR_PRIO_1>,
2015                                  <&gce1 21 CMDQ_THR_PRIO_1>,
2016                                  <&gce1 22 CMDQ_THR_PRIO_1>;
2017                         #dma-cells = <1>;
2018                 };
2019
2020                 display@14002000 {
2021                         compatible = "mediatek,mt8195-mdp3-fg";
2022                         reg = <0 0x14002000 0 0x1000>;
2023                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
2024                         clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
2025                 };
2026
2027                 display@14003000 {
2028                         compatible = "mediatek,mt8195-mdp3-stitch";
2029                         reg = <0 0x14003000 0 0x1000>;
2030                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
2031                         clocks = <&vppsys0 CLK_VPP0_STITCH>;
2032                 };
2033
2034                 display@14004000 {
2035                         compatible = "mediatek,mt8195-mdp3-hdr";
2036                         reg = <0 0x14004000 0 0x1000>;
2037                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
2038                         clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
2039                 };
2040
2041                 display@14005000 {
2042                         compatible = "mediatek,mt8195-mdp3-aal";
2043                         reg = <0 0x14005000 0 0x1000>;
2044                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
2045                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
2046                         clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
2047                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2048                 };
2049
2050                 display@14006000 {
2051                         compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2052                         reg = <0 0x14006000 0 0x1000>;
2053                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
2054                         mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
2055                                               <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
2056                         clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
2057                 };
2058
2059                 display@14007000 {
2060                         compatible = "mediatek,mt8195-mdp3-tdshp";
2061                         reg = <0 0x14007000 0 0x1000>;
2062                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
2063                         clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
2064                 };
2065
2066                 display@14008000 {
2067                         compatible = "mediatek,mt8195-mdp3-color";
2068                         reg = <0 0x14008000 0 0x1000>;
2069                         interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
2070                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
2071                         clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
2072                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2073                 };
2074
2075                 display@14009000 {
2076                         compatible = "mediatek,mt8195-mdp3-ovl";
2077                         reg = <0 0x14009000 0 0x1000>;
2078                         interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
2079                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
2080                         clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
2081                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2082                         iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>;
2083                 };
2084
2085                 display@1400a000 {
2086                         compatible = "mediatek,mt8195-mdp3-padding";
2087                         reg = <0 0x1400a000 0 0x1000>;
2088                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
2089                         clocks = <&vppsys0 CLK_VPP0_PADDING>;
2090                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2091                 };
2092
2093                 display@1400b000 {
2094                         compatible = "mediatek,mt8195-mdp3-tcc";
2095                         reg = <0 0x1400b000 0 0x1000>;
2096                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
2097                         clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
2098                 };
2099
2100                 dma-controller@1400c000 {
2101                         compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2102                         reg = <0 0x1400c000 0 0x1000>;
2103                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
2104                         mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
2105                                               <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
2106                         clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
2107                         iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
2108                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2109                         #dma-cells = <1>;
2110                 };
2111
2112                 mutex@1400f000 {
2113                         compatible = "mediatek,mt8195-vpp-mutex";
2114                         reg = <0 0x1400f000 0 0x1000>;
2115                         interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
2116                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
2117                         clocks = <&vppsys0 CLK_VPP0_MUTEX>;
2118                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2119                 };
2120
2121                 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
2122                         compatible = "mediatek,mt8195-smi-sub-common";
2123                         reg = <0 0x14010000 0 0x1000>;
2124                         clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2125                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2126                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2127                         clock-names = "apb", "smi", "gals0";
2128                         mediatek,smi = <&smi_common_vpp>;
2129                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2130                 };
2131
2132                 smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
2133                         compatible = "mediatek,mt8195-smi-sub-common";
2134                         reg = <0 0x14011000 0 0x1000>;
2135                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2136                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2137                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
2138                         clock-names = "apb", "smi", "gals0";
2139                         mediatek,smi = <&smi_common_vpp>;
2140                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2141                 };
2142
2143                 smi_common_vpp: smi@14012000 {
2144                         compatible = "mediatek,mt8195-smi-common-vpp";
2145                         reg = <0 0x14012000 0 0x1000>;
2146                         clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2147                                <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2148                                <&vppsys0 CLK_VPP0_SMI_RSI>,
2149                                <&vppsys0 CLK_VPP0_SMI_RSI>;
2150                         clock-names = "apb", "smi", "gals0", "gals1";
2151                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2152                 };
2153
2154                 larb4: larb@14013000 {
2155                         compatible = "mediatek,mt8195-smi-larb";
2156                         reg = <0 0x14013000 0 0x1000>;
2157                         mediatek,larb-id = <4>;
2158                         mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2159                         clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2160                                <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2161                         clock-names = "apb", "smi";
2162                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2163                 };
2164
2165                 iommu_vpp: iommu@14018000 {
2166                         compatible = "mediatek,mt8195-iommu-vpp";
2167                         reg = <0 0x14018000 0 0x1000>;
2168                         mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
2169                                           &larb12 &larb14 &larb16 &larb18
2170                                           &larb20 &larb22 &larb23 &larb26
2171                                           &larb27>;
2172                         interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
2173                         clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2174                         clock-names = "bclk";
2175                         #iommu-cells = <1>;
2176                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2177                 };
2178
2179                 wpesys: clock-controller@14e00000 {
2180                         compatible = "mediatek,mt8195-wpesys";
2181                         reg = <0 0x14e00000 0 0x1000>;
2182                         #clock-cells = <1>;
2183                 };
2184
2185                 wpesys_vpp0: clock-controller@14e02000 {
2186                         compatible = "mediatek,mt8195-wpesys_vpp0";
2187                         reg = <0 0x14e02000 0 0x1000>;
2188                         #clock-cells = <1>;
2189                 };
2190
2191                 wpesys_vpp1: clock-controller@14e03000 {
2192                         compatible = "mediatek,mt8195-wpesys_vpp1";
2193                         reg = <0 0x14e03000 0 0x1000>;
2194                         #clock-cells = <1>;
2195                 };
2196
2197                 larb7: larb@14e04000 {
2198                         compatible = "mediatek,mt8195-smi-larb";
2199                         reg = <0 0x14e04000 0 0x1000>;
2200                         mediatek,larb-id = <7>;
2201                         mediatek,smi = <&smi_common_vdo>;
2202                         clocks = <&wpesys CLK_WPE_SMI_LARB7>,
2203                                  <&wpesys CLK_WPE_SMI_LARB7>;
2204                         clock-names = "apb", "smi";
2205                         power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2206                 };
2207
2208                 larb8: larb@14e05000 {
2209                         compatible = "mediatek,mt8195-smi-larb";
2210                         reg = <0 0x14e05000 0 0x1000>;
2211                         mediatek,larb-id = <8>;
2212                         mediatek,smi = <&smi_common_vpp>;
2213                         clocks = <&wpesys CLK_WPE_SMI_LARB8>,
2214                                <&wpesys CLK_WPE_SMI_LARB8>,
2215                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2216                         clock-names = "apb", "smi", "gals";
2217                         power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2218                 };
2219
2220                 vppsys1: syscon@14f00000 {
2221                         compatible = "mediatek,mt8195-vppsys1", "syscon";
2222                         reg = <0 0x14f00000 0 0x1000>;
2223                         #clock-cells = <1>;
2224                 };
2225
2226                 mutex@14f01000 {
2227                         compatible = "mediatek,mt8195-vpp-mutex";
2228                         reg = <0 0x14f01000 0 0x1000>;
2229                         interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
2230                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2231                         clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
2232                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2233                 };
2234
2235                 larb5: larb@14f02000 {
2236                         compatible = "mediatek,mt8195-smi-larb";
2237                         reg = <0 0x14f02000 0 0x1000>;
2238                         mediatek,larb-id = <5>;
2239                         mediatek,smi = <&smi_common_vdo>;
2240                         clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2241                                <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2242                                <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2243                         clock-names = "apb", "smi", "gals";
2244                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2245                 };
2246
2247                 larb6: larb@14f03000 {
2248                         compatible = "mediatek,mt8195-smi-larb";
2249                         reg = <0 0x14f03000 0 0x1000>;
2250                         mediatek,larb-id = <6>;
2251                         mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2252                         clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2253                                <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2254                                <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2255                         clock-names = "apb", "smi", "gals";
2256                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2257                 };
2258
2259                 display@14f06000 {
2260                         compatible = "mediatek,mt8195-mdp3-split";
2261                         reg = <0 0x14f06000 0 0x1000>;
2262                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
2263                         clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
2264                                  <&vppsys1 CLK_VPP1_HDMI_META>,
2265                                  <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
2266                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2267                 };
2268
2269                 display@14f07000 {
2270                         compatible = "mediatek,mt8195-mdp3-tcc";
2271                         reg = <0 0x14f07000 0 0x1000>;
2272                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
2273                         clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
2274                 };
2275
2276                 dma-controller@14f08000 {
2277                         compatible = "mediatek,mt8195-mdp3-rdma";
2278                         reg = <0 0x14f08000 0 0x1000>;
2279                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
2280                         mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
2281                                               <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>;
2282                         clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>;
2283                         iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>;
2284                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2285                         #dma-cells = <1>;
2286                 };
2287
2288                 dma-controller@14f09000 {
2289                         compatible = "mediatek,mt8195-mdp3-rdma";
2290                         reg = <0 0x14f09000 0 0x1000>;
2291                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
2292                         mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
2293                                               <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
2294                         clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
2295                         iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>;
2296                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2297                         #dma-cells = <1>;
2298                 };
2299
2300                 dma-controller@14f0a000 {
2301                         compatible = "mediatek,mt8195-mdp3-rdma";
2302                         reg = <0 0x14f0a000 0 0x1000>;
2303                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
2304                         mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
2305                                               <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
2306                         clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
2307                         iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>;
2308                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2309                         #dma-cells = <1>;
2310                 };
2311
2312                 display@14f0b000 {
2313                         compatible = "mediatek,mt8195-mdp3-fg";
2314                         reg = <0 0x14f0b000 0 0x1000>;
2315                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
2316                         clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
2317                 };
2318
2319                 display@14f0c000 {
2320                         compatible = "mediatek,mt8195-mdp3-fg";
2321                         reg = <0 0x14f0c000 0 0x1000>;
2322                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
2323                         clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
2324                 };
2325
2326                 display@14f0d000 {
2327                         compatible = "mediatek,mt8195-mdp3-fg";
2328                         reg = <0 0x14f0d000 0 0x1000>;
2329                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
2330                         clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
2331                 };
2332
2333                 display@14f0e000 {
2334                         compatible = "mediatek,mt8195-mdp3-hdr";
2335                         reg = <0 0x14f0e000 0 0x1000>;
2336                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
2337                         clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
2338                 };
2339
2340                 display@14f0f000 {
2341                         compatible = "mediatek,mt8195-mdp3-hdr";
2342                         reg = <0 0x14f0f000 0 0x1000>;
2343                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
2344                         clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
2345                 };
2346
2347                 display@14f10000 {
2348                         compatible = "mediatek,mt8195-mdp3-hdr";
2349                         reg = <0 0x14f10000 0 0x1000>;
2350                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
2351                         clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
2352                 };
2353
2354                 display@14f11000 {
2355                         compatible = "mediatek,mt8195-mdp3-aal";
2356                         reg = <0 0x14f11000 0 0x1000>;
2357                         interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
2358                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
2359                         clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
2360                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2361                 };
2362
2363                 display@14f12000 {
2364                         compatible = "mediatek,mt8195-mdp3-aal";
2365                         reg = <0 0x14f12000 0 0x1000>;
2366                         interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
2367                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
2368                         clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
2369                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2370                 };
2371
2372                 display@14f13000 {
2373                         compatible = "mediatek,mt8195-mdp3-aal";
2374                         reg = <0 0x14f13000 0 0x1000>;
2375                         interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
2376                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
2377                         clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
2378                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2379                 };
2380
2381                 display@14f14000 {
2382                         compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2383                         reg = <0 0x14f14000 0 0x1000>;
2384                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
2385                         mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
2386                                               <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>;
2387                         clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
2388                 };
2389
2390                 display@14f15000 {
2391                         compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2392                         reg = <0 0x14f15000 0 0x1000>;
2393                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
2394                         mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
2395                                               <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
2396                         clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
2397                 };
2398
2399                 display@14f16000 {
2400                         compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
2401                         reg = <0 0x14f16000 0 0x1000>;
2402                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
2403                         mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
2404                                               <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
2405                         clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
2406                 };
2407
2408                 display@14f17000 {
2409                         compatible = "mediatek,mt8195-mdp3-tdshp";
2410                         reg = <0 0x14f17000 0 0x1000>;
2411                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
2412                         clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
2413                 };
2414
2415                 display@14f18000 {
2416                         compatible = "mediatek,mt8195-mdp3-tdshp";
2417                         reg = <0 0x14f18000 0 0x1000>;
2418                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
2419                         clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
2420                 };
2421
2422                 display@14f19000 {
2423                         compatible = "mediatek,mt8195-mdp3-tdshp";
2424                         reg = <0 0x14f19000 0 0x1000>;
2425                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
2426                         clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
2427                 };
2428
2429                 display@14f1a000 {
2430                         compatible = "mediatek,mt8195-mdp3-merge";
2431                         reg = <0 0x14f1a000 0 0x1000>;
2432                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
2433                         clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
2434                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2435                 };
2436
2437                 display@14f1b000 {
2438                         compatible = "mediatek,mt8195-mdp3-merge";
2439                         reg = <0 0x14f1b000 0 0x1000>;
2440                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
2441                         clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
2442                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2443                 };
2444
2445                 display@14f1c000 {
2446                         compatible = "mediatek,mt8195-mdp3-color";
2447                         reg = <0 0x14f1c000 0 0x1000>;
2448                         interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
2449                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
2450                         clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
2451                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2452                 };
2453
2454                 display@14f1d000 {
2455                         compatible = "mediatek,mt8195-mdp3-color";
2456                         reg = <0 0x14f1d000 0 0x1000>;
2457                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
2458                         interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
2459                         clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
2460                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2461                 };
2462
2463                 display@14f1e000 {
2464                         compatible = "mediatek,mt8195-mdp3-color";
2465                         reg = <0 0x14f1e000 0 0x1000>;
2466                         interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
2467                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
2468                         clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
2469                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2470                 };
2471
2472                 display@14f1f000 {
2473                         compatible = "mediatek,mt8195-mdp3-ovl";
2474                         reg = <0 0x14f1f000 0 0x1000>;
2475                         interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
2476                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
2477                         clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
2478                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2479                         iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>;
2480                 };
2481
2482                 display@14f20000 {
2483                         compatible = "mediatek,mt8195-mdp3-padding";
2484                         reg = <0 0x14f20000 0 0x1000>;
2485                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
2486                         clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
2487                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2488                 };
2489
2490                 display@14f21000 {
2491                         compatible = "mediatek,mt8195-mdp3-padding";
2492                         reg = <0 0x14f21000 0 0x1000>;
2493                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
2494                         clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
2495                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2496                 };
2497
2498                 display@14f22000 {
2499                         compatible = "mediatek,mt8195-mdp3-padding";
2500                         reg = <0 0x14f22000 0 0x1000>;
2501                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
2502                         clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
2503                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2504                 };
2505
2506                 dma-controller@14f23000 {
2507                         compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2508                         reg = <0 0x14f23000 0 0x1000>;
2509                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
2510                         mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
2511                                               <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>;
2512                         clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
2513                         iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
2514                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2515                         #dma-cells = <1>;
2516                 };
2517
2518                 dma-controller@14f24000 {
2519                         compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2520                         reg = <0 0x14f24000 0 0x1000>;
2521                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
2522                         mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
2523                                         <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
2524                         clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
2525                         iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
2526                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2527                         #dma-cells = <1>;
2528                 };
2529
2530                 dma-controller@14f25000 {
2531                         compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
2532                         reg = <0 0x14f25000 0 0x1000>;
2533                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
2534                         mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
2535                                         <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
2536                         clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
2537                         iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
2538                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2539                         #dma-cells = <1>;
2540                 };
2541
2542                 imgsys: clock-controller@15000000 {
2543                         compatible = "mediatek,mt8195-imgsys";
2544                         reg = <0 0x15000000 0 0x1000>;
2545                         #clock-cells = <1>;
2546                 };
2547
2548                 larb9: larb@15001000 {
2549                         compatible = "mediatek,mt8195-smi-larb";
2550                         reg = <0 0x15001000 0 0x1000>;
2551                         mediatek,larb-id = <9>;
2552                         mediatek,smi = <&smi_sub_common_img1_3x1>;
2553                         clocks = <&imgsys CLK_IMG_LARB9>,
2554                                  <&imgsys CLK_IMG_LARB9>,
2555                                  <&imgsys CLK_IMG_GALS>;
2556                         clock-names = "apb", "smi", "gals";
2557                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2558                 };
2559
2560                 smi_sub_common_img0_3x1: smi@15002000 {
2561                         compatible = "mediatek,mt8195-smi-sub-common";
2562                         reg = <0 0x15002000 0 0x1000>;
2563                         clocks = <&imgsys CLK_IMG_IPE>,
2564                                  <&imgsys CLK_IMG_IPE>,
2565                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2566                         clock-names = "apb", "smi", "gals0";
2567                         mediatek,smi = <&smi_common_vpp>;
2568                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2569                 };
2570
2571                 smi_sub_common_img1_3x1: smi@15003000 {
2572                         compatible = "mediatek,mt8195-smi-sub-common";
2573                         reg = <0 0x15003000 0 0x1000>;
2574                         clocks = <&imgsys CLK_IMG_LARB9>,
2575                                  <&imgsys CLK_IMG_LARB9>,
2576                                  <&imgsys CLK_IMG_GALS>;
2577                         clock-names = "apb", "smi", "gals0";
2578                         mediatek,smi = <&smi_common_vdo>;
2579                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2580                 };
2581
2582                 imgsys1_dip_top: clock-controller@15110000 {
2583                         compatible = "mediatek,mt8195-imgsys1_dip_top";
2584                         reg = <0 0x15110000 0 0x1000>;
2585                         #clock-cells = <1>;
2586                 };
2587
2588                 larb10: larb@15120000 {
2589                         compatible = "mediatek,mt8195-smi-larb";
2590                         reg = <0 0x15120000 0 0x1000>;
2591                         mediatek,larb-id = <10>;
2592                         mediatek,smi = <&smi_sub_common_img1_3x1>;
2593                         clocks = <&imgsys CLK_IMG_DIP0>,
2594                                <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
2595                         clock-names = "apb", "smi";
2596                         power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2597                 };
2598
2599                 imgsys1_dip_nr: clock-controller@15130000 {
2600                         compatible = "mediatek,mt8195-imgsys1_dip_nr";
2601                         reg = <0 0x15130000 0 0x1000>;
2602                         #clock-cells = <1>;
2603                 };
2604
2605                 imgsys1_wpe: clock-controller@15220000 {
2606                         compatible = "mediatek,mt8195-imgsys1_wpe";
2607                         reg = <0 0x15220000 0 0x1000>;
2608                         #clock-cells = <1>;
2609                 };
2610
2611                 larb11: larb@15230000 {
2612                         compatible = "mediatek,mt8195-smi-larb";
2613                         reg = <0 0x15230000 0 0x1000>;
2614                         mediatek,larb-id = <11>;
2615                         mediatek,smi = <&smi_sub_common_img1_3x1>;
2616                         clocks = <&imgsys CLK_IMG_WPE0>,
2617                                <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
2618                         clock-names = "apb", "smi";
2619                         power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2620                 };
2621
2622                 ipesys: clock-controller@15330000 {
2623                         compatible = "mediatek,mt8195-ipesys";
2624                         reg = <0 0x15330000 0 0x1000>;
2625                         #clock-cells = <1>;
2626                 };
2627
2628                 larb12: larb@15340000 {
2629                         compatible = "mediatek,mt8195-smi-larb";
2630                         reg = <0 0x15340000 0 0x1000>;
2631                         mediatek,larb-id = <12>;
2632                         mediatek,smi = <&smi_sub_common_img0_3x1>;
2633                         clocks = <&ipesys CLK_IPE_SMI_LARB12>,
2634                                  <&ipesys CLK_IPE_SMI_LARB12>;
2635                         clock-names = "apb", "smi";
2636                         power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2637                 };
2638
2639                 camsys: clock-controller@16000000 {
2640                         compatible = "mediatek,mt8195-camsys";
2641                         reg = <0 0x16000000 0 0x1000>;
2642                         #clock-cells = <1>;
2643                 };
2644
2645                 larb13: larb@16001000 {
2646                         compatible = "mediatek,mt8195-smi-larb";
2647                         reg = <0 0x16001000 0 0x1000>;
2648                         mediatek,larb-id = <13>;
2649                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2650                         clocks = <&camsys CLK_CAM_LARB13>,
2651                                <&camsys CLK_CAM_LARB13>,
2652                                <&camsys CLK_CAM_CAM2MM0_GALS>;
2653                         clock-names = "apb", "smi", "gals";
2654                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2655                 };
2656
2657                 larb14: larb@16002000 {
2658                         compatible = "mediatek,mt8195-smi-larb";
2659                         reg = <0 0x16002000 0 0x1000>;
2660                         mediatek,larb-id = <14>;
2661                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2662                         clocks = <&camsys CLK_CAM_LARB14>,
2663                                  <&camsys CLK_CAM_LARB14>;
2664                         clock-names = "apb", "smi";
2665                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2666                 };
2667
2668                 smi_sub_common_cam_4x1: smi@16004000 {
2669                         compatible = "mediatek,mt8195-smi-sub-common";
2670                         reg = <0 0x16004000 0 0x1000>;
2671                         clocks = <&camsys CLK_CAM_LARB13>,
2672                                  <&camsys CLK_CAM_LARB13>,
2673                                  <&camsys CLK_CAM_CAM2MM0_GALS>;
2674                         clock-names = "apb", "smi", "gals0";
2675                         mediatek,smi = <&smi_common_vdo>;
2676                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2677                 };
2678
2679                 smi_sub_common_cam_7x1: smi@16005000 {
2680                         compatible = "mediatek,mt8195-smi-sub-common";
2681                         reg = <0 0x16005000 0 0x1000>;
2682                         clocks = <&camsys CLK_CAM_LARB14>,
2683                                  <&camsys CLK_CAM_CAM2MM1_GALS>,
2684                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2685                         clock-names = "apb", "smi", "gals0";
2686                         mediatek,smi = <&smi_common_vpp>;
2687                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2688                 };
2689
2690                 larb16: larb@16012000 {
2691                         compatible = "mediatek,mt8195-smi-larb";
2692                         reg = <0 0x16012000 0 0x1000>;
2693                         mediatek,larb-id = <16>;
2694                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2695                         clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
2696                                  <&camsys_rawa CLK_CAM_RAWA_LARBX>;
2697                         clock-names = "apb", "smi";
2698                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2699                 };
2700
2701                 larb17: larb@16013000 {
2702                         compatible = "mediatek,mt8195-smi-larb";
2703                         reg = <0 0x16013000 0 0x1000>;
2704                         mediatek,larb-id = <17>;
2705                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2706                         clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
2707                                  <&camsys_yuva CLK_CAM_YUVA_LARBX>;
2708                         clock-names = "apb", "smi";
2709                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2710                 };
2711
2712                 larb27: larb@16014000 {
2713                         compatible = "mediatek,mt8195-smi-larb";
2714                         reg = <0 0x16014000 0 0x1000>;
2715                         mediatek,larb-id = <27>;
2716                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2717                         clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
2718                                  <&camsys_rawb CLK_CAM_RAWB_LARBX>;
2719                         clock-names = "apb", "smi";
2720                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2721                 };
2722
2723                 larb28: larb@16015000 {
2724                         compatible = "mediatek,mt8195-smi-larb";
2725                         reg = <0 0x16015000 0 0x1000>;
2726                         mediatek,larb-id = <28>;
2727                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2728                         clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
2729                                  <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
2730                         clock-names = "apb", "smi";
2731                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2732                 };
2733
2734                 camsys_rawa: clock-controller@1604f000 {
2735                         compatible = "mediatek,mt8195-camsys_rawa";
2736                         reg = <0 0x1604f000 0 0x1000>;
2737                         #clock-cells = <1>;
2738                 };
2739
2740                 camsys_yuva: clock-controller@1606f000 {
2741                         compatible = "mediatek,mt8195-camsys_yuva";
2742                         reg = <0 0x1606f000 0 0x1000>;
2743                         #clock-cells = <1>;
2744                 };
2745
2746                 camsys_rawb: clock-controller@1608f000 {
2747                         compatible = "mediatek,mt8195-camsys_rawb";
2748                         reg = <0 0x1608f000 0 0x1000>;
2749                         #clock-cells = <1>;
2750                 };
2751
2752                 camsys_yuvb: clock-controller@160af000 {
2753                         compatible = "mediatek,mt8195-camsys_yuvb";
2754                         reg = <0 0x160af000 0 0x1000>;
2755                         #clock-cells = <1>;
2756                 };
2757
2758                 camsys_mraw: clock-controller@16140000 {
2759                         compatible = "mediatek,mt8195-camsys_mraw";
2760                         reg = <0 0x16140000 0 0x1000>;
2761                         #clock-cells = <1>;
2762                 };
2763
2764                 larb25: larb@16141000 {
2765                         compatible = "mediatek,mt8195-smi-larb";
2766                         reg = <0 0x16141000 0 0x1000>;
2767                         mediatek,larb-id = <25>;
2768                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2769                         clocks = <&camsys CLK_CAM_LARB13>,
2770                                  <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2771                                  <&camsys CLK_CAM_CAM2MM0_GALS>;
2772                         clock-names = "apb", "smi", "gals";
2773                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2774                 };
2775
2776                 larb26: larb@16142000 {
2777                         compatible = "mediatek,mt8195-smi-larb";
2778                         reg = <0 0x16142000 0 0x1000>;
2779                         mediatek,larb-id = <26>;
2780                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2781                         clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2782                                  <&camsys_mraw CLK_CAM_MRAW_LARBX>;
2783                         clock-names = "apb", "smi";
2784                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2785
2786                 };
2787
2788                 ccusys: clock-controller@17200000 {
2789                         compatible = "mediatek,mt8195-ccusys";
2790                         reg = <0 0x17200000 0 0x1000>;
2791                         #clock-cells = <1>;
2792                 };
2793
2794                 larb18: larb@17201000 {
2795                         compatible = "mediatek,mt8195-smi-larb";
2796                         reg = <0 0x17201000 0 0x1000>;
2797                         mediatek,larb-id = <18>;
2798                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2799                         clocks = <&ccusys CLK_CCU_LARB18>,
2800                                  <&ccusys CLK_CCU_LARB18>;
2801                         clock-names = "apb", "smi";
2802                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2803                 };
2804
2805                 video-codec@18000000 {
2806                         compatible = "mediatek,mt8195-vcodec-dec";
2807                         mediatek,scp = <&scp>;
2808                         iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
2809                         #address-cells = <2>;
2810                         #size-cells = <2>;
2811                         reg = <0 0x18000000 0 0x1000>,
2812                               <0 0x18004000 0 0x1000>;
2813                         ranges = <0 0 0 0x18000000 0 0x26000>;
2814
2815                         video-codec@2000 {
2816                                 compatible = "mediatek,mtk-vcodec-lat-soc";
2817                                 reg = <0 0x2000 0 0x800>;
2818                                 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
2819                                          <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
2820                                 clocks = <&topckgen CLK_TOP_VDEC>,
2821                                          <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2822                                          <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2823                                          <&topckgen CLK_TOP_UNIVPLL_D4>;
2824                                 clock-names = "sel", "vdec", "lat", "top";
2825                                 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2826                                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2827                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2828                         };
2829
2830                         video-codec@10000 {
2831                                 compatible = "mediatek,mtk-vcodec-lat";
2832                                 reg = <0 0x10000 0 0x800>;
2833                                 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
2834                                 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
2835                                          <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
2836                                          <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
2837                                          <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
2838                                          <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
2839                                          <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;
2840                                 clocks = <&topckgen CLK_TOP_VDEC>,
2841                                          <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2842                                          <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2843                                          <&topckgen CLK_TOP_UNIVPLL_D4>;
2844                                 clock-names = "sel", "vdec", "lat", "top";
2845                                 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2846                                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2847                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2848                         };
2849
2850                         video-codec@25000 {
2851                                 compatible = "mediatek,mtk-vcodec-core";
2852                                 reg = <0 0x25000 0 0x1000>;             /* VDEC_CORE_MISC */
2853                                 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
2854                                 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,
2855                                          <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,
2856                                          <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,
2857                                          <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,
2858                                          <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,
2859                                          <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,
2860                                          <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,
2861                                          <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,
2862                                          <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,
2863                                          <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;
2864                                 clocks = <&topckgen CLK_TOP_VDEC>,
2865                                          <&vdecsys CLK_VDEC_VDEC>,
2866                                          <&vdecsys CLK_VDEC_LAT>,
2867                                          <&topckgen CLK_TOP_UNIVPLL_D4>;
2868                                 clock-names = "sel", "vdec", "lat", "top";
2869                                 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2870                                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2871                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2872                         };
2873                 };
2874
2875                 larb24: larb@1800d000 {
2876                         compatible = "mediatek,mt8195-smi-larb";
2877                         reg = <0 0x1800d000 0 0x1000>;
2878                         mediatek,larb-id = <24>;
2879                         mediatek,smi = <&smi_common_vdo>;
2880                         clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
2881                                  <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2882                         clock-names = "apb", "smi";
2883                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2884                 };
2885
2886                 larb23: larb@1800e000 {
2887                         compatible = "mediatek,mt8195-smi-larb";
2888                         reg = <0 0x1800e000 0 0x1000>;
2889                         mediatek,larb-id = <23>;
2890                         mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2891                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2892                                  <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2893                         clock-names = "apb", "smi";
2894                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2895                 };
2896
2897                 vdecsys_soc: clock-controller@1800f000 {
2898                         compatible = "mediatek,mt8195-vdecsys_soc";
2899                         reg = <0 0x1800f000 0 0x1000>;
2900                         #clock-cells = <1>;
2901                 };
2902
2903                 larb21: larb@1802e000 {
2904                         compatible = "mediatek,mt8195-smi-larb";
2905                         reg = <0 0x1802e000 0 0x1000>;
2906                         mediatek,larb-id = <21>;
2907                         mediatek,smi = <&smi_common_vdo>;
2908                         clocks = <&vdecsys CLK_VDEC_LARB1>,
2909                                  <&vdecsys CLK_VDEC_LARB1>;
2910                         clock-names = "apb", "smi";
2911                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2912                 };
2913
2914                 vdecsys: clock-controller@1802f000 {
2915                         compatible = "mediatek,mt8195-vdecsys";
2916                         reg = <0 0x1802f000 0 0x1000>;
2917                         #clock-cells = <1>;
2918                 };
2919
2920                 larb22: larb@1803e000 {
2921                         compatible = "mediatek,mt8195-smi-larb";
2922                         reg = <0 0x1803e000 0 0x1000>;
2923                         mediatek,larb-id = <22>;
2924                         mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2925                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2926                                  <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
2927                         clock-names = "apb", "smi";
2928                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2929                 };
2930
2931                 vdecsys_core1: clock-controller@1803f000 {
2932                         compatible = "mediatek,mt8195-vdecsys_core1";
2933                         reg = <0 0x1803f000 0 0x1000>;
2934                         #clock-cells = <1>;
2935                 };
2936
2937                 apusys_pll: clock-controller@190f3000 {
2938                         compatible = "mediatek,mt8195-apusys_pll";
2939                         reg = <0 0x190f3000 0 0x1000>;
2940                         #clock-cells = <1>;
2941                 };
2942
2943                 vencsys: clock-controller@1a000000 {
2944                         compatible = "mediatek,mt8195-vencsys";
2945                         reg = <0 0x1a000000 0 0x1000>;
2946                         #clock-cells = <1>;
2947                 };
2948
2949                 larb19: larb@1a010000 {
2950                         compatible = "mediatek,mt8195-smi-larb";
2951                         reg = <0 0x1a010000 0 0x1000>;
2952                         mediatek,larb-id = <19>;
2953                         mediatek,smi = <&smi_common_vdo>;
2954                         clocks = <&vencsys CLK_VENC_VENC>,
2955                                  <&vencsys CLK_VENC_GALS>;
2956                         clock-names = "apb", "smi";
2957                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2958                 };
2959
2960                 venc: video-codec@1a020000 {
2961                         compatible = "mediatek,mt8195-vcodec-enc";
2962                         reg = <0 0x1a020000 0 0x10000>;
2963                         iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
2964                                  <&iommu_vdo M4U_PORT_L19_VENC_REC>,
2965                                  <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
2966                                  <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
2967                                  <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
2968                                  <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
2969                                  <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
2970                                  <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
2971                                  <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
2972                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
2973                         mediatek,scp = <&scp>;
2974                         clocks = <&vencsys CLK_VENC_VENC>;
2975                         clock-names = "venc_sel";
2976                         assigned-clocks = <&topckgen CLK_TOP_VENC>;
2977                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2978                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2979                         #address-cells = <2>;
2980                         #size-cells = <2>;
2981                 };
2982
2983                 jpgdec-master {
2984                         compatible = "mediatek,mt8195-jpgdec";
2985                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2986                         iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
2987                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
2988                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
2989                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
2990                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
2991                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
2992                         #address-cells = <2>;
2993                         #size-cells = <2>;
2994                         ranges;
2995
2996                         jpgdec@1a040000 {
2997                                 compatible = "mediatek,mt8195-jpgdec-hw";
2998                                 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
2999                                 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3000                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3001                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3002                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3003                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3004                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3005                                 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
3006                                 clocks = <&vencsys CLK_VENC_JPGDEC>;
3007                                 clock-names = "jpgdec";
3008                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
3009                         };
3010
3011                         jpgdec@1a050000 {
3012                                 compatible = "mediatek,mt8195-jpgdec-hw";
3013                                 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
3014                                 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
3015                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
3016                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
3017                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
3018                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
3019                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
3020                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
3021                                 clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
3022                                 clock-names = "jpgdec";
3023                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
3024                         };
3025
3026                         jpgdec@1b040000 {
3027                                 compatible = "mediatek,mt8195-jpgdec-hw";
3028                                 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
3029                                 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
3030                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
3031                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
3032                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
3033                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
3034                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
3035                                 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
3036                                 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
3037                                 clock-names = "jpgdec";
3038                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
3039                         };
3040                 };
3041
3042                 vencsys_core1: clock-controller@1b000000 {
3043                         compatible = "mediatek,mt8195-vencsys_core1";
3044                         reg = <0 0x1b000000 0 0x1000>;
3045                         #clock-cells = <1>;
3046                 };
3047
3048                 vdosys0: syscon@1c01a000 {
3049                         compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
3050                         reg = <0 0x1c01a000 0 0x1000>;
3051                         mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
3052                         #clock-cells = <1>;
3053                 };
3054
3055
3056                 jpgenc-master {
3057                         compatible = "mediatek,mt8195-jpgenc";
3058                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3059                         iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3060                                         <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3061                                         <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3062                                         <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
3063                         #address-cells = <2>;
3064                         #size-cells = <2>;
3065                         ranges;
3066
3067                         jpgenc@1a030000 {
3068                                 compatible = "mediatek,mt8195-jpgenc-hw";
3069                                 reg = <0 0x1a030000 0 0x10000>;
3070                                 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
3071                                                 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
3072                                                 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
3073                                                 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
3074                                 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
3075                                 clocks = <&vencsys CLK_VENC_JPGENC>;
3076                                 clock-names = "jpgenc";
3077                                 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
3078                         };
3079
3080                         jpgenc@1b030000 {
3081                                 compatible = "mediatek,mt8195-jpgenc-hw";
3082                                 reg = <0 0x1b030000 0 0x10000>;
3083                                 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
3084                                                 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
3085                                                 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
3086                                                 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
3087                                 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
3088                                 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
3089                                 clock-names = "jpgenc";
3090                                 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3091                         };
3092                 };
3093
3094                 larb20: larb@1b010000 {
3095                         compatible = "mediatek,mt8195-smi-larb";
3096                         reg = <0 0x1b010000 0 0x1000>;
3097                         mediatek,larb-id = <20>;
3098                         mediatek,smi = <&smi_common_vpp>;
3099                         clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
3100                                  <&vencsys_core1 CLK_VENC_CORE1_GALS>,
3101                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3102                         clock-names = "apb", "smi", "gals";
3103                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
3104                 };
3105
3106                 ovl0: ovl@1c000000 {
3107                         compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
3108                         reg = <0 0x1c000000 0 0x1000>;
3109                         interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
3110                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3111                         clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
3112                         iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
3113                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
3114                 };
3115
3116                 rdma0: rdma@1c002000 {
3117                         compatible = "mediatek,mt8195-disp-rdma";
3118                         reg = <0 0x1c002000 0 0x1000>;
3119                         interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
3120                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3121                         clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
3122                         iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
3123                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
3124                 };
3125
3126                 color0: color@1c003000 {
3127                         compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
3128                         reg = <0 0x1c003000 0 0x1000>;
3129                         interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
3130                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3131                         clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
3132                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
3133                 };
3134
3135                 ccorr0: ccorr@1c004000 {
3136                         compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
3137                         reg = <0 0x1c004000 0 0x1000>;
3138                         interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
3139                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3140                         clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
3141                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
3142                 };
3143
3144                 aal0: aal@1c005000 {
3145                         compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
3146                         reg = <0 0x1c005000 0 0x1000>;
3147                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
3148                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3149                         clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
3150                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
3151                 };
3152
3153                 gamma0: gamma@1c006000 {
3154                         compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
3155                         reg = <0 0x1c006000 0 0x1000>;
3156                         interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
3157                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3158                         clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
3159                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
3160                 };
3161
3162                 dither0: dither@1c007000 {
3163                         compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
3164                         reg = <0 0x1c007000 0 0x1000>;
3165                         interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
3166                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3167                         clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
3168                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
3169                 };
3170
3171                 dsi0: dsi@1c008000 {
3172                         compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3173                         reg = <0 0x1c008000 0 0x1000>;
3174                         interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
3175                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3176                         clocks = <&vdosys0 CLK_VDO0_DSI0>,
3177                                  <&vdosys0 CLK_VDO0_DSI0_DSI>,
3178                                  <&mipi_tx0>;
3179                         clock-names = "engine", "digital", "hs";
3180                         phys = <&mipi_tx0>;
3181                         phy-names = "dphy";
3182                         status = "disabled";
3183                 };
3184
3185                 dsc0: dsc@1c009000 {
3186                         compatible = "mediatek,mt8195-disp-dsc";
3187                         reg = <0 0x1c009000 0 0x1000>;
3188                         interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
3189                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3190                         clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
3191                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
3192                 };
3193
3194                 dsi1: dsi@1c012000 {
3195                         compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
3196                         reg = <0 0x1c012000 0 0x1000>;
3197                         interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>;
3198                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3199                         clocks = <&vdosys0 CLK_VDO0_DSI1>,
3200                                  <&vdosys0 CLK_VDO0_DSI1_DSI>,
3201                                  <&mipi_tx1>;
3202                         clock-names = "engine", "digital", "hs";
3203                         phys = <&mipi_tx1>;
3204                         phy-names = "dphy";
3205                         status = "disabled";
3206                 };
3207
3208                 merge0: merge@1c014000 {
3209                         compatible = "mediatek,mt8195-disp-merge";
3210                         reg = <0 0x1c014000 0 0x1000>;
3211                         interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
3212                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3213                         clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
3214                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
3215                 };
3216
3217                 dp_intf0: dp-intf@1c015000 {
3218                         compatible = "mediatek,mt8195-dp-intf";
3219                         reg = <0 0x1c015000 0 0x1000>;
3220                         interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
3221                         clocks = <&vdosys0  CLK_VDO0_DP_INTF0>,
3222                                  <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
3223                                  <&apmixedsys CLK_APMIXED_TVDPLL1>;
3224                         clock-names = "engine", "pixel", "pll";
3225                         status = "disabled";
3226                 };
3227
3228                 mutex: mutex@1c016000 {
3229                         compatible = "mediatek,mt8195-disp-mutex";
3230                         reg = <0 0x1c016000 0 0x1000>;
3231                         interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
3232                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3233                         clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
3234                         mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
3235                 };
3236
3237                 larb0: larb@1c018000 {
3238                         compatible = "mediatek,mt8195-smi-larb";
3239                         reg = <0 0x1c018000 0 0x1000>;
3240                         mediatek,larb-id = <0>;
3241                         mediatek,smi = <&smi_common_vdo>;
3242                         clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3243                                  <&vdosys0 CLK_VDO0_SMI_LARB>,
3244                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
3245                         clock-names = "apb", "smi", "gals";
3246                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3247                 };
3248
3249                 larb1: larb@1c019000 {
3250                         compatible = "mediatek,mt8195-smi-larb";
3251                         reg = <0 0x1c019000 0 0x1000>;
3252                         mediatek,larb-id = <1>;
3253                         mediatek,smi = <&smi_common_vpp>;
3254                         clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
3255                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
3256                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
3257                         clock-names = "apb", "smi", "gals";
3258                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3259                 };
3260
3261                 vdosys1: syscon@1c100000 {
3262                         compatible = "mediatek,mt8195-vdosys1", "syscon";
3263                         reg = <0 0x1c100000 0 0x1000>;
3264                         mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
3265                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
3266                         #clock-cells = <1>;
3267                         #reset-cells = <1>;
3268                 };
3269
3270                 smi_common_vdo: smi@1c01b000 {
3271                         compatible = "mediatek,mt8195-smi-common-vdo";
3272                         reg = <0 0x1c01b000 0 0x1000>;
3273                         clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
3274                                  <&vdosys0 CLK_VDO0_SMI_EMI>,
3275                                  <&vdosys0 CLK_VDO0_SMI_RSI>,
3276                                  <&vdosys0 CLK_VDO0_SMI_GALS>;
3277                         clock-names = "apb", "smi", "gals0", "gals1";
3278                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3279
3280                 };
3281
3282                 iommu_vdo: iommu@1c01f000 {
3283                         compatible = "mediatek,mt8195-iommu-vdo";
3284                         reg = <0 0x1c01f000 0 0x1000>;
3285                         mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
3286                                           &larb10 &larb11 &larb13 &larb17
3287                                           &larb19 &larb21 &larb24 &larb25
3288                                           &larb28>;
3289                         interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
3290                         #iommu-cells = <1>;
3291                         clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
3292                         clock-names = "bclk";
3293                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
3294                 };
3295
3296                 mutex1: mutex@1c101000 {
3297                         compatible = "mediatek,mt8195-disp-mutex";
3298                         reg = <0 0x1c101000 0 0x1000>;
3299                         reg-names = "vdo1_mutex";
3300                         interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
3301                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3302                         clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
3303                         clock-names = "vdo1_mutex";
3304                         mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
3305                 };
3306
3307                 larb2: larb@1c102000 {
3308                         compatible = "mediatek,mt8195-smi-larb";
3309                         reg = <0 0x1c102000 0 0x1000>;
3310                         mediatek,larb-id = <2>;
3311                         mediatek,smi = <&smi_common_vdo>;
3312                         clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
3313                                  <&vdosys1 CLK_VDO1_SMI_LARB2>,
3314                                  <&vdosys1 CLK_VDO1_GALS>;
3315                         clock-names = "apb", "smi", "gals";
3316                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3317                 };
3318
3319                 larb3: larb@1c103000 {
3320                         compatible = "mediatek,mt8195-smi-larb";
3321                         reg = <0 0x1c103000 0 0x1000>;
3322                         mediatek,larb-id = <3>;
3323                         mediatek,smi = <&smi_common_vpp>;
3324                         clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
3325                                  <&vdosys1 CLK_VDO1_GALS>,
3326                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3327                         clock-names = "apb", "smi", "gals";
3328                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3329                 };
3330
3331                 vdo1_rdma0: dma-controller@1c104000 {
3332                         compatible = "mediatek,mt8195-vdo1-rdma";
3333                         reg = <0 0x1c104000 0 0x1000>;
3334                         interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
3335                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
3336                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3337                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
3338                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
3339                         #dma-cells = <1>;
3340                 };
3341
3342                 vdo1_rdma1: dma-controller@1c105000 {
3343                         compatible = "mediatek,mt8195-vdo1-rdma";
3344                         reg = <0 0x1c105000 0 0x1000>;
3345                         interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
3346                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
3347                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3348                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
3349                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
3350                         #dma-cells = <1>;
3351                 };
3352
3353                 vdo1_rdma2: dma-controller@1c106000 {
3354                         compatible = "mediatek,mt8195-vdo1-rdma";
3355                         reg = <0 0x1c106000 0 0x1000>;
3356                         interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
3357                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
3358                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3359                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
3360                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
3361                         #dma-cells = <1>;
3362                 };
3363
3364                 vdo1_rdma3: dma-controller@1c107000 {
3365                         compatible = "mediatek,mt8195-vdo1-rdma";
3366                         reg = <0 0x1c107000 0 0x1000>;
3367                         interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
3368                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
3369                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3370                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
3371                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
3372                         #dma-cells = <1>;
3373                 };
3374
3375                 vdo1_rdma4: dma-controller@1c108000 {
3376                         compatible = "mediatek,mt8195-vdo1-rdma";
3377                         reg = <0 0x1c108000 0 0x1000>;
3378                         interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
3379                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
3380                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3381                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
3382                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
3383                         #dma-cells = <1>;
3384                 };
3385
3386                 vdo1_rdma5: dma-controller@1c109000 {
3387                         compatible = "mediatek,mt8195-vdo1-rdma";
3388                         reg = <0 0x1c109000 0 0x1000>;
3389                         interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
3390                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
3391                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3392                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
3393                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
3394                         #dma-cells = <1>;
3395                 };
3396
3397                 vdo1_rdma6: dma-controller@1c10a000 {
3398                         compatible = "mediatek,mt8195-vdo1-rdma";
3399                         reg = <0 0x1c10a000 0 0x1000>;
3400                         interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
3401                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
3402                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3403                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
3404                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
3405                         #dma-cells = <1>;
3406                 };
3407
3408                 vdo1_rdma7: dma-controller@1c10b000 {
3409                         compatible = "mediatek,mt8195-vdo1-rdma";
3410                         reg = <0 0x1c10b000 0 0x1000>;
3411                         interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
3412                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
3413                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3414                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
3415                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
3416                         #dma-cells = <1>;
3417                 };
3418
3419                 merge1: vpp-merge@1c10c000 {
3420                         compatible = "mediatek,mt8195-disp-merge";
3421                         reg = <0 0x1c10c000 0 0x1000>;
3422                         interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
3423                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
3424                                  <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
3425                         clock-names = "merge","merge_async";
3426                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3427                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
3428                         mediatek,merge-mute;
3429                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
3430                 };
3431
3432                 merge2: vpp-merge@1c10d000 {
3433                         compatible = "mediatek,mt8195-disp-merge";
3434                         reg = <0 0x1c10d000 0 0x1000>;
3435                         interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
3436                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
3437                                  <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
3438                         clock-names = "merge","merge_async";
3439                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3440                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
3441                         mediatek,merge-mute;
3442                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
3443                 };
3444
3445                 merge3: vpp-merge@1c10e000 {
3446                         compatible = "mediatek,mt8195-disp-merge";
3447                         reg = <0 0x1c10e000 0 0x1000>;
3448                         interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
3449                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
3450                                  <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
3451                         clock-names = "merge","merge_async";
3452                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3453                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
3454                         mediatek,merge-mute;
3455                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
3456                 };
3457
3458                 merge4: vpp-merge@1c10f000 {
3459                         compatible = "mediatek,mt8195-disp-merge";
3460                         reg = <0 0x1c10f000 0 0x1000>;
3461                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
3462                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
3463                                  <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
3464                         clock-names = "merge","merge_async";
3465                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3466                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3467                         mediatek,merge-mute;
3468                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
3469                 };
3470
3471                 merge5: vpp-merge@1c110000 {
3472                         compatible = "mediatek,mt8195-disp-merge";
3473                         reg = <0 0x1c110000 0 0x1000>;
3474                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
3475                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
3476                                  <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
3477                         clock-names = "merge","merge_async";
3478                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3479                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3480                         mediatek,merge-fifo-en;
3481                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3482                 };
3483
3484                 dp_intf1: dp-intf@1c113000 {
3485                         compatible = "mediatek,mt8195-dp-intf";
3486                         reg = <0 0x1c113000 0 0x1000>;
3487                         interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
3488                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3489                         clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
3490                                  <&vdosys1 CLK_VDO1_DPINTF>,
3491                                  <&apmixedsys CLK_APMIXED_TVDPLL2>;
3492                         clock-names = "engine", "pixel", "pll";
3493                         status = "disabled";
3494                 };
3495
3496                 ethdr0: hdr-engine@1c114000 {
3497                         compatible = "mediatek,mt8195-disp-ethdr";
3498                         reg = <0 0x1c114000 0 0x1000>,
3499                               <0 0x1c115000 0 0x1000>,
3500                               <0 0x1c117000 0 0x1000>,
3501                               <0 0x1c119000 0 0x1000>,
3502                               <0 0x1c11a000 0 0x1000>,
3503                               <0 0x1c11b000 0 0x1000>,
3504                               <0 0x1c11c000 0 0x1000>;
3505                         reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3506                                     "vdo_be", "adl_ds";
3507                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3508                                                   <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
3509                                                   <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
3510                                                   <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
3511                                                   <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
3512                                                   <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
3513                                                   <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
3514                         clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
3515                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
3516                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
3517                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
3518                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
3519                                  <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
3520                                  <&vdosys1 CLK_VDO1_26M_SLOW>,
3521                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
3522                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
3523                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
3524                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
3525                                  <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
3526                                  <&topckgen CLK_TOP_ETHDR>;
3527                         clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3528                                       "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
3529                                       "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
3530                                       "ethdr_top";
3531                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3532                         iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
3533                                  <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
3534                         interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
3535                         resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
3536                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
3537                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
3538                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
3539                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
3540                         reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3541                                       "gfx_fe1_async", "vdo_be_async";
3542                 };
3543
3544                 edp_tx: edp-tx@1c500000 {
3545                         compatible = "mediatek,mt8195-edp-tx";
3546                         reg = <0 0x1c500000 0 0x8000>;
3547                         nvmem-cells = <&dp_calibration>;
3548                         nvmem-cell-names = "dp_calibration_data";
3549                         power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3550                         interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
3551                         max-linkrate-mhz = <8100>;
3552                         status = "disabled";
3553                 };
3554
3555                 dp_tx: dp-tx@1c600000 {
3556                         compatible = "mediatek,mt8195-dp-tx";
3557                         reg = <0 0x1c600000 0 0x8000>;
3558                         nvmem-cells = <&dp_calibration>;
3559                         nvmem-cell-names = "dp_calibration_data";
3560                         power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3561                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
3562                         max-linkrate-mhz = <8100>;
3563                         status = "disabled";
3564                 };
3565         };
3566
3567         thermal_zones: thermal-zones {
3568                 cpu0-thermal {
3569                         polling-delay = <1000>;
3570                         polling-delay-passive = <250>;
3571                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3572
3573                         trips {
3574                                 cpu0_alert: trip-alert {
3575                                         temperature = <85000>;
3576                                         hysteresis = <2000>;
3577                                         type = "passive";
3578                                 };
3579
3580                                 cpu0_crit: trip-crit {
3581                                         temperature = <100000>;
3582                                         hysteresis = <2000>;
3583                                         type = "critical";
3584                                 };
3585                         };
3586
3587                         cooling-maps {
3588                                 map0 {
3589                                         trip = <&cpu0_alert>;
3590                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3591                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3592                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3593                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3594                                 };
3595                         };
3596                 };
3597
3598                 cpu1-thermal {
3599                         polling-delay = <1000>;
3600                         polling-delay-passive = <250>;
3601                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3602
3603                         trips {
3604                                 cpu1_alert: trip-alert {
3605                                         temperature = <85000>;
3606                                         hysteresis = <2000>;
3607                                         type = "passive";
3608                                 };
3609
3610                                 cpu1_crit: trip-crit {
3611                                         temperature = <100000>;
3612                                         hysteresis = <2000>;
3613                                         type = "critical";
3614                                 };
3615                         };
3616
3617                         cooling-maps {
3618                                 map0 {
3619                                         trip = <&cpu1_alert>;
3620                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3621                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3622                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3623                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3624                                 };
3625                         };
3626                 };
3627
3628                 cpu2-thermal {
3629                         polling-delay = <1000>;
3630                         polling-delay-passive = <250>;
3631                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3632
3633                         trips {
3634                                 cpu2_alert: trip-alert {
3635                                         temperature = <85000>;
3636                                         hysteresis = <2000>;
3637                                         type = "passive";
3638                                 };
3639
3640                                 cpu2_crit: trip-crit {
3641                                         temperature = <100000>;
3642                                         hysteresis = <2000>;
3643                                         type = "critical";
3644                                 };
3645                         };
3646
3647                         cooling-maps {
3648                                 map0 {
3649                                         trip = <&cpu2_alert>;
3650                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3651                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3652                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3653                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3654                                 };
3655                         };
3656                 };
3657
3658                 cpu3-thermal {
3659                         polling-delay = <1000>;
3660                         polling-delay-passive = <250>;
3661                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3662
3663                         trips {
3664                                 cpu3_alert: trip-alert {
3665                                         temperature = <85000>;
3666                                         hysteresis = <2000>;
3667                                         type = "passive";
3668                                 };
3669
3670                                 cpu3_crit: trip-crit {
3671                                         temperature = <100000>;
3672                                         hysteresis = <2000>;
3673                                         type = "critical";
3674                                 };
3675                         };
3676
3677                         cooling-maps {
3678                                 map0 {
3679                                         trip = <&cpu3_alert>;
3680                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3681                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3682                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3683                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3684                                 };
3685                         };
3686                 };
3687
3688                 cpu4-thermal {
3689                         polling-delay = <1000>;
3690                         polling-delay-passive = <250>;
3691                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3692
3693                         trips {
3694                                 cpu4_alert: trip-alert {
3695                                         temperature = <85000>;
3696                                         hysteresis = <2000>;
3697                                         type = "passive";
3698                                 };
3699
3700                                 cpu4_crit: trip-crit {
3701                                         temperature = <100000>;
3702                                         hysteresis = <2000>;
3703                                         type = "critical";
3704                                 };
3705                         };
3706
3707                         cooling-maps {
3708                                 map0 {
3709                                         trip = <&cpu4_alert>;
3710                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3711                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3712                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3713                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3714                                 };
3715                         };
3716                 };
3717
3718                 cpu5-thermal {
3719                         polling-delay = <1000>;
3720                         polling-delay-passive = <250>;
3721                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3722
3723                         trips {
3724                                 cpu5_alert: trip-alert {
3725                                         temperature = <85000>;
3726                                         hysteresis = <2000>;
3727                                         type = "passive";
3728                                 };
3729
3730                                 cpu5_crit: trip-crit {
3731                                         temperature = <100000>;
3732                                         hysteresis = <2000>;
3733                                         type = "critical";
3734                                 };
3735                         };
3736
3737                         cooling-maps {
3738                                 map0 {
3739                                         trip = <&cpu5_alert>;
3740                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3741                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3742                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3743                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3744                                 };
3745                         };
3746                 };
3747
3748                 cpu6-thermal {
3749                         polling-delay = <1000>;
3750                         polling-delay-passive = <250>;
3751                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3752
3753                         trips {
3754                                 cpu6_alert: trip-alert {
3755                                         temperature = <85000>;
3756                                         hysteresis = <2000>;
3757                                         type = "passive";
3758                                 };
3759
3760                                 cpu6_crit: trip-crit {
3761                                         temperature = <100000>;
3762                                         hysteresis = <2000>;
3763                                         type = "critical";
3764                                 };
3765                         };
3766
3767                         cooling-maps {
3768                                 map0 {
3769                                         trip = <&cpu6_alert>;
3770                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3771                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3772                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3773                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3774                                 };
3775                         };
3776                 };
3777
3778                 cpu7-thermal {
3779                         polling-delay = <1000>;
3780                         polling-delay-passive = <250>;
3781                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3782
3783                         trips {
3784                                 cpu7_alert: trip-alert {
3785                                         temperature = <85000>;
3786                                         hysteresis = <2000>;
3787                                         type = "passive";
3788                                 };
3789
3790                                 cpu7_crit: trip-crit {
3791                                         temperature = <100000>;
3792                                         hysteresis = <2000>;
3793                                         type = "critical";
3794                                 };
3795                         };
3796
3797                         cooling-maps {
3798                                 map0 {
3799                                         trip = <&cpu7_alert>;
3800                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3801                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3802                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3803                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3804                                 };
3805                         };
3806                 };
3807
3808                 vpu0-thermal {
3809                         polling-delay = <1000>;
3810                         polling-delay-passive = <250>;
3811                         thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3812
3813                         trips {
3814                                 vpu0_alert: trip-alert {
3815                                         temperature = <85000>;
3816                                         hysteresis = <2000>;
3817                                         type = "passive";
3818                                 };
3819
3820                                 vpu0_crit: trip-crit {
3821                                         temperature = <100000>;
3822                                         hysteresis = <2000>;
3823                                         type = "critical";
3824                                 };
3825                         };
3826                 };
3827
3828                 vpu1-thermal {
3829                         polling-delay = <1000>;
3830                         polling-delay-passive = <250>;
3831                         thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3832
3833                         trips {
3834                                 vpu1_alert: trip-alert {
3835                                         temperature = <85000>;
3836                                         hysteresis = <2000>;
3837                                         type = "passive";
3838                                 };
3839
3840                                 vpu1_crit: trip-crit {
3841                                         temperature = <100000>;
3842                                         hysteresis = <2000>;
3843                                         type = "critical";
3844                                 };
3845                         };
3846                 };
3847
3848                 gpu0-thermal {
3849                         polling-delay = <1000>;
3850                         polling-delay-passive = <250>;
3851                         thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3852
3853                         trips {
3854                                 gpu0_alert: trip-alert {
3855                                         temperature = <85000>;
3856                                         hysteresis = <2000>;
3857                                         type = "passive";
3858                                 };
3859
3860                                 gpu0_crit: trip-crit {
3861                                         temperature = <100000>;
3862                                         hysteresis = <2000>;
3863                                         type = "critical";
3864                                 };
3865                         };
3866                 };
3867
3868                 gpu1-thermal {
3869                         polling-delay = <1000>;
3870                         polling-delay-passive = <250>;
3871                         thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3872
3873                         trips {
3874                                 gpu1_alert: trip-alert {
3875                                         temperature = <85000>;
3876                                         hysteresis = <2000>;
3877                                         type = "passive";
3878                                 };
3879
3880                                 gpu1_crit: trip-crit {
3881                                         temperature = <100000>;
3882                                         hysteresis = <2000>;
3883                                         type = "critical";
3884                                 };
3885                         };
3886                 };
3887
3888                 vdec-thermal {
3889                         polling-delay = <1000>;
3890                         polling-delay-passive = <250>;
3891                         thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3892
3893                         trips {
3894                                 vdec_alert: trip-alert {
3895                                         temperature = <85000>;
3896                                         hysteresis = <2000>;
3897                                         type = "passive";
3898                                 };
3899
3900                                 vdec_crit: trip-crit {
3901                                         temperature = <100000>;
3902                                         hysteresis = <2000>;
3903                                         type = "critical";
3904                                 };
3905                         };
3906                 };
3907
3908                 img-thermal {
3909                         polling-delay = <1000>;
3910                         polling-delay-passive = <250>;
3911                         thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3912
3913                         trips {
3914                                 img_alert: trip-alert {
3915                                         temperature = <85000>;
3916                                         hysteresis = <2000>;
3917                                         type = "passive";
3918                                 };
3919
3920                                 img_crit: trip-crit {
3921                                         temperature = <100000>;
3922                                         hysteresis = <2000>;
3923                                         type = "critical";
3924                                 };
3925                         };
3926                 };
3927
3928                 infra-thermal {
3929                         polling-delay = <1000>;
3930                         polling-delay-passive = <250>;
3931                         thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3932
3933                         trips {
3934                                 infra_alert: trip-alert {
3935                                         temperature = <85000>;
3936                                         hysteresis = <2000>;
3937                                         type = "passive";
3938                                 };
3939
3940                                 infra_crit: trip-crit {
3941                                         temperature = <100000>;
3942                                         hysteresis = <2000>;
3943                                         type = "critical";
3944                                 };
3945                         };
3946                 };
3947
3948                 cam0-thermal {
3949                         polling-delay = <1000>;
3950                         polling-delay-passive = <250>;
3951                         thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3952
3953                         trips {
3954                                 cam0_alert: trip-alert {
3955                                         temperature = <85000>;
3956                                         hysteresis = <2000>;
3957                                         type = "passive";
3958                                 };
3959
3960                                 cam0_crit: trip-crit {
3961                                         temperature = <100000>;
3962                                         hysteresis = <2000>;
3963                                         type = "critical";
3964                                 };
3965                         };
3966                 };
3967
3968                 cam1-thermal {
3969                         polling-delay = <1000>;
3970                         polling-delay-passive = <250>;
3971                         thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
3972
3973                         trips {
3974                                 cam1_alert: trip-alert {
3975                                         temperature = <85000>;
3976                                         hysteresis = <2000>;
3977                                         type = "passive";
3978                                 };
3979
3980                                 cam1_crit: trip-crit {
3981                                         temperature = <100000>;
3982                                         hysteresis = <2000>;
3983                                         type = "critical";
3984                                 };
3985                         };
3986                 };
3987         };
3988 };