arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt8173-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/memory/mt8173-larb-port.h>
  18 #include <dt-bindings/phy/phy.h>
  19 #include <dt-bindings/power/mt8173-power.h>
  20 #include <dt-bindings/reset/mt8173-resets.h>
  21 #include "mt8173-pinfunc.h"
  22
  23 / {
  24         compatible = "mediatek,mt8173";
  25         interrupt-parent = <&sysirq>;
  26         #address-cells = <2>;
  27         #size-cells = <2>;
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu-map {
  34                         cluster0 {
  35                                 core0 {
  36                                         cpu = <&cpu0>;
  37                                 };
  38                                 core1 {
  39                                         cpu = <&cpu1>;
  40                                 };
  41                         };
  42
  43                         cluster1 {
  44                                 core0 {
  45                                         cpu = <&cpu2>;
  46                                 };
  47                                 core1 {
  48                                         cpu = <&cpu3>;
  49                                 };
  50                         };
  51                 };
  52
  53                 cpu0: cpu@0 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a53";
  56                         reg = <0x000>;
  57                         enable-method = "psci";
  58                         cpu-idle-states = <&CPU_SLEEP_0>;
  59                 };
  60
  61                 cpu1: cpu@1 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a53";
  64                         reg = <0x001>;
  65                         enable-method = "psci";
  66                         cpu-idle-states = <&CPU_SLEEP_0>;
  67                 };
  68
  69                 cpu2: cpu@100 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a57";
  72                         reg = <0x100>;
  73                         enable-method = "psci";
  74                         cpu-idle-states = <&CPU_SLEEP_0>;
  75                 };
  76
  77                 cpu3: cpu@101 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a57";
  80                         reg = <0x101>;
  81                         enable-method = "psci";
  82                         cpu-idle-states = <&CPU_SLEEP_0>;
  83                 };
  84
  85                 idle-states {
  86                         entry-method = "psci";
  87
  88                         CPU_SLEEP_0: cpu-sleep-0 {
  89                                 compatible = "arm,idle-state";
  90                                 local-timer-stop;
  91                                 entry-latency-us = <639>;
  92                                 exit-latency-us = <680>;
  93                                 min-residency-us = <1088>;
  94                                 arm,psci-suspend-param = <0x0010000>;
  95                         };
  96                 };
  97         };
  98
  99         psci {
 100                 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 101                 method = "smc";
 102                 cpu_suspend   = <0x84000001>;
 103                 cpu_off       = <0x84000002>;
 104                 cpu_on        = <0x84000003>;
 105         };
 106
 107         clk26m: oscillator@0 {
 108                 compatible = "fixed-clock";
 109                 #clock-cells = <0>;
 110                 clock-frequency = <26000000>;
 111                 clock-output-names = "clk26m";
 112         };
 113
 114         clk32k: oscillator@1 {
 115                 compatible = "fixed-clock";
 116                 #clock-cells = <0>;
 117                 clock-frequency = <32000>;
 118                 clock-output-names = "clk32k";
 119         };
 120
 121         cpum_ck: oscillator@2 {
 122                 compatible = "fixed-clock";
 123                 #clock-cells = <0>;
 124                 clock-frequency = <0>;
 125                 clock-output-names = "cpum_ck";
 126         };
 127
 128         timer {
 129                 compatible = "arm,armv8-timer";
 130                 interrupt-parent = <&gic>;
 131                 interrupts = <GIC_PPI 13
 132                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 133                              <GIC_PPI 14
 134                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 135                              <GIC_PPI 11
 136                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 137                              <GIC_PPI 10
 138                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 139         };
 140
 141         soc {
 142                 #address-cells = <2>;
 143                 #size-cells = <2>;
 144                 compatible = "simple-bus";
 145                 ranges;
 146
 147                 topckgen: clock-controller@10000000 {
 148                         compatible = "mediatek,mt8173-topckgen";
 149                         reg = <0 0x10000000 0 0x1000>;
 150                         #clock-cells = <1>;
 151                 };
 152
 153                 infracfg: power-controller@10001000 {
 154                         compatible = "mediatek,mt8173-infracfg", "syscon";
 155                         reg = <0 0x10001000 0 0x1000>;
 156                         #clock-cells = <1>;
 157                         #reset-cells = <1>;
 158                 };
 159
 160                 pericfg: power-controller@10003000 {
 161                         compatible = "mediatek,mt8173-pericfg", "syscon";
 162                         reg = <0 0x10003000 0 0x1000>;
 163                         #clock-cells = <1>;
 164                         #reset-cells = <1>;
 165                 };
 166
 167                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 168                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 169                         reg = <0 0x10005000 0 0x1000>;
 170                 };
 171
 172                 pio: pinctrl@0x10005000 {
 173                         compatible = "mediatek,mt8173-pinctrl";
 174                         reg = <0 0x1000b000 0 0x1000>;
 175                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 176                         pins-are-numbered;
 177                         gpio-controller;
 178                         #gpio-cells = <2>;
 179                         interrupt-controller;
 180                         #interrupt-cells = <2>;
 181                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 183                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 184
 185                         i2c0_pins_a: i2c0 {
 186                                 pins1 {
 187                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 188                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 189                                         bias-disable;
 190                                 };
 191                         };
 192
 193                         i2c1_pins_a: i2c1 {
 194                                 pins1 {
 195                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 196                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 197                                         bias-disable;
 198                                 };
 199                         };
 200
 201                         i2c2_pins_a: i2c2 {
 202                                 pins1 {
 203                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 204                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 205                                         bias-disable;
 206                                 };
 207                         };
 208
 209                         i2c3_pins_a: i2c3 {
 210                                 pins1 {
 211                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 212                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 213                                         bias-disable;
 214                                 };
 215                         };
 216
 217                         i2c4_pins_a: i2c4 {
 218                                 pins1 {
 219                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 220                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 221                                         bias-disable;
 222                                 };
 223                         };
 224
 225                         i2c6_pins_a: i2c6 {
 226                                 pins1 {
 227                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 228                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 229                                         bias-disable;
 230                                 };
 231                         };
 232                 };
 233
 234                 scpsys: scpsys@10006000 {
 235                         compatible = "mediatek,mt8173-scpsys";
 236                         #power-domain-cells = <1>;
 237                         reg = <0 0x10006000 0 0x1000>;
 238                         clocks = <&clk26m>,
 239                                  <&topckgen CLK_TOP_MM_SEL>,
 240                                  <&topckgen CLK_TOP_VENC_SEL>,
 241                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
 242                         clock-names = "mfg", "mm", "venc", "venc_lt";
 243                         infracfg = <&infracfg>;
 244                 };
 245
 246                 watchdog: watchdog@10007000 {
 247                         compatible = "mediatek,mt8173-wdt",
 248                                      "mediatek,mt6589-wdt";
 249                         reg = <0 0x10007000 0 0x100>;
 250                 };
 251
 252                 timer: timer@10008000 {
 253                         compatible = "mediatek,mt8173-timer",
 254                                      "mediatek,mt6577-timer";
 255                         reg = <0 0x10008000 0 0x1000>;
 256                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
 257                         clocks = <&infracfg CLK_INFRA_CLK_13M>,
 258                                  <&topckgen CLK_TOP_RTC_SEL>;
 259                 };
 260
 261                 pwrap: pwrap@1000d000 {
 262                         compatible = "mediatek,mt8173-pwrap";
 263                         reg = <0 0x1000d000 0 0x1000>;
 264                         reg-names = "pwrap";
 265                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 266                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 267                         reset-names = "pwrap";
 268                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 269                         clock-names = "spi", "wrap";
 270                 };
 271
 272                 sysirq: intpol-controller@10200620 {
 273                         compatible = "mediatek,mt8173-sysirq",
 274                                      "mediatek,mt6577-sysirq";
 275                         interrupt-controller;
 276                         #interrupt-cells = <3>;
 277                         interrupt-parent = <&gic>;
 278                         reg = <0 0x10200620 0 0x20>;
 279                 };
 280
 281                 iommu: iommu@10205000 {
 282                         compatible = "mediatek,mt8173-m4u";
 283                         reg = <0 0x10205000 0 0x1000>;
 284                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
 285                         clocks = <&infracfg CLK_INFRA_M4U>;
 286                         clock-names = "bclk";
 287                         mediatek,larbs = <&larb0 &larb1 &larb2
 288                                           &larb3 &larb4 &larb5>;
 289                         #iommu-cells = <1>;
 290                 };
 291
 292                 efuse: efuse@10206000 {
 293                         compatible = "mediatek,mt8173-efuse";
 294                         reg = <0 0x10206000 0 0x1000>;
 295                 };
 296
 297                 apmixedsys: clock-controller@10209000 {
 298                         compatible = "mediatek,mt8173-apmixedsys";
 299                         reg = <0 0x10209000 0 0x1000>;
 300                         #clock-cells = <1>;
 301                 };
 302
 303                 gic: interrupt-controller@10220000 {
 304                         compatible = "arm,gic-400";
 305                         #interrupt-cells = <3>;
 306                         interrupt-parent = <&gic>;
 307                         interrupt-controller;
 308                         reg = <0 0x10221000 0 0x1000>,
 309                               <0 0x10222000 0 0x2000>,
 310                               <0 0x10224000 0 0x2000>,
 311                               <0 0x10226000 0 0x2000>;
 312                         interrupts = <GIC_PPI 9
 313                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 314                 };
 315
 316                 uart0: serial@11002000 {
 317                         compatible = "mediatek,mt8173-uart",
 318                                      "mediatek,mt6577-uart";
 319                         reg = <0 0x11002000 0 0x400>;
 320                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 321                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 322                         clock-names = "baud", "bus";
 323                         status = "disabled";
 324                 };
 325
 326                 uart1: serial@11003000 {
 327                         compatible = "mediatek,mt8173-uart",
 328                                      "mediatek,mt6577-uart";
 329                         reg = <0 0x11003000 0 0x400>;
 330                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 331                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 332                         clock-names = "baud", "bus";
 333                         status = "disabled";
 334                 };
 335
 336                 uart2: serial@11004000 {
 337                         compatible = "mediatek,mt8173-uart",
 338                                      "mediatek,mt6577-uart";
 339                         reg = <0 0x11004000 0 0x400>;
 340                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 341                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 342                         clock-names = "baud", "bus";
 343                         status = "disabled";
 344                 };
 345
 346                 uart3: serial@11005000 {
 347                         compatible = "mediatek,mt8173-uart",
 348                                      "mediatek,mt6577-uart";
 349                         reg = <0 0x11005000 0 0x400>;
 350                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 351                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 352                         clock-names = "baud", "bus";
 353                         status = "disabled";
 354                 };
 355
 356                 i2c0: i2c@11007000 {
 357                         compatible = "mediatek,mt8173-i2c";
 358                         reg = <0 0x11007000 0 0x70>,
 359                               <0 0x11000100 0 0x80>;
 360                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 361                         clock-div = <16>;
 362                         clocks = <&pericfg CLK_PERI_I2C0>,
 363                                  <&pericfg CLK_PERI_AP_DMA>;
 364                         clock-names = "main", "dma";
 365                         pinctrl-names = "default";
 366                         pinctrl-0 = <&i2c0_pins_a>;
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         status = "disabled";
 370                 };
 371
 372                 i2c1: i2c@11008000 {
 373                         compatible = "mediatek,mt8173-i2c";
 374                         reg = <0 0x11008000 0 0x70>,
 375                               <0 0x11000180 0 0x80>;
 376                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 377                         clock-div = <16>;
 378                         clocks = <&pericfg CLK_PERI_I2C1>,
 379                                  <&pericfg CLK_PERI_AP_DMA>;
 380                         clock-names = "main", "dma";
 381                         pinctrl-names = "default";
 382                         pinctrl-0 = <&i2c1_pins_a>;
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         status = "disabled";
 386                 };
 387
 388                 i2c2: i2c@11009000 {
 389                         compatible = "mediatek,mt8173-i2c";
 390                         reg = <0 0x11009000 0 0x70>,
 391                               <0 0x11000200 0 0x80>;
 392                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 393                         clock-div = <16>;
 394                         clocks = <&pericfg CLK_PERI_I2C2>,
 395                                  <&pericfg CLK_PERI_AP_DMA>;
 396                         clock-names = "main", "dma";
 397                         pinctrl-names = "default";
 398                         pinctrl-0 = <&i2c2_pins_a>;
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         status = "disabled";
 402                 };
 403
 404                 spi: spi@1100a000 {
 405                         compatible = "mediatek,mt8173-spi";
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                         reg = <0 0x1100a000 0 0x1000>;
 409                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 410                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 411                                  <&topckgen CLK_TOP_SPI_SEL>,
 412                                  <&pericfg CLK_PERI_SPI0>;
 413                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 414                         status = "disabled";
 415                 };
 416
 417                 nor_flash: spi@1100d000 {
 418                         compatible = "mediatek,mt8173-nor";
 419                         reg = <0 0x1100d000 0 0xe0>;
 420                         clocks = <&pericfg CLK_PERI_SPI>,
 421                                  <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
 422                         clock-names = "spi", "sf";
 423                         #address-cells = <1>;
 424                         #size-cells = <0>;
 425                         status = "disabled";
 426                 };
 427
 428                 i2c3: i2c@11010000 {
 429                         compatible = "mediatek,mt8173-i2c";
 430                         reg = <0 0x11010000 0 0x70>,
 431                               <0 0x11000280 0 0x80>;
 432                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 433                         clock-div = <16>;
 434                         clocks = <&pericfg CLK_PERI_I2C3>,
 435                                  <&pericfg CLK_PERI_AP_DMA>;
 436                         clock-names = "main", "dma";
 437                         pinctrl-names = "default";
 438                         pinctrl-0 = <&i2c3_pins_a>;
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         status = "disabled";
 442                 };
 443
 444                 i2c4: i2c@11011000 {
 445                         compatible = "mediatek,mt8173-i2c";
 446                         reg = <0 0x11011000 0 0x70>,
 447                               <0 0x11000300 0 0x80>;
 448                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 449                         clock-div = <16>;
 450                         clocks = <&pericfg CLK_PERI_I2C4>,
 451                                  <&pericfg CLK_PERI_AP_DMA>;
 452                         clock-names = "main", "dma";
 453                         pinctrl-names = "default";
 454                         pinctrl-0 = <&i2c4_pins_a>;
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         status = "disabled";
 458                 };
 459
 460                 i2c6: i2c@11013000 {
 461                         compatible = "mediatek,mt8173-i2c";
 462                         reg = <0 0x11013000 0 0x70>,
 463                               <0 0x11000080 0 0x80>;
 464                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 465                         clock-div = <16>;
 466                         clocks = <&pericfg CLK_PERI_I2C6>,
 467                                  <&pericfg CLK_PERI_AP_DMA>;
 468                         clock-names = "main", "dma";
 469                         pinctrl-names = "default";
 470                         pinctrl-0 = <&i2c6_pins_a>;
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473                         status = "disabled";
 474                 };
 475
 476                 afe: audio-controller@11220000  {
 477                         compatible = "mediatek,mt8173-afe-pcm";
 478                         reg = <0 0x11220000 0 0x1000>;
 479                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 480                         power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
 481                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 482                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 483                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 484                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 485                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 486                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 487                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 488                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 489                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 490                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 491                         clock-names = "infra_sys_audio_clk",
 492                                       "top_pdn_audio",
 493                                       "top_pdn_aud_intbus",
 494                                       "bck0",
 495                                       "bck1",
 496                                       "i2s0_m",
 497                                       "i2s1_m",
 498                                       "i2s2_m",
 499                                       "i2s3_m",
 500                                       "i2s3_b";
 501                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 502                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 503                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 504                                                  <&topckgen CLK_TOP_APLL2>;
 505                 };
 506
 507                 mmc0: mmc@11230000 {
 508                         compatible = "mediatek,mt8173-mmc",
 509                                      "mediatek,mt8135-mmc";
 510                         reg = <0 0x11230000 0 0x1000>;
 511                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 512                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 513                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 514                         clock-names = "source", "hclk";
 515                         status = "disabled";
 516                 };
 517
 518                 mmc1: mmc@11240000 {
 519                         compatible = "mediatek,mt8173-mmc",
 520                                      "mediatek,mt8135-mmc";
 521                         reg = <0 0x11240000 0 0x1000>;
 522                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 523                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 524                                  <&topckgen CLK_TOP_AXI_SEL>;
 525                         clock-names = "source", "hclk";
 526                         status = "disabled";
 527                 };
 528
 529                 mmc2: mmc@11250000 {
 530                         compatible = "mediatek,mt8173-mmc",
 531                                      "mediatek,mt8135-mmc";
 532                         reg = <0 0x11250000 0 0x1000>;
 533                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 534                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 535                                  <&topckgen CLK_TOP_AXI_SEL>;
 536                         clock-names = "source", "hclk";
 537                         status = "disabled";
 538                 };
 539
 540                 mmc3: mmc@11260000 {
 541                         compatible = "mediatek,mt8173-mmc",
 542                                      "mediatek,mt8135-mmc";
 543                         reg = <0 0x11260000 0 0x1000>;
 544                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 545                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 546                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 547                         clock-names = "source", "hclk";
 548                         status = "disabled";
 549                 };
 550
 551                 usb30: usb@11270000 {
 552                         compatible = "mediatek,mt8173-xhci";
 553                         reg = <0 0x11270000 0 0x1000>,
 554                               <0 0x11280700 0 0x0100>;
 555                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
 556                         power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 557                         clocks = <&topckgen CLK_TOP_USB30_SEL>,
 558                                  <&pericfg CLK_PERI_USB0>,
 559                                  <&pericfg CLK_PERI_USB1>;
 560                         clock-names = "sys_ck",
 561                                       "wakeup_deb_p0",
 562                                       "wakeup_deb_p1";
 563                         phys = <&phy_port0 PHY_TYPE_USB3>,
 564                                <&phy_port1 PHY_TYPE_USB2>;
 565                         mediatek,syscon-wakeup = <&pericfg>;
 566                         status = "okay";
 567                 };
 568
 569                 u3phy: usb-phy@11290000 {
 570                         compatible = "mediatek,mt8173-u3phy";
 571                         reg = <0 0x11290000 0 0x800>;
 572                         clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 573                         clock-names = "u3phya_ref";
 574                         #address-cells = <2>;
 575                         #size-cells = <2>;
 576                         ranges;
 577                         status = "okay";
 578
 579                         phy_port0: port@11290800 {
 580                                 reg = <0 0x11290800 0 0x800>;
 581                                 #phy-cells = <1>;
 582                                 status = "okay";
 583                         };
 584
 585                         phy_port1: port@11291000 {
 586                                 reg = <0 0x11291000 0 0x800>;
 587                                 #phy-cells = <1>;
 588                                 status = "okay";
 589                         };
 590                 };
 591
 592                 mmsys: clock-controller@14000000 {
 593                         compatible = "mediatek,mt8173-mmsys", "syscon";
 594                         reg = <0 0x14000000 0 0x1000>;
 595                         #clock-cells = <1>;
 596                 };
 597
 598                 pwm0: pwm@1401e000 {
 599                         compatible = "mediatek,mt8173-disp-pwm",
 600                                      "mediatek,mt6595-disp-pwm";
 601                         reg = <0 0x1401e000 0 0x1000>;
 602                         #pwm-cells = <2>;
 603                         clocks = <&mmsys CLK_MM_DISP_PWM026M>,
 604                                  <&mmsys CLK_MM_DISP_PWM0MM>;
 605                         clock-names = "main", "mm";
 606                         status = "disabled";
 607                 };
 608
 609                 pwm1: pwm@1401f000 {
 610                         compatible = "mediatek,mt8173-disp-pwm",
 611                                      "mediatek,mt6595-disp-pwm";
 612                         reg = <0 0x1401f000 0 0x1000>;
 613                         #pwm-cells = <2>;
 614                         clocks = <&mmsys CLK_MM_DISP_PWM126M>,
 615                                  <&mmsys CLK_MM_DISP_PWM1MM>;
 616                         clock-names = "main", "mm";
 617                         status = "disabled";
 618                 };
 619
 620                 larb0: larb@14021000 {
 621                         compatible = "mediatek,mt8173-smi-larb";
 622                         reg = <0 0x14021000 0 0x1000>;
 623                         mediatek,smi = <&smi_common>;
 624                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 625                         clocks = <&mmsys CLK_MM_SMI_LARB0>,
 626                                  <&mmsys CLK_MM_SMI_LARB0>;
 627                         clock-names = "apb", "smi";
 628                 };
 629
 630                 smi_common: smi@14022000 {
 631                         compatible = "mediatek,mt8173-smi-common";
 632                         reg = <0 0x14022000 0 0x1000>;
 633                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 634                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
 635                                  <&mmsys CLK_MM_SMI_COMMON>;
 636                         clock-names = "apb", "smi";
 637                 };
 638
 639                 larb4: larb@14027000 {
 640                         compatible = "mediatek,mt8173-smi-larb";
 641                         reg = <0 0x14027000 0 0x1000>;
 642                         mediatek,smi = <&smi_common>;
 643                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 644                         clocks = <&mmsys CLK_MM_SMI_LARB4>,
 645                                  <&mmsys CLK_MM_SMI_LARB4>;
 646                         clock-names = "apb", "smi";
 647                 };
 648
 649                 imgsys: clock-controller@15000000 {
 650                         compatible = "mediatek,mt8173-imgsys", "syscon";
 651                         reg = <0 0x15000000 0 0x1000>;
 652                         #clock-cells = <1>;
 653                 };
 654
 655                 larb2: larb@15001000 {
 656                         compatible = "mediatek,mt8173-smi-larb";
 657                         reg = <0 0x15001000 0 0x1000>;
 658                         mediatek,smi = <&smi_common>;
 659                         power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
 660                         clocks = <&imgsys CLK_IMG_LARB2_SMI>,
 661                                  <&imgsys CLK_IMG_LARB2_SMI>;
 662                         clock-names = "apb", "smi";
 663                 };
 664
 665                 vdecsys: clock-controller@16000000 {
 666                         compatible = "mediatek,mt8173-vdecsys", "syscon";
 667                         reg = <0 0x16000000 0 0x1000>;
 668                         #clock-cells = <1>;
 669                 };
 670
 671                 larb1: larb@16010000 {
 672                         compatible = "mediatek,mt8173-smi-larb";
 673                         reg = <0 0x16010000 0 0x1000>;
 674                         mediatek,smi = <&smi_common>;
 675                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
 676                         clocks = <&vdecsys CLK_VDEC_CKEN>,
 677                                  <&vdecsys CLK_VDEC_LARB_CKEN>;
 678                         clock-names = "apb", "smi";
 679                 };
 680
 681                 vencsys: clock-controller@18000000 {
 682                         compatible = "mediatek,mt8173-vencsys", "syscon";
 683                         reg = <0 0x18000000 0 0x1000>;
 684                         #clock-cells = <1>;
 685                 };
 686
 687                 larb3: larb@18001000 {
 688                         compatible = "mediatek,mt8173-smi-larb";
 689                         reg = <0 0x18001000 0 0x1000>;
 690                         mediatek,smi = <&smi_common>;
 691                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
 692                         clocks = <&vencsys CLK_VENC_CKE1>,
 693                                  <&vencsys CLK_VENC_CKE0>;
 694                         clock-names = "apb", "smi";
 695                 };
 696
 697                 vencltsys: clock-controller@19000000 {
 698                         compatible = "mediatek,mt8173-vencltsys", "syscon";
 699                         reg = <0 0x19000000 0 0x1000>;
 700                         #clock-cells = <1>;
 701                 };
 702
 703                 larb5: larb@19001000 {
 704                         compatible = "mediatek,mt8173-smi-larb";
 705                         reg = <0 0x19001000 0 0x1000>;
 706                         mediatek,smi = <&smi_common>;
 707                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
 708                         clocks = <&vencltsys CLK_VENCLT_CKE1>,
 709                                  <&vencltsys CLK_VENCLT_CKE0>;
 710                         clock-names = "apb", "smi";
 711                 };
 712         };
 713 };
 714