2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
13 #include "mt7622.dtsi"
14 #include "mt6380.dtsi"
17 model = "MediaTek MT7622 RFB1 board";
18 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
21 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
26 proc-supply = <&mt6380_vcpu_reg>;
27 sram-supply = <&mt6380_vm_reg>;
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
37 compatible = "gpio-keys";
38 poll-interval = <100>;
48 linux,code = <KEY_WPS_BUTTON>;
54 reg = <0 0x40000000 0 0x3F000000>;
57 reg_1p8v: regulator-1p8v {
58 compatible = "regulator-fixed";
59 regulator-name = "fixed-1.8V";
60 regulator-min-microvolt = <1800000>;
61 regulator-max-microvolt = <1800000>;
65 reg_3p3v: regulator-3p3v {
66 compatible = "regulator-fixed";
67 regulator-name = "fixed-3.3V";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
74 reg_5v: regulator-5v {
75 compatible = "regulator-fixed";
76 regulator-name = "fixed-5V";
77 regulator-min-microvolt = <5000000>;
78 regulator-max-microvolt = <5000000>;
85 pinctrl-names = "default";
86 pinctrl-0 = <&pcie0_pins>;
95 /* eMMC is shared pin with parallel NAND */
96 emmc_pins_default: emmc-pins-default {
98 function = "emmc", "emmc_rst";
102 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
103 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
104 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
107 pins = "NDL0", "NDL1", "NDL2",
108 "NDL3", "NDL4", "NDL5",
109 "NDL6", "NDL7", "NRB";
120 emmc_pins_uhs: emmc-pins-uhs {
127 pins = "NDL0", "NDL1", "NDL2",
128 "NDL3", "NDL4", "NDL5",
129 "NDL6", "NDL7", "NRB";
131 drive-strength = <4>;
137 drive-strength = <4>;
145 groups = "mdc_mdio", "rgmii_via_gmac2";
149 i2c1_pins: i2c1-pins {
156 i2c2_pins: i2c2-pins {
163 i2s1_pins: i2s1-pins {
166 groups = "i2s_out_mclk_bclk_ws",
172 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
173 "I2S_WS", "I2S_MCLK";
174 drive-strength = <12>;
179 irrx_pins: irrx-pins {
186 irtx_pins: irtx-pins {
193 /* Parallel nand is shared pin with eMMC */
194 parallel_nand_pins: parallel-nand-pins {
201 pcie0_pins: pcie0-pins {
204 groups = "pcie0_pad_perst",
210 pcie1_pins: pcie1-pins {
213 groups = "pcie1_pad_perst",
219 pmic_bus_pins: pmic-bus-pins {
226 pwm7_pins: pwm1-2-pins {
229 groups = "pwm_ch7_2";
233 wled_pins: wled-pins {
240 sd0_pins_default: sd0-pins-default {
246 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
247 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
248 * DAT2, DAT3, CMD, CLK for SD respectively.
251 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
252 "I2S2_IN","I2S4_OUT";
254 drive-strength = <8>;
259 drive-strength = <12>;
268 sd0_pins_uhs: sd0-pins-uhs {
275 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
276 "I2S2_IN","I2S4_OUT";
287 /* Serial NAND is shared pin with SPI-NOR */
288 serial_nand_pins: serial-nand-pins {
295 spic0_pins: spic0-pins {
302 spic1_pins: spic1-pins {
309 /* SPI-NOR is shared pin with serial NAND */
310 spi_nor_pins: spi-nor-pins {
317 /* serial NAND is shared pin with SPI-NOR */
318 serial_nand_pins: serial-nand-pins {
325 uart0_pins: uart0-pins {
328 groups = "uart0_0_tx_rx" ;
332 uart2_pins: uart2-pins {
335 groups = "uart2_1_tx_rx" ;
339 watchdog_pins: watchdog-pins {
341 function = "watchdog";
356 pinctrl-names = "default";
357 pinctrl-0 = <&irrx_pins>;
362 pinctrl-names = "default";
363 pinctrl-0 = <ð_pins>;
367 compatible = "mediatek,eth-mac";
369 phy-handle = <&phy5>;
373 #address-cells = <1>;
376 phy5: ethernet-phy@5 {
384 pinctrl-names = "default";
385 pinctrl-0 = <&i2c1_pins>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&i2c2_pins>;
396 pinctrl-names = "default", "state_uhs";
397 pinctrl-0 = <&emmc_pins_default>;
398 pinctrl-1 = <&emmc_pins_uhs>;
401 max-frequency = <50000000>;
404 vmmc-supply = <®_3p3v>;
405 vqmmc-supply = <®_1p8v>;
406 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
407 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
412 pinctrl-names = "default", "state_uhs";
413 pinctrl-0 = <&sd0_pins_default>;
414 pinctrl-1 = <&sd0_pins_uhs>;
417 max-frequency = <50000000>;
420 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
421 vmmc-supply = <®_3p3v>;
422 vqmmc-supply = <®_3p3v>;
423 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
424 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
428 pinctrl-names = "default";
429 pinctrl-0 = <¶llel_nand_pins>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&spi_nor_pins>;
439 compatible = "jedec,spi-nor";
445 pinctrl-names = "default";
446 pinctrl-0 = <&pwm7_pins>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&pmic_bus_pins>;
466 pinctrl-names = "default";
467 pinctrl-0 = <&spic0_pins>;
472 pinctrl-names = "default";
473 pinctrl-0 = <&spic1_pins>;
478 vusb33-supply = <®_3p3v>;
479 vbus-supply = <®_5v>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&uart0_pins>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&uart2_pins>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&watchdog_pins>;