1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada CP110.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
13 #define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
14 #define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
15 #define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
19 * The contents of the node are defined below, in order to
20 * save one indentation level
22 CP110_NAME: CP110_NAME { };
25 * CPs only have one sensor in the thermal IC.
27 * The cooling maps are empty as there are no cooling devices.
30 CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
31 polling-delay-passive = <1000>;
32 polling-delay = <1000>;
34 thermal-sensors = <&CP110_LABEL(thermal) 0>;
45 compatible = "simple-bus";
46 interrupt-parent = <&CP110_LABEL(icu_nsr)>;
49 config-space@CP110_BASE {
52 compatible = "simple-bus";
53 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
55 CP110_LABEL(ethernet): ethernet@0 {
56 compatible = "marvell,armada-7k-pp22";
57 reg = <0x0 0x100000>, <0x129000 0xb000>;
58 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
59 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
60 <&CP110_LABEL(clk) 1 18>;
61 clock-names = "pp_clk", "gop_clk",
62 "mg_clk", "mg_core_clk", "axi_clk";
63 marvell,system-controller = <&CP110_LABEL(syscon0)>;
67 CP110_LABEL(eth0): eth0 {
68 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
69 <43 IRQ_TYPE_LEVEL_HIGH>,
70 <47 IRQ_TYPE_LEVEL_HIGH>,
71 <51 IRQ_TYPE_LEVEL_HIGH>,
72 <55 IRQ_TYPE_LEVEL_HIGH>,
73 <59 IRQ_TYPE_LEVEL_HIGH>,
74 <63 IRQ_TYPE_LEVEL_HIGH>,
75 <67 IRQ_TYPE_LEVEL_HIGH>,
76 <71 IRQ_TYPE_LEVEL_HIGH>,
77 <129 IRQ_TYPE_LEVEL_HIGH>;
78 interrupt-names = "hif0", "hif1", "hif2",
79 "hif3", "hif4", "hif5", "hif6", "hif7",
86 CP110_LABEL(eth1): eth1 {
87 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
88 <44 IRQ_TYPE_LEVEL_HIGH>,
89 <48 IRQ_TYPE_LEVEL_HIGH>,
90 <52 IRQ_TYPE_LEVEL_HIGH>,
91 <56 IRQ_TYPE_LEVEL_HIGH>,
92 <60 IRQ_TYPE_LEVEL_HIGH>,
93 <64 IRQ_TYPE_LEVEL_HIGH>,
94 <68 IRQ_TYPE_LEVEL_HIGH>,
95 <72 IRQ_TYPE_LEVEL_HIGH>,
96 <128 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-names = "hif0", "hif1", "hif2",
98 "hif3", "hif4", "hif5", "hif6", "hif7",
105 CP110_LABEL(eth2): eth2 {
106 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
107 <45 IRQ_TYPE_LEVEL_HIGH>,
108 <49 IRQ_TYPE_LEVEL_HIGH>,
109 <53 IRQ_TYPE_LEVEL_HIGH>,
110 <57 IRQ_TYPE_LEVEL_HIGH>,
111 <61 IRQ_TYPE_LEVEL_HIGH>,
112 <65 IRQ_TYPE_LEVEL_HIGH>,
113 <69 IRQ_TYPE_LEVEL_HIGH>,
114 <73 IRQ_TYPE_LEVEL_HIGH>,
115 <127 IRQ_TYPE_LEVEL_HIGH>;
116 interrupt-names = "hif0", "hif1", "hif2",
117 "hif3", "hif4", "hif5", "hif6", "hif7",
125 CP110_LABEL(comphy): phy@120000 {
126 compatible = "marvell,comphy-cp110";
127 reg = <0x120000 0x6000>;
128 marvell,system-controller = <&CP110_LABEL(syscon0)>;
129 #address-cells = <1>;
132 CP110_LABEL(comphy0): phy@0 {
137 CP110_LABEL(comphy1): phy@1 {
142 CP110_LABEL(comphy2): phy@2 {
147 CP110_LABEL(comphy3): phy@3 {
152 CP110_LABEL(comphy4): phy@4 {
157 CP110_LABEL(comphy5): phy@5 {
163 CP110_LABEL(mdio): mdio@12a200 {
164 #address-cells = <1>;
166 compatible = "marvell,orion-mdio";
167 reg = <0x12a200 0x10>;
168 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
169 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
173 CP110_LABEL(xmdio): mdio@12a600 {
174 #address-cells = <1>;
176 compatible = "marvell,xmdio";
177 reg = <0x12a600 0x10>;
178 clocks = <&CP110_LABEL(clk) 1 5>,
179 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
183 CP110_LABEL(icu): interrupt-controller@1e0000 {
184 compatible = "marvell,cp110-icu";
185 reg = <0x1e0000 0x440>;
186 #address-cells = <1>;
189 CP110_LABEL(icu_nsr): interrupt-controller@10 {
190 compatible = "marvell,cp110-icu-nsr";
192 #interrupt-cells = <2>;
193 interrupt-controller;
194 msi-parent = <&gicp>;
197 CP110_LABEL(icu_sei): interrupt-controller@50 {
198 compatible = "marvell,cp110-icu-sei";
200 #interrupt-cells = <2>;
201 interrupt-controller;
206 CP110_LABEL(rtc): rtc@284000 {
207 compatible = "marvell,armada-8k-rtc";
208 reg = <0x284000 0x20>, <0x284080 0x24>;
209 reg-names = "rtc", "rtc-soc";
210 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
213 CP110_LABEL(syscon0): system-controller@440000 {
214 compatible = "syscon", "simple-mfd";
215 reg = <0x440000 0x2000>;
217 CP110_LABEL(clk): clock {
218 compatible = "marvell,cp110-clock";
222 CP110_LABEL(gpio1): gpio@100 {
223 compatible = "marvell,armada-8k-gpio";
228 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
229 interrupt-controller;
230 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
231 <85 IRQ_TYPE_LEVEL_HIGH>,
232 <84 IRQ_TYPE_LEVEL_HIGH>,
233 <83 IRQ_TYPE_LEVEL_HIGH>;
237 CP110_LABEL(gpio2): gpio@140 {
238 compatible = "marvell,armada-8k-gpio";
243 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
244 interrupt-controller;
245 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
246 <81 IRQ_TYPE_LEVEL_HIGH>,
247 <80 IRQ_TYPE_LEVEL_HIGH>,
248 <79 IRQ_TYPE_LEVEL_HIGH>;
253 CP110_LABEL(syscon1): system-controller@400000 {
254 compatible = "syscon", "simple-mfd";
255 reg = <0x400000 0x1000>;
256 #address-cells = <1>;
259 CP110_LABEL(thermal): thermal-sensor@70 {
260 compatible = "marvell,armada-cp110-thermal";
262 #thermal-sensor-cells = <1>;
266 CP110_LABEL(usb3_0): usb3@500000 {
267 compatible = "marvell,armada-8k-xhci",
269 reg = <0x500000 0x4000>;
271 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
272 clock-names = "core", "reg";
273 clocks = <&CP110_LABEL(clk) 1 22>,
274 <&CP110_LABEL(clk) 1 16>;
278 CP110_LABEL(usb3_1): usb3@510000 {
279 compatible = "marvell,armada-8k-xhci",
281 reg = <0x510000 0x4000>;
283 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
284 clock-names = "core", "reg";
285 clocks = <&CP110_LABEL(clk) 1 23>,
286 <&CP110_LABEL(clk) 1 16>;
290 CP110_LABEL(sata0): sata@540000 {
291 compatible = "marvell,armada-8k-ahci",
293 reg = <0x540000 0x30000>;
295 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&CP110_LABEL(clk) 1 15>,
297 <&CP110_LABEL(clk) 1 16>;
301 CP110_LABEL(xor0): xor@6a0000 {
302 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
303 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
305 msi-parent = <&gic_v2m0>;
306 clock-names = "core", "reg";
307 clocks = <&CP110_LABEL(clk) 1 8>,
308 <&CP110_LABEL(clk) 1 14>;
311 CP110_LABEL(xor1): xor@6c0000 {
312 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
313 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
315 msi-parent = <&gic_v2m0>;
316 clock-names = "core", "reg";
317 clocks = <&CP110_LABEL(clk) 1 7>,
318 <&CP110_LABEL(clk) 1 14>;
321 CP110_LABEL(spi0): spi@700600 {
322 compatible = "marvell,armada-380-spi";
323 reg = <0x700600 0x50>;
324 #address-cells = <0x1>;
326 clock-names = "core", "axi";
327 clocks = <&CP110_LABEL(clk) 1 21>,
328 <&CP110_LABEL(clk) 1 17>;
332 CP110_LABEL(spi1): spi@700680 {
333 compatible = "marvell,armada-380-spi";
334 reg = <0x700680 0x50>;
335 #address-cells = <1>;
337 clock-names = "core", "axi";
338 clocks = <&CP110_LABEL(clk) 1 21>,
339 <&CP110_LABEL(clk) 1 17>;
343 CP110_LABEL(i2c0): i2c@701000 {
344 compatible = "marvell,mv78230-i2c";
345 reg = <0x701000 0x20>;
346 #address-cells = <1>;
348 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
349 clock-names = "core", "reg";
350 clocks = <&CP110_LABEL(clk) 1 21>,
351 <&CP110_LABEL(clk) 1 17>;
355 CP110_LABEL(i2c1): i2c@701100 {
356 compatible = "marvell,mv78230-i2c";
357 reg = <0x701100 0x20>;
358 #address-cells = <1>;
360 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
361 clock-names = "core", "reg";
362 clocks = <&CP110_LABEL(clk) 1 21>,
363 <&CP110_LABEL(clk) 1 17>;
367 CP110_LABEL(uart0): serial@702000 {
368 compatible = "snps,dw-apb-uart";
369 reg = <0x702000 0x100>;
371 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
373 clock-names = "baudclk", "apb_pclk";
374 clocks = <&CP110_LABEL(clk) 1 21>,
375 <&CP110_LABEL(clk) 1 17>;
379 CP110_LABEL(uart1): serial@702100 {
380 compatible = "snps,dw-apb-uart";
381 reg = <0x702100 0x100>;
383 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
385 clock-names = "baudclk", "apb_pclk";
386 clocks = <&CP110_LABEL(clk) 1 21>,
387 <&CP110_LABEL(clk) 1 17>;
391 CP110_LABEL(uart2): serial@702200 {
392 compatible = "snps,dw-apb-uart";
393 reg = <0x702200 0x100>;
395 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
397 clock-names = "baudclk", "apb_pclk";
398 clocks = <&CP110_LABEL(clk) 1 21>,
399 <&CP110_LABEL(clk) 1 17>;
403 CP110_LABEL(uart3): serial@702300 {
404 compatible = "snps,dw-apb-uart";
405 reg = <0x702300 0x100>;
407 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
409 clock-names = "baudclk", "apb_pclk";
410 clocks = <&CP110_LABEL(clk) 1 21>,
411 <&CP110_LABEL(clk) 1 17>;
415 CP110_LABEL(nand_controller): nand@720000 {
417 * Due to the limitation of the pins available
418 * this controller is only usable on the CPM
419 * for A7K and on the CPS for A8K.
421 compatible = "marvell,armada-8k-nand-controller",
422 "marvell,armada370-nand-controller";
423 reg = <0x720000 0x54>;
424 #address-cells = <1>;
426 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
427 clock-names = "core", "reg";
428 clocks = <&CP110_LABEL(clk) 1 2>,
429 <&CP110_LABEL(clk) 1 17>;
430 marvell,system-controller = <&CP110_LABEL(syscon0)>;
434 CP110_LABEL(trng): trng@760000 {
435 compatible = "marvell,armada-8k-rng",
436 "inside-secure,safexcel-eip76";
437 reg = <0x760000 0x7d>;
438 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
439 clock-names = "core", "reg";
440 clocks = <&CP110_LABEL(clk) 1 25>,
441 <&CP110_LABEL(clk) 1 17>;
445 CP110_LABEL(sdhci0): sdhci@780000 {
446 compatible = "marvell,armada-cp110-sdhci";
447 reg = <0x780000 0x300>;
448 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
449 clock-names = "core", "axi";
450 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
455 CP110_LABEL(crypto): crypto@800000 {
456 compatible = "inside-secure,safexcel-eip197b";
457 reg = <0x800000 0x200000>;
458 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
459 <88 IRQ_TYPE_LEVEL_HIGH>,
460 <89 IRQ_TYPE_LEVEL_HIGH>,
461 <90 IRQ_TYPE_LEVEL_HIGH>,
462 <91 IRQ_TYPE_LEVEL_HIGH>,
463 <92 IRQ_TYPE_LEVEL_HIGH>;
464 interrupt-names = "mem", "ring0", "ring1",
465 "ring2", "ring3", "eip";
466 clock-names = "core", "reg";
467 clocks = <&CP110_LABEL(clk) 1 26>,
468 <&CP110_LABEL(clk) 1 17>;
473 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
474 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
475 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
476 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
477 reg-names = "ctrl", "config";
478 #address-cells = <3>;
480 #interrupt-cells = <1>;
483 msi-parent = <&gic_v2m0>;
485 bus-range = <0 0xff>;
488 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
489 /* non-prefetchable memory */
490 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
491 interrupt-map-mask = <0 0 0 0>;
492 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
493 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
495 clock-names = "core", "reg";
496 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
500 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
501 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
502 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
503 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
504 reg-names = "ctrl", "config";
505 #address-cells = <3>;
507 #interrupt-cells = <1>;
510 msi-parent = <&gic_v2m0>;
512 bus-range = <0 0xff>;
515 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
516 /* non-prefetchable memory */
517 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
518 interrupt-map-mask = <0 0 0 0>;
519 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
520 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
523 clock-names = "core", "reg";
524 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
528 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
529 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
530 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
531 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
532 reg-names = "ctrl", "config";
533 #address-cells = <3>;
535 #interrupt-cells = <1>;
538 msi-parent = <&gic_v2m0>;
540 bus-range = <0 0xff>;
543 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
544 /* non-prefetchable memory */
545 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
546 interrupt-map-mask = <0 0 0 0>;
547 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
548 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
551 clock-names = "core", "reg";
552 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;