1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada CP110.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
10 #include "armada-common.dtsi"
12 #define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
13 #define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
14 #define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
18 * The contents of the node are defined below, in order to
19 * save one indentation level
21 CP110_NAME: CP110_NAME { };
27 compatible = "simple-bus";
28 interrupt-parent = <&CP110_LABEL(icu)>;
31 config-space@CP110_BASE {
34 compatible = "simple-bus";
35 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
37 CP110_LABEL(ethernet): ethernet@0 {
38 compatible = "marvell,armada-7k-pp22";
39 reg = <0x0 0x100000>, <0x129000 0xb000>;
40 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
41 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>;
42 clock-names = "pp_clk", "gop_clk",
44 marvell,system-controller = <&CP110_LABEL(syscon0)>;
48 CP110_LABEL(eth0): eth0 {
49 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
50 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
51 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
52 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
53 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
54 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
55 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
56 "tx-cpu3", "rx-shared", "link";
62 CP110_LABEL(eth1): eth1 {
63 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
64 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
65 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
66 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
67 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
68 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
70 "tx-cpu3", "rx-shared", "link";
76 CP110_LABEL(eth2): eth2 {
77 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
78 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
79 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
80 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
81 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
82 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
83 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
84 "tx-cpu3", "rx-shared", "link";
91 CP110_LABEL(comphy): phy@120000 {
92 compatible = "marvell,comphy-cp110";
93 reg = <0x120000 0x6000>;
94 marvell,system-controller = <&CP110_LABEL(syscon0)>;
98 CP110_LABEL(comphy0): phy@0 {
103 CP110_LABEL(comphy1): phy@1 {
108 CP110_LABEL(comphy2): phy@2 {
113 CP110_LABEL(comphy3): phy@3 {
118 CP110_LABEL(comphy4): phy@4 {
123 CP110_LABEL(comphy5): phy@5 {
129 CP110_LABEL(mdio): mdio@12a200 {
130 #address-cells = <1>;
132 compatible = "marvell,orion-mdio";
133 reg = <0x12a200 0x10>;
134 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
135 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
139 CP110_LABEL(xmdio): mdio@12a600 {
140 #address-cells = <1>;
142 compatible = "marvell,xmdio";
143 reg = <0x12a600 0x10>;
147 CP110_LABEL(icu): interrupt-controller@1e0000 {
148 compatible = "marvell,cp110-icu";
149 reg = <0x1e0000 0x10>;
150 #interrupt-cells = <3>;
151 interrupt-controller;
152 msi-parent = <&gicp>;
155 CP110_LABEL(rtc): rtc@284000 {
156 compatible = "marvell,armada-8k-rtc";
157 reg = <0x284000 0x20>, <0x284080 0x24>;
158 reg-names = "rtc", "rtc-soc";
159 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
162 CP110_LABEL(thermal): thermal@400078 {
163 compatible = "marvell,armada-cp110-thermal";
164 reg = <0x400078 0x4>,
168 CP110_LABEL(syscon0): system-controller@440000 {
169 compatible = "syscon", "simple-mfd";
170 reg = <0x440000 0x2000>;
172 CP110_LABEL(clk): clock {
173 compatible = "marvell,cp110-clock";
177 CP110_LABEL(gpio1): gpio@100 {
178 compatible = "marvell,armada-8k-gpio";
183 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
184 interrupt-controller;
185 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
186 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
187 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
188 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
192 CP110_LABEL(gpio2): gpio@140 {
193 compatible = "marvell,armada-8k-gpio";
198 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
199 interrupt-controller;
200 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
201 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
202 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
203 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
208 CP110_LABEL(usb3_0): usb3@500000 {
209 compatible = "marvell,armada-8k-xhci",
211 reg = <0x500000 0x4000>;
213 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
214 clock-names = "core", "reg";
215 clocks = <&CP110_LABEL(clk) 1 22>,
216 <&CP110_LABEL(clk) 1 16>;
220 CP110_LABEL(usb3_1): usb3@510000 {
221 compatible = "marvell,armada-8k-xhci",
223 reg = <0x510000 0x4000>;
225 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
226 clock-names = "core", "reg";
227 clocks = <&CP110_LABEL(clk) 1 23>,
228 <&CP110_LABEL(clk) 1 16>;
232 CP110_LABEL(sata0): sata@540000 {
233 compatible = "marvell,armada-8k-ahci",
235 reg = <0x540000 0x30000>;
236 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&CP110_LABEL(clk) 1 15>,
238 <&CP110_LABEL(clk) 1 16>;
242 CP110_LABEL(xor0): xor@6a0000 {
243 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
244 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
246 msi-parent = <&gic_v2m0>;
247 clock-names = "core", "reg";
248 clocks = <&CP110_LABEL(clk) 1 8>,
249 <&CP110_LABEL(clk) 1 14>;
252 CP110_LABEL(xor1): xor@6c0000 {
253 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
254 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
256 msi-parent = <&gic_v2m0>;
257 clock-names = "core", "reg";
258 clocks = <&CP110_LABEL(clk) 1 7>,
259 <&CP110_LABEL(clk) 1 14>;
262 CP110_LABEL(spi0): spi@700600 {
263 compatible = "marvell,armada-380-spi";
264 reg = <0x700600 0x50>;
265 #address-cells = <0x1>;
267 clock-names = "core", "axi";
268 clocks = <&CP110_LABEL(clk) 1 21>,
269 <&CP110_LABEL(clk) 1 17>;
273 CP110_LABEL(spi1): spi@700680 {
274 compatible = "marvell,armada-380-spi";
275 reg = <0x700680 0x50>;
276 #address-cells = <1>;
278 clock-names = "core", "axi";
279 clocks = <&CP110_LABEL(clk) 1 21>,
280 <&CP110_LABEL(clk) 1 17>;
284 CP110_LABEL(i2c0): i2c@701000 {
285 compatible = "marvell,mv78230-i2c";
286 reg = <0x701000 0x20>;
287 #address-cells = <1>;
289 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
290 clock-names = "core", "reg";
291 clocks = <&CP110_LABEL(clk) 1 21>,
292 <&CP110_LABEL(clk) 1 17>;
296 CP110_LABEL(i2c1): i2c@701100 {
297 compatible = "marvell,mv78230-i2c";
298 reg = <0x701100 0x20>;
299 #address-cells = <1>;
301 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
302 clock-names = "core", "reg";
303 clocks = <&CP110_LABEL(clk) 1 21>,
304 <&CP110_LABEL(clk) 1 17>;
308 CP110_LABEL(uart0): serial@702000 {
309 compatible = "snps,dw-apb-uart";
310 reg = <0x702000 0x100>;
312 interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
314 clock-names = "baudclk", "apb_pclk";
315 clocks = <&CP110_LABEL(clk) 1 21>,
316 <&CP110_LABEL(clk) 1 17>;
320 CP110_LABEL(uart1): serial@702100 {
321 compatible = "snps,dw-apb-uart";
322 reg = <0x702100 0x100>;
324 interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
326 clock-names = "baudclk", "apb_pclk";
327 clocks = <&CP110_LABEL(clk) 1 21>,
328 <&CP110_LABEL(clk) 1 17>;
332 CP110_LABEL(uart2): serial@702200 {
333 compatible = "snps,dw-apb-uart";
334 reg = <0x702200 0x100>;
336 interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
338 clock-names = "baudclk", "apb_pclk";
339 clocks = <&CP110_LABEL(clk) 1 21>,
340 <&CP110_LABEL(clk) 1 17>;
344 CP110_LABEL(uart3): serial@702300 {
345 compatible = "snps,dw-apb-uart";
346 reg = <0x702300 0x100>;
348 interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
350 clock-names = "baudclk", "apb_pclk";
351 clocks = <&CP110_LABEL(clk) 1 21>,
352 <&CP110_LABEL(clk) 1 17>;
356 CP110_LABEL(nand_controller): nand@720000 {
358 * Due to the limitation of the pins available
359 * this controller is only usable on the CPM
360 * for A7K and on the CPS for A8K.
362 compatible = "marvell,armada-8k-nand-controller",
363 "marvell,armada370-nand-controller";
364 reg = <0x720000 0x54>;
365 #address-cells = <1>;
367 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
368 clock-names = "core", "reg";
369 clocks = <&CP110_LABEL(clk) 1 2>,
370 <&CP110_LABEL(clk) 1 17>;
371 marvell,system-controller = <&CP110_LABEL(syscon0)>;
375 CP110_LABEL(trng): trng@760000 {
376 compatible = "marvell,armada-8k-rng",
377 "inside-secure,safexcel-eip76";
378 reg = <0x760000 0x7d>;
379 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
380 clock-names = "core", "reg";
381 clocks = <&CP110_LABEL(clk) 1 25>,
382 <&CP110_LABEL(clk) 1 17>;
386 CP110_LABEL(sdhci0): sdhci@780000 {
387 compatible = "marvell,armada-cp110-sdhci";
388 reg = <0x780000 0x300>;
389 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
390 clock-names = "core", "axi";
391 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
396 CP110_LABEL(crypto): crypto@800000 {
397 compatible = "inside-secure,safexcel-eip197";
398 reg = <0x800000 0x200000>;
399 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
400 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
401 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
402 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
403 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
404 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
405 interrupt-names = "mem", "ring0", "ring1",
406 "ring2", "ring3", "eip";
407 clock-names = "core", "reg";
408 clocks = <&CP110_LABEL(clk) 1 26>,
409 <&CP110_LABEL(clk) 1 17>;
414 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
415 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
416 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
417 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
418 reg-names = "ctrl", "config";
419 #address-cells = <3>;
421 #interrupt-cells = <1>;
424 msi-parent = <&gic_v2m0>;
426 bus-range = <0 0xff>;
429 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
430 /* non-prefetchable memory */
431 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
432 interrupt-map-mask = <0 0 0 0>;
433 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
434 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
436 clock-names = "core", "reg";
437 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
441 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
442 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
443 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
444 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
445 reg-names = "ctrl", "config";
446 #address-cells = <3>;
448 #interrupt-cells = <1>;
451 msi-parent = <&gic_v2m0>;
453 bus-range = <0 0xff>;
456 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
457 /* non-prefetchable memory */
458 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
459 interrupt-map-mask = <0 0 0 0>;
460 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
461 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
464 clock-names = "core", "reg";
465 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
469 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
470 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
471 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
472 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
473 reg-names = "ctrl", "config";
474 #address-cells = <3>;
476 #interrupt-cells = <1>;
479 msi-parent = <&gic_v2m0>;
481 bus-range = <0 0xff>;
484 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
485 /* non-prefetchable memory */
486 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
487 interrupt-map-mask = <0 0 0 0>;
488 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
489 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
492 clock-names = "core", "reg";
493 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;