arch/arm64/boot/dts/marvell/armada-ap806.dtsi

   1 /*
   2  * Copyright (C) 2016 Marvell Technology Group Ltd.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPLv2 or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /*
  44  * Device Tree file for Marvell Armada AP806.
  45  */
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 /dts-v1/;
  50
  51 / {
  52         model = "Marvell Armada AP806";
  53         compatible = "marvell,armada-ap806";
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         psci {
  58                 compatible = "arm,psci-0.2";
  59                 method = "smc";
  60         };
  61
  62
  63         ap806 {
  64                 #address-cells = <2>;
  65                 #size-cells = <2>;
  66                 compatible = "simple-bus";
  67                 interrupt-parent = <&gic>;
  68                 ranges;
  69
  70                 config-space {
  71                         #address-cells = <1>;
  72                         #size-cells = <1>;
  73                         compatible = "simple-bus";
  74                         ranges = <0x0 0x0 0xf0000000 0x1000000>;
  75
  76                         gic: interrupt-controller@210000 {
  77                                 compatible = "arm,gic-400";
  78                                 #interrupt-cells = <3>;
  79                                 #address-cells = <1>;
  80                                 #size-cells = <1>;
  81                                 ranges;
  82                                 interrupt-controller;
  83                                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  84                                 reg = <0x210000 0x10000>,
  85                                       <0x220000 0x20000>,
  86                                       <0x240000 0x20000>,
  87                                       <0x260000 0x20000>;
  88
  89                                 gic_v2m0: v2m@280000 {
  90                                         compatible = "arm,gic-v2m-frame";
  91                                         msi-controller;
  92                                         reg = <0x280000 0x1000>;
  93                                         arm,msi-base-spi = <160>;
  94                                         arm,msi-num-spis = <32>;
  95                                 };
  96                                 gic_v2m1: v2m@290000 {
  97                                         compatible = "arm,gic-v2m-frame";
  98                                         msi-controller;
  99                                         reg = <0x290000 0x1000>;
 100                                         arm,msi-base-spi = <192>;
 101                                         arm,msi-num-spis = <32>;
 102                                 };
 103                                 gic_v2m2: v2m@2a0000 {
 104                                         compatible = "arm,gic-v2m-frame";
 105                                         msi-controller;
 106                                         reg = <0x2a0000 0x1000>;
 107                                         arm,msi-base-spi = <224>;
 108                                         arm,msi-num-spis = <32>;
 109                                 };
 110                                 gic_v2m3: v2m@2b0000 {
 111                                         compatible = "arm,gic-v2m-frame";
 112                                         msi-controller;
 113                                         reg = <0x2b0000 0x1000>;
 114                                         arm,msi-base-spi = <256>;
 115                                         arm,msi-num-spis = <32>;
 116                                 };
 117                         };
 118
 119                         timer {
 120                                 compatible = "arm,armv8-timer";
 121                                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
 122                                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
 123                                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
 124                                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 125                         };
 126
 127                         odmi: odmi@300000 {
 128                                 compatible = "marvell,odmi-controller";
 129                                 interrupt-controller;
 130                                 msi-controller;
 131                                 marvell,odmi-frames = <4>;
 132                                 reg = <0x300000 0x4000>,
 133                                       <0x304000 0x4000>,
 134                                       <0x308000 0x4000>,
 135                                       <0x30C000 0x4000>;
 136                                 marvell,spi-base = <128>, <136>, <144>, <152>;
 137                         };
 138
 139                         xor0@400000 {
 140                                 compatible = "marvell,mv-xor-v2";
 141                                 reg = <0x400000 0x1000>,
 142                                       <0x410000 0x1000>;
 143                                 msi-parent = <&gic_v2m0>;
 144                                 dma-coherent;
 145                         };
 146
 147                         xor1@420000 {
 148                                 compatible = "marvell,mv-xor-v2";
 149                                 reg = <0x420000 0x1000>,
 150                                       <0x430000 0x1000>;
 151                                 msi-parent = <&gic_v2m0>;
 152                                 dma-coherent;
 153                         };
 154
 155                         xor2@440000 {
 156                                 compatible = "marvell,mv-xor-v2";
 157                                 reg = <0x440000 0x1000>,
 158                                       <0x450000 0x1000>;
 159                                 msi-parent = <&gic_v2m0>;
 160                                 dma-coherent;
 161                         };
 162
 163                         xor3@460000 {
 164                                 compatible = "marvell,mv-xor-v2";
 165                                 reg = <0x460000 0x1000>,
 166                                       <0x470000 0x1000>;
 167                                 msi-parent = <&gic_v2m0>;
 168                                 dma-coherent;
 169                         };
 170
 171                         spi0: spi@510600 {
 172                                 compatible = "marvell,armada-380-spi";
 173                                 reg = <0x510600 0x50>;
 174                                 #address-cells = <1>;
 175                                 #size-cells = <0>;
 176                                 cell-index = <0>;
 177                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 178                                 clocks = <&ringclk 2>;
 179                                 status = "disabled";
 180                         };
 181
 182                         i2c0: i2c@511000 {
 183                                 compatible = "marvell,mv64xxx-i2c";
 184                                 reg = <0x511000 0x20>;
 185                                 #address-cells = <1>;
 186                                 #size-cells = <0>;
 187                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 188                                 timeout-ms = <1000>;
 189                                 clocks = <&ringclk 2>;
 190                                 status = "disabled";
 191                         };
 192
 193                         serial@512000 {
 194                                 compatible = "snps,dw-apb-uart";
 195                                 reg = <0x512000 0x100>;
 196                                 reg-shift = <2>;
 197                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 198                                 reg-io-width = <1>;
 199                                 clocks = <&ringclk 2>;
 200                                 status = "disabled";
 201                         };
 202
 203                         serial@512100 {
 204                                 compatible = "snps,dw-apb-uart";
 205                                 reg = <0x512100 0x100>;
 206                                 reg-shift = <2>;
 207                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 208                                 reg-io-width = <1>;
 209                                 clocks = <&ringclk 2>;
 210                                 status = "disabled";
 211
 212                         };
 213
 214                         dfx-server@6f8000 {
 215                                 compatible = "simple-mfd", "syscon";
 216                                 reg = <0x6f8000 0x70000>;
 217
 218                                 coreclk: clk@204 {
 219                                         compatible = "marvell,armada-ap806-core-clock";
 220                                         #clock-cells = <1>;
 221                                         clock-output-names = "ddr", "ring", "cpu";
 222                                 };
 223
 224                                 ringclk: clk@250 {
 225                                         compatible = "marvell,armada-ap806-ring-clock";
 226                                         #clock-cells = <1>;
 227                                         clock-output-names = "ring-0", "ring-2",
 228                                                              "ring-3", "ring-4",
 229                                                              "ring-5";
 230                                         clocks = <&coreclk 1>;
 231                                 };
 232                         };
 233                 };
 234         };
 235
 236 };
 237