arch/arm64/boot/dts/marvell/armada-8040-db.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2016 Marvell Technology Group Ltd.
   4  *
   5  * Device Tree file for Marvell Armada 8040 Development board platform
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include "armada-8040.dtsi"
  10
  11 / {
  12         model = "Marvell Armada 8040 DB board";
  13         compatible = "marvell,armada8040-db", "marvell,armada8040",
  14                      "marvell,armada-ap806-quad", "marvell,armada-ap806";
  15
  16         chosen {
  17                 stdout-path = "serial0:115200n8";
  18         };
  19
  20         memory@0 {
  21                 device_type = "memory";
  22                 reg = <0x0 0x0 0x0 0x80000000>;
  23         };
  24
  25         aliases {
  26                 ethernet0 = &cp0_eth0;
  27                 ethernet1 = &cp0_eth2;
  28                 ethernet2 = &cp1_eth0;
  29                 ethernet3 = &cp1_eth1;
  30         };
  31
  32         cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "cp0-usb3h0-vbus";
  35                 regulator-min-microvolt = <5000000>;
  36                 regulator-max-microvolt = <5000000>;
  37                 enable-active-high;
  38                 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
  39         };
  40
  41         cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
  42                 compatible = "regulator-fixed";
  43                 regulator-name = "cp0-usb3h1-vbus";
  44                 regulator-min-microvolt = <5000000>;
  45                 regulator-max-microvolt = <5000000>;
  46                 enable-active-high;
  47                 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
  48         };
  49
  50         cp0_usb3_0_phy: cp0-usb3-0-phy {
  51                 compatible = "usb-nop-xceiv";
  52                 vcc-supply = <&cp0_reg_usb3_0_vbus>;
  53         };
  54
  55         cp0_usb3_1_phy: cp0-usb3-1-phy {
  56                 compatible = "usb-nop-xceiv";
  57                 vcc-supply = <&cp0_reg_usb3_1_vbus>;
  58         };
  59
  60         cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
  61                 compatible = "regulator-fixed";
  62                 regulator-name = "cp1-usb3h0-vbus";
  63                 regulator-min-microvolt = <5000000>;
  64                 regulator-max-microvolt = <5000000>;
  65                 enable-active-high;
  66                 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
  67         };
  68
  69         cp1_usb3_0_phy: cp1-usb3-0-phy {
  70                 compatible = "usb-nop-xceiv";
  71                 vcc-supply = <&cp1_reg_usb3_0_vbus>;
  72         };
  73 };
  74
  75 &i2c0 {
  76         status = "okay";
  77         clock-frequency = <100000>;
  78 };
  79
  80 &spi0 {
  81         status = "okay";
  82
  83         spi-flash@0 {
  84                 #address-cells = <1>;
  85                 #size-cells = <1>;
  86                 compatible = "jedec,spi-nor";
  87                 reg = <0>;
  88                 spi-max-frequency = <10000000>;
  89
  90                 partitions {
  91                         compatible = "fixed-partitions";
  92                         #address-cells = <1>;
  93                         #size-cells = <1>;
  94
  95                         partition@0 {
  96                                 label = "U-Boot";
  97                                 reg = <0 0x200000>;
  98                         };
  99                         partition@400000 {
 100                                 label = "Filesystem";
 101                                 reg = <0x200000 0xce0000>;
 102                         };
 103                 };
 104         };
 105 };
 106
 107 /* Accessible over the mini-USB CON9 connector on the main board */
 108 &uart0 {
 109         status = "okay";
 110         pinctrl-0 = <&uart0_pins>;
 111         pinctrl-names = "default";
 112 };
 113
 114 /* CON6 on CP0 expansion */
 115 &cp0_pcie0 {
 116         status = "okay";
 117 };
 118
 119 /* CON5 on CP0 expansion */
 120 &cp0_pcie2 {
 121         status = "okay";
 122 };
 123
 124 &cp0_i2c0 {
 125         status = "okay";
 126         clock-frequency = <100000>;
 127
 128         /* U31 */
 129         expander0: pca9555@21 {
 130                 compatible = "nxp,pca9555";
 131                 pinctrl-names = "default";
 132                 gpio-controller;
 133                 #gpio-cells = <2>;
 134                 reg = <0x21>;
 135         };
 136
 137         /* U25 */
 138         expander1: pca9555@25 {
 139                 compatible = "nxp,pca9555";
 140                 pinctrl-names = "default";
 141                 gpio-controller;
 142                 #gpio-cells = <2>;
 143                 reg = <0x25>;
 144         };
 145
 146 };
 147
 148 /* CON4 on CP0 expansion */
 149 &cp0_sata0 {
 150         status = "okay";
 151 };
 152
 153 /* CON9 on CP0 expansion */
 154 &cp0_usb3_0 {
 155         usb-phy = <&cp0_usb3_0_phy>;
 156         status = "okay";
 157 };
 158
 159 /* CON10 on CP0 expansion */
 160 &cp0_usb3_1 {
 161         usb-phy = <&cp0_usb3_1_phy>;
 162         status = "okay";
 163 };
 164
 165 &cp0_mdio {
 166         status = "okay";
 167
 168         phy1: ethernet-phy@1 {
 169                 reg = <1>;
 170         };
 171 };
 172
 173 &cp0_ethernet {
 174         status = "okay";
 175 };
 176
 177 &cp0_eth0 {
 178         status = "okay";
 179         phy-mode = "10gbase-kr";
 180 };
 181
 182 &cp0_eth2 {
 183         status = "okay";
 184         phy = <&phy1>;
 185         phy-mode = "rgmii-id";
 186 };
 187
 188 /* CON6 on CP1 expansion */
 189 &cp1_pcie0 {
 190         status = "okay";
 191 };
 192
 193 /* CON7 on CP1 expansion */
 194 &cp1_pcie1 {
 195         status = "okay";
 196 };
 197
 198 /* CON5 on CP1 expansion */
 199 &cp1_pcie2 {
 200         status = "okay";
 201 };
 202
 203 &cp1_i2c0 {
 204         status = "okay";
 205         clock-frequency = <100000>;
 206 };
 207
 208 &cp1_spi1 {
 209         status = "okay";
 210
 211         spi-flash@0 {
 212                 #address-cells = <0x1>;
 213                 #size-cells = <0x1>;
 214                 compatible = "jedec,spi-nor";
 215                 reg = <0x0>;
 216                 spi-max-frequency = <20000000>;
 217
 218                 partitions {
 219                         compatible = "fixed-partitions";
 220                         #address-cells = <1>;
 221                         #size-cells = <1>;
 222
 223                         partition@0 {
 224                                 label = "Boot";
 225                                 reg = <0x0 0x200000>;
 226                         };
 227                         partition@200000 {
 228                                 label = "Filesystem";
 229                                 reg = <0x200000 0xd00000>;
 230                         };
 231                         partition@f00000 {
 232                                 label = "Boot_2nd";
 233                                 reg = <0xf00000 0x100000>;
 234                         };
 235                 };
 236         };
 237 };
 238
 239 /*
 240  * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
 241  * MDIO signal of CP1.
 242  */
 243 &cp1_nand_controller {
 244         pinctrl-0 = <&nand_pins>, <&nand_rb>;
 245         pinctrl-names = "default";
 246
 247         nand@0 {
 248                 reg = <0>;
 249                 nand-rb = <0>;
 250                 nand-on-flash-bbt;
 251                 nand-ecc-strength = <4>;
 252                 nand-ecc-step-size = <512>;
 253
 254                 partitions {
 255                         compatible = "fixed-partitions";
 256                         #address-cells = <1>;
 257                         #size-cells = <1>;
 258
 259                         partition@0 {
 260                                 label = "U-Boot";
 261                                 reg = <0 0x200000>;
 262                         };
 263                         partition@200000 {
 264                                 label = "Linux";
 265                                 reg = <0x200000 0xe00000>;
 266                         };
 267                         partition@1000000 {
 268                                 label = "Filesystem";
 269                                 reg = <0x1000000 0x3f000000>;
 270                         };
 271                 };
 272         };
 273 };
 274
 275 /* CON4 on CP1 expansion */
 276 &cp1_sata0 {
 277         status = "okay";
 278 };
 279
 280 /* CON9 on CP1 expansion */
 281 &cp1_usb3_0 {
 282         usb-phy = <&cp1_usb3_0_phy>;
 283         status = "okay";
 284 };
 285
 286 /* CON10 on CP1 expansion */
 287 &cp1_usb3_1 {
 288         status = "okay";
 289 };
 290
 291 &cp1_mdio {
 292         status = "okay";
 293
 294         phy0: ethernet-phy@0 {
 295                 reg = <0>;
 296         };
 297 };
 298
 299 &cp1_ethernet {
 300         status = "okay";
 301 };
 302
 303 &cp1_eth0 {
 304         status = "okay";
 305         phy-mode = "10gbase-kr";
 306 };
 307
 308 &cp1_eth1 {
 309         status = "okay";
 310         phy = <&phy0>;
 311         phy-mode = "rgmii-id";
 312 };
 313
 314 &ap_sdhci0 {
 315         status = "okay";
 316         bus-width = <4>;
 317         non-removable;
 318 };
 319
 320 &cp0_sdhci0 {
 321         status = "okay";
 322         bus-width = <8>;
 323         non-removable;
 324 };