1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek BehĂșn <kabel@kernel.org>
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
15 model = "CZ.NIC Turris Mox Board";
16 compatible = "cznic,turris-mox", "marvell,armada3720",
28 stdout-path = "serial0:115200n8";
32 device_type = "memory";
33 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
37 compatible = "gpio-leds";
39 label = "mox:red:activity";
40 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
41 linux,default-trigger = "default-on";
46 compatible = "gpio-keys";
50 linux,code = <KEY_RESTART>;
51 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
52 debounce-interval = <60>;
56 exp_usb3_vbus: usb3-vbus {
57 compatible = "regulator-fixed";
58 regulator-name = "usb3-vbus";
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
63 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
67 compatible = "regulator-gpio";
68 regulator-name = "vsdc";
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <3300000>;
73 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
80 vsdio_reg: vsdio-reg {
81 compatible = "regulator-gpio";
82 regulator-name = "vsdio";
83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <3300000>;
87 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
94 sdhci1_pwrseq: sdhci1-pwrseq {
95 compatible = "mmc-pwrseq-simple";
96 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
101 compatible = "sff,sfp";
103 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
104 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
105 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
106 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
107 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
108 maximum-power-milliwatt = <3000>;
110 /* enabled by U-Boot if SFP module is present */
116 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
122 pinctrl-names = "default";
123 pinctrl-0 = <&i2c1_pins>;
124 clock-frequency = <100000>;
125 /delete-property/ mrvl,i2c-fast-mode;
129 compatible = "microchip,mcp7940x";
135 pinctrl-names = "default";
136 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
138 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
140 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
141 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
142 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
143 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
144 * no remapping) and that this address is the lowest from all specified ranges. If these
145 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
146 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
147 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
148 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
149 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
150 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
151 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
152 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
153 * Bug related to requirement of same child and parent addresses for first range is fixed
154 * in U-Boot version 2022.04 by following commit:
155 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
157 #address-cells = <3>;
159 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
160 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
162 /* enabled by U-Boot if PCIe module is present */
171 pinctrl-names = "default";
172 pinctrl-0 = <&rgmii_pins>;
173 phy-mode = "rgmii-id";
174 phy-handle = <&phy1>;
179 phy-mode = "2500base-x";
180 managed = "in-band-status";
187 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
188 vqmmc-supply = <&vsdc_reg>;
189 marvell,pad-type = "sd";
194 pinctrl-names = "default";
195 pinctrl-0 = <&sdio_pins>;
198 marvell,pad-type = "sd";
199 vqmmc-supply = <&vsdio_reg>;
200 mmc-pwrseq = <&sdhci1_pwrseq>;
201 /* forbid SDR104 for FCC purposes */
202 sdhci-caps-mask = <0x2 0x0>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
210 assigned-clocks = <&nb_periph_clk 7>;
211 assigned-clock-parents = <&tbg 1>;
212 assigned-clock-rates = <20000000>;
215 #address-cells = <1>;
217 compatible = "jedec,spi-nor";
219 spi-max-frequency = <20000000>;
222 compatible = "fixed-partitions";
223 #address-cells = <1>;
227 label = "secure-firmware";
232 label = "a53-firmware";
233 reg = <0x20000 0x160000>;
237 label = "u-boot-env";
238 reg = <0x180000 0x10000>;
242 label = "Rescue system";
243 reg = <0x190000 0x660000>;
248 reg = <0x7f0000 0x10000>;
254 #address-cells = <1>;
256 compatible = "cznic,moxtet";
258 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
259 spi-max-frequency = <10000000>;
262 interrupt-controller;
263 #interrupt-cells = <1>;
264 interrupt-parent = <&gpiosb>;
265 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
269 compatible = "cznic,moxtet-gpio";
284 compatible = "usb-a-connector";
285 phy-supply = <&exp_usb3_vbus>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&smi_pins>;
299 phy1: ethernet-phy@1 {
303 /* switch nodes are enabled by U-Boot if modules are present */
305 compatible = "marvell,mv88e6190";
308 interrupt-parent = <&moxtet>;
309 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
313 #address-cells = <1>;
316 switch0phy1: switch0phy1@1 {
320 switch0phy2: switch0phy2@2 {
324 switch0phy3: switch0phy3@3 {
328 switch0phy4: switch0phy4@4 {
332 switch0phy5: switch0phy5@5 {
336 switch0phy6: switch0phy6@6 {
340 switch0phy7: switch0phy7@7 {
344 switch0phy8: switch0phy8@8 {
350 #address-cells = <1>;
356 phy-handle = <&switch0phy1>;
362 phy-handle = <&switch0phy2>;
368 phy-handle = <&switch0phy3>;
374 phy-handle = <&switch0phy4>;
380 phy-handle = <&switch0phy5>;
386 phy-handle = <&switch0phy6>;
392 phy-handle = <&switch0phy7>;
398 phy-handle = <&switch0phy8>;
405 phy-mode = "2500base-x";
406 managed = "in-band-status";
409 switch0port10: port@a {
412 phy-mode = "2500base-x";
413 managed = "in-band-status";
414 link = <&switch1port9 &switch2port9>;
423 managed = "in-band-status";
430 compatible = "marvell,mv88e6085";
433 interrupt-parent = <&moxtet>;
434 interrupts = <MOXTET_IRQ_TOPAZ>;
438 #address-cells = <1>;
441 switch0phy1_topaz: switch0phy1@11 {
445 switch0phy2_topaz: switch0phy2@12 {
449 switch0phy3_topaz: switch0phy3@13 {
453 switch0phy4_topaz: switch0phy4@14 {
459 #address-cells = <1>;
465 phy-handle = <&switch0phy1_topaz>;
471 phy-handle = <&switch0phy2_topaz>;
477 phy-handle = <&switch0phy3_topaz>;
483 phy-handle = <&switch0phy4_topaz>;
489 phy-mode = "2500base-x";
490 managed = "in-band-status";
497 compatible = "marvell,mv88e6190";
500 interrupt-parent = <&moxtet>;
501 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
505 #address-cells = <1>;
508 switch1phy1: switch1phy1@1 {
512 switch1phy2: switch1phy2@2 {
516 switch1phy3: switch1phy3@3 {
520 switch1phy4: switch1phy4@4 {
524 switch1phy5: switch1phy5@5 {
528 switch1phy6: switch1phy6@6 {
532 switch1phy7: switch1phy7@7 {
536 switch1phy8: switch1phy8@8 {
542 #address-cells = <1>;
548 phy-handle = <&switch1phy1>;
554 phy-handle = <&switch1phy2>;
560 phy-handle = <&switch1phy3>;
566 phy-handle = <&switch1phy4>;
572 phy-handle = <&switch1phy5>;
578 phy-handle = <&switch1phy6>;
584 phy-handle = <&switch1phy7>;
590 phy-handle = <&switch1phy8>;
593 switch1port9: port@9 {
596 phy-mode = "2500base-x";
597 managed = "in-band-status";
598 link = <&switch0port10>;
601 switch1port10: port@a {
604 phy-mode = "2500base-x";
605 managed = "in-band-status";
606 link = <&switch2port9>;
615 managed = "in-band-status";
622 compatible = "marvell,mv88e6085";
625 interrupt-parent = <&moxtet>;
626 interrupts = <MOXTET_IRQ_TOPAZ>;
630 #address-cells = <1>;
633 switch1phy1_topaz: switch1phy1@11 {
637 switch1phy2_topaz: switch1phy2@12 {
641 switch1phy3_topaz: switch1phy3@13 {
645 switch1phy4_topaz: switch1phy4@14 {
651 #address-cells = <1>;
657 phy-handle = <&switch1phy1_topaz>;
663 phy-handle = <&switch1phy2_topaz>;
669 phy-handle = <&switch1phy3_topaz>;
675 phy-handle = <&switch1phy4_topaz>;
681 phy-mode = "2500base-x";
682 managed = "in-band-status";
683 link = <&switch0port10>;
689 compatible = "marvell,mv88e6190";
692 interrupt-parent = <&moxtet>;
693 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
697 #address-cells = <1>;
700 switch2phy1: switch2phy1@1 {
704 switch2phy2: switch2phy2@2 {
708 switch2phy3: switch2phy3@3 {
712 switch2phy4: switch2phy4@4 {
716 switch2phy5: switch2phy5@5 {
720 switch2phy6: switch2phy6@6 {
724 switch2phy7: switch2phy7@7 {
728 switch2phy8: switch2phy8@8 {
734 #address-cells = <1>;
740 phy-handle = <&switch2phy1>;
746 phy-handle = <&switch2phy2>;
752 phy-handle = <&switch2phy3>;
758 phy-handle = <&switch2phy4>;
764 phy-handle = <&switch2phy5>;
770 phy-handle = <&switch2phy6>;
776 phy-handle = <&switch2phy7>;
782 phy-handle = <&switch2phy8>;
785 switch2port9: port@9 {
788 phy-mode = "2500base-x";
789 managed = "in-band-status";
790 link = <&switch1port10 &switch0port10>;
798 managed = "in-band-status";
805 compatible = "marvell,mv88e6085";
808 interrupt-parent = <&moxtet>;
809 interrupts = <MOXTET_IRQ_TOPAZ>;
813 #address-cells = <1>;
816 switch2phy1_topaz: switch2phy1@11 {
820 switch2phy2_topaz: switch2phy2@12 {
824 switch2phy3_topaz: switch2phy3@13 {
828 switch2phy4_topaz: switch2phy4@14 {
834 #address-cells = <1>;
840 phy-handle = <&switch2phy1_topaz>;
846 phy-handle = <&switch2phy2_topaz>;
852 phy-handle = <&switch2phy3_topaz>;
858 phy-handle = <&switch2phy4_topaz>;
864 phy-mode = "2500base-x";
865 managed = "in-band-status";
866 link = <&switch1port10 &switch0port10>;