1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for lg1313 SoC
5 * Copyright (C) 2016, LG Electronics
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "lge,lg1313";
16 interrupt-parent = <&gic>;
24 compatible = "arm,cortex-a53";
26 next-level-cache = <&L2_0>;
30 compatible = "arm,cortex-a53";
32 enable-method = "psci";
33 next-level-cache = <&L2_0>;
37 compatible = "arm,cortex-a53";
39 enable-method = "psci";
40 next-level-cache = <&L2_0>;
44 compatible = "arm,cortex-a53";
46 enable-method = "psci";
47 next-level-cache = <&L2_0>;
57 compatible = "arm,psci-0.2", "arm,psci";
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
64 gic: interrupt-controller@c0001000 {
65 #interrupt-cells = <3>;
66 compatible = "arm,gic-400";
68 reg = <0x0 0xc0001000 0x1000>,
69 <0x0 0xc0002000 0x2000>,
70 <0x0 0xc0004000 0x2000>,
71 <0x0 0xc0006000 0x2000>;
75 compatible = "arm,cortex-a53-pmu";
76 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
80 interrupt-affinity = <&cpu0>,
87 compatible = "arm,armv8-timer";
88 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
90 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
92 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
94 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
101 compatible = "fixed-clock";
102 clock-frequency = <198000000>;
103 clock-output-names = "BUSCLK";
107 #address-cells = <2>;
110 compatible = "simple-bus";
111 interrupt-parent = <&gic>;
114 eth0: ethernet@c3700000 {
115 compatible = "cdns,gem";
116 reg = <0x0 0xc3700000 0x1000>;
117 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&clk_bus>, <&clk_bus>;
119 clock-names = "hclk", "pclk";
121 /* Filled in by boot */
122 mac-address = [ 00 00 00 00 00 00 ];
127 #address-cells = <2>;
130 compatible = "simple-bus";
131 interrupt-parent = <&gic>;
134 timers: timer@fd100000 {
135 compatible = "arm,sp804", "arm,primecell";
136 reg = <0x0 0xfd100000 0x1000>;
137 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
139 clock-names = "timer0clk", "timer1clk", "apb_pclk";
141 wdog: watchdog@fd200000 {
142 compatible = "arm,sp805", "arm,primecell";
143 reg = <0x0 0xfd200000 0x1000>;
144 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&clk_bus>, <&clk_bus>;
146 clock-names = "wdog_clk", "apb_pclk";
148 uart0: serial@fe000000 {
149 compatible = "arm,pl011", "arm,primecell";
150 reg = <0x0 0xfe000000 0x1000>;
151 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
153 clock-names = "apb_pclk";
156 uart1: serial@fe100000 {
157 compatible = "arm,pl011", "arm,primecell";
158 reg = <0x0 0xfe100000 0x1000>;
159 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
161 clock-names = "apb_pclk";
164 uart2: serial@fe200000 {
165 compatible = "arm,pl011", "arm,primecell";
166 reg = <0x0 0xfe200000 0x1000>;
167 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
169 clock-names = "apb_pclk";
173 compatible = "arm,pl022", "arm,primecell";
174 reg = <0x0 0xfe800000 0x1000>;
175 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
177 clock-names = "apb_pclk";
180 compatible = "arm,pl022", "arm,primecell";
181 reg = <0x0 0xfe900000 0x1000>;
182 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
184 clock-names = "apb_pclk";
186 dmac0: dma-controller@c1128000 {
187 compatible = "arm,pl330", "arm,primecell";
188 reg = <0x0 0xc1128000 0x1000>;
189 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
191 clock-names = "apb_pclk";
194 gpio0: gpio@fd400000 {
196 compatible = "arm,pl061", "arm,primecell";
198 reg = <0x0 0xfd400000 0x1000>;
200 clock-names = "apb_pclk";
203 gpio1: gpio@fd410000 {
205 compatible = "arm,pl061", "arm,primecell";
207 reg = <0x0 0xfd410000 0x1000>;
209 clock-names = "apb_pclk";
212 gpio2: gpio@fd420000 {
214 compatible = "arm,pl061", "arm,primecell";
216 reg = <0x0 0xfd420000 0x1000>;
218 clock-names = "apb_pclk";
221 gpio3: gpio@fd430000 {
223 compatible = "arm,pl061", "arm,primecell";
225 reg = <0x0 0xfd430000 0x1000>;
227 clock-names = "apb_pclk";
229 gpio4: gpio@fd440000 {
231 compatible = "arm,pl061", "arm,primecell";
233 reg = <0x0 0xfd440000 0x1000>;
235 clock-names = "apb_pclk";
238 gpio5: gpio@fd450000 {
240 compatible = "arm,pl061", "arm,primecell";
242 reg = <0x0 0xfd450000 0x1000>;
244 clock-names = "apb_pclk";
247 gpio6: gpio@fd460000 {
249 compatible = "arm,pl061", "arm,primecell";
251 reg = <0x0 0xfd460000 0x1000>;
253 clock-names = "apb_pclk";
256 gpio7: gpio@fd470000 {
258 compatible = "arm,pl061", "arm,primecell";
260 reg = <0x0 0xfd470000 0x1000>;
262 clock-names = "apb_pclk";
265 gpio8: gpio@fd480000 {
267 compatible = "arm,pl061", "arm,primecell";
269 reg = <0x0 0xfd480000 0x1000>;
271 clock-names = "apb_pclk";
274 gpio9: gpio@fd490000 {
276 compatible = "arm,pl061", "arm,primecell";
278 reg = <0x0 0xfd490000 0x1000>;
280 clock-names = "apb_pclk";
283 gpio10: gpio@fd4a0000 {
285 compatible = "arm,pl061", "arm,primecell";
287 reg = <0x0 0xfd4a0000 0x1000>;
289 clock-names = "apb_pclk";
292 gpio11: gpio@fd4b0000 {
294 compatible = "arm,pl061", "arm,primecell";
296 reg = <0x0 0xfd4b0000 0x1000>;
298 clock-names = "apb_pclk";
300 gpio12: gpio@fd4c0000 {
302 compatible = "arm,pl061", "arm,primecell";
304 reg = <0x0 0xfd4c0000 0x1000>;
306 clock-names = "apb_pclk";
309 gpio13: gpio@fd4d0000 {
311 compatible = "arm,pl061", "arm,primecell";
313 reg = <0x0 0xfd4d0000 0x1000>;
315 clock-names = "apb_pclk";
318 gpio14: gpio@fd4e0000 {
320 compatible = "arm,pl061", "arm,primecell";
322 reg = <0x0 0xfd4e0000 0x1000>;
324 clock-names = "apb_pclk";
327 gpio15: gpio@fd4f0000 {
329 compatible = "arm,pl061", "arm,primecell";
331 reg = <0x0 0xfd4f0000 0x1000>;
333 clock-names = "apb_pclk";
336 gpio16: gpio@fd500000 {
338 compatible = "arm,pl061", "arm,primecell";
340 reg = <0x0 0xfd500000 0x1000>;
342 clock-names = "apb_pclk";
345 gpio17: gpio@fd510000 {
347 compatible = "arm,pl061", "arm,primecell";
349 reg = <0x0 0xfd510000 0x1000>;
351 clock-names = "apb_pclk";