arch/arm64/boot/dts/freescale/imx8mp.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mp-clock.h>
   7 #include <dt-bindings/power/imx8mp-power.h>
   8 #include <dt-bindings/reset/imx8mp-reset.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 #include "imx8mp-pinfunc.h"
  16
  17 / {
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 ethernet0 = &fec;
  24                 ethernet1 = &eqos;
  25                 gpio0 = &gpio1;
  26                 gpio1 = &gpio2;
  27                 gpio2 = &gpio3;
  28                 gpio3 = &gpio4;
  29                 gpio4 = &gpio5;
  30                 i2c0 = &i2c1;
  31                 i2c1 = &i2c2;
  32                 i2c2 = &i2c3;
  33                 i2c3 = &i2c4;
  34                 i2c4 = &i2c5;
  35                 i2c5 = &i2c6;
  36                 mmc0 = &usdhc1;
  37                 mmc1 = &usdhc2;
  38                 mmc2 = &usdhc3;
  39                 serial0 = &uart1;
  40                 serial1 = &uart2;
  41                 serial2 = &uart3;
  42                 serial3 = &uart4;
  43                 spi0 = &flexspi;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 A53_0: cpu@0 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53";
  53                         reg = <0x0>;
  54                         clock-latency = <61036>;
  55                         clocks = <&clk IMX8MP_CLK_ARM>;
  56                         enable-method = "psci";
  57                         i-cache-size = <0x8000>;
  58                         i-cache-line-size = <64>;
  59                         i-cache-sets = <256>;
  60                         d-cache-size = <0x8000>;
  61                         d-cache-line-size = <64>;
  62                         d-cache-sets = <128>;
  63                         next-level-cache = <&A53_L2>;
  64                         nvmem-cells = <&cpu_speed_grade>;
  65                         nvmem-cell-names = "speed_grade";
  66                         operating-points-v2 = <&a53_opp_table>;
  67                         #cooling-cells = <2>;
  68                 };
  69
  70                 A53_1: cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53";
  73                         reg = <0x1>;
  74                         clock-latency = <61036>;
  75                         clocks = <&clk IMX8MP_CLK_ARM>;
  76                         enable-method = "psci";
  77                         i-cache-size = <0x8000>;
  78                         i-cache-line-size = <64>;
  79                         i-cache-sets = <256>;
  80                         d-cache-size = <0x8000>;
  81                         d-cache-line-size = <64>;
  82                         d-cache-sets = <128>;
  83                         next-level-cache = <&A53_L2>;
  84                         operating-points-v2 = <&a53_opp_table>;
  85                         #cooling-cells = <2>;
  86                 };
  87
  88                 A53_2: cpu@2 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a53";
  91                         reg = <0x2>;
  92                         clock-latency = <61036>;
  93                         clocks = <&clk IMX8MP_CLK_ARM>;
  94                         enable-method = "psci";
  95                         i-cache-size = <0x8000>;
  96                         i-cache-line-size = <64>;
  97                         i-cache-sets = <256>;
  98                         d-cache-size = <0x8000>;
  99                         d-cache-line-size = <64>;
 100                         d-cache-sets = <128>;
 101                         next-level-cache = <&A53_L2>;
 102                         operating-points-v2 = <&a53_opp_table>;
 103                         #cooling-cells = <2>;
 104                 };
 105
 106                 A53_3: cpu@3 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a53";
 109                         reg = <0x3>;
 110                         clock-latency = <61036>;
 111                         clocks = <&clk IMX8MP_CLK_ARM>;
 112                         enable-method = "psci";
 113                         i-cache-size = <0x8000>;
 114                         i-cache-line-size = <64>;
 115                         i-cache-sets = <256>;
 116                         d-cache-size = <0x8000>;
 117                         d-cache-line-size = <64>;
 118                         d-cache-sets = <128>;
 119                         next-level-cache = <&A53_L2>;
 120                         operating-points-v2 = <&a53_opp_table>;
 121                         #cooling-cells = <2>;
 122                 };
 123
 124                 A53_L2: l2-cache0 {
 125                         compatible = "cache";
 126                         cache-unified;
 127                         cache-level = <2>;
 128                         cache-size = <0x80000>;
 129                         cache-line-size = <64>;
 130                         cache-sets = <512>;
 131                 };
 132         };
 133
 134         a53_opp_table: opp-table {
 135                 compatible = "operating-points-v2";
 136                 opp-shared;
 137
 138                 opp-1200000000 {
 139                         opp-hz = /bits/ 64 <1200000000>;
 140                         opp-microvolt = <850000>;
 141                         opp-supported-hw = <0x8a0>, <0x7>;
 142                         clock-latency-ns = <150000>;
 143                         opp-suspend;
 144                 };
 145
 146                 opp-1600000000 {
 147                         opp-hz = /bits/ 64 <1600000000>;
 148                         opp-microvolt = <950000>;
 149                         opp-supported-hw = <0xa0>, <0x7>;
 150                         clock-latency-ns = <150000>;
 151                         opp-suspend;
 152                 };
 153
 154                 opp-1800000000 {
 155                         opp-hz = /bits/ 64 <1800000000>;
 156                         opp-microvolt = <1000000>;
 157                         opp-supported-hw = <0x20>, <0x3>;
 158                         clock-latency-ns = <150000>;
 159                         opp-suspend;
 160                 };
 161         };
 162
 163         osc_32k: clock-osc-32k {
 164                 compatible = "fixed-clock";
 165                 #clock-cells = <0>;
 166                 clock-frequency = <32768>;
 167                 clock-output-names = "osc_32k";
 168         };
 169
 170         osc_24m: clock-osc-24m {
 171                 compatible = "fixed-clock";
 172                 #clock-cells = <0>;
 173                 clock-frequency = <24000000>;
 174                 clock-output-names = "osc_24m";
 175         };
 176
 177         clk_ext1: clock-ext1 {
 178                 compatible = "fixed-clock";
 179                 #clock-cells = <0>;
 180                 clock-frequency = <133000000>;
 181                 clock-output-names = "clk_ext1";
 182         };
 183
 184         clk_ext2: clock-ext2 {
 185                 compatible = "fixed-clock";
 186                 #clock-cells = <0>;
 187                 clock-frequency = <133000000>;
 188                 clock-output-names = "clk_ext2";
 189         };
 190
 191         clk_ext3: clock-ext3 {
 192                 compatible = "fixed-clock";
 193                 #clock-cells = <0>;
 194                 clock-frequency = <133000000>;
 195                 clock-output-names = "clk_ext3";
 196         };
 197
 198         clk_ext4: clock-ext4 {
 199                 compatible = "fixed-clock";
 200                 #clock-cells = <0>;
 201                 clock-frequency = <133000000>;
 202                 clock-output-names = "clk_ext4";
 203         };
 204
 205         reserved-memory {
 206                 #address-cells = <2>;
 207                 #size-cells = <2>;
 208                 ranges;
 209
 210                 dsp_reserved: dsp@92400000 {
 211                         reg = <0 0x92400000 0 0x2000000>;
 212                         no-map;
 213                 };
 214         };
 215
 216         pmu {
 217                 compatible = "arm,cortex-a53-pmu";
 218                 interrupts = <GIC_PPI 7
 219                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 220         };
 221
 222         psci {
 223                 compatible = "arm,psci-1.0";
 224                 method = "smc";
 225         };
 226
 227         thermal-zones {
 228                 cpu-thermal {
 229                         polling-delay-passive = <250>;
 230                         polling-delay = <2000>;
 231                         thermal-sensors = <&tmu 0>;
 232                         trips {
 233                                 cpu_alert0: trip0 {
 234                                         temperature = <85000>;
 235                                         hysteresis = <2000>;
 236                                         type = "passive";
 237                                 };
 238
 239                                 cpu_crit0: trip1 {
 240                                         temperature = <95000>;
 241                                         hysteresis = <2000>;
 242                                         type = "critical";
 243                                 };
 244                         };
 245
 246                         cooling-maps {
 247                                 map0 {
 248                                         trip = <&cpu_alert0>;
 249                                         cooling-device =
 250                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 251                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 252                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 253                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 254                                 };
 255                         };
 256                 };
 257
 258                 soc-thermal {
 259                         polling-delay-passive = <250>;
 260                         polling-delay = <2000>;
 261                         thermal-sensors = <&tmu 1>;
 262                         trips {
 263                                 soc_alert0: trip0 {
 264                                         temperature = <85000>;
 265                                         hysteresis = <2000>;
 266                                         type = "passive";
 267                                 };
 268
 269                                 soc_crit0: trip1 {
 270                                         temperature = <95000>;
 271                                         hysteresis = <2000>;
 272                                         type = "critical";
 273                                 };
 274                         };
 275
 276                         cooling-maps {
 277                                 map0 {
 278                                         trip = <&soc_alert0>;
 279                                         cooling-device =
 280                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 281                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 282                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 283                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 284                                 };
 285                         };
 286                 };
 287         };
 288
 289         timer {
 290                 compatible = "arm,armv8-timer";
 291                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 292                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 293                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 294                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 295                 clock-frequency = <8000000>;
 296                 arm,no-tick-in-suspend;
 297         };
 298
 299         soc: soc@0 {
 300                 compatible = "fsl,imx8mp-soc", "simple-bus";
 301                 #address-cells = <1>;
 302                 #size-cells = <1>;
 303                 ranges = <0x0 0x0 0x0 0x3e000000>;
 304                 nvmem-cells = <&imx8mp_uid>;
 305                 nvmem-cell-names = "soc_unique_id";
 306
 307                 etm0: etm@28440000 {
 308                         compatible = "arm,coresight-etm4x", "arm,primecell";
 309                         reg = <0x28440000 0x1000>;
 310                         cpu = <&A53_0>;
 311                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 312                         clock-names = "apb_pclk";
 313
 314                         out-ports {
 315                                 port {
 316                                         etm0_out_port: endpoint {
 317                                                 remote-endpoint = <&ca_funnel_in_port0>;
 318                                         };
 319                                 };
 320                         };
 321                 };
 322
 323                 etm1: etm@28540000 {
 324                         compatible = "arm,coresight-etm4x", "arm,primecell";
 325                         reg = <0x28540000 0x1000>;
 326                         cpu = <&A53_1>;
 327                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 328                         clock-names = "apb_pclk";
 329
 330                         out-ports {
 331                                 port {
 332                                         etm1_out_port: endpoint {
 333                                                 remote-endpoint = <&ca_funnel_in_port1>;
 334                                         };
 335                                 };
 336                         };
 337                 };
 338
 339                 etm2: etm@28640000 {
 340                         compatible = "arm,coresight-etm4x", "arm,primecell";
 341                         reg = <0x28640000 0x1000>;
 342                         cpu = <&A53_2>;
 343                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 344                         clock-names = "apb_pclk";
 345
 346                         out-ports {
 347                                 port {
 348                                         etm2_out_port: endpoint {
 349                                                 remote-endpoint = <&ca_funnel_in_port2>;
 350                                         };
 351                                 };
 352                         };
 353                 };
 354
 355                 etm3: etm@28740000 {
 356                         compatible = "arm,coresight-etm4x", "arm,primecell";
 357                         reg = <0x28740000 0x1000>;
 358                         cpu = <&A53_3>;
 359                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 360                         clock-names = "apb_pclk";
 361
 362                         out-ports {
 363                                 port {
 364                                         etm3_out_port: endpoint {
 365                                                 remote-endpoint = <&ca_funnel_in_port3>;
 366                                         };
 367                                 };
 368                         };
 369                 };
 370
 371                 funnel {
 372                         /*
 373                          * non-configurable funnel don't show up on the AMBA
 374                          * bus.  As such no need to add "arm,primecell".
 375                          */
 376                         compatible = "arm,coresight-static-funnel";
 377
 378                         in-ports {
 379                                 #address-cells = <1>;
 380                                 #size-cells = <0>;
 381
 382                                 port@0 {
 383                                         reg = <0>;
 384
 385                                         ca_funnel_in_port0: endpoint {
 386                                                 remote-endpoint = <&etm0_out_port>;
 387                                         };
 388                                 };
 389
 390                                 port@1 {
 391                                         reg = <1>;
 392
 393                                         ca_funnel_in_port1: endpoint {
 394                                                 remote-endpoint = <&etm1_out_port>;
 395                                         };
 396                                 };
 397
 398                                 port@2 {
 399                                         reg = <2>;
 400
 401                                         ca_funnel_in_port2: endpoint {
 402                                                 remote-endpoint = <&etm2_out_port>;
 403                                         };
 404                                 };
 405
 406                                 port@3 {
 407                                         reg = <3>;
 408
 409                                         ca_funnel_in_port3: endpoint {
 410                                                 remote-endpoint = <&etm3_out_port>;
 411                                         };
 412                                 };
 413                         };
 414
 415                         out-ports {
 416                                 port {
 417                                         ca_funnel_out_port0: endpoint {
 418                                                 remote-endpoint = <&hugo_funnel_in_port0>;
 419                                         };
 420                                 };
 421                         };
 422                 };
 423
 424                 funnel@28c03000 {
 425                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 426                         reg = <0x28c03000 0x1000>;
 427                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 428                         clock-names = "apb_pclk";
 429
 430                         in-ports {
 431                                 #address-cells = <1>;
 432                                 #size-cells = <0>;
 433
 434                                 port@0 {
 435                                         reg = <0>;
 436
 437                                         hugo_funnel_in_port0: endpoint {
 438                                                 remote-endpoint = <&ca_funnel_out_port0>;
 439                                         };
 440                                 };
 441
 442                                 port@1 {
 443                                         reg = <1>;
 444
 445                                         hugo_funnel_in_port1: endpoint {
 446                                         /* M7 input */
 447                                         };
 448                                 };
 449
 450                                 port@2 {
 451                                         reg = <2>;
 452
 453                                         hugo_funnel_in_port2: endpoint {
 454                                         /* DSP input */
 455                                         };
 456                                 };
 457                                 /* the other input ports are not connect to anything */
 458                         };
 459
 460                         out-ports {
 461                                 port {
 462                                         hugo_funnel_out_port0: endpoint {
 463                                                 remote-endpoint = <&etf_in_port>;
 464                                         };
 465                                 };
 466                         };
 467                 };
 468
 469                 etf@28c04000 {
 470                         compatible = "arm,coresight-tmc", "arm,primecell";
 471                         reg = <0x28c04000 0x1000>;
 472                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 473                         clock-names = "apb_pclk";
 474
 475                         in-ports {
 476                                 port {
 477                                         etf_in_port: endpoint {
 478                                                 remote-endpoint = <&hugo_funnel_out_port0>;
 479                                         };
 480                                 };
 481                         };
 482
 483                         out-ports {
 484                                 port {
 485                                         etf_out_port: endpoint {
 486                                                 remote-endpoint = <&etr_in_port>;
 487                                         };
 488                                 };
 489                         };
 490                 };
 491
 492                 etr@28c06000 {
 493                         compatible = "arm,coresight-tmc", "arm,primecell";
 494                         reg = <0x28c06000 0x1000>;
 495                         clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
 496                         clock-names = "apb_pclk";
 497
 498                         in-ports {
 499                                 port {
 500                                         etr_in_port: endpoint {
 501                                                 remote-endpoint = <&etf_out_port>;
 502                                         };
 503                                 };
 504                         };
 505                 };
 506
 507                 aips1: bus@30000000 {
 508                         compatible = "fsl,aips-bus", "simple-bus";
 509                         reg = <0x30000000 0x400000>;
 510                         #address-cells = <1>;
 511                         #size-cells = <1>;
 512                         ranges;
 513
 514                         gpio1: gpio@30200000 {
 515                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 516                                 reg = <0x30200000 0x10000>;
 517                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 518                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 519                                 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
 520                                 gpio-controller;
 521                                 #gpio-cells = <2>;
 522                                 interrupt-controller;
 523                                 #interrupt-cells = <2>;
 524                                 gpio-ranges = <&iomuxc 0 5 30>;
 525                         };
 526
 527                         gpio2: gpio@30210000 {
 528                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 529                                 reg = <0x30210000 0x10000>;
 530                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 531                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 532                                 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
 533                                 gpio-controller;
 534                                 #gpio-cells = <2>;
 535                                 interrupt-controller;
 536                                 #interrupt-cells = <2>;
 537                                 gpio-ranges = <&iomuxc 0 35 21>;
 538                         };
 539
 540                         gpio3: gpio@30220000 {
 541                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 542                                 reg = <0x30220000 0x10000>;
 543                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 544                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 545                                 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
 546                                 gpio-controller;
 547                                 #gpio-cells = <2>;
 548                                 interrupt-controller;
 549                                 #interrupt-cells = <2>;
 550                                 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
 551                         };
 552
 553                         gpio4: gpio@30230000 {
 554                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 555                                 reg = <0x30230000 0x10000>;
 556                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 557                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 558                                 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
 559                                 gpio-controller;
 560                                 #gpio-cells = <2>;
 561                                 interrupt-controller;
 562                                 #interrupt-cells = <2>;
 563                                 gpio-ranges = <&iomuxc 0 82 32>;
 564                         };
 565
 566                         gpio5: gpio@30240000 {
 567                                 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
 568                                 reg = <0x30240000 0x10000>;
 569                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 570                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 571                                 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
 572                                 gpio-controller;
 573                                 #gpio-cells = <2>;
 574                                 interrupt-controller;
 575                                 #interrupt-cells = <2>;
 576                                 gpio-ranges = <&iomuxc 0 114 30>;
 577                         };
 578
 579                         tmu: tmu@30260000 {
 580                                 compatible = "fsl,imx8mp-tmu";
 581                                 reg = <0x30260000 0x10000>;
 582                                 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
 583                                 nvmem-cells = <&tmu_calib>;
 584                                 nvmem-cell-names = "calib";
 585                                 #thermal-sensor-cells = <1>;
 586                         };
 587
 588                         wdog1: watchdog@30280000 {
 589                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 590                                 reg = <0x30280000 0x10000>;
 591                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 592                                 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
 593                                 status = "disabled";
 594                         };
 595
 596                         wdog2: watchdog@30290000 {
 597                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 598                                 reg = <0x30290000 0x10000>;
 599                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 600                                 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
 601                                 status = "disabled";
 602                         };
 603
 604                         wdog3: watchdog@302a0000 {
 605                                 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
 606                                 reg = <0x302a0000 0x10000>;
 607                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 608                                 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
 609                                 status = "disabled";
 610                         };
 611
 612                         gpt1: timer@302d0000 {
 613                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 614                                 reg = <0x302d0000 0x10000>;
 615                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 616                                 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>;
 617                                 clock-names = "ipg", "per";
 618                         };
 619
 620                         gpt2: timer@302e0000 {
 621                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 622                                 reg = <0x302e0000 0x10000>;
 623                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 624                                 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>;
 625                                 clock-names = "ipg", "per";
 626                         };
 627
 628                         gpt3: timer@302f0000 {
 629                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 630                                 reg = <0x302f0000 0x10000>;
 631                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 632                                 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>;
 633                                 clock-names = "ipg", "per";
 634                         };
 635
 636                         iomuxc: pinctrl@30330000 {
 637                                 compatible = "fsl,imx8mp-iomuxc";
 638                                 reg = <0x30330000 0x10000>;
 639                         };
 640
 641                         gpr: syscon@30340000 {
 642                                 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
 643                                 reg = <0x30340000 0x10000>;
 644                         };
 645
 646                         ocotp: efuse@30350000 {
 647                                 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
 648                                 reg = <0x30350000 0x10000>;
 649                                 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
 650                                 /* For nvmem subnodes */
 651                                 #address-cells = <1>;
 652                                 #size-cells = <1>;
 653
 654                                 /*
 655                                  * The register address below maps to the MX8M
 656                                  * Fusemap Description Table entries this way.
 657                                  * Assuming
 658                                  *   reg = <ADDR SIZE>;
 659                                  * then
 660                                  *   Fuse Address = (ADDR * 4) + 0x400
 661                                  * Note that if SIZE is greater than 4, then
 662                                  * each subsequent fuse is located at offset
 663                                  * +0x10 in Fusemap Description Table (e.g.
 664                                  * reg = <0x8 0x8> describes fuses 0x420 and
 665                                  * 0x430).
 666                                  */
 667                                 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
 668                                         reg = <0x8 0x8>;
 669                                 };
 670
 671                                 cpu_speed_grade: speed-grade@10 { /* 0x440 */
 672                                         reg = <0x10 4>;
 673                                 };
 674
 675                                 eth_mac1: mac-address@90 { /* 0x640 */
 676                                         reg = <0x90 6>;
 677                                 };
 678
 679                                 eth_mac2: mac-address@96 { /* 0x658 */
 680                                         reg = <0x96 6>;
 681                                 };
 682
 683                                 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
 684                                         reg = <0x264 0x10>;
 685                                 };
 686                         };
 687
 688                         anatop: clock-controller@30360000 {
 689                                 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
 690                                 reg = <0x30360000 0x10000>;
 691                                 #clock-cells = <1>;
 692                         };
 693
 694                         snvs: snvs@30370000 {
 695                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 696                                 reg = <0x30370000 0x10000>;
 697
 698                                 snvs_rtc: snvs-rtc-lp {
 699                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 700                                         regmap = <&snvs>;
 701                                         offset = <0x34>;
 702                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 703                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 704                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 705                                         clock-names = "snvs-rtc";
 706                                 };
 707
 708                                 snvs_pwrkey: snvs-powerkey {
 709                                         compatible = "fsl,sec-v4.0-pwrkey";
 710                                         regmap = <&snvs>;
 711                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 712                                         clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 713                                         clock-names = "snvs-pwrkey";
 714                                         linux,keycode = <KEY_POWER>;
 715                                         wakeup-source;
 716                                         status = "disabled";
 717                                 };
 718
 719                                 snvs_lpgpr: snvs-lpgpr {
 720                                         compatible = "fsl,imx8mp-snvs-lpgpr",
 721                                                      "fsl,imx7d-snvs-lpgpr";
 722                                 };
 723                         };
 724
 725                         clk: clock-controller@30380000 {
 726                                 compatible = "fsl,imx8mp-ccm";
 727                                 reg = <0x30380000 0x10000>;
 728                                 #clock-cells = <1>;
 729                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 730                                          <&clk_ext3>, <&clk_ext4>;
 731                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 732                                               "clk_ext3", "clk_ext4";
 733                                 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
 734                                                   <&clk IMX8MP_CLK_A53_CORE>,
 735                                                   <&clk IMX8MP_CLK_NOC>,
 736                                                   <&clk IMX8MP_CLK_NOC_IO>,
 737                                                   <&clk IMX8MP_CLK_GIC>;
 738                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 739                                                          <&clk IMX8MP_ARM_PLL_OUT>,
 740                                                          <&clk IMX8MP_SYS_PLL2_1000M>,
 741                                                          <&clk IMX8MP_SYS_PLL1_800M>,
 742                                                          <&clk IMX8MP_SYS_PLL2_500M>;
 743                                 assigned-clock-rates = <0>, <0>,
 744                                                        <1000000000>,
 745                                                        <800000000>,
 746                                                        <500000000>;
 747                         };
 748
 749                         src: reset-controller@30390000 {
 750                                 compatible = "fsl,imx8mp-src", "syscon";
 751                                 reg = <0x30390000 0x10000>;
 752                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 753                                 #reset-cells = <1>;
 754                         };
 755
 756                         gpc: gpc@303a0000 {
 757                                 compatible = "fsl,imx8mp-gpc";
 758                                 reg = <0x303a0000 0x1000>;
 759                                 interrupt-parent = <&gic>;
 760                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 761                                 interrupt-controller;
 762                                 #interrupt-cells = <3>;
 763
 764                                 pgc {
 765                                         #address-cells = <1>;
 766                                         #size-cells = <0>;
 767
 768                                         pgc_mipi_phy1: power-domain@0 {
 769                                                 #power-domain-cells = <0>;
 770                                                 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
 771                                         };
 772
 773                                         pgc_pcie_phy: power-domain@1 {
 774                                                 #power-domain-cells = <0>;
 775                                                 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
 776                                         };
 777
 778                                         pgc_usb1_phy: power-domain@2 {
 779                                                 #power-domain-cells = <0>;
 780                                                 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
 781                                         };
 782
 783                                         pgc_usb2_phy: power-domain@3 {
 784                                                 #power-domain-cells = <0>;
 785                                                 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
 786                                         };
 787
 788                                         pgc_audio: power-domain@5 {
 789                                                 #power-domain-cells = <0>;
 790                                                 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
 791                                                 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
 792                                                          <&clk IMX8MP_CLK_AUDIO_AXI>;
 793                                                 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
 794                                                                   <&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
 795                                                 assigned-clock-parents =  <&clk IMX8MP_SYS_PLL1_800M>,
 796                                                                           <&clk IMX8MP_SYS_PLL1_800M>;
 797                                                 assigned-clock-rates = <400000000>,
 798                                                                        <600000000>;
 799                                         };
 800
 801                                         pgc_gpu2d: power-domain@6 {
 802                                                 #power-domain-cells = <0>;
 803                                                 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
 804                                                 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
 805                                                 power-domains = <&pgc_gpumix>;
 806                                         };
 807
 808                                         pgc_gpumix: power-domain@7 {
 809                                                 #power-domain-cells = <0>;
 810                                                 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
 811                                                 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
 812                                                          <&clk IMX8MP_CLK_GPU_AHB>;
 813                                                 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
 814                                                                   <&clk IMX8MP_CLK_GPU_AHB>;
 815                                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 816                                                                          <&clk IMX8MP_SYS_PLL1_800M>;
 817                                                 assigned-clock-rates = <800000000>, <400000000>;
 818                                         };
 819
 820                                         pgc_gpu3d: power-domain@9 {
 821                                                 #power-domain-cells = <0>;
 822                                                 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
 823                                                 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
 824                                                          <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
 825                                                 power-domains = <&pgc_gpumix>;
 826                                         };
 827
 828                                         pgc_mediamix: power-domain@10 {
 829                                                 #power-domain-cells = <0>;
 830                                                 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
 831                                                 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
 832                                                          <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
 833                                         };
 834
 835                                         pgc_mipi_phy2: power-domain@16 {
 836                                                 #power-domain-cells = <0>;
 837                                                 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
 838                                         };
 839
 840                                         pgc_hsiomix: power-domain@17 {
 841                                                 #power-domain-cells = <0>;
 842                                                 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
 843                                                 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
 844                                                          <&clk IMX8MP_CLK_HSIO_ROOT>;
 845                                                 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
 846                                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 847                                                 assigned-clock-rates = <500000000>;
 848                                         };
 849
 850                                         pgc_ispdwp: power-domain@18 {
 851                                                 #power-domain-cells = <0>;
 852                                                 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
 853                                                 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
 854                                         };
 855
 856                                         pgc_vpumix: power-domain@19 {
 857                                                 #power-domain-cells = <0>;
 858                                                 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
 859                                                 clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
 860                                         };
 861
 862                                         pgc_vpu_g1: power-domain@20 {
 863                                                 #power-domain-cells = <0>;
 864                                                 power-domains = <&pgc_vpumix>;
 865                                                 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
 866                                                 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
 867                                         };
 868
 869                                         pgc_vpu_g2: power-domain@21 {
 870                                                 #power-domain-cells = <0>;
 871                                                 power-domains = <&pgc_vpumix>;
 872                                                 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
 873                                                 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
 874                                         };
 875
 876                                         pgc_vpu_vc8000e: power-domain@22 {
 877                                                 #power-domain-cells = <0>;
 878                                                 power-domains = <&pgc_vpumix>;
 879                                                 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
 880                                                 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
 881                                         };
 882
 883                                         pgc_mlmix: power-domain@24 {
 884                                                 #power-domain-cells = <0>;
 885                                                 reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
 886                                                 clocks = <&clk IMX8MP_CLK_ML_AXI>,
 887                                                          <&clk IMX8MP_CLK_ML_AHB>,
 888                                                          <&clk IMX8MP_CLK_NPU_ROOT>;
 889                                         };
 890                                 };
 891                         };
 892                 };
 893
 894                 aips2: bus@30400000 {
 895                         compatible = "fsl,aips-bus", "simple-bus";
 896                         reg = <0x30400000 0x400000>;
 897                         #address-cells = <1>;
 898                         #size-cells = <1>;
 899                         ranges;
 900
 901                         pwm1: pwm@30660000 {
 902                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 903                                 reg = <0x30660000 0x10000>;
 904                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 905                                 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
 906                                          <&clk IMX8MP_CLK_PWM1_ROOT>;
 907                                 clock-names = "ipg", "per";
 908                                 #pwm-cells = <3>;
 909                                 status = "disabled";
 910                         };
 911
 912                         pwm2: pwm@30670000 {
 913                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 914                                 reg = <0x30670000 0x10000>;
 915                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 916                                 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
 917                                          <&clk IMX8MP_CLK_PWM2_ROOT>;
 918                                 clock-names = "ipg", "per";
 919                                 #pwm-cells = <3>;
 920                                 status = "disabled";
 921                         };
 922
 923                         pwm3: pwm@30680000 {
 924                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 925                                 reg = <0x30680000 0x10000>;
 926                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 927                                 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
 928                                          <&clk IMX8MP_CLK_PWM3_ROOT>;
 929                                 clock-names = "ipg", "per";
 930                                 #pwm-cells = <3>;
 931                                 status = "disabled";
 932                         };
 933
 934                         pwm4: pwm@30690000 {
 935                                 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
 936                                 reg = <0x30690000 0x10000>;
 937                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 938                                 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
 939                                          <&clk IMX8MP_CLK_PWM4_ROOT>;
 940                                 clock-names = "ipg", "per";
 941                                 #pwm-cells = <3>;
 942                                 status = "disabled";
 943                         };
 944
 945                         system_counter: timer@306a0000 {
 946                                 compatible = "nxp,sysctr-timer";
 947                                 reg = <0x306a0000 0x20000>;
 948                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 949                                 clocks = <&osc_24m>;
 950                                 clock-names = "per";
 951                         };
 952
 953                         gpt6: timer@306e0000 {
 954                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 955                                 reg = <0x306e0000 0x10000>;
 956                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 957                                 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>;
 958                                 clock-names = "ipg", "per";
 959                         };
 960
 961                         gpt5: timer@306f0000 {
 962                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 963                                 reg = <0x306f0000 0x10000>;
 964                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 965                                 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>;
 966                                 clock-names = "ipg", "per";
 967                         };
 968
 969                         gpt4: timer@30700000 {
 970                                 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
 971                                 reg = <0x30700000 0x10000>;
 972                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 973                                 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>;
 974                                 clock-names = "ipg", "per";
 975                         };
 976                 };
 977
 978                 aips3: bus@30800000 {
 979                         compatible = "fsl,aips-bus", "simple-bus";
 980                         reg = <0x30800000 0x400000>;
 981                         #address-cells = <1>;
 982                         #size-cells = <1>;
 983                         ranges;
 984
 985                         spba-bus@30800000 {
 986                                 compatible = "fsl,spba-bus", "simple-bus";
 987                                 reg = <0x30800000 0x100000>;
 988                                 #address-cells = <1>;
 989                                 #size-cells = <1>;
 990                                 ranges;
 991
 992                                 ecspi1: spi@30820000 {
 993                                         #address-cells = <1>;
 994                                         #size-cells = <0>;
 995                                         compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
 996                                         reg = <0x30820000 0x10000>;
 997                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 998                                         clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
 999                                                  <&clk IMX8MP_CLK_ECSPI1_ROOT>;
1000                                         clock-names = "ipg", "per";
1001                                         assigned-clock-rates = <80000000>;
1002                                         assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
1003                                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1004                                         dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1005                                         dma-names = "rx", "tx";
1006                                         status = "disabled";
1007                                 };
1008
1009                                 ecspi2: spi@30830000 {
1010                                         #address-cells = <1>;
1011                                         #size-cells = <0>;
1012                                         compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1013                                         reg = <0x30830000 0x10000>;
1014                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1015                                         clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
1016                                                  <&clk IMX8MP_CLK_ECSPI2_ROOT>;
1017                                         clock-names = "ipg", "per";
1018                                         assigned-clock-rates = <80000000>;
1019                                         assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
1020                                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1021                                         dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
1022                                         dma-names = "rx", "tx";
1023                                         status = "disabled";
1024                                 };
1025
1026                                 ecspi3: spi@30840000 {
1027                                         #address-cells = <1>;
1028                                         #size-cells = <0>;
1029                                         compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1030                                         reg = <0x30840000 0x10000>;
1031                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1032                                         clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
1033                                                  <&clk IMX8MP_CLK_ECSPI3_ROOT>;
1034                                         clock-names = "ipg", "per";
1035                                         assigned-clock-rates = <80000000>;
1036                                         assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
1037                                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1038                                         dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
1039                                         dma-names = "rx", "tx";
1040                                         status = "disabled";
1041                                 };
1042
1043                                 uart1: serial@30860000 {
1044                                         compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1045                                         reg = <0x30860000 0x10000>;
1046                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1047                                         clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
1048                                                  <&clk IMX8MP_CLK_UART1_ROOT>;
1049                                         clock-names = "ipg", "per";
1050                                         dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1051                                         dma-names = "rx", "tx";
1052                                         status = "disabled";
1053                                 };
1054
1055                                 uart3: serial@30880000 {
1056                                         compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1057                                         reg = <0x30880000 0x10000>;
1058                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1059                                         clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
1060                                                  <&clk IMX8MP_CLK_UART3_ROOT>;
1061                                         clock-names = "ipg", "per";
1062                                         dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1063                                         dma-names = "rx", "tx";
1064                                         status = "disabled";
1065                                 };
1066
1067                                 uart2: serial@30890000 {
1068                                         compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1069                                         reg = <0x30890000 0x10000>;
1070                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1071                                         clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
1072                                                  <&clk IMX8MP_CLK_UART2_ROOT>;
1073                                         clock-names = "ipg", "per";
1074                                         dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1075                                         dma-names = "rx", "tx";
1076                                         status = "disabled";
1077                                 };
1078
1079                                 flexcan1: can@308c0000 {
1080                                         compatible = "fsl,imx8mp-flexcan";
1081                                         reg = <0x308c0000 0x10000>;
1082                                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
1083                                         clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1084                                                  <&clk IMX8MP_CLK_CAN1_ROOT>;
1085                                         clock-names = "ipg", "per";
1086                                         assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1087                                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1088                                         assigned-clock-rates = <40000000>;
1089                                         fsl,clk-source = /bits/ 8 <0>;
1090                                         fsl,stop-mode = <&gpr 0x10 4>;
1091                                         status = "disabled";
1092                                 };
1093
1094                                 flexcan2: can@308d0000 {
1095                                         compatible = "fsl,imx8mp-flexcan";
1096                                         reg = <0x308d0000 0x10000>;
1097                                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1098                                         clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1099                                                  <&clk IMX8MP_CLK_CAN2_ROOT>;
1100                                         clock-names = "ipg", "per";
1101                                         assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1102                                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1103                                         assigned-clock-rates = <40000000>;
1104                                         fsl,clk-source = /bits/ 8 <0>;
1105                                         fsl,stop-mode = <&gpr 0x10 5>;
1106                                         status = "disabled";
1107                                 };
1108                         };
1109
1110                         crypto: crypto@30900000 {
1111                                 compatible = "fsl,sec-v4.0";
1112                                 #address-cells = <1>;
1113                                 #size-cells = <1>;
1114                                 reg = <0x30900000 0x40000>;
1115                                 ranges = <0 0x30900000 0x40000>;
1116                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1117                                 clocks = <&clk IMX8MP_CLK_AHB>,
1118                                          <&clk IMX8MP_CLK_IPG_ROOT>;
1119                                 clock-names = "aclk", "ipg";
1120
1121                                 sec_jr0: jr@1000 {
1122                                         compatible = "fsl,sec-v4.0-job-ring";
1123                                         reg = <0x1000 0x1000>;
1124                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1125                                         status = "disabled";
1126                                 };
1127
1128                                 sec_jr1: jr@2000 {
1129                                         compatible = "fsl,sec-v4.0-job-ring";
1130                                         reg = <0x2000 0x1000>;
1131                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1132                                 };
1133
1134                                 sec_jr2: jr@3000 {
1135                                         compatible = "fsl,sec-v4.0-job-ring";
1136                                         reg = <0x3000 0x1000>;
1137                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1138                                 };
1139                         };
1140
1141                         i2c1: i2c@30a20000 {
1142                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1143                                 #address-cells = <1>;
1144                                 #size-cells = <0>;
1145                                 reg = <0x30a20000 0x10000>;
1146                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1147                                 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
1148                                 status = "disabled";
1149                         };
1150
1151                         i2c2: i2c@30a30000 {
1152                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1153                                 #address-cells = <1>;
1154                                 #size-cells = <0>;
1155                                 reg = <0x30a30000 0x10000>;
1156                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1157                                 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
1158                                 status = "disabled";
1159                         };
1160
1161                         i2c3: i2c@30a40000 {
1162                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1163                                 #address-cells = <1>;
1164                                 #size-cells = <0>;
1165                                 reg = <0x30a40000 0x10000>;
1166                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1167                                 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
1168                                 status = "disabled";
1169                         };
1170
1171                         i2c4: i2c@30a50000 {
1172                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1173                                 #address-cells = <1>;
1174                                 #size-cells = <0>;
1175                                 reg = <0x30a50000 0x10000>;
1176                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1177                                 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
1178                                 status = "disabled";
1179                         };
1180
1181                         uart4: serial@30a60000 {
1182                                 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1183                                 reg = <0x30a60000 0x10000>;
1184                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1185                                 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
1186                                          <&clk IMX8MP_CLK_UART4_ROOT>;
1187                                 clock-names = "ipg", "per";
1188                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1189                                 dma-names = "rx", "tx";
1190                                 status = "disabled";
1191                         };
1192
1193                         mu: mailbox@30aa0000 {
1194                                 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1195                                 reg = <0x30aa0000 0x10000>;
1196                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1197                                 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
1198                                 #mbox-cells = <2>;
1199                         };
1200
1201                         mu2: mailbox@30e60000 {
1202                                 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1203                                 reg = <0x30e60000 0x10000>;
1204                                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1205                                 #mbox-cells = <2>;
1206                                 status = "disabled";
1207                         };
1208
1209                         i2c5: i2c@30ad0000 {
1210                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1211                                 #address-cells = <1>;
1212                                 #size-cells = <0>;
1213                                 reg = <0x30ad0000 0x10000>;
1214                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1215                                 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
1216                                 status = "disabled";
1217                         };
1218
1219                         i2c6: i2c@30ae0000 {
1220                                 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1221                                 #address-cells = <1>;
1222                                 #size-cells = <0>;
1223                                 reg = <0x30ae0000 0x10000>;
1224                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1225                                 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
1226                                 status = "disabled";
1227                         };
1228
1229                         usdhc1: mmc@30b40000 {
1230                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1231                                 reg = <0x30b40000 0x10000>;
1232                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1233                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
1234                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1235                                          <&clk IMX8MP_CLK_USDHC1_ROOT>;
1236                                 clock-names = "ipg", "ahb", "per";
1237                                 fsl,tuning-start-tap = <20>;
1238                                 fsl,tuning-step = <2>;
1239                                 bus-width = <4>;
1240                                 status = "disabled";
1241                         };
1242
1243                         usdhc2: mmc@30b50000 {
1244                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1245                                 reg = <0x30b50000 0x10000>;
1246                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1247                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
1248                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1249                                          <&clk IMX8MP_CLK_USDHC2_ROOT>;
1250                                 clock-names = "ipg", "ahb", "per";
1251                                 fsl,tuning-start-tap = <20>;
1252                                 fsl,tuning-step = <2>;
1253                                 bus-width = <4>;
1254                                 status = "disabled";
1255                         };
1256
1257                         usdhc3: mmc@30b60000 {
1258                                 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1259                                 reg = <0x30b60000 0x10000>;
1260                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1261                                 clocks = <&clk IMX8MP_CLK_DUMMY>,
1262                                          <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1263                                          <&clk IMX8MP_CLK_USDHC3_ROOT>;
1264                                 clock-names = "ipg", "ahb", "per";
1265                                 fsl,tuning-start-tap = <20>;
1266                                 fsl,tuning-step = <2>;
1267                                 bus-width = <4>;
1268                                 status = "disabled";
1269                         };
1270
1271                         flexspi: spi@30bb0000 {
1272                                 compatible = "nxp,imx8mp-fspi";
1273                                 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1274                                 reg-names = "fspi_base", "fspi_mmap";
1275                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1276                                 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
1277                                          <&clk IMX8MP_CLK_QSPI_ROOT>;
1278                                 clock-names = "fspi_en", "fspi";
1279                                 assigned-clock-rates = <80000000>;
1280                                 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1281                                 #address-cells = <1>;
1282                                 #size-cells = <0>;
1283                                 status = "disabled";
1284                         };
1285
1286                         sdma1: dma-controller@30bd0000 {
1287                                 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1288                                 reg = <0x30bd0000 0x10000>;
1289                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1290                                 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
1291                                          <&clk IMX8MP_CLK_AHB>;
1292                                 clock-names = "ipg", "ahb";
1293                                 #dma-cells = <3>;
1294                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1295                         };
1296
1297                         fec: ethernet@30be0000 {
1298                                 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1299                                 reg = <0x30be0000 0x10000>;
1300                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1301                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1302                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1303                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1304                                 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1305                                          <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1306                                          <&clk IMX8MP_CLK_ENET_TIMER>,
1307                                          <&clk IMX8MP_CLK_ENET_REF>,
1308                                          <&clk IMX8MP_CLK_ENET_PHY_REF>;
1309                                 clock-names = "ipg", "ahb", "ptp",
1310                                               "enet_clk_ref", "enet_out";
1311                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1312                                                   <&clk IMX8MP_CLK_ENET_TIMER>,
1313                                                   <&clk IMX8MP_CLK_ENET_REF>,
1314                                                   <&clk IMX8MP_CLK_ENET_PHY_REF>;
1315                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1316                                                          <&clk IMX8MP_SYS_PLL2_100M>,
1317                                                          <&clk IMX8MP_SYS_PLL2_125M>,
1318                                                          <&clk IMX8MP_SYS_PLL2_50M>;
1319                                 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1320                                 fsl,num-tx-queues = <3>;
1321                                 fsl,num-rx-queues = <3>;
1322                                 nvmem-cells = <&eth_mac1>;
1323                                 nvmem-cell-names = "mac-address";
1324                                 fsl,stop-mode = <&gpr 0x10 3>;
1325                                 status = "disabled";
1326                         };
1327
1328                         eqos: ethernet@30bf0000 {
1329                                 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1330                                 reg = <0x30bf0000 0x10000>;
1331                                 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1332                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1333                                 interrupt-names = "macirq", "eth_wake_irq";
1334                                 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1335                                          <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1336                                          <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1337                                          <&clk IMX8MP_CLK_ENET_QOS>;
1338                                 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1339                                 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1340                                                   <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1341                                                   <&clk IMX8MP_CLK_ENET_QOS>;
1342                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1343                                                          <&clk IMX8MP_SYS_PLL2_100M>,
1344                                                          <&clk IMX8MP_SYS_PLL2_125M>;
1345                                 assigned-clock-rates = <0>, <100000000>, <125000000>;
1346                                 nvmem-cells = <&eth_mac2>;
1347                                 nvmem-cell-names = "mac-address";
1348                                 intf_mode = <&gpr 0x4>;
1349                                 status = "disabled";
1350                         };
1351                 };
1352
1353                 aips5: bus@30c00000 {
1354                         compatible = "fsl,aips-bus", "simple-bus";
1355                         reg = <0x30c00000 0x400000>;
1356                         #address-cells = <1>;
1357                         #size-cells = <1>;
1358                         ranges;
1359
1360                         spba-bus@30c00000 {
1361                                 compatible = "fsl,spba-bus", "simple-bus";
1362                                 reg = <0x30c00000 0x100000>;
1363                                 #address-cells = <1>;
1364                                 #size-cells = <1>;
1365                                 ranges;
1366
1367                                 sai1: sai@30c10000 {
1368                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1369                                         reg = <0x30c10000 0x10000>;
1370                                         #sound-dai-cells = <0>;
1371                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
1372                                                  <&clk IMX8MP_CLK_DUMMY>,
1373                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
1374                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
1375                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
1376                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1377                                         dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
1378                                         dma-names = "rx", "tx";
1379                                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1380                                         status = "disabled";
1381                                 };
1382
1383                                 sai2: sai@30c20000 {
1384                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1385                                         reg = <0x30c20000 0x10000>;
1386                                         #sound-dai-cells = <0>;
1387                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
1388                                                  <&clk IMX8MP_CLK_DUMMY>,
1389                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
1390                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
1391                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
1392                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1393                                         dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
1394                                         dma-names = "rx", "tx";
1395                                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1396                                         status = "disabled";
1397                                 };
1398
1399                                 sai3: sai@30c30000 {
1400                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1401                                         reg = <0x30c30000 0x10000>;
1402                                         #sound-dai-cells = <0>;
1403                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
1404                                                  <&clk IMX8MP_CLK_DUMMY>,
1405                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
1406                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
1407                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
1408                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1409                                         dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
1410                                         dma-names = "rx", "tx";
1411                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1412                                         status = "disabled";
1413                                 };
1414
1415                                 sai5: sai@30c50000 {
1416                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1417                                         reg = <0x30c50000 0x10000>;
1418                                         #sound-dai-cells = <0>;
1419                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
1420                                                  <&clk IMX8MP_CLK_DUMMY>,
1421                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
1422                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
1423                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
1424                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1425                                         dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
1426                                         dma-names = "rx", "tx";
1427                                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1428                                         status = "disabled";
1429                                 };
1430
1431                                 sai6: sai@30c60000 {
1432                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1433                                         reg = <0x30c60000 0x10000>;
1434                                         #sound-dai-cells = <0>;
1435                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
1436                                                  <&clk IMX8MP_CLK_DUMMY>,
1437                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
1438                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
1439                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
1440                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1441                                         dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
1442                                         dma-names = "rx", "tx";
1443                                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1444                                         status = "disabled";
1445                                 };
1446
1447                                 sai7: sai@30c80000 {
1448                                         compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1449                                         reg = <0x30c80000 0x10000>;
1450                                         #sound-dai-cells = <0>;
1451                                         clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
1452                                                  <&clk IMX8MP_CLK_DUMMY>,
1453                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
1454                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
1455                                                  <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
1456                                         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1457                                         dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
1458                                         dma-names = "rx", "tx";
1459                                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1460                                         status = "disabled";
1461                                 };
1462                         };
1463
1464                         sdma3: dma-controller@30e00000 {
1465                                 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1466                                 reg = <0x30e00000 0x10000>;
1467                                 #dma-cells = <3>;
1468                                 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
1469                                          <&clk IMX8MP_CLK_AUDIO_ROOT>;
1470                                 clock-names = "ipg", "ahb";
1471                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1472                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1473                         };
1474
1475                         sdma2: dma-controller@30e10000 {
1476                                 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1477                                 reg = <0x30e10000 0x10000>;
1478                                 #dma-cells = <3>;
1479                                 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
1480                                          <&clk IMX8MP_CLK_AUDIO_ROOT>;
1481                                 clock-names = "ipg", "ahb";
1482                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1483                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1484                         };
1485
1486                         audio_blk_ctrl: clock-controller@30e20000 {
1487                                 compatible = "fsl,imx8mp-audio-blk-ctrl";
1488                                 reg = <0x30e20000 0x10000>;
1489                                 #clock-cells = <1>;
1490                                 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
1491                                          <&clk IMX8MP_CLK_SAI1>,
1492                                          <&clk IMX8MP_CLK_SAI2>,
1493                                          <&clk IMX8MP_CLK_SAI3>,
1494                                          <&clk IMX8MP_CLK_SAI5>,
1495                                          <&clk IMX8MP_CLK_SAI6>,
1496                                          <&clk IMX8MP_CLK_SAI7>;
1497                                 clock-names = "ahb",
1498                                               "sai1", "sai2", "sai3",
1499                                               "sai5", "sai6", "sai7";
1500                                 power-domains = <&pgc_audio>;
1501                         };
1502                 };
1503
1504                 noc: interconnect@32700000 {
1505                         compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1506                         reg = <0x32700000 0x100000>;
1507                         clocks = <&clk IMX8MP_CLK_NOC>;
1508                         #interconnect-cells = <1>;
1509                         operating-points-v2 = <&noc_opp_table>;
1510
1511                         noc_opp_table: opp-table {
1512                                 compatible = "operating-points-v2";
1513
1514                                 opp-200000000 {
1515                                         opp-hz = /bits/ 64 <200000000>;
1516                                 };
1517
1518                                 opp-1000000000 {
1519                                         opp-hz = /bits/ 64 <1000000000>;
1520                                 };
1521                         };
1522                 };
1523
1524                 aips4: bus@32c00000 {
1525                         compatible = "fsl,aips-bus", "simple-bus";
1526                         reg = <0x32c00000 0x400000>;
1527                         #address-cells = <1>;
1528                         #size-cells = <1>;
1529                         ranges;
1530
1531                         isi_0: isi@32e00000 {
1532                                 compatible = "fsl,imx8mp-isi";
1533                                 reg = <0x32e00000 0x4000>;
1534                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1535                                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1536                                 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1537                                          <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1538                                 clock-names = "axi", "apb";
1539                                 fsl,blk-ctrl = <&media_blk_ctrl>;
1540                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
1541                                 status = "disabled";
1542
1543                                 ports {
1544                                         #address-cells = <1>;
1545                                         #size-cells = <0>;
1546
1547                                         port@0 {
1548                                                 reg = <0>;
1549
1550                                                 isi_in_0: endpoint {
1551                                                         remote-endpoint = <&mipi_csi_0_out>;
1552                                                 };
1553                                         };
1554
1555                                         port@1 {
1556                                                 reg = <1>;
1557
1558                                                 isi_in_1: endpoint {
1559                                                         remote-endpoint = <&mipi_csi_1_out>;
1560                                                 };
1561                                         };
1562                                 };
1563                         };
1564
1565                         dewarp: dwe@32e30000 {
1566                                 compatible = "nxp,imx8mp-dw100";
1567                                 reg = <0x32e30000 0x10000>;
1568                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1569                                 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1570                                          <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1571                                 clock-names = "axi", "ahb";
1572                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
1573                         };
1574
1575                         mipi_csi_0: csi@32e40000 {
1576                                 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1577                                 reg = <0x32e40000 0x10000>;
1578                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1579                                 clock-frequency = <500000000>;
1580                                 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1581                                          <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1582                                          <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1583                                          <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1584                                 clock-names = "pclk", "wrap", "phy", "axi";
1585                                 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
1586                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1587                                 assigned-clock-rates = <500000000>;
1588                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
1589                                 status = "disabled";
1590
1591                                 ports {
1592                                         #address-cells = <1>;
1593                                         #size-cells = <0>;
1594
1595                                         port@0 {
1596                                                 reg = <0>;
1597                                         };
1598
1599                                         port@1 {
1600                                                 reg = <1>;
1601
1602                                                 mipi_csi_0_out: endpoint {
1603                                                         remote-endpoint = <&isi_in_0>;
1604                                                 };
1605                                         };
1606                                 };
1607                         };
1608
1609                         mipi_csi_1: csi@32e50000 {
1610                                 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1611                                 reg = <0x32e50000 0x10000>;
1612                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1613                                 clock-frequency = <266000000>;
1614                                 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1615                                          <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1616                                          <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1617                                          <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1618                                 clock-names = "pclk", "wrap", "phy", "axi";
1619                                 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
1620                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1621                                 assigned-clock-rates = <266000000>;
1622                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
1623                                 status = "disabled";
1624
1625                                 ports {
1626                                         #address-cells = <1>;
1627                                         #size-cells = <0>;
1628
1629                                         port@0 {
1630                                                 reg = <0>;
1631                                         };
1632
1633                                         port@1 {
1634                                                 reg = <1>;
1635
1636                                                 mipi_csi_1_out: endpoint {
1637                                                         remote-endpoint = <&isi_in_1>;
1638                                                 };
1639                                         };
1640                                 };
1641                         };
1642
1643                         mipi_dsi: dsi@32e60000 {
1644                                 compatible = "fsl,imx8mp-mipi-dsim";
1645                                 reg = <0x32e60000 0x400>;
1646                                 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1647                                          <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1648                                 clock-names = "bus_clk", "sclk_mipi";
1649                                 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
1650                                                   <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1651                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1652                                                          <&clk IMX8MP_CLK_24M>;
1653                                 assigned-clock-rates = <200000000>, <24000000>;
1654                                 samsung,pll-clock-frequency = <24000000>;
1655                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1656                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
1657                                 status = "disabled";
1658
1659                                 ports {
1660                                         #address-cells = <1>;
1661                                         #size-cells = <0>;
1662
1663                                         port@0 {
1664                                                 reg = <0>;
1665
1666                                                 dsim_from_lcdif1: endpoint {
1667                                                         remote-endpoint = <&lcdif1_to_dsim>;
1668                                                 };
1669                                         };
1670                                 };
1671                         };
1672
1673                         lcdif1: display-controller@32e80000 {
1674                                 compatible = "fsl,imx8mp-lcdif";
1675                                 reg = <0x32e80000 0x10000>;
1676                                 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1677                                          <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1678                                          <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1679                                 clock-names = "pix", "axi", "disp_axi";
1680                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1681                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
1682                                 status = "disabled";
1683
1684                                 port {
1685                                         lcdif1_to_dsim: endpoint {
1686                                                 remote-endpoint = <&dsim_from_lcdif1>;
1687                                         };
1688                                 };
1689                         };
1690
1691                         lcdif2: display-controller@32e90000 {
1692                                 compatible = "fsl,imx8mp-lcdif";
1693                                 reg = <0x32e90000 0x10000>;
1694                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1695                                 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1696                                          <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1697                                          <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1698                                 clock-names = "pix", "axi", "disp_axi";
1699                                 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
1700                                 status = "disabled";
1701
1702                                 port {
1703                                         lcdif2_to_ldb: endpoint {
1704                                                 remote-endpoint = <&ldb_from_lcdif2>;
1705                                         };
1706                                 };
1707                         };
1708
1709                         media_blk_ctrl: blk-ctrl@32ec0000 {
1710                                 compatible = "fsl,imx8mp-media-blk-ctrl",
1711                                              "syscon";
1712                                 reg = <0x32ec0000 0x10000>;
1713                                 #address-cells = <1>;
1714                                 #size-cells = <1>;
1715                                 power-domains = <&pgc_mediamix>,
1716                                                 <&pgc_mipi_phy1>,
1717                                                 <&pgc_mipi_phy1>,
1718                                                 <&pgc_mediamix>,
1719                                                 <&pgc_mediamix>,
1720                                                 <&pgc_mipi_phy2>,
1721                                                 <&pgc_mediamix>,
1722                                                 <&pgc_ispdwp>,
1723                                                 <&pgc_ispdwp>,
1724                                                 <&pgc_mipi_phy2>;
1725                                 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1726                                                      "lcdif1", "isi", "mipi-csi2",
1727                                                      "lcdif2", "isp", "dwe",
1728                                                      "mipi-dsi2";
1729                                 interconnects =
1730                                         <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>,
1731                                         <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>,
1732                                         <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>,
1733                                         <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>,
1734                                         <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>,
1735                                         <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>,
1736                                         <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>,
1737                                         <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>;
1738                                 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1739                                                      "isi1", "isi2", "isp0", "isp1",
1740                                                      "dwe";
1741                                 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1742                                          <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1743                                          <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1744                                          <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1745                                          <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1746                                          <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1747                                          <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1748                                          <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1749                                 clock-names = "apb", "axi", "cam1", "cam2",
1750                                               "disp1", "disp2", "isp", "phy";
1751
1752                                 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1753                                                   <&clk IMX8MP_CLK_MEDIA_APB>,
1754                                                   <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
1755                                                   <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
1756                                                   <&clk IMX8MP_VIDEO_PLL1>;
1757                                 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1758                                                          <&clk IMX8MP_SYS_PLL1_800M>,
1759                                                          <&clk IMX8MP_VIDEO_PLL1_OUT>,
1760                                                          <&clk IMX8MP_VIDEO_PLL1_OUT>;
1761                                 assigned-clock-rates = <500000000>, <200000000>,
1762                                                        <0>, <0>, <1039500000>;
1763                                 #power-domain-cells = <1>;
1764
1765                                 lvds_bridge: bridge@5c {
1766                                         compatible = "fsl,imx8mp-ldb";
1767                                         reg = <0x5c 0x4>, <0x128 0x4>;
1768                                         reg-names = "ldb", "lvds";
1769                                         clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1770                                         clock-names = "ldb";
1771                                         assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1772                                         assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
1773                                         status = "disabled";
1774
1775                                         ports {
1776                                                 #address-cells = <1>;
1777                                                 #size-cells = <0>;
1778
1779                                                 port@0 {
1780                                                         reg = <0>;
1781
1782                                                         ldb_from_lcdif2: endpoint {
1783                                                                 remote-endpoint = <&lcdif2_to_ldb>;
1784                                                         };
1785                                                 };
1786
1787                                                 port@1 {
1788                                                         reg = <1>;
1789
1790                                                         ldb_lvds_ch0: endpoint {
1791                                                         };
1792                                                 };
1793
1794                                                 port@2 {
1795                                                         reg = <2>;
1796
1797                                                         ldb_lvds_ch1: endpoint {
1798                                                         };
1799                                                 };
1800                                         };
1801                                 };
1802                         };
1803
1804                         pcie_phy: pcie-phy@32f00000 {
1805                                 compatible = "fsl,imx8mp-pcie-phy";
1806                                 reg = <0x32f00000 0x10000>;
1807                                 resets = <&src IMX8MP_RESET_PCIEPHY>,
1808                                          <&src IMX8MP_RESET_PCIEPHY_PERST>;
1809                                 reset-names = "pciephy", "perst";
1810                                 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1811                                 #phy-cells = <0>;
1812                                 status = "disabled";
1813                         };
1814
1815                         hsio_blk_ctrl: blk-ctrl@32f10000 {
1816                                 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1817                                 reg = <0x32f10000 0x24>;
1818                                 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1819                                          <&clk IMX8MP_CLK_PCIE_ROOT>;
1820                                 clock-names = "usb", "pcie";
1821                                 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1822                                                 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1823                                                 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1824                                 power-domain-names = "bus", "usb", "usb-phy1",
1825                                                      "usb-phy2", "pcie", "pcie-phy";
1826                                 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>,
1827                                                 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>,
1828                                                 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>,
1829                                                 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
1830                                 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
1831                                 #power-domain-cells = <1>;
1832                                 #clock-cells = <0>;
1833                         };
1834                 };
1835
1836                 pcie: pcie@33800000 {
1837                         compatible = "fsl,imx8mp-pcie";
1838                         reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1839                         reg-names = "dbi", "config";
1840                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1841                                  <&clk IMX8MP_CLK_HSIO_AXI>,
1842                                  <&clk IMX8MP_CLK_PCIE_ROOT>;
1843                         clock-names = "pcie", "pcie_bus", "pcie_aux";
1844                         assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
1845                         assigned-clock-rates = <10000000>;
1846                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
1847                         #address-cells = <3>;
1848                         #size-cells = <2>;
1849                         device_type = "pci";
1850                         bus-range = <0x00 0xff>;
1851                         ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1852                                  <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1853                         num-lanes = <1>;
1854                         num-viewport = <4>;
1855                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1856                         interrupt-names = "msi";
1857                         #interrupt-cells = <1>;
1858                         interrupt-map-mask = <0 0 0 0x7>;
1859                         interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1860                                         <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1861                                         <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1862                                         <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1863                         fsl,max-link-speed = <3>;
1864                         linux,pci-domain = <0>;
1865                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1866                         resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
1867                                  <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
1868                         reset-names = "apps", "turnoff";
1869                         phys = <&pcie_phy>;
1870                         phy-names = "pcie-phy";
1871                         status = "disabled";
1872                 };
1873
1874                 pcie_ep: pcie-ep@33800000 {
1875                         compatible = "fsl,imx8mp-pcie-ep";
1876                         reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
1877                         reg-names = "dbi", "addr_space";
1878                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1879                                  <&clk IMX8MP_CLK_HSIO_AXI>,
1880                                  <&clk IMX8MP_CLK_PCIE_ROOT>;
1881                         clock-names = "pcie", "pcie_bus", "pcie_aux";
1882                         assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
1883                         assigned-clock-rates = <10000000>;
1884                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
1885                         num-lanes = <1>;
1886                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
1887                         interrupt-names = "dma";
1888                         fsl,max-link-speed = <3>;
1889                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1890                         resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
1891                                  <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
1892                         reset-names = "apps", "turnoff";
1893                         phys = <&pcie_phy>;
1894                         phy-names = "pcie-phy";
1895                         num-ib-windows = <4>;
1896                         num-ob-windows = <4>;
1897                         status = "disabled";
1898                 };
1899
1900                 gpu3d: gpu@38000000 {
1901                         compatible = "vivante,gc";
1902                         reg = <0x38000000 0x8000>;
1903                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1904                         clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
1905                                  <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
1906                                  <&clk IMX8MP_CLK_GPU_ROOT>,
1907                                  <&clk IMX8MP_CLK_GPU_AHB>;
1908                         clock-names = "core", "shader", "bus", "reg";
1909                         assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1910                                           <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
1911                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1912                                                  <&clk IMX8MP_SYS_PLL1_800M>;
1913                         assigned-clock-rates = <800000000>, <800000000>;
1914                         power-domains = <&pgc_gpu3d>;
1915                 };
1916
1917                 gpu2d: gpu@38008000 {
1918                         compatible = "vivante,gc";
1919                         reg = <0x38008000 0x8000>;
1920                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1921                         clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
1922                                  <&clk IMX8MP_CLK_GPU_ROOT>,
1923                                  <&clk IMX8MP_CLK_GPU_AHB>;
1924                         clock-names = "core", "bus", "reg";
1925                         assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1926                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1927                         assigned-clock-rates = <800000000>;
1928                         power-domains = <&pgc_gpu2d>;
1929                 };
1930
1931                 vpu_g1: video-codec@38300000 {
1932                         compatible = "nxp,imx8mm-vpu-g1";
1933                         reg = <0x38300000 0x10000>;
1934                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1935                         clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
1936                         assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
1937                         assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
1938                         assigned-clock-rates = <600000000>;
1939                         power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
1940                 };
1941
1942                 vpu_g2: video-codec@38310000 {
1943                         compatible = "nxp,imx8mq-vpu-g2";
1944                         reg = <0x38310000 0x10000>;
1945                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1946                         clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
1947                         assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
1948                         assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1949                         assigned-clock-rates = <500000000>;
1950                         power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
1951                 };
1952
1953                 vpumix_blk_ctrl: blk-ctrl@38330000 {
1954                         compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
1955                         reg = <0x38330000 0x100>;
1956                         #power-domain-cells = <1>;
1957                         power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1958                                         <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>;
1959                         power-domain-names = "bus", "g1", "g2", "vc8000e";
1960                         clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
1961                                  <&clk IMX8MP_CLK_VPU_G2_ROOT>,
1962                                  <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
1963                         clock-names = "g1", "g2", "vc8000e";
1964                         assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
1965                         assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
1966                         assigned-clock-rates = <600000000>, <600000000>;
1967                         interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
1968                                         <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
1969                                         <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
1970                         interconnect-names = "g1", "g2", "vc8000e";
1971                 };
1972
1973                 gic: interrupt-controller@38800000 {
1974                         compatible = "arm,gic-v3";
1975                         reg = <0x38800000 0x10000>,
1976                               <0x38880000 0xc0000>;
1977                         #interrupt-cells = <3>;
1978                         interrupt-controller;
1979                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1980                         interrupt-parent = <&gic>;
1981                 };
1982
1983                 edacmc: memory-controller@3d400000 {
1984                         compatible = "snps,ddrc-3.80a";
1985                         reg = <0x3d400000 0x400000>;
1986                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1987                 };
1988
1989                 ddr-pmu@3d800000 {
1990                         compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1991                         reg = <0x3d800000 0x400000>;
1992                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1993                 };
1994
1995                 usb3_phy0: usb-phy@381f0040 {
1996                         compatible = "fsl,imx8mp-usb-phy";
1997                         reg = <0x381f0040 0x40>;
1998                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1999                         clock-names = "phy";
2000                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2001                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2002                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2003                         #phy-cells = <0>;
2004                         status = "disabled";
2005                 };
2006
2007                 usb3_0: usb@32f10100 {
2008                         compatible = "fsl,imx8mp-dwc3";
2009                         reg = <0x32f10100 0x8>,
2010                               <0x381f0000 0x20>;
2011                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2012                                  <&clk IMX8MP_CLK_USB_SUSP>;
2013                         clock-names = "hsio", "suspend";
2014                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2015                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2016                         #address-cells = <1>;
2017                         #size-cells = <1>;
2018                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2019                         ranges;
2020                         status = "disabled";
2021
2022                         usb_dwc3_0: usb@38100000 {
2023                                 compatible = "snps,dwc3";
2024                                 reg = <0x38100000 0x10000>;
2025                                 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2026                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
2027                                          <&clk IMX8MP_CLK_USB_SUSP>;
2028                                 clock-names = "bus_early", "ref", "suspend";
2029                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
2030                                 phys = <&usb3_phy0>, <&usb3_phy0>;
2031                                 phy-names = "usb2-phy", "usb3-phy";
2032                                 snps,gfladj-refclk-lpm-sel-quirk;
2033                         };
2034
2035                 };
2036
2037                 usb3_phy1: usb-phy@382f0040 {
2038                         compatible = "fsl,imx8mp-usb-phy";
2039                         reg = <0x382f0040 0x40>;
2040                         clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2041                         clock-names = "phy";
2042                         assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2043                         assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2044                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2045                         #phy-cells = <0>;
2046                         status = "disabled";
2047                 };
2048
2049                 usb3_1: usb@32f10108 {
2050                         compatible = "fsl,imx8mp-dwc3";
2051                         reg = <0x32f10108 0x8>,
2052                               <0x382f0000 0x20>;
2053                         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2054                                  <&clk IMX8MP_CLK_USB_SUSP>;
2055                         clock-names = "hsio", "suspend";
2056                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
2057                         power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2058                         #address-cells = <1>;
2059                         #size-cells = <1>;
2060                         dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2061                         ranges;
2062                         status = "disabled";
2063
2064                         usb_dwc3_1: usb@38200000 {
2065                                 compatible = "snps,dwc3";
2066                                 reg = <0x38200000 0x10000>;
2067                                 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2068                                          <&clk IMX8MP_CLK_USB_CORE_REF>,
2069                                          <&clk IMX8MP_CLK_USB_SUSP>;
2070                                 clock-names = "bus_early", "ref", "suspend";
2071                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
2072                                 phys = <&usb3_phy1>, <&usb3_phy1>;
2073                                 phy-names = "usb2-phy", "usb3-phy";
2074                                 snps,gfladj-refclk-lpm-sel-quirk;
2075                         };
2076                 };
2077
2078                 dsp: dsp@3b6e8000 {
2079                         compatible = "fsl,imx8mp-dsp";
2080                         reg = <0x3b6e8000 0x88000>;
2081                         mbox-names = "txdb0", "txdb1",
2082                                 "rxdb0", "rxdb1";
2083                         mboxes = <&mu2 2 0>, <&mu2 2 1>,
2084                                 <&mu2 3 0>, <&mu2 3 1>;
2085                         memory-region = <&dsp_reserved>;
2086                         status = "disabled";
2087                 };
2088         };
2089 };