arch/arm64/boot/dts/freescale/imx8mp-evk.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/phy/phy-imx8-pcie.h>
   9 #include "imx8mp.dtsi"
  10
  11 / {
  12         model = "NXP i.MX8MPlus EVK board";
  13         compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
  14
  15         chosen {
  16                 stdout-path = &uart2;
  17         };
  18
  19         gpio-leds {
  20                 compatible = "gpio-leds";
  21                 pinctrl-names = "default";
  22                 pinctrl-0 = <&pinctrl_gpio_led>;
  23
  24                 status {
  25                         label = "yellow:status";
  26                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  27                         default-state = "on";
  28                 };
  29         };
  30
  31         memory@40000000 {
  32                 device_type = "memory";
  33                 reg = <0x0 0x40000000 0 0xc0000000>,
  34                       <0x1 0x00000000 0 0xc0000000>;
  35         };
  36
  37         pcie0_refclk: pcie0-refclk {
  38                 compatible = "fixed-clock";
  39                 #clock-cells = <0>;
  40                 clock-frequency = <100000000>;
  41         };
  42
  43         reg_can1_stby: regulator-can1-stby {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "can1-stby";
  46                 pinctrl-names = "default";
  47                 pinctrl-0 = <&pinctrl_flexcan1_reg>;
  48                 regulator-min-microvolt = <3300000>;
  49                 regulator-max-microvolt = <3300000>;
  50                 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  51                 enable-active-high;
  52         };
  53
  54         reg_can2_stby: regulator-can2-stby {
  55                 compatible = "regulator-fixed";
  56                 regulator-name = "can2-stby";
  57                 pinctrl-names = "default";
  58                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
  59                 regulator-min-microvolt = <3300000>;
  60                 regulator-max-microvolt = <3300000>;
  61                 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
  62                 enable-active-high;
  63         };
  64
  65         reg_pcie0: regulator-pcie {
  66                 compatible = "regulator-fixed";
  67                 pinctrl-names = "default";
  68                 pinctrl-0 = <&pinctrl_pcie0_reg>;
  69                 regulator-name = "MPCIE_3V3";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72                 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
  73                 enable-active-high;
  74         };
  75
  76         reg_usdhc2_vmmc: regulator-usdhc2 {
  77                 compatible = "regulator-fixed";
  78                 pinctrl-names = "default";
  79                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  80                 regulator-name = "VSD_3V3";
  81                 regulator-min-microvolt = <3300000>;
  82                 regulator-max-microvolt = <3300000>;
  83                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  84                 enable-active-high;
  85         };
  86 };
  87
  88 &flexspi {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_flexspi0>;
  91         status = "okay";
  92
  93         flash@0 {
  94                 compatible = "jedec,spi-nor";
  95                 reg = <0>;
  96                 spi-max-frequency = <80000000>;
  97                 spi-tx-bus-width = <1>;
  98                 spi-rx-bus-width = <4>;
  99         };
 100 };
 101
 102 &A53_0 {
 103         cpu-supply = <&reg_arm>;
 104 };
 105
 106 &A53_1 {
 107         cpu-supply = <&reg_arm>;
 108 };
 109
 110 &A53_2 {
 111         cpu-supply = <&reg_arm>;
 112 };
 113
 114 &A53_3 {
 115         cpu-supply = <&reg_arm>;
 116 };
 117
 118 &eqos {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_eqos>;
 121         phy-mode = "rgmii-id";
 122         phy-handle = <&ethphy0>;
 123         snps,force_thresh_dma_mode;
 124         snps,mtl-tx-config = <&mtl_tx_setup>;
 125         snps,mtl-rx-config = <&mtl_rx_setup>;
 126         status = "okay";
 127
 128         mdio {
 129                 compatible = "snps,dwmac-mdio";
 130                 #address-cells = <1>;
 131                 #size-cells = <0>;
 132
 133                 ethphy0: ethernet-phy@1 {
 134                         compatible = "ethernet-phy-ieee802.3-c22";
 135                         reg = <1>;
 136                         eee-broken-1000t;
 137                         reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 138                         reset-assert-us = <10000>;
 139                         reset-deassert-us = <80000>;
 140                         realtek,clkout-disable;
 141                 };
 142         };
 143
 144         mtl_tx_setup: tx-queues-config {
 145                 snps,tx-queues-to-use = <5>;
 146                 snps,tx-sched-sp;
 147
 148                 queue0 {
 149                         snps,dcb-algorithm;
 150                         snps,priority = <0x1>;
 151                 };
 152
 153                 queue1 {
 154                         snps,dcb-algorithm;
 155                         snps,priority = <0x2>;
 156                 };
 157
 158                 queue2 {
 159                         snps,dcb-algorithm;
 160                         snps,priority = <0x4>;
 161                 };
 162
 163                 queue3 {
 164                         snps,dcb-algorithm;
 165                         snps,priority = <0x8>;
 166                 };
 167
 168                 queue4 {
 169                         snps,dcb-algorithm;
 170                         snps,priority = <0xf0>;
 171                 };
 172         };
 173
 174         mtl_rx_setup: rx-queues-config {
 175                 snps,rx-queues-to-use = <5>;
 176                 snps,rx-sched-sp;
 177
 178                 queue0 {
 179                         snps,dcb-algorithm;
 180                         snps,priority = <0x1>;
 181                         snps,map-to-dma-channel = <0>;
 182                 };
 183
 184                 queue1 {
 185                         snps,dcb-algorithm;
 186                         snps,priority = <0x2>;
 187                         snps,map-to-dma-channel = <1>;
 188                 };
 189
 190                 queue2 {
 191                         snps,dcb-algorithm;
 192                         snps,priority = <0x4>;
 193                         snps,map-to-dma-channel = <2>;
 194                 };
 195
 196                 queue3 {
 197                         snps,dcb-algorithm;
 198                         snps,priority = <0x8>;
 199                         snps,map-to-dma-channel = <3>;
 200                 };
 201
 202                 queue4 {
 203                         snps,dcb-algorithm;
 204                         snps,priority = <0xf0>;
 205                         snps,map-to-dma-channel = <4>;
 206                 };
 207         };
 208 };
 209
 210 &fec {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_fec>;
 213         phy-mode = "rgmii-id";
 214         phy-handle = <&ethphy1>;
 215         fsl,magic-packet;
 216         status = "okay";
 217
 218         mdio {
 219                 #address-cells = <1>;
 220                 #size-cells = <0>;
 221
 222                 ethphy1: ethernet-phy@1 {
 223                         compatible = "ethernet-phy-ieee802.3-c22";
 224                         reg = <1>;
 225                         eee-broken-1000t;
 226                         reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 227                         reset-assert-us = <10000>;
 228                         reset-deassert-us = <80000>;
 229                         realtek,clkout-disable;
 230                 };
 231         };
 232 };
 233
 234 &flexcan1 {
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&pinctrl_flexcan1>;
 237         xceiver-supply = <&reg_can1_stby>;
 238         status = "okay";
 239 };
 240
 241 &flexcan2 {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_flexcan2>;
 244         xceiver-supply = <&reg_can2_stby>;
 245         status = "disabled";/* can2 pin conflict with pdm */
 246 };
 247
 248 &i2c1 {
 249         clock-frequency = <400000>;
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&pinctrl_i2c1>;
 252         status = "okay";
 253
 254         pmic@25 {
 255                 compatible = "nxp,pca9450c";
 256                 reg = <0x25>;
 257                 pinctrl-names = "default";
 258                 pinctrl-0 = <&pinctrl_pmic>;
 259                 interrupt-parent = <&gpio1>;
 260                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 261
 262                 regulators {
 263                         BUCK1 {
 264                                 regulator-name = "BUCK1";
 265                                 regulator-min-microvolt = <720000>;
 266                                 regulator-max-microvolt = <1000000>;
 267                                 regulator-boot-on;
 268                                 regulator-always-on;
 269                                 regulator-ramp-delay = <3125>;
 270                         };
 271
 272                         reg_arm: BUCK2 {
 273                                 regulator-name = "BUCK2";
 274                                 regulator-min-microvolt = <720000>;
 275                                 regulator-max-microvolt = <1025000>;
 276                                 regulator-boot-on;
 277                                 regulator-always-on;
 278                                 regulator-ramp-delay = <3125>;
 279                                 nxp,dvs-run-voltage = <950000>;
 280                                 nxp,dvs-standby-voltage = <850000>;
 281                         };
 282
 283                         BUCK4 {
 284                                 regulator-name = "BUCK4";
 285                                 regulator-min-microvolt = <3000000>;
 286                                 regulator-max-microvolt = <3600000>;
 287                                 regulator-boot-on;
 288                                 regulator-always-on;
 289                         };
 290
 291                         BUCK5 {
 292                                 regulator-name = "BUCK5";
 293                                 regulator-min-microvolt = <1650000>;
 294                                 regulator-max-microvolt = <1950000>;
 295                                 regulator-boot-on;
 296                                 regulator-always-on;
 297                         };
 298
 299                         BUCK6 {
 300                                 regulator-name = "BUCK6";
 301                                 regulator-min-microvolt = <1045000>;
 302                                 regulator-max-microvolt = <1155000>;
 303                                 regulator-boot-on;
 304                                 regulator-always-on;
 305                         };
 306
 307                         LDO1 {
 308                                 regulator-name = "LDO1";
 309                                 regulator-min-microvolt = <1650000>;
 310                                 regulator-max-microvolt = <1950000>;
 311                                 regulator-boot-on;
 312                                 regulator-always-on;
 313                         };
 314
 315                         LDO3 {
 316                                 regulator-name = "LDO3";
 317                                 regulator-min-microvolt = <1710000>;
 318                                 regulator-max-microvolt = <1890000>;
 319                                 regulator-boot-on;
 320                                 regulator-always-on;
 321                         };
 322
 323                         LDO5 {
 324                                 regulator-name = "LDO5";
 325                                 regulator-min-microvolt = <1800000>;
 326                                 regulator-max-microvolt = <3300000>;
 327                                 regulator-boot-on;
 328                                 regulator-always-on;
 329                         };
 330                 };
 331         };
 332 };
 333
 334 &i2c2 {
 335         clock-frequency = <400000>;
 336         pinctrl-names = "default";
 337         pinctrl-0 = <&pinctrl_i2c2>;
 338         status = "okay";
 339 };
 340
 341 &i2c3 {
 342         clock-frequency = <400000>;
 343         pinctrl-names = "default";
 344         pinctrl-0 = <&pinctrl_i2c3>;
 345         status = "okay";
 346
 347         pca6416: gpio@20 {
 348                 compatible = "ti,tca6416";
 349                 reg = <0x20>;
 350                 gpio-controller;
 351                 #gpio-cells = <2>;
 352                 interrupt-controller;
 353                 #interrupt-cells = <2>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&pinctrl_pca6416_int>;
 356                 interrupt-parent = <&gpio1>;
 357                 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
 358                 gpio-line-names = "EXT_PWREN1",
 359                         "EXT_PWREN2",
 360                         "CAN1/I2C5_SEL",
 361                         "PDM/CAN2_SEL",
 362                         "FAN_EN",
 363                         "PWR_MEAS_IO1",
 364                         "PWR_MEAS_IO2",
 365                         "EXP_P0_7",
 366                         "EXP_P1_0",
 367                         "EXP_P1_1",
 368                         "EXP_P1_2",
 369                         "EXP_P1_3",
 370                         "EXP_P1_4",
 371                         "EXP_P1_5",
 372                         "EXP_P1_6",
 373                         "EXP_P1_7";
 374         };
 375 };
 376
 377 /* I2C on expansion connector J22. */
 378 &i2c5 {
 379         clock-frequency = <100000>; /* Lower clock speed for external bus. */
 380         pinctrl-names = "default";
 381         pinctrl-0 = <&pinctrl_i2c5>;
 382         status = "disabled"; /* can1 pins conflict with i2c5 */
 383
 384         /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
 385          *     LOW:  CAN1 (default, pull-down)
 386          *     HIGH: I2C5
 387          * You need to set it to high to enable I2C5 (for example, add gpio-hog
 388          * in pca6416 node).
 389          */
 390 };
 391
 392 &pcie_phy {
 393         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 394         clocks = <&pcie0_refclk>;
 395         clock-names = "ref";
 396         status = "okay";
 397 };
 398
 399 &pcie {
 400         pinctrl-names = "default";
 401         pinctrl-0 = <&pinctrl_pcie0>;
 402         reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
 403         clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
 404                  <&clk IMX8MP_CLK_PCIE_ROOT>,
 405                  <&clk IMX8MP_CLK_HSIO_AXI>;
 406         clock-names = "pcie", "pcie_aux", "pcie_bus";
 407         assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
 408         assigned-clock-rates = <10000000>;
 409         assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
 410         vpcie-supply = <&reg_pcie0>;
 411         status = "okay";
 412 };
 413
 414 &pwm1 {
 415         pinctrl-names = "default";
 416         pinctrl-0 = <&pinctrl_pwm1>;
 417         status = "okay";
 418 };
 419
 420 &pwm2 {
 421         pinctrl-names = "default";
 422         pinctrl-0 = <&pinctrl_pwm2>;
 423         status = "okay";
 424 };
 425
 426 &pwm4 {
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&pinctrl_pwm4>;
 429         status = "okay";
 430 };
 431
 432 &snvs_pwrkey {
 433         status = "okay";
 434 };
 435
 436 &uart1 { /* BT */
 437         pinctrl-names = "default";
 438         pinctrl-0 = <&pinctrl_uart1>;
 439         assigned-clocks = <&clk IMX8MP_CLK_UART1>;
 440         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
 441         uart-has-rtscts;
 442         status = "okay";
 443 };
 444
 445 &uart2 {
 446         /* console */
 447         pinctrl-names = "default";
 448         pinctrl-0 = <&pinctrl_uart2>;
 449         status = "okay";
 450 };
 451
 452 &usb3_phy1 {
 453         status = "okay";
 454 };
 455
 456 &usb3_1 {
 457         status = "okay";
 458 };
 459
 460 &usb_dwc3_1 {
 461         pinctrl-names = "default";
 462         pinctrl-0 = <&pinctrl_usb1_vbus>;
 463         dr_mode = "host";
 464         status = "okay";
 465 };
 466
 467 &uart3 {
 468         pinctrl-names = "default";
 469         pinctrl-0 = <&pinctrl_uart3>;
 470         assigned-clocks = <&clk IMX8MP_CLK_UART3>;
 471         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
 472         uart-has-rtscts;
 473         status = "okay";
 474 };
 475
 476 &usdhc2 {
 477         assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 478         assigned-clock-rates = <400000000>;
 479         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 480         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 481         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 482         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 483         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 484         vmmc-supply = <&reg_usdhc2_vmmc>;
 485         bus-width = <4>;
 486         status = "okay";
 487 };
 488
 489 &usdhc3 {
 490         assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
 491         assigned-clock-rates = <400000000>;
 492         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 493         pinctrl-0 = <&pinctrl_usdhc3>;
 494         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 495         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 496         bus-width = <8>;
 497         non-removable;
 498         status = "okay";
 499 };
 500
 501 &wdog1 {
 502         pinctrl-names = "default";
 503         pinctrl-0 = <&pinctrl_wdog>;
 504         fsl,ext-reset-output;
 505         status = "okay";
 506 };
 507
 508 &iomuxc {
 509         pinctrl_eqos: eqosgrp {
 510                 fsl,pins = <
 511                         MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                             0x2
 512                         MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                           0x2
 513                         MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                       0x90
 514                         MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                       0x90
 515                         MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                       0x90
 516                         MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                       0x90
 517                         MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x90
 518                         MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL                 0x90
 519                         MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                       0x16
 520                         MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                       0x16
 521                         MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                       0x16
 522                         MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                       0x16
 523                         MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL                 0x16
 524                         MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x16
 525                         MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22                               0x10
 526                 >;
 527         };
 528
 529         pinctrl_fec: fecgrp {
 530                 fsl,pins = <
 531                         MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x2
 532                         MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x2
 533                         MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x90
 534                         MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x90
 535                         MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x90
 536                         MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x90
 537                         MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x90
 538                         MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x90
 539                         MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x16
 540                         MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x16
 541                         MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x16
 542                         MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x16
 543                         MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x16
 544                         MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x16
 545                         MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02              0x10
 546                 >;
 547         };
 548
 549         pinctrl_flexcan1: flexcan1grp {
 550                 fsl,pins = <
 551                         MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154
 552                         MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154
 553                 >;
 554         };
 555
 556         pinctrl_flexcan2: flexcan2grp {
 557                 fsl,pins = <
 558                         MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
 559                         MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
 560                 >;
 561         };
 562
 563         pinctrl_flexcan1_reg: flexcan1reggrp {
 564                 fsl,pins = <
 565                         MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154   /* CAN1_STBY */
 566                 >;
 567         };
 568
 569         pinctrl_flexcan2_reg: flexcan2reggrp {
 570                 fsl,pins = <
 571                         MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */
 572                 >;
 573         };
 574
 575         pinctrl_flexspi0: flexspi0grp {
 576                 fsl,pins = <
 577                         MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2
 578                         MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82
 579                         MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82
 580                         MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82
 581                         MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82
 582                         MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82
 583                 >;
 584         };
 585
 586         pinctrl_gpio_led: gpioledgrp {
 587                 fsl,pins = <
 588                         MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16   0x140
 589                 >;
 590         };
 591
 592         pinctrl_i2c1: i2c1grp {
 593                 fsl,pins = <
 594                         MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL         0x400001c2
 595                         MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA         0x400001c2
 596                 >;
 597         };
 598
 599         pinctrl_i2c2: i2c2grp {
 600                 fsl,pins = <
 601                         MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL         0x400001c2
 602                         MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA         0x400001c2
 603                 >;
 604         };
 605
 606         pinctrl_i2c3: i2c3grp {
 607                 fsl,pins = <
 608                         MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL         0x400001c2
 609                         MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA         0x400001c2
 610                 >;
 611         };
 612
 613         pinctrl_i2c5: i2c5grp {
 614                 fsl,pins = <
 615                         MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA         0x400001c2
 616                         MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2
 617                 >;
 618         };
 619
 620         pinctrl_pcie0: pcie0grp {
 621                 fsl,pins = <
 622                         MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B    0x60 /* open drain, pull up */
 623                         MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07      0x40
 624                 >;
 625         };
 626
 627         pinctrl_pcie0_reg: pcie0reggrp {
 628                 fsl,pins = <
 629                         MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x40
 630                 >;
 631         };
 632
 633         pinctrl_pmic: pmicgrp {
 634                 fsl,pins = <
 635                         MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03     0x000001c0
 636                 >;
 637         };
 638
 639         pinctrl_pca6416_int: pca6416_int_grp {
 640                 fsl,pins = <
 641                         MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12     0x146 /* Input pull-up. */
 642                 >;
 643         };
 644
 645         pinctrl_pwm1: pwm1grp {
 646                 fsl,pins = <
 647                         MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT       0x116
 648                 >;
 649         };
 650
 651         pinctrl_pwm2: pwm2grp {
 652                 fsl,pins = <
 653                         MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT       0x116
 654                 >;
 655         };
 656
 657         pinctrl_pwm4: pwm4grp {
 658                 fsl,pins = <
 659                         MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT        0x116
 660                 >;
 661         };
 662
 663         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 664                 fsl,pins = <
 665                         MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19    0x40
 666                 >;
 667         };
 668
 669         pinctrl_uart1: uart1grp {
 670                 fsl,pins = <
 671                         MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX    0x140
 672                         MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX    0x140
 673                         MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS   0x140
 674                         MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS   0x140
 675                 >;
 676         };
 677
 678         pinctrl_uart2: uart2grp {
 679                 fsl,pins = <
 680                         MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX    0x140
 681                         MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX    0x140
 682                 >;
 683         };
 684
 685         pinctrl_usb1_vbus: usb1grp {
 686                 fsl,pins = <
 687                         MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR   0x10
 688                 >;
 689         };
 690
 691         pinctrl_uart3: uart3grp {
 692                 fsl,pins = <
 693                         MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX          0x140
 694                         MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX          0x140
 695                         MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS          0x140
 696                         MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS         0x140
 697                 >;
 698         };
 699
 700         pinctrl_usdhc2: usdhc2grp {
 701                 fsl,pins = <
 702                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190
 703                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d0
 704                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d0
 705                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d0
 706                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d0
 707                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d0
 708                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
 709                 >;
 710         };
 711
 712         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 713                 fsl,pins = <
 714                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x194
 715                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d4
 716                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d4
 717                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d4
 718                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d4
 719                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d4
 720                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
 721                 >;
 722         };
 723
 724         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 725                 fsl,pins = <
 726                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x196
 727                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d6
 728                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d6
 729                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d6
 730                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d6
 731                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d6
 732                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
 733                 >;
 734         };
 735
 736         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 737                 fsl,pins = <
 738                         MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12       0x1c4
 739                 >;
 740         };
 741
 742         pinctrl_usdhc3: usdhc3grp {
 743                 fsl,pins = <
 744                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x190
 745                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d0
 746                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d0
 747                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d0
 748                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d0
 749                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d0
 750                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d0
 751                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d0
 752                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d0
 753                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d0
 754                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x190
 755                 >;
 756         };
 757
 758         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 759                 fsl,pins = <
 760                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x194
 761                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d4
 762                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d4
 763                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d4
 764                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d4
 765                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d4
 766                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d4
 767                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d4
 768                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d4
 769                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d4
 770                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x194
 771                 >;
 772         };
 773
 774         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 775                 fsl,pins = <
 776                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x196
 777                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d6
 778                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d6
 779                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d6
 780                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d6
 781                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d6
 782                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d6
 783                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d6
 784                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d6
 785                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d6
 786                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x196
 787                 >;
 788         };
 789
 790         pinctrl_wdog: wdoggrp {
 791                 fsl,pins = <
 792                         MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B   0x166
 793                 >;
 794         };
 795 };