arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2022 Gateworks Corporation
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/linux-event-codes.h>
  10 #include <dt-bindings/leds/common.h>
  11 #include <dt-bindings/phy/phy-imx8-pcie.h>
  12
  13 #include "imx8mm.dtsi"
  14
  15 / {
  16         model = "Gateworks Venice GW7904 i.MX8MM board";
  17         compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
  18
  19         chosen {
  20                 stdout-path = &uart2;
  21         };
  22
  23         memory@40000000 {
  24                 device_type = "memory";
  25                 reg = <0x0 0x40000000 0 0x80000000>;
  26         };
  27
  28         gpio-keys {
  29                 compatible = "gpio-keys";
  30
  31                 key-0 {
  32                         label = "user_pb";
  33                         gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
  34                         linux,code = <BTN_0>;
  35                 };
  36
  37                 key-1 {
  38                         label = "user_pb1x";
  39                         linux,code = <BTN_1>;
  40                         interrupt-parent = <&gsc>;
  41                         interrupts = <0>;
  42                 };
  43
  44                 key-2 {
  45                         label = "key_erased";
  46                         linux,code = <BTN_2>;
  47                         interrupt-parent = <&gsc>;
  48                         interrupts = <1>;
  49                 };
  50
  51                 key-3 {
  52                         label = "eeprom_wp";
  53                         linux,code = <BTN_3>;
  54                         interrupt-parent = <&gsc>;
  55                         interrupts = <2>;
  56                 };
  57
  58                 key-4 {
  59                         label = "switch_hold";
  60                         linux,code = <BTN_5>;
  61                         interrupt-parent = <&gsc>;
  62                         interrupts = <7>;
  63                 };
  64         };
  65
  66         led-controller {
  67                 compatible = "gpio-leds";
  68                 pinctrl-names = "default";
  69                 pinctrl-0 = <&pinctrl_gpio_leds>;
  70
  71                 led-0 {
  72                         function = LED_FUNCTION_STATUS;
  73                         color = <LED_COLOR_ID_GREEN>;
  74                         label = "led01_grn";
  75                         gpios = <&gpioled 0 GPIO_ACTIVE_LOW>;
  76                         default-state = "off";
  77                 };
  78
  79                 led-1 {
  80                         function = LED_FUNCTION_STATUS;
  81                         color = <LED_COLOR_ID_YELLOW>;
  82                         label = "led01_yel";
  83                         gpios = <&gpioled 1 GPIO_ACTIVE_LOW>;
  84                         default-state = "off";
  85                 };
  86
  87                 led-2 {
  88                         function = LED_FUNCTION_STATUS;
  89                         color = <LED_COLOR_ID_GREEN>;
  90                         label = "led02_grn";
  91                         gpios = <&gpioled 2 GPIO_ACTIVE_LOW>;
  92                         default-state = "off";
  93                 };
  94
  95                 led-3 {
  96                         function = LED_FUNCTION_STATUS;
  97                         color = <LED_COLOR_ID_YELLOW>;
  98                         label = "led02_yel";
  99                         gpios = <&gpioled 3 GPIO_ACTIVE_LOW>;
 100                         default-state = "off";
 101                 };
 102
 103                 led-4 {
 104                         function = LED_FUNCTION_STATUS;
 105                         color = <LED_COLOR_ID_GREEN>;
 106                         label = "led03_grn";
 107                         gpios = <&gpioled 4 GPIO_ACTIVE_LOW>;
 108                         default-state = "off";
 109                 };
 110
 111                 led-5 {
 112                         function = LED_FUNCTION_STATUS;
 113                         color = <LED_COLOR_ID_YELLOW>;
 114                         label = "led03_yel";
 115                         gpios = <&gpioled 5 GPIO_ACTIVE_LOW>;
 116                         default-state = "off";
 117                 };
 118
 119                 led-6 {
 120                         function = LED_FUNCTION_STATUS;
 121                         color = <LED_COLOR_ID_GREEN>;
 122                         label = "led04_grn";
 123                         gpios = <&gpioled 6 GPIO_ACTIVE_LOW>;
 124                         default-state = "off";
 125                 };
 126
 127                 led-7 {
 128                         function = LED_FUNCTION_STATUS;
 129                         color = <LED_COLOR_ID_YELLOW>;
 130                         label = "led04_yel";
 131                         gpios = <&gpioled 7 GPIO_ACTIVE_LOW>;
 132                         default-state = "off";
 133                 };
 134
 135                 led-8 {
 136                         function = LED_FUNCTION_STATUS;
 137                         color = <LED_COLOR_ID_GREEN>;
 138                         label = "led05_grn";
 139                         gpios = <&gpioled 8 GPIO_ACTIVE_LOW>;
 140                         default-state = "off";
 141                 };
 142
 143                 led-9 {
 144                         function = LED_FUNCTION_STATUS;
 145                         color = <LED_COLOR_ID_YELLOW>;
 146                         label = "led05_yel";
 147                         gpios = <&gpioled 9 GPIO_ACTIVE_LOW>;
 148                         default-state = "off";
 149                 };
 150
 151                 led-10 {
 152                         function = LED_FUNCTION_STATUS;
 153                         color = <LED_COLOR_ID_GREEN>;
 154                         label = "led06_grn";
 155                         gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
 156                         default-state = "off";
 157                 };
 158
 159                 led-11 {
 160                         function = LED_FUNCTION_STATUS;
 161                         color = <LED_COLOR_ID_RED>;
 162                         label = "led06_red";
 163                         gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 164                         default-state = "off";
 165                 };
 166
 167                 led-12 {
 168                         function = LED_FUNCTION_STATUS;
 169                         color = <LED_COLOR_ID_GREEN>;
 170                         label = "led07_grn";
 171                         gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
 172                         default-state = "off";
 173                 };
 174
 175                 led-13 {
 176                         function = LED_FUNCTION_STATUS;
 177                         color = <LED_COLOR_ID_RED>;
 178                         label = "led07_red";
 179                         gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 180                         default-state = "off";
 181                 };
 182
 183                 led-14 {
 184                         function = LED_FUNCTION_STATUS;
 185                         color = <LED_COLOR_ID_GREEN>;
 186                         label = "led08_grn";
 187                         gpios = <&gpioled 10 GPIO_ACTIVE_LOW>;
 188                         default-state = "off";
 189                 };
 190
 191                 led-15 {
 192                         function = LED_FUNCTION_STATUS;
 193                         color = <LED_COLOR_ID_YELLOW>;
 194                         label = "led08_yel";
 195                         gpios = <&gpioled 11 GPIO_ACTIVE_LOW>;
 196                         default-state = "off";
 197                 };
 198
 199                 led-16 {
 200                         function = LED_FUNCTION_STATUS;
 201                         color = <LED_COLOR_ID_GREEN>;
 202                         label = "led09_grn";
 203                         gpios = <&gpioled 12 GPIO_ACTIVE_LOW>;
 204                         default-state = "off";
 205                 };
 206
 207                 led-17 {
 208                         function = LED_FUNCTION_STATUS;
 209                         color = <LED_COLOR_ID_YELLOW>;
 210                         label = "led09_yel";
 211                         gpios = <&gpioled 13 GPIO_ACTIVE_LOW>;
 212                         default-state = "off";
 213                 };
 214
 215                 led-18 {
 216                         function = LED_FUNCTION_STATUS;
 217                         color = <LED_COLOR_ID_GREEN>;
 218                         label = "led10_grn";
 219                         gpios = <&gpioled 14 GPIO_ACTIVE_LOW>;
 220                         default-state = "off";
 221                 };
 222
 223                 led-19 {
 224                         function = LED_FUNCTION_STATUS;
 225                         color = <LED_COLOR_ID_YELLOW>;
 226                         label = "led10_yel";
 227                         gpios = <&gpioled 15 GPIO_ACTIVE_LOW>;
 228                         default-state = "off";
 229                 };
 230         };
 231
 232         pcie0_refclk: pcie0-refclk {
 233                 compatible = "fixed-clock";
 234                 #clock-cells = <0>;
 235                 clock-frequency = <100000000>;
 236         };
 237
 238         reg_3p3v: regulator-3p3v {
 239                 compatible = "regulator-fixed";
 240                 regulator-name = "3P3V";
 241                 regulator-min-microvolt = <3300000>;
 242                 regulator-max-microvolt = <3300000>;
 243                 regulator-always-on;
 244         };
 245 };
 246
 247 &A53_0 {
 248         cpu-supply = <&buck2>;
 249 };
 250
 251 &A53_1 {
 252         cpu-supply = <&buck2>;
 253 };
 254
 255 &A53_2 {
 256         cpu-supply = <&buck2>;
 257 };
 258
 259 &A53_3 {
 260         cpu-supply = <&buck2>;
 261 };
 262
 263 &ddrc {
 264         operating-points-v2 = <&ddrc_opp_table>;
 265
 266         ddrc_opp_table: opp-table {
 267                 compatible = "operating-points-v2";
 268
 269                 opp-25000000 {
 270                         opp-hz = /bits/ 64 <25000000>;
 271                 };
 272
 273                 opp-100000000 {
 274                         opp-hz = /bits/ 64 <100000000>;
 275                 };
 276
 277                 opp-750000000 {
 278                         opp-hz = /bits/ 64 <750000000>;
 279                 };
 280         };
 281 };
 282
 283 &fec1 {
 284         pinctrl-names = "default";
 285         pinctrl-0 = <&pinctrl_fec1>;
 286         phy-mode = "rgmii-id";
 287         phy-handle = <&ethphy0>;
 288         local-mac-address = [00 00 00 00 00 00];
 289         status = "okay";
 290
 291         mdio {
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294
 295                 ethphy0: ethernet-phy@0 {
 296                         compatible = "ethernet-phy-ieee802.3-c22";
 297                         reg = <0>;
 298                 };
 299         };
 300 };
 301
 302 &gpio1 {
 303         gpio-line-names = "", "", "", "", "", "", "", "",
 304                 "", "", "", "", "rs232_en#", "", "", "",
 305                 "", "", "", "", "", "", "", "",
 306                 "", "", "", "", "", "", "", "";
 307 };
 308
 309 &gpio5 {
 310         gpio-line-names = "", "", "", "", "", "", "", "",
 311                 "", "", "", "", "pci_wdis#", "", "", "",
 312                 "", "", "", "", "", "", "", "",
 313                 "", "", "", "", "", "", "", "";
 314 };
 315
 316 &i2c1 {
 317         clock-frequency = <100000>;
 318         pinctrl-names = "default", "gpio";
 319         pinctrl-0 = <&pinctrl_i2c1>;
 320         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 321         scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 322         sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 323         status = "okay";
 324
 325         gsc: gsc@20 {
 326                 compatible = "gw,gsc";
 327                 reg = <0x20>;
 328                 pinctrl-0 = <&pinctrl_gsc>;
 329                 interrupt-parent = <&gpio4>;
 330                 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
 331                 interrupt-controller;
 332                 #interrupt-cells = <1>;
 333
 334                 adc {
 335                         compatible = "gw,gsc-adc";
 336                         #address-cells = <1>;
 337                         #size-cells = <0>;
 338
 339                         channel@6 {
 340                                 gw,mode = <0>;
 341                                 reg = <0x06>;
 342                                 label = "temp";
 343                         };
 344
 345                         channel@82 {
 346                                 gw,mode = <2>;
 347                                 reg = <0x82>;
 348                                 label = "vin";
 349                                 gw,voltage-divider-ohms = <22100 1000>;
 350                                 gw,voltage-offset-microvolt = <700000>;
 351                         };
 352
 353                         channel@84 {
 354                                 gw,mode = <2>;
 355                                 reg = <0x84>;
 356                                 label = "vdd_5p0";
 357                                 gw,voltage-divider-ohms = <10000 10000>;
 358                         };
 359
 360                         channel@86 {
 361                                 gw,mode = <2>;
 362                                 reg = <0x86>;
 363                                 label = "vdd_3p3";
 364                                 gw,voltage-divider-ohms = <10000 10000>;
 365                         };
 366
 367                         channel@88 {
 368                                 gw,mode = <2>;
 369                                 reg = <0x88>;
 370                                 label = "vdd_0p9";
 371                         };
 372
 373                         channel@8c {
 374                                 gw,mode = <2>;
 375                                 reg = <0x8c>;
 376                                 label = "vdd_soc";
 377                         };
 378
 379                         channel@8e {
 380                                 gw,mode = <2>;
 381                                 reg = <0x8e>;
 382                                 label = "vdd_arm";
 383                         };
 384
 385                         channel@90 {
 386                                 gw,mode = <2>;
 387                                 reg = <0x90>;
 388                                 label = "vdd_1p8";
 389                         };
 390
 391                         channel@92 {
 392                                 gw,mode = <2>;
 393                                 reg = <0x92>;
 394                                 label = "vdd_dram";
 395                         };
 396
 397                         channel@a2 {
 398                                 gw,mode = <2>;
 399                                 reg = <0xa2>;
 400                                 label = "vdd_gsc";
 401                                 gw,voltage-divider-ohms = <10000 10000>;
 402                         };
 403                 };
 404         };
 405
 406         gpio: gpio@23 {
 407                 compatible = "nxp,pca9555";
 408                 reg = <0x23>;
 409                 gpio-controller;
 410                 #gpio-cells = <2>;
 411                 interrupt-parent = <&gsc>;
 412                 interrupts = <4>;
 413         };
 414
 415         eeprom@50 {
 416                 compatible = "atmel,24c02";
 417                 reg = <0x50>;
 418                 pagesize = <16>;
 419         };
 420
 421         eeprom@51 {
 422                 compatible = "atmel,24c02";
 423                 reg = <0x51>;
 424                 pagesize = <16>;
 425         };
 426
 427         eeprom@52 {
 428                 compatible = "atmel,24c02";
 429                 reg = <0x52>;
 430                 pagesize = <16>;
 431         };
 432
 433         eeprom@53 {
 434                 compatible = "atmel,24c02";
 435                 reg = <0x53>;
 436                 pagesize = <16>;
 437         };
 438
 439         rtc@68 {
 440                 compatible = "dallas,ds1672";
 441                 reg = <0x68>;
 442         };
 443 };
 444
 445 &i2c2 {
 446         clock-frequency = <400000>;
 447         pinctrl-names = "default", "gpio";
 448         pinctrl-0 = <&pinctrl_i2c2>;
 449         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 450         scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 451         sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 452         status = "okay";
 453
 454         pmic@4b {
 455                 compatible = "rohm,bd71847";
 456                 reg = <0x4b>;
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&pinctrl_pmic>;
 459                 interrupt-parent = <&gpio3>;
 460                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 461                 rohm,reset-snvs-powered;
 462                 #clock-cells = <0>;
 463                 clocks = <&osc_32k 0>;
 464                 clock-output-names = "clk-32k-out";
 465
 466                 regulators {
 467                         /* vdd_soc: 0.805-0.900V (typ=0.8V) */
 468                         BUCK1 {
 469                                 regulator-name = "buck1";
 470                                 regulator-min-microvolt = <700000>;
 471                                 regulator-max-microvolt = <1300000>;
 472                                 regulator-boot-on;
 473                                 regulator-always-on;
 474                                 regulator-ramp-delay = <1250>;
 475                         };
 476
 477                         /* vdd_arm: 0.805-1.0V (typ=0.9V) */
 478                         buck2: BUCK2 {
 479                                 regulator-name = "buck2";
 480                                 regulator-min-microvolt = <700000>;
 481                                 regulator-max-microvolt = <1300000>;
 482                                 regulator-boot-on;
 483                                 regulator-always-on;
 484                                 regulator-ramp-delay = <1250>;
 485                                 rohm,dvs-run-voltage = <1000000>;
 486                                 rohm,dvs-idle-voltage = <900000>;
 487                         };
 488
 489                         /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
 490                         BUCK3 {
 491                                 regulator-name = "buck3";
 492                                 regulator-min-microvolt = <700000>;
 493                                 regulator-max-microvolt = <1350000>;
 494                                 regulator-boot-on;
 495                                 regulator-always-on;
 496                         };
 497
 498                         /* vdd_3p3 */
 499                         BUCK4 {
 500                                 regulator-name = "buck4";
 501                                 regulator-min-microvolt = <3000000>;
 502                                 regulator-max-microvolt = <3300000>;
 503                                 regulator-boot-on;
 504                                 regulator-always-on;
 505                         };
 506
 507                         /* vdd_1p8 */
 508                         BUCK5 {
 509                                 regulator-name = "buck5";
 510                                 regulator-min-microvolt = <1605000>;
 511                                 regulator-max-microvolt = <1995000>;
 512                                 regulator-boot-on;
 513                                 regulator-always-on;
 514                         };
 515
 516                         /* vdd_dram */
 517                         BUCK6 {
 518                                 regulator-name = "buck6";
 519                                 regulator-min-microvolt = <800000>;
 520                                 regulator-max-microvolt = <1400000>;
 521                                 regulator-boot-on;
 522                                 regulator-always-on;
 523                         };
 524
 525                         /* nvcc_snvs_1p8 */
 526                         LDO1 {
 527                                 regulator-name = "ldo1";
 528                                 regulator-min-microvolt = <1600000>;
 529                                 regulator-max-microvolt = <1900000>;
 530                                 regulator-boot-on;
 531                                 regulator-always-on;
 532                         };
 533
 534                         /* vdd_snvs_0p8 */
 535                         LDO2 {
 536                                 regulator-name = "ldo2";
 537                                 regulator-min-microvolt = <800000>;
 538                                 regulator-max-microvolt = <900000>;
 539                                 regulator-boot-on;
 540                                 regulator-always-on;
 541                         };
 542
 543                         /* vdda_1p8 */
 544                         LDO3 {
 545                                 regulator-name = "ldo3";
 546                                 regulator-min-microvolt = <1800000>;
 547                                 regulator-max-microvolt = <3300000>;
 548                                 regulator-boot-on;
 549                                 regulator-always-on;
 550                         };
 551
 552                         LDO4 {
 553                                 regulator-name = "ldo4";
 554                                 regulator-min-microvolt = <900000>;
 555                                 regulator-max-microvolt = <1800000>;
 556                                 regulator-boot-on;
 557                                 regulator-always-on;
 558                         };
 559
 560                         LDO6 {
 561                                 regulator-name = "ldo6";
 562                                 regulator-min-microvolt = <900000>;
 563                                 regulator-max-microvolt = <1800000>;
 564                                 regulator-boot-on;
 565                                 regulator-always-on;
 566                         };
 567                 };
 568         };
 569 };
 570
 571 &i2c3 {
 572         clock-frequency = <400000>;
 573         pinctrl-names = "default", "gpio";
 574         pinctrl-0 = <&pinctrl_i2c3>;
 575         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 576         scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 577         sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 578         status = "okay";
 579
 580         accelerometer@19 {
 581                 pinctrl-names = "default";
 582                 pinctrl-0 = <&pinctrl_accel>;
 583                 compatible = "st,lis2de12";
 584                 reg = <0x19>;
 585                 st,drdy-int-pin = <1>;
 586                 interrupt-parent = <&gpio1>;
 587                 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
 588                 interrupt-names = "INT1";
 589         };
 590 };
 591
 592 &i2c4 {
 593         clock-frequency = <400000>;
 594         pinctrl-names = "default", "gpio";
 595         pinctrl-0 = <&pinctrl_i2c4>;
 596         pinctrl-1 = <&pinctrl_i2c4_gpio>;
 597         scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 598         sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 599         status = "okay";
 600
 601         gpioled: gpio@27 {
 602                 compatible = "nxp,pca9555";
 603                 reg = <0x27>;
 604                 gpio-controller;
 605                 #gpio-cells = <2>;
 606         };
 607 };
 608
 609 &pcie_phy {
 610         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 611         fsl,clkreq-unsupported;
 612         clocks = <&pcie0_refclk>;
 613         clock-names = "ref";
 614         status = "okay";
 615 };
 616
 617 &pcie0 {
 618         pinctrl-names = "default";
 619         pinctrl-0 = <&pinctrl_pcie0>;
 620         reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
 621         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
 622                  <&clk IMX8MM_CLK_PCIE1_AUX>;
 623         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 624                           <&clk IMX8MM_CLK_PCIE1_CTRL>;
 625         assigned-clock-rates = <10000000>, <250000000>;
 626         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 627                                  <&clk IMX8MM_SYS_PLL2_250M>;
 628         status = "okay";
 629 };
 630
 631 &disp_blk_ctrl {
 632         status = "disabled";
 633 };
 634
 635 &pgc_mipi {
 636         status = "disabled";
 637 };
 638
 639 /* off-board RS232 */
 640 &uart1 {
 641         pinctrl-names = "default";
 642         pinctrl-0 = <&pinctrl_uart1>;
 643         status = "okay";
 644 };
 645
 646 /* console */
 647 &uart2 {
 648         pinctrl-names = "default";
 649         pinctrl-0 = <&pinctrl_uart2>;
 650         status = "okay";
 651 };
 652
 653 /* off-board RS232 */
 654 &uart3 {
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&pinctrl_uart3>;
 657         status = "okay";
 658 };
 659
 660 &usbotg1 {
 661         dr_mode = "host";
 662         disable-over-current;
 663         status = "okay";
 664 };
 665
 666 /* microSD */
 667 &usdhc2 {
 668         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 669         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 670         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 671         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 672         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 673         bus-width = <4>;
 674         vmmc-supply = <&reg_3p3v>;
 675         status = "okay";
 676 };
 677
 678 /* eMMC */
 679 &usdhc3 {
 680         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 681         pinctrl-0 = <&pinctrl_usdhc3>;
 682         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 683         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 684         bus-width = <8>;
 685         non-removable;
 686         status = "okay";
 687 };
 688
 689 &wdog1 {
 690         pinctrl-names = "default";
 691         pinctrl-0 = <&pinctrl_wdog>;
 692         fsl,ext-reset-output;
 693         status = "okay";
 694 };
 695
 696 &iomuxc {
 697         pinctrl-names = "default";
 698         pinctrl-0 = <&pinctrl_hog>;
 699
 700         pinctrl_hog: hoggrp {
 701                 fsl,pins = <
 702                         MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x40000041 /* RS232# */
 703                         MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12     0x40000041 /* PCI_WDIS# */
 704                 >;
 705         };
 706
 707         pinctrl_accel: accelgrp {
 708                 fsl,pins = <
 709                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x159
 710                 >;
 711         };
 712
 713         pinctrl_fec1: fec1grp {
 714                 fsl,pins = <
 715                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 716                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 717                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 718                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 719                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 720                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 721                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 722                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 723                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 724                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 725                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 726                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 727                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 728                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 729                         MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24               0x19 /* IRQ# */
 730                         MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25                0x19 /* RST# */
 731                 >;
 732         };
 733
 734         pinctrl_gpio_leds: gpioledsgrp {
 735                 fsl,pins = <
 736                         MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8       0x40000019
 737                         MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9       0x40000019
 738                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10      0x40000019
 739                         MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11      0x40000019
 740                 >;
 741         };
 742
 743         pinctrl_gsc: gscgrp {
 744                 fsl,pins = <
 745                         MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26       0x159
 746                 >;
 747         };
 748
 749         pinctrl_i2c1: i2c1grp {
 750                 fsl,pins = <
 751                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 752                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 753                 >;
 754         };
 755
 756         pinctrl_i2c1_gpio: i2c1gpiogrp {
 757                 fsl,pins = <
 758                         MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14        0x400001c3
 759                         MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15        0x400001c3
 760                 >;
 761         };
 762
 763         pinctrl_i2c2: i2c2grp {
 764                 fsl,pins = <
 765                         MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 766                         MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 767                 >;
 768         };
 769
 770         pinctrl_i2c2_gpio: i2c2gpiogrp {
 771                 fsl,pins = <
 772                         MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16        0x400001c3
 773                         MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17        0x400001c3
 774                 >;
 775         };
 776
 777         pinctrl_i2c3: i2c3grp {
 778                 fsl,pins = <
 779                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 780                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 781                 >;
 782         };
 783
 784         pinctrl_i2c3_gpio: i2c3gpiogrp {
 785                 fsl,pins = <
 786                         MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18        0x400001c3
 787                         MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19        0x400001c3
 788                 >;
 789         };
 790
 791         pinctrl_i2c4: i2c4grp {
 792                 fsl,pins = <
 793                         MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL          0x400001c3
 794                         MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA          0x400001c3
 795                 >;
 796         };
 797
 798         pinctrl_i2c4_gpio: i2c4gpiogrp {
 799                 fsl,pins = <
 800                         MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20        0x400001c3
 801                         MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21        0x400001c3
 802                 >;
 803         };
 804
 805         pinctrl_pcie0: pciegrp {
 806                 fsl,pins = <
 807                         MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11     0x41
 808                 >;
 809         };
 810
 811         pinctrl_pmic: pmicgrp {
 812                 fsl,pins = <
 813                         MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8      0x41
 814                 >;
 815         };
 816
 817         pinctrl_uart1: uart1grp {
 818                 fsl,pins = <
 819                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 820                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 821                 >;
 822         };
 823
 824         pinctrl_uart2: uart2grp {
 825                 fsl,pins = <
 826                         MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 827                         MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 828                 >;
 829         };
 830
 831         pinctrl_uart3: uart3grp {
 832                 fsl,pins = <
 833                         MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
 834                         MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
 835                 >;
 836         };
 837
 838         pinctrl_usdhc2: usdhc2grp {
 839                 fsl,pins = <
 840                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 841                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 842                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 843                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 844                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 845                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 846                 >;
 847         };
 848
 849         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 850                 fsl,pins = <
 851                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 852                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 853                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 854                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 855                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 856                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 857                 >;
 858         };
 859
 860         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 861                 fsl,pins = <
 862                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 863                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 864                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 865                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 866                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 867                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 868                 >;
 869         };
 870
 871         pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
 872                 fsl,pins = <
 873                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12        0x1c4
 874                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 875                 >;
 876         };
 877
 878         pinctrl_usdhc3: usdhc3grp {
 879                 fsl,pins = <
 880                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
 881                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
 882                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
 883                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
 884                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
 885                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
 886                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0
 887                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0
 888                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0
 889                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0
 890                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190
 891                 >;
 892         };
 893
 894         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 895                 fsl,pins = <
 896                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
 897                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
 898                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
 899                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
 900                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
 901                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
 902                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4
 903                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4
 904                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4
 905                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4
 906                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194
 907                 >;
 908         };
 909
 910         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 911                 fsl,pins = <
 912                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
 913                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
 914                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
 915                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
 916                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
 917                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
 918                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6
 919                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6
 920                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6
 921                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6
 922                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196
 923                 >;
 924         };
 925
 926         pinctrl_wdog: wdoggrp {
 927                 fsl,pins = <
 928                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
 929                 >;
 930         };
 931 };