arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  *      Dong Aisheng <aisheng.dong@nxp.com>
   5  */
   6
   7 #include <dt-bindings/clock/imx8-lpcg.h>
   8 #include <dt-bindings/firmware/imx/rsrc.h>
   9
  10 audio_ipg_clk: clock-audio-ipg {
  11         compatible = "fixed-clock";
  12         #clock-cells = <0>;
  13         clock-frequency = <120000000>;
  14         clock-output-names = "audio_ipg_clk";
  15 };
  16
  17 clk_ext_aud_mclk0: clock-ext-aud-mclk0 {
  18         compatible = "fixed-clock";
  19         #clock-cells = <0>;
  20         clock-frequency = <0>;
  21         clock-output-names = "ext_aud_mclk0";
  22 };
  23
  24 clk_ext_aud_mclk1: clock-ext-aud-mclk1 {
  25         compatible = "fixed-clock";
  26         #clock-cells = <0>;
  27         clock-frequency = <0>;
  28         clock-output-names = "ext_aud_mclk1";
  29 };
  30
  31 clk_esai0_rx_clk: clock-esai0-rx {
  32         compatible = "fixed-clock";
  33         #clock-cells = <0>;
  34         clock-frequency = <0>;
  35         clock-output-names = "esai0_rx_clk";
  36 };
  37
  38 clk_esai0_rx_hf_clk: clock-esai0-rx-hf {
  39         compatible = "fixed-clock";
  40         #clock-cells = <0>;
  41         clock-frequency = <0>;
  42         clock-output-names = "esai0_rx_hf_clk";
  43 };
  44
  45 clk_esai0_tx_clk: clock-esai0-tx {
  46         compatible = "fixed-clock";
  47         #clock-cells = <0>;
  48         clock-frequency = <0>;
  49         clock-output-names = "esai0_tx_clk";
  50 };
  51
  52 clk_esai0_tx_hf_clk: clock-esai0-tx-hf {
  53         compatible = "fixed-clock";
  54         #clock-cells = <0>;
  55         clock-frequency = <0>;
  56         clock-output-names = "esai0_tx_hf_clk";
  57 };
  58
  59 clk_spdif0_rx: clock-spdif0-rx {
  60         compatible = "fixed-clock";
  61         #clock-cells = <0>;
  62         clock-frequency = <0>;
  63         clock-output-names = "spdif0_rx";
  64 };
  65
  66 clk_sai0_rx_bclk: clock-sai0-rx-bclk {
  67         compatible = "fixed-clock";
  68         #clock-cells = <0>;
  69         clock-frequency = <0>;
  70         clock-output-names = "sai0_rx_bclk";
  71 };
  72
  73 clk_sai0_tx_bclk: clock-sai0-tx-bclk {
  74         compatible = "fixed-clock";
  75         #clock-cells = <0>;
  76         clock-frequency = <0>;
  77         clock-output-names = "sai0_tx_bclk";
  78 };
  79
  80 clk_sai1_rx_bclk: clock-sai1-rx-bclk {
  81         compatible = "fixed-clock";
  82         #clock-cells = <0>;
  83         clock-frequency = <0>;
  84         clock-output-names = "sai1_rx_bclk";
  85 };
  86
  87 clk_sai1_tx_bclk: clock-sai1-tx-bclk {
  88         compatible = "fixed-clock";
  89         #clock-cells = <0>;
  90         clock-frequency = <0>;
  91         clock-output-names = "sai1_tx_bclk";
  92 };
  93
  94 clk_sai2_rx_bclk: clock-sai2-rx-bclk {
  95         compatible = "fixed-clock";
  96         #clock-cells = <0>;
  97         clock-frequency = <0>;
  98         clock-output-names = "sai2_rx_bclk";
  99 };
 100
 101 clk_sai3_rx_bclk: clock-sai3-rx-bclk {
 102         compatible = "fixed-clock";
 103         #clock-cells = <0>;
 104         clock-frequency = <0>;
 105         clock-output-names = "sai3_rx_bclk";
 106 };
 107
 108 clk_sai4_rx_bclk: clock-sai4-rx-bclk {
 109         compatible = "fixed-clock";
 110         #clock-cells = <0>;
 111         clock-frequency = <0>;
 112         clock-output-names = "sai4_rx_bclk";
 113 };
 114
 115 audio_subsys: bus@59000000 {
 116         compatible = "simple-bus";
 117         #address-cells = <1>;
 118         #size-cells = <1>;
 119         ranges = <0x59000000 0x0 0x59000000 0x1000000>;
 120
 121         edma0: dma-controller@591f0000 {
 122                 compatible = "fsl,imx8qm-edma";
 123                 reg = <0x591f0000 0x190000>;
 124                 #dma-cells = <3>;
 125                 dma-channels = <24>;
 126                 dma-channel-mask = <0x5c0c00>;
 127                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */
 128                              <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, /* 1 */
 129                              <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, /* 2 */
 130                              <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, /* 3 */
 131                              <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* 4 */
 132                              <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, /* 5 */
 133                              <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 6 esai0 */
 134                              <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 7 */
 135                              <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* 8 spdif0 */
 136                              <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, /* 9 */
 137                              <GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>, /* 10 unused */
 138                              <GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>, /* 11 unused */
 139                              <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 12 sai0 */
 140                              <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 13 */
 141                              <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 14 sai1 */
 142                              <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 15 */
 143                              <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* 16 sai2 */
 144                              <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* 17 sai3 */
 145                              <GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>, /* 18 unused */
 146                              <GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>, /* 19 unused */
 147                              <GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */
 148                              <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, /* 21 */
 149                              <GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */
 150                              <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; /* 23 unused */
 151                 power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
 152                                 <&pd IMX_SC_R_DMA_0_CH1>,
 153                                 <&pd IMX_SC_R_DMA_0_CH2>,
 154                                 <&pd IMX_SC_R_DMA_0_CH3>,
 155                                 <&pd IMX_SC_R_DMA_0_CH4>,
 156                                 <&pd IMX_SC_R_DMA_0_CH5>,
 157                                 <&pd IMX_SC_R_DMA_0_CH6>,
 158                                 <&pd IMX_SC_R_DMA_0_CH7>,
 159                                 <&pd IMX_SC_R_DMA_0_CH8>,
 160                                 <&pd IMX_SC_R_DMA_0_CH9>,
 161                                 <&pd IMX_SC_R_DMA_0_CH10>,
 162                                 <&pd IMX_SC_R_DMA_0_CH11>,
 163                                 <&pd IMX_SC_R_DMA_0_CH12>,
 164                                 <&pd IMX_SC_R_DMA_0_CH13>,
 165                                 <&pd IMX_SC_R_DMA_0_CH14>,
 166                                 <&pd IMX_SC_R_DMA_0_CH15>,
 167                                 <&pd IMX_SC_R_DMA_0_CH16>,
 168                                 <&pd IMX_SC_R_DMA_0_CH17>,
 169                                 <&pd IMX_SC_R_DMA_0_CH18>,
 170                                 <&pd IMX_SC_R_DMA_0_CH19>,
 171                                 <&pd IMX_SC_R_DMA_0_CH20>,
 172                                 <&pd IMX_SC_R_DMA_0_CH21>,
 173                                 <&pd IMX_SC_R_DMA_0_CH22>,
 174                                 <&pd IMX_SC_R_DMA_0_CH23>;
 175         };
 176
 177         dsp_lpcg: clock-controller@59580000 {
 178                 compatible = "fsl,imx8qxp-lpcg";
 179                 reg = <0x59580000 0x10000>;
 180                 #clock-cells = <1>;
 181                 clocks = <&audio_ipg_clk>,
 182                          <&audio_ipg_clk>,
 183                          <&audio_ipg_clk>;
 184                 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
 185                                 <IMX_LPCG_CLK_7>;
 186                 clock-output-names = "dsp_lpcg_adb_clk",
 187                                      "dsp_lpcg_ipg_clk",
 188                                      "dsp_lpcg_core_clk";
 189                 power-domains = <&pd IMX_SC_R_DSP>;
 190         };
 191
 192         dsp_ram_lpcg: clock-controller@59590000 {
 193                 compatible = "fsl,imx8qxp-lpcg";
 194                 reg = <0x59590000 0x10000>;
 195                 #clock-cells = <1>;
 196                 clocks = <&audio_ipg_clk>;
 197                 clock-indices = <IMX_LPCG_CLK_4>;
 198                 clock-output-names = "dsp_ram_lpcg_ipg_clk";
 199                 power-domains = <&pd IMX_SC_R_DSP_RAM>;
 200         };
 201
 202         dsp: dsp@596e8000 {
 203                 compatible = "fsl,imx8qxp-dsp";
 204                 reg = <0x596e8000 0x88000>;
 205                 clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
 206                          <&dsp_ram_lpcg IMX_LPCG_CLK_4>,
 207                          <&dsp_lpcg IMX_LPCG_CLK_7>;
 208                 clock-names = "ipg", "ocram", "core";
 209                 power-domains = <&pd IMX_SC_R_MU_13A>,
 210                         <&pd IMX_SC_R_MU_13B>,
 211                         <&pd IMX_SC_R_DSP>,
 212                         <&pd IMX_SC_R_DSP_RAM>;
 213                 mbox-names = "txdb0", "txdb1",
 214                         "rxdb0", "rxdb1";
 215                 mboxes = <&lsio_mu13 2 0>,
 216                         <&lsio_mu13 2 1>,
 217                         <&lsio_mu13 3 0>,
 218                         <&lsio_mu13 3 1>;
 219                 memory-region = <&dsp_reserved>;
 220                 status = "disabled";
 221         };
 222
 223         edma1: dma-controller@599f0000 {
 224                 compatible = "fsl,imx8qm-edma";
 225                 reg = <0x599f0000 0xc0000>;
 226                 #dma-cells = <3>;
 227                 dma-channels = <11>;
 228                 dma-channel-mask = <0xc0>;
 229                 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */
 230                              <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, /* 1 */
 231                              <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, /* 2 */
 232                              <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, /* 3 */
 233                              <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, /* 4 */
 234                              <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, /* 5 */
 235                              <GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>, /* 6 unused */
 236                              <GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */
 237                              <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
 238                              <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
 240                 power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
 241                                 <&pd IMX_SC_R_DMA_1_CH1>,
 242                                 <&pd IMX_SC_R_DMA_1_CH2>,
 243                                 <&pd IMX_SC_R_DMA_1_CH3>,
 244                                 <&pd IMX_SC_R_DMA_1_CH4>,
 245                                 <&pd IMX_SC_R_DMA_1_CH5>,
 246                                 <&pd IMX_SC_R_DMA_1_CH6>,
 247                                 <&pd IMX_SC_R_DMA_1_CH7>,
 248                                 <&pd IMX_SC_R_DMA_1_CH8>,
 249                                 <&pd IMX_SC_R_DMA_1_CH9>,
 250                                 <&pd IMX_SC_R_DMA_1_CH10>;
 251         };
 252
 253         aud_rec0_lpcg: clock-controller@59d00000 {
 254                 compatible = "fsl,imx8qxp-lpcg";
 255                 reg = <0x59d00000 0x10000>;
 256                 #clock-cells = <1>;
 257                 clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
 258                 clock-indices = <IMX_LPCG_CLK_0>;
 259                 clock-output-names = "aud_rec_clk0_lpcg_clk";
 260                 power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
 261         };
 262
 263         aud_rec1_lpcg: clock-controller@59d10000 {
 264                 compatible = "fsl,imx8qxp-lpcg";
 265                 reg = <0x59d10000 0x10000>;
 266                 #clock-cells = <1>;
 267                 clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>;
 268                 clock-indices = <IMX_LPCG_CLK_0>;
 269                 clock-output-names = "aud_rec_clk1_lpcg_clk";
 270                 power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
 271         };
 272
 273         aud_pll_div0_lpcg: clock-controller@59d20000 {
 274                 compatible = "fsl,imx8qxp-lpcg";
 275                 reg = <0x59d20000 0x10000>;
 276                 #clock-cells = <1>;
 277                 clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>;
 278                 clock-indices = <IMX_LPCG_CLK_0>;
 279                 clock-output-names = "aud_pll_div_clk0_lpcg_clk";
 280                 power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
 281         };
 282
 283         aud_pll_div1_lpcg: clock-controller@59d30000 {
 284                 compatible = "fsl,imx8qxp-lpcg";
 285                 reg = <0x59d30000 0x10000>;
 286                 #clock-cells = <1>;
 287                 clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>;
 288                 clock-indices = <IMX_LPCG_CLK_0>;
 289                 clock-output-names = "aud_pll_div_clk1_lpcg_clk";
 290                 power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
 291         };
 292 };