arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1088A family SoC.
   4  *
   5  * Copyright 2017-2020 NXP
   6  *
   7  * Harninder Rai <harninder.rai@nxp.com>
   8  *
   9  */
  10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "fsl,ls1088a";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 crypto = &crypto;
  22                 rtc1 = &ftm_alarm0;
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 /* We have 2 clusters having 4 Cortex-A53 cores each */
  30                 cpu0: cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a53";
  33                         reg = <0x0>;
  34                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  35                         cpu-idle-states = <&CPU_PH20>;
  36                         #cooling-cells = <2>;
  37                 };
  38
  39                 cpu1: cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53";
  42                         reg = <0x1>;
  43                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  44                         cpu-idle-states = <&CPU_PH20>;
  45                         #cooling-cells = <2>;
  46                 };
  47
  48                 cpu2: cpu@2 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53";
  51                         reg = <0x2>;
  52                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  53                         cpu-idle-states = <&CPU_PH20>;
  54                         #cooling-cells = <2>;
  55                 };
  56
  57                 cpu3: cpu@3 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a53";
  60                         reg = <0x3>;
  61                         clocks = <&clockgen QORIQ_CLK_CMUX 0>;
  62                         cpu-idle-states = <&CPU_PH20>;
  63                         #cooling-cells = <2>;
  64                 };
  65
  66                 cpu4: cpu@100 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a53";
  69                         reg = <0x100>;
  70                         clocks = <&clockgen QORIQ_CLK_CMUX 1>;
  71                         cpu-idle-states = <&CPU_PH20>;
  72                         #cooling-cells = <2>;
  73                 };
  74
  75                 cpu5: cpu@101 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a53";
  78                         reg = <0x101>;
  79                         clocks = <&clockgen QORIQ_CLK_CMUX 1>;
  80                         cpu-idle-states = <&CPU_PH20>;
  81                         #cooling-cells = <2>;
  82                 };
  83
  84                 cpu6: cpu@102 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a53";
  87                         reg = <0x102>;
  88                         clocks = <&clockgen QORIQ_CLK_CMUX 1>;
  89                         cpu-idle-states = <&CPU_PH20>;
  90                         #cooling-cells = <2>;
  91                 };
  92
  93                 cpu7: cpu@103 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53";
  96                         reg = <0x103>;
  97                         clocks = <&clockgen QORIQ_CLK_CMUX 1>;
  98                         cpu-idle-states = <&CPU_PH20>;
  99                         #cooling-cells = <2>;
 100                 };
 101
 102                 CPU_PH20: cpu-ph20 {
 103                         compatible = "arm,idle-state";
 104                         idle-state-name = "PH20";
 105                         arm,psci-suspend-param = <0x0>;
 106                         entry-latency-us = <1000>;
 107                         exit-latency-us = <1000>;
 108                         min-residency-us = <3000>;
 109                 };
 110         };
 111
 112         gic: interrupt-controller@6000000 {
 113                 compatible = "arm,gic-v3";
 114                 #interrupt-cells = <3>;
 115                 interrupt-controller;
 116                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 117                       <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
 118                       <0x0 0x0c0c0000 0 0x2000>, /* GICC */
 119                       <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 120                       <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 121                 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
 122                 #address-cells = <2>;
 123                 #size-cells = <2>;
 124                 ranges;
 125
 126                 its: msi-controller@6020000 {
 127                         compatible = "arm,gic-v3-its";
 128                         msi-controller;
 129                         reg = <0x0 0x6020000 0 0x20000>;
 130                 };
 131         };
 132
 133         thermal-zones {
 134                 core-cluster {
 135                         polling-delay-passive = <1000>;
 136                         polling-delay = <5000>;
 137                         thermal-sensors = <&tmu 0>;
 138
 139                         trips {
 140                                 core_cluster_alert: core-cluster-alert {
 141                                         temperature = <85000>;
 142                                         hysteresis = <2000>;
 143                                         type = "passive";
 144                                 };
 145
 146                                 core-cluster-crit {
 147                                         temperature = <95000>;
 148                                         hysteresis = <2000>;
 149                                         type = "critical";
 150                                 };
 151                         };
 152
 153                         cooling-maps {
 154                                 map0 {
 155                                         trip = <&core_cluster_alert>;
 156                                         cooling-device =
 157                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 158                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 159                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 160                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 161                                                 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 162                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 163                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 164                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 165                                 };
 166                         };
 167                 };
 168
 169                 soc {
 170                         polling-delay-passive = <1000>;
 171                         polling-delay = <5000>;
 172                         thermal-sensors = <&tmu 1>;
 173
 174                         trips {
 175                                 soc-crit {
 176                                         temperature = <95000>;
 177                                         hysteresis = <2000>;
 178                                         type = "critical";
 179                                 };
 180                         };
 181                 };
 182         };
 183
 184         timer {
 185                 compatible = "arm,armv8-timer";
 186                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
 187                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
 188                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
 189                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
 190         };
 191
 192         pmu {
 193                 compatible = "arm,cortex-a53-pmu";
 194                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 195         };
 196
 197         psci {
 198                 compatible = "arm,psci-0.2";
 199                 method = "smc";
 200         };
 201
 202         sysclk: sysclk {
 203                 compatible = "fixed-clock";
 204                 #clock-cells = <0>;
 205                 clock-frequency = <100000000>;
 206                 clock-output-names = "sysclk";
 207         };
 208
 209         reboot {
 210                 compatible = "syscon-reboot";
 211                 regmap = <&reset>;
 212                 offset = <0x0>;
 213                 mask = <0x02>;
 214         };
 215
 216         soc {
 217                 compatible = "simple-bus";
 218                 #address-cells = <2>;
 219                 #size-cells = <2>;
 220                 ranges;
 221                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
 222
 223                 clockgen: clocking@1300000 {
 224                         compatible = "fsl,ls1088a-clockgen";
 225                         reg = <0 0x1300000 0 0xa0000>;
 226                         #clock-cells = <2>;
 227                         clocks = <&sysclk>;
 228                 };
 229
 230                 dcfg: dcfg@1e00000 {
 231                         compatible = "fsl,ls1088a-dcfg", "syscon";
 232                         reg = <0x0 0x1e00000 0x0 0x10000>;
 233                         little-endian;
 234                 };
 235
 236                 reset: syscon@1e60000 {
 237                         compatible = "fsl,ls1088a-reset", "syscon";
 238                         reg = <0x0 0x1e60000 0x0 0x10000>;
 239                 };
 240
 241                 isc: syscon@1f70000 {
 242                         compatible = "fsl,ls1088a-isc", "syscon";
 243                         reg = <0x0 0x1f70000 0x0 0x10000>;
 244                         little-endian;
 245                         #address-cells = <1>;
 246                         #size-cells = <1>;
 247                         ranges = <0x0 0x0 0x1f70000 0x10000>;
 248
 249                         extirq: interrupt-controller@14 {
 250                                 compatible = "fsl,ls1088a-extirq";
 251                                 #interrupt-cells = <2>;
 252                                 #address-cells = <0>;
 253                                 interrupt-controller;
 254                                 reg = <0x14 4>;
 255                                 interrupt-map =
 256                                         <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 257                                         <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 258                                         <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 259                                         <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 260                                         <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 261                                         <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 262                                         <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 263                                         <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 264                                         <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 265                                         <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 266                                         <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 267                                         <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 268                                 interrupt-map-mask = <0xf 0x0>;
 269                         };
 270                 };
 271
 272                 sfp: efuse@1e80000 {
 273                         compatible = "fsl,ls1028a-sfp";
 274                         reg = <0x0 0x1e80000 0x0 0x10000>;
 275                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 276                                             QORIQ_CLK_PLL_DIV(4)>;
 277                         clock-names = "sfp";
 278                 };
 279
 280                 tmu: tmu@1f80000 {
 281                         compatible = "fsl,qoriq-tmu";
 282                         reg = <0x0 0x1f80000 0x0 0x10000>;
 283                         interrupts = <0 23 0x4>;
 284                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
 285                         fsl,tmu-calibration =
 286                                 /* Calibration data group 1 */
 287                                 <0x00000000 0x00000023>,
 288                                 <0x00000001 0x0000002a>,
 289                                 <0x00000002 0x00000030>,
 290                                 <0x00000003 0x00000037>,
 291                                 <0x00000004 0x0000003d>,
 292                                 <0x00000005 0x00000044>,
 293                                 <0x00000006 0x0000004a>,
 294                                 <0x00000007 0x00000051>,
 295                                 <0x00000008 0x00000057>,
 296                                 <0x00000009 0x0000005e>,
 297                                 <0x0000000a 0x00000064>,
 298                                 <0x0000000b 0x0000006b>,
 299                                 /* Calibration data group 2 */
 300                                 <0x00010000 0x00000022>,
 301                                 <0x00010001 0x0000002a>,
 302                                 <0x00010002 0x00000032>,
 303                                 <0x00010003 0x0000003a>,
 304                                 <0x00010004 0x00000042>,
 305                                 <0x00010005 0x0000004a>,
 306                                 <0x00010006 0x00000052>,
 307                                 <0x00010007 0x0000005a>,
 308                                 <0x00010008 0x00000062>,
 309                                 <0x00010009 0x0000006a>,
 310                                 /* Calibration data group 3 */
 311                                 <0x00020000 0x00000021>,
 312                                 <0x00020001 0x0000002b>,
 313                                 <0x00020002 0x00000035>,
 314                                 <0x00020003 0x00000040>,
 315                                 <0x00020004 0x0000004a>,
 316                                 <0x00020005 0x00000054>,
 317                                 <0x00020006 0x0000005e>,
 318                                 /* Calibration data group 4 */
 319                                 <0x00030000 0x00000010>,
 320                                 <0x00030001 0x0000001c>,
 321                                 <0x00030002 0x00000027>,
 322                                 <0x00030003 0x00000032>,
 323                                 <0x00030004 0x0000003e>,
 324                                 <0x00030005 0x00000049>,
 325                                 <0x00030006 0x00000054>,
 326                                 <0x00030007 0x00000060>;
 327                         little-endian;
 328                         #thermal-sensor-cells = <1>;
 329                 };
 330
 331                 dspi: spi@2100000 {
 332                         compatible = "fsl,ls1088a-dspi",
 333                                      "fsl,ls1021a-v1.0-dspi";
 334                         #address-cells = <1>;
 335                         #size-cells = <0>;
 336                         reg = <0x0 0x2100000 0x0 0x10000>;
 337                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 338                         clock-names = "dspi";
 339                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 340                                             QORIQ_CLK_PLL_DIV(2)>;
 341                         spi-num-chipselects = <6>;
 342                         status = "disabled";
 343                 };
 344
 345                 duart0: serial@21c0500 {
 346                         compatible = "fsl,ns16550", "ns16550a";
 347                         reg = <0x0 0x21c0500 0x0 0x100>;
 348                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 349                                             QORIQ_CLK_PLL_DIV(4)>;
 350                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 351                         status = "disabled";
 352                 };
 353
 354                 duart1: serial@21c0600 {
 355                         compatible = "fsl,ns16550", "ns16550a";
 356                         reg = <0x0 0x21c0600 0x0 0x100>;
 357                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 358                                             QORIQ_CLK_PLL_DIV(4)>;
 359                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 360                         status = "disabled";
 361                 };
 362
 363                 gpio0: gpio@2300000 {
 364                         compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 365                         reg = <0x0 0x2300000 0x0 0x10000>;
 366                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 367                         little-endian;
 368                         gpio-controller;
 369                         #gpio-cells = <2>;
 370                         interrupt-controller;
 371                         #interrupt-cells = <2>;
 372                 };
 373
 374                 gpio1: gpio@2310000 {
 375                         compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 376                         reg = <0x0 0x2310000 0x0 0x10000>;
 377                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 378                         little-endian;
 379                         gpio-controller;
 380                         #gpio-cells = <2>;
 381                         interrupt-controller;
 382                         #interrupt-cells = <2>;
 383                 };
 384
 385                 gpio2: gpio@2320000 {
 386                         compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 387                         reg = <0x0 0x2320000 0x0 0x10000>;
 388                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 389                         little-endian;
 390                         gpio-controller;
 391                         #gpio-cells = <2>;
 392                         interrupt-controller;
 393                         #interrupt-cells = <2>;
 394                 };
 395
 396                 gpio3: gpio@2330000 {
 397                         compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
 398                         reg = <0x0 0x2330000 0x0 0x10000>;
 399                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 400                         little-endian;
 401                         gpio-controller;
 402                         #gpio-cells = <2>;
 403                         interrupt-controller;
 404                         #interrupt-cells = <2>;
 405                 };
 406
 407                 ifc: memory-controller@2240000 {
 408                         compatible = "fsl,ifc";
 409                         reg = <0x0 0x2240000 0x0 0x20000>;
 410                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 411                         little-endian;
 412                         #address-cells = <2>;
 413                         #size-cells = <1>;
 414                         status = "disabled";
 415                 };
 416
 417                 i2c0: i2c@2000000 {
 418                         compatible = "fsl,vf610-i2c";
 419                         #address-cells = <1>;
 420                         #size-cells = <0>;
 421                         reg = <0x0 0x2000000 0x0 0x10000>;
 422                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 423                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 424                                             QORIQ_CLK_PLL_DIV(8)>;
 425                         status = "disabled";
 426                 };
 427
 428                 i2c1: i2c@2010000 {
 429                         compatible = "fsl,vf610-i2c";
 430                         #address-cells = <1>;
 431                         #size-cells = <0>;
 432                         reg = <0x0 0x2010000 0x0 0x10000>;
 433                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 434                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 435                                             QORIQ_CLK_PLL_DIV(8)>;
 436                         status = "disabled";
 437                 };
 438
 439                 i2c2: i2c@2020000 {
 440                         compatible = "fsl,vf610-i2c";
 441                         #address-cells = <1>;
 442                         #size-cells = <0>;
 443                         reg = <0x0 0x2020000 0x0 0x10000>;
 444                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 445                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 446                                             QORIQ_CLK_PLL_DIV(8)>;
 447                         status = "disabled";
 448                 };
 449
 450                 i2c3: i2c@2030000 {
 451                         compatible = "fsl,vf610-i2c";
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         reg = <0x0 0x2030000 0x0 0x10000>;
 455                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 457                                             QORIQ_CLK_PLL_DIV(8)>;
 458                         status = "disabled";
 459                 };
 460
 461                 qspi: spi@20c0000 {
 462                         compatible = "fsl,ls2080a-qspi";
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465                         reg = <0x0 0x20c0000 0x0 0x10000>,
 466                               <0x0 0x20000000 0x0 0x10000000>;
 467                         reg-names = "QuadSPI", "QuadSPI-memory";
 468                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 469                         clock-names = "qspi_en", "qspi";
 470                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 471                                             QORIQ_CLK_PLL_DIV(4)>,
 472                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 473                                             QORIQ_CLK_PLL_DIV(4)>;
 474                         status = "disabled";
 475                 };
 476
 477                 esdhc: esdhc@2140000 {
 478                         compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
 479                         reg = <0x0 0x2140000 0x0 0x10000>;
 480                         interrupts = <0 28 0x4>; /* Level high type */
 481                         clock-frequency = <0>;
 482                         clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
 483                         voltage-ranges = <1800 1800 3300 3300>;
 484                         sdhci,auto-cmd12;
 485                         little-endian;
 486                         bus-width = <4>;
 487                         status = "disabled";
 488                 };
 489
 490                 usb0: usb@3100000 {
 491                         compatible = "snps,dwc3";
 492                         reg = <0x0 0x3100000 0x0 0x10000>;
 493                         interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 494                         dr_mode = "host";
 495                         snps,quirk-frame-length-adjustment = <0x20>;
 496                         snps,dis_rxdet_inp3_quirk;
 497                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 498                         status = "disabled";
 499                 };
 500
 501                 usb1: usb@3110000 {
 502                         compatible = "snps,dwc3";
 503                         reg = <0x0 0x3110000 0x0 0x10000>;
 504                         interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 505                         dr_mode = "host";
 506                         snps,quirk-frame-length-adjustment = <0x20>;
 507                         snps,dis_rxdet_inp3_quirk;
 508                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 509                         status = "disabled";
 510                 };
 511
 512                 sata: sata@3200000 {
 513                         compatible = "fsl,ls1088a-ahci";
 514                         reg = <0x0 0x3200000 0x0 0x10000>,
 515                                 <0x7 0x100520 0x0 0x4>;
 516                         reg-names = "ahci", "sata-ecc";
 517                         interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
 518                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 519                                             QORIQ_CLK_PLL_DIV(4)>;
 520                         dma-coherent;
 521                         status = "disabled";
 522                 };
 523
 524                 crypto: crypto@8000000 {
 525                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 526                         fsl,sec-era = <8>;
 527                         #address-cells = <1>;
 528                         #size-cells = <1>;
 529                         ranges = <0x0 0x00 0x8000000 0x100000>;
 530                         reg = <0x00 0x8000000 0x0 0x100000>;
 531                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 532                         dma-coherent;
 533
 534                         sec_jr0: jr@10000 {
 535                                 compatible = "fsl,sec-v5.0-job-ring",
 536                                              "fsl,sec-v4.0-job-ring";
 537                                 reg = <0x10000 0x10000>;
 538                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 539                         };
 540
 541                         sec_jr1: jr@20000 {
 542                                 compatible = "fsl,sec-v5.0-job-ring",
 543                                              "fsl,sec-v4.0-job-ring";
 544                                 reg = <0x20000 0x10000>;
 545                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 546                         };
 547
 548                         sec_jr2: jr@30000 {
 549                                 compatible = "fsl,sec-v5.0-job-ring",
 550                                              "fsl,sec-v4.0-job-ring";
 551                                 reg = <0x30000 0x10000>;
 552                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 553                         };
 554
 555                         sec_jr3: jr@40000 {
 556                                 compatible = "fsl,sec-v5.0-job-ring",
 557                                              "fsl,sec-v4.0-job-ring";
 558                                 reg = <0x40000 0x10000>;
 559                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 560                         };
 561                 };
 562
 563                 pcie1: pcie@3400000 {
 564                         compatible = "fsl,ls1088a-pcie";
 565                         reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
 566                               <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 567                         reg-names = "regs", "config";
 568                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 569                         interrupt-names = "aer";
 570                         #address-cells = <3>;
 571                         #size-cells = <2>;
 572                         device_type = "pci";
 573                         dma-coherent;
 574                         num-viewport = <256>;
 575                         bus-range = <0x0 0xff>;
 576                         ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
 577                                   0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 578                         msi-parent = <&its>;
 579                         #interrupt-cells = <1>;
 580                         interrupt-map-mask = <0 0 0 7>;
 581                         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
 582                                         <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
 583                                         <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
 584                                         <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
 585                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 586                         status = "disabled";
 587                 };
 588
 589                 pcie_ep1: pcie-ep@3400000 {
 590                         compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
 591                         reg = <0x00 0x03400000 0x0 0x00100000>,
 592                               <0x20 0x00000000 0x8 0x00000000>;
 593                         reg-names = "regs", "addr_space";
 594                         num-ib-windows = <24>;
 595                         num-ob-windows = <256>;
 596                         max-functions = /bits/ 8 <2>;
 597                         status = "disabled";
 598                 };
 599
 600                 pcie2: pcie@3500000 {
 601                         compatible = "fsl,ls1088a-pcie";
 602                         reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
 603                               <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 604                         reg-names = "regs", "config";
 605                         interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 606                         interrupt-names = "aer";
 607                         #address-cells = <3>;
 608                         #size-cells = <2>;
 609                         device_type = "pci";
 610                         dma-coherent;
 611                         num-viewport = <6>;
 612                         bus-range = <0x0 0xff>;
 613                         ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
 614                                   0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 615                         msi-parent = <&its>;
 616                         #interrupt-cells = <1>;
 617                         interrupt-map-mask = <0 0 0 7>;
 618                         interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
 619                                         <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
 620                                         <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
 621                                         <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
 622                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 623                         status = "disabled";
 624                 };
 625
 626                 pcie_ep2: pcie-ep@3500000 {
 627                         compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
 628                         reg = <0x00 0x03500000 0x0 0x00100000>,
 629                               <0x28 0x00000000 0x8 0x00000000>;
 630                         reg-names = "regs", "addr_space";
 631                         num-ib-windows = <6>;
 632                         num-ob-windows = <6>;
 633                         status = "disabled";
 634                 };
 635
 636                 pcie3: pcie@3600000 {
 637                         compatible = "fsl,ls1088a-pcie";
 638                         reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
 639                               <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 640                         reg-names = "regs", "config";
 641                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 642                         interrupt-names = "aer";
 643                         #address-cells = <3>;
 644                         #size-cells = <2>;
 645                         device_type = "pci";
 646                         dma-coherent;
 647                         num-viewport = <6>;
 648                         bus-range = <0x0 0xff>;
 649                         ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
 650                                   0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 651                         msi-parent = <&its>;
 652                         #interrupt-cells = <1>;
 653                         interrupt-map-mask = <0 0 0 7>;
 654                         interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
 655                                         <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
 656                                         <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
 657                                         <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
 658                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 659                         status = "disabled";
 660                 };
 661
 662                 pcie_ep3: pcie-ep@3600000 {
 663                         compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
 664                         reg = <0x00 0x03600000 0x0 0x00100000>,
 665                               <0x30 0x00000000 0x8 0x00000000>;
 666                         reg-names = "regs", "addr_space";
 667                         num-ib-windows = <6>;
 668                         num-ob-windows = <6>;
 669                         status = "disabled";
 670                 };
 671
 672                 smmu: iommu@5000000 {
 673                         compatible = "arm,mmu-500";
 674                         reg = <0 0x5000000 0 0x800000>;
 675                         #iommu-cells = <1>;
 676                         stream-match-mask = <0x7C00>;
 677                         dma-coherent;
 678                         #global-interrupts = <12>;
 679                                      // global secure fault
 680                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 681                                      // combined secure
 682                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 683                                      // global non-secure fault
 684                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 685                                      // combined non-secure
 686                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 687                                      // performance counter interrupts 0-7
 688                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 689                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 690                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 693                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
 695                                      <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 696                                      // per context interrupt, 64 interrupts
 697                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 698                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 699                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 700                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 701                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 702                                      <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 703                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 704                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 706                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 707                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 708                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 709                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 710                                      <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 711                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 712                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 713                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 714                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 715                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 716                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 717                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 718                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 719                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 720                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 721                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 722                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 723                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
 724                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 725                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
 726                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
 727                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 728                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 729                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 730                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 731                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
 732                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 733                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 734                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 735                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 736                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 738                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 739                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 740                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 741                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 742                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 743                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 744                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
 745                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 746                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 748                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 749                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 750                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 752                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 753                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 754                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 755                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 756                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
 757                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 758                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 759                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 760                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 761                 };
 762
 763                 console@8340020 {
 764                         compatible = "fsl,dpaa2-console";
 765                         reg = <0x00000000 0x08340020 0 0x2>;
 766                 };
 767
 768                 ptp-timer@8b95000 {
 769                         compatible = "fsl,dpaa2-ptp";
 770                         reg = <0x0 0x8b95000 0x0 0x100>;
 771                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 772                                             QORIQ_CLK_PLL_DIV(1)>;
 773                         little-endian;
 774                         fsl,extts-fifo;
 775                 };
 776
 777                 emdio1: mdio@8b96000 {
 778                         compatible = "fsl,fman-memac-mdio";
 779                         reg = <0x0 0x8b96000 0x0 0x1000>;
 780                         little-endian;
 781                         #address-cells = <1>;
 782                         #size-cells = <0>;
 783                         clock-frequency = <2500000>;
 784                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 785                                             QORIQ_CLK_PLL_DIV(1)>;
 786                         status = "disabled";
 787                 };
 788
 789                 emdio2: mdio@8b97000 {
 790                         compatible = "fsl,fman-memac-mdio";
 791                         reg = <0x0 0x8b97000 0x0 0x1000>;
 792                         little-endian;
 793                         #address-cells = <1>;
 794                         #size-cells = <0>;
 795                         clock-frequency = <2500000>;
 796                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 797                                             QORIQ_CLK_PLL_DIV(1)>;
 798                         status = "disabled";
 799                 };
 800
 801                 pcs_mdio1: mdio@8c07000 {
 802                         compatible = "fsl,fman-memac-mdio";
 803                         reg = <0x0 0x8c07000 0x0 0x1000>;
 804                         little-endian;
 805                         #address-cells = <1>;
 806                         #size-cells = <0>;
 807                         status = "disabled";
 808
 809                         pcs1: ethernet-phy@0 {
 810                                 reg = <0>;
 811                         };
 812                 };
 813
 814                 pcs_mdio2: mdio@8c0b000 {
 815                         compatible = "fsl,fman-memac-mdio";
 816                         reg = <0x0 0x8c0b000 0x0 0x1000>;
 817                         little-endian;
 818                         #address-cells = <1>;
 819                         #size-cells = <0>;
 820                         status = "disabled";
 821
 822                         pcs2: ethernet-phy@0 {
 823                                 reg = <0>;
 824                         };
 825                 };
 826
 827                 pcs_mdio3: mdio@8c0f000 {
 828                         compatible = "fsl,fman-memac-mdio";
 829                         reg = <0x0 0x8c0f000 0x0 0x1000>;
 830                         little-endian;
 831                         #address-cells = <1>;
 832                         #size-cells = <0>;
 833                         status = "disabled";
 834
 835                         pcs3_0: ethernet-phy@0 {
 836                                 reg = <0>;
 837                         };
 838
 839                         pcs3_1: ethernet-phy@1 {
 840                                 reg = <1>;
 841                         };
 842
 843                         pcs3_2: ethernet-phy@2 {
 844                                 reg = <2>;
 845                         };
 846
 847                         pcs3_3: ethernet-phy@3 {
 848                                 reg = <3>;
 849                         };
 850                 };
 851
 852                 pcs_mdio7: mdio@8c1f000 {
 853                         compatible = "fsl,fman-memac-mdio";
 854                         reg = <0x0 0x8c1f000 0x0 0x1000>;
 855                         little-endian;
 856                         #address-cells = <1>;
 857                         #size-cells = <0>;
 858                         status = "disabled";
 859
 860                         pcs7_0: ethernet-phy@0 {
 861                                 reg = <0>;
 862                         };
 863
 864                         pcs7_1: ethernet-phy@1 {
 865                                 reg = <1>;
 866                         };
 867
 868                         pcs7_2: ethernet-phy@2 {
 869                                 reg = <2>;
 870                         };
 871
 872                         pcs7_3: ethernet-phy@3 {
 873                                 reg = <3>;
 874                         };
 875                 };
 876
 877                 cluster1_core0_watchdog: wdt@c000000 {
 878                         compatible = "arm,sp805", "arm,primecell";
 879                         reg = <0x0 0xc000000 0x0 0x1000>;
 880                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 881                                             QORIQ_CLK_PLL_DIV(16)>,
 882                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 883                                             QORIQ_CLK_PLL_DIV(16)>;
 884                         clock-names = "wdog_clk", "apb_pclk";
 885                 };
 886
 887                 cluster1_core1_watchdog: wdt@c010000 {
 888                         compatible = "arm,sp805", "arm,primecell";
 889                         reg = <0x0 0xc010000 0x0 0x1000>;
 890                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 891                                             QORIQ_CLK_PLL_DIV(16)>,
 892                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 893                                             QORIQ_CLK_PLL_DIV(16)>;
 894                         clock-names = "wdog_clk", "apb_pclk";
 895                 };
 896
 897                 cluster1_core2_watchdog: wdt@c020000 {
 898                         compatible = "arm,sp805", "arm,primecell";
 899                         reg = <0x0 0xc020000 0x0 0x1000>;
 900                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 901                                             QORIQ_CLK_PLL_DIV(16)>,
 902                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 903                                             QORIQ_CLK_PLL_DIV(16)>;
 904                         clock-names = "wdog_clk", "apb_pclk";
 905                 };
 906
 907                 cluster1_core3_watchdog: wdt@c030000 {
 908                         compatible = "arm,sp805", "arm,primecell";
 909                         reg = <0x0 0xc030000 0x0 0x1000>;
 910                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 911                                             QORIQ_CLK_PLL_DIV(16)>,
 912                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 913                                             QORIQ_CLK_PLL_DIV(16)>;
 914                         clock-names = "wdog_clk", "apb_pclk";
 915                 };
 916
 917                 cluster2_core0_watchdog: wdt@c100000 {
 918                         compatible = "arm,sp805", "arm,primecell";
 919                         reg = <0x0 0xc100000 0x0 0x1000>;
 920                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 921                                             QORIQ_CLK_PLL_DIV(16)>,
 922                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 923                                             QORIQ_CLK_PLL_DIV(16)>;
 924                         clock-names = "wdog_clk", "apb_pclk";
 925                 };
 926
 927                 cluster2_core1_watchdog: wdt@c110000 {
 928                         compatible = "arm,sp805", "arm,primecell";
 929                         reg = <0x0 0xc110000 0x0 0x1000>;
 930                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 931                                             QORIQ_CLK_PLL_DIV(16)>,
 932                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 933                                             QORIQ_CLK_PLL_DIV(16)>;
 934                         clock-names = "wdog_clk", "apb_pclk";
 935                 };
 936
 937                 cluster2_core2_watchdog: wdt@c120000 {
 938                         compatible = "arm,sp805", "arm,primecell";
 939                         reg = <0x0 0xc120000 0x0 0x1000>;
 940                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 941                                             QORIQ_CLK_PLL_DIV(16)>,
 942                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 943                                             QORIQ_CLK_PLL_DIV(16)>;
 944                         clock-names = "wdog_clk", "apb_pclk";
 945                 };
 946
 947                 cluster2_core3_watchdog: wdt@c130000 {
 948                         compatible = "arm,sp805", "arm,primecell";
 949                         reg = <0x0 0xc130000 0x0 0x1000>;
 950                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 951                                             QORIQ_CLK_PLL_DIV(16)>,
 952                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 953                                             QORIQ_CLK_PLL_DIV(16)>;
 954                         clock-names = "wdog_clk", "apb_pclk";
 955                 };
 956
 957                 fsl_mc: fsl-mc@80c000000 {
 958                         compatible = "fsl,qoriq-mc";
 959                         reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 960                               <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 961                         msi-parent = <&its>;
 962                         iommu-map = <0 &smmu 0 0>;      /* This is fixed-up by u-boot */
 963                         dma-coherent;
 964                         #address-cells = <3>;
 965                         #size-cells = <1>;
 966
 967                         /*
 968                          * Region type 0x0 - MC portals
 969                          * Region type 0x1 - QBMAN portals
 970                          */
 971                         ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 972                                   0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 973
 974                         dpmacs {
 975                                 #address-cells = <1>;
 976                                 #size-cells = <0>;
 977
 978                                 dpmac1: ethernet@1 {
 979                                         compatible = "fsl,qoriq-mc-dpmac";
 980                                         reg = <1>;
 981                                 };
 982
 983                                 dpmac2: ethernet@2 {
 984                                         compatible = "fsl,qoriq-mc-dpmac";
 985                                         reg = <2>;
 986                                 };
 987
 988                                 dpmac3: ethernet@3 {
 989                                         compatible = "fsl,qoriq-mc-dpmac";
 990                                         reg = <3>;
 991                                 };
 992
 993                                 dpmac4: ethernet@4 {
 994                                         compatible = "fsl,qoriq-mc-dpmac";
 995                                         reg = <4>;
 996                                 };
 997
 998                                 dpmac5: ethernet@5 {
 999                                         compatible = "fsl,qoriq-mc-dpmac";
1000                                         reg = <5>;
1001                                 };
1002
1003                                 dpmac6: ethernet@6 {
1004                                         compatible = "fsl,qoriq-mc-dpmac";
1005                                         reg = <6>;
1006                                 };
1007
1008                                 dpmac7: ethernet@7 {
1009                                         compatible = "fsl,qoriq-mc-dpmac";
1010                                         reg = <7>;
1011                                 };
1012
1013                                 dpmac8: ethernet@8 {
1014                                         compatible = "fsl,qoriq-mc-dpmac";
1015                                         reg = <8>;
1016                                 };
1017
1018                                 dpmac9: ethernet@9 {
1019                                         compatible = "fsl,qoriq-mc-dpmac";
1020                                         reg = <9>;
1021                                 };
1022
1023                                 dpmac10: ethernet@a {
1024                                         compatible = "fsl,qoriq-mc-dpmac";
1025                                         reg = <0xa>;
1026                                 };
1027                         };
1028                 };
1029
1030                 rcpm: power-controller@1e34040 {
1031                         compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
1032                         reg = <0x0 0x1e34040 0x0 0x18>;
1033                         #fsl,rcpm-wakeup-cells = <6>;
1034                         little-endian;
1035                 };
1036
1037                 ftm_alarm0: timer@2800000 {
1038                         compatible = "fsl,ls1088a-ftm-alarm";
1039                         reg = <0x0 0x2800000 0x0 0x10000>;
1040                         fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1041                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1042                 };
1043         };
1044
1045         firmware {
1046                 optee {
1047                         compatible = "linaro,optee-tz";
1048                         method = "smc";
1049                 };
1050         };
1051 };