1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
5 * Copyright 2016 Freescale Semiconductor, Inc.
8 * Mingkai Hu <mingkai.hu@nxp.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "fsl,ls1046a";
16 interrupt-parent = <&gic>;
39 compatible = "arm,cortex-a72";
41 clocks = <&clockgen 1 0>;
42 next-level-cache = <&l2>;
43 cpu-idle-states = <&CPU_PH20>;
49 compatible = "arm,cortex-a72";
51 clocks = <&clockgen 1 0>;
52 next-level-cache = <&l2>;
53 cpu-idle-states = <&CPU_PH20>;
59 compatible = "arm,cortex-a72";
61 clocks = <&clockgen 1 0>;
62 next-level-cache = <&l2>;
63 cpu-idle-states = <&CPU_PH20>;
69 compatible = "arm,cortex-a72";
71 clocks = <&clockgen 1 0>;
72 next-level-cache = <&l2>;
73 cpu-idle-states = <&CPU_PH20>;
84 * PSCI node is not added default, U-boot will add missing
85 * parts if it determines to use PSCI.
87 entry-method = "psci";
90 compatible = "arm,idle-state";
91 idle-state-name = "PH20";
92 arm,psci-suspend-param = <0x0>;
93 entry-latency-us = <1000>;
94 exit-latency-us = <1000>;
95 min-residency-us = <3000>;
100 device_type = "memory";
101 /* Real size will be filled by bootloader */
102 reg = <0x0 0x80000000 0x0 0x0>;
106 compatible = "fixed-clock";
108 clock-frequency = <100000000>;
109 clock-output-names = "sysclk";
113 compatible ="syscon-reboot";
120 cpu_thermal: cpu-thermal {
121 polling-delay-passive = <1000>;
122 polling-delay = <5000>;
123 thermal-sensors = <&tmu 3>;
126 cpu_alert: cpu-alert {
127 temperature = <85000>;
133 temperature = <95000>;
143 <&cpu0 THERMAL_NO_LIMIT
151 compatible = "arm,armv8-timer";
152 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
153 IRQ_TYPE_LEVEL_LOW)>,
154 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
155 IRQ_TYPE_LEVEL_LOW)>,
156 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
157 IRQ_TYPE_LEVEL_LOW)>,
158 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
159 IRQ_TYPE_LEVEL_LOW)>;
163 compatible = "arm,cortex-a72-pmu";
164 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
168 interrupt-affinity = <&cpu0>,
174 gic: interrupt-controller@1400000 {
175 compatible = "arm,gic-400";
176 #interrupt-cells = <3>;
177 interrupt-controller;
178 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
179 <0x0 0x1420000 0 0x20000>, /* GICC */
180 <0x0 0x1440000 0 0x20000>, /* GICH */
181 <0x0 0x1460000 0 0x20000>; /* GICV */
182 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
183 IRQ_TYPE_LEVEL_LOW)>;
187 compatible = "simple-bus";
188 #address-cells = <2>;
192 ddr: memory-controller@1080000 {
193 compatible = "fsl,qoriq-memory-controller";
194 reg = <0x0 0x1080000 0x0 0x1000>;
195 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
200 compatible = "fsl,ifc", "simple-bus";
201 reg = <0x0 0x1530000 0x0 0x10000>;
202 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
206 compatible = "fsl,ls1021a-qspi";
207 #address-cells = <1>;
209 reg = <0x0 0x1550000 0x0 0x10000>,
210 <0x0 0x40000000 0x0 0x10000000>;
211 reg-names = "QuadSPI", "QuadSPI-memory";
212 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
213 clock-names = "qspi_en", "qspi";
214 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
216 fsl,qspi-has-second-chip;
220 esdhc: esdhc@1560000 {
221 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
222 reg = <0x0 0x1560000 0x0 0x10000>;
223 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clockgen 2 1>;
225 voltage-ranges = <1800 1800 3300 3300>;
232 compatible = "fsl,ls1046a-scfg", "syscon";
233 reg = <0x0 0x1570000 0x0 0x10000>;
237 crypto: crypto@1700000 {
238 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
241 #address-cells = <1>;
243 ranges = <0x0 0x00 0x1700000 0x100000>;
244 reg = <0x00 0x1700000 0x0 0x100000>;
245 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
248 compatible = "fsl,sec-v5.4-job-ring",
249 "fsl,sec-v5.0-job-ring",
250 "fsl,sec-v4.0-job-ring";
251 reg = <0x10000 0x10000>;
252 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
256 compatible = "fsl,sec-v5.4-job-ring",
257 "fsl,sec-v5.0-job-ring",
258 "fsl,sec-v4.0-job-ring";
259 reg = <0x20000 0x10000>;
260 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
264 compatible = "fsl,sec-v5.4-job-ring",
265 "fsl,sec-v5.0-job-ring",
266 "fsl,sec-v4.0-job-ring";
267 reg = <0x30000 0x10000>;
268 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
272 compatible = "fsl,sec-v5.4-job-ring",
273 "fsl,sec-v5.0-job-ring",
274 "fsl,sec-v4.0-job-ring";
275 reg = <0x40000 0x10000>;
276 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
281 compatible = "fsl,qman";
282 reg = <0x0 0x1880000 0x0 0x10000>;
283 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
284 memory-region = <&qman_fqd &qman_pfdr>;
289 compatible = "fsl,bman";
290 reg = <0x0 0x1890000 0x0 0x10000>;
291 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
292 memory-region = <&bman_fbpr>;
296 qportals: qman-portals@500000000 {
297 ranges = <0x0 0x5 0x00000000 0x8000000>;
300 bportals: bman-portals@508000000 {
301 ranges = <0x0 0x5 0x08000000 0x8000000>;
305 compatible = "fsl,ls1046a-dcfg", "syscon";
306 reg = <0x0 0x1ee0000 0x0 0x10000>;
310 clockgen: clocking@1ee1000 {
311 compatible = "fsl,ls1046a-clockgen";
312 reg = <0x0 0x1ee1000 0x0 0x1000>;
318 compatible = "fsl,qoriq-tmu";
319 reg = <0x0 0x1f00000 0x0 0x10000>;
320 interrupts = <0 33 0x4>;
321 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
322 fsl,tmu-calibration =
323 /* Calibration data group 1 */
324 <0x00000000 0x00000026
325 0x00000001 0x0000002d
326 0x00000002 0x00000032
327 0x00000003 0x00000039
328 0x00000004 0x0000003f
329 0x00000005 0x00000046
330 0x00000006 0x0000004d
331 0x00000007 0x00000054
332 0x00000008 0x0000005a
333 0x00000009 0x00000061
334 0x0000000a 0x0000006a
335 0x0000000b 0x00000071
336 /* Calibration data group 2 */
337 0x00010000 0x00000025
338 0x00010001 0x0000002c
339 0x00010002 0x00000035
340 0x00010003 0x0000003d
341 0x00010004 0x00000045
342 0x00010005 0x0000004e
343 0x00010006 0x00000057
344 0x00010007 0x00000061
345 0x00010008 0x0000006b
346 0x00010009 0x00000076
347 /* Calibration data group 3 */
348 0x00020000 0x00000029
349 0x00020001 0x00000033
350 0x00020002 0x0000003d
351 0x00020003 0x00000049
352 0x00020004 0x00000056
353 0x00020005 0x00000061
354 0x00020006 0x0000006d
355 /* Calibration data group 4 */
356 0x00030000 0x00000021
357 0x00030001 0x0000002a
358 0x00030002 0x0000003c
359 0x00030003 0x0000004e>;
361 #thermal-sensor-cells = <1>;
365 compatible = "fsl,ls1021a-v1.0-dspi";
366 #address-cells = <1>;
368 reg = <0x0 0x2100000 0x0 0x10000>;
369 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
370 clock-names = "dspi";
371 clocks = <&clockgen 4 1>;
372 spi-num-chipselects = <5>;
378 compatible = "fsl,vf610-i2c";
379 #address-cells = <1>;
381 reg = <0x0 0x2180000 0x0 0x10000>;
382 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&clockgen 4 1>;
384 dmas = <&edma0 1 39>,
386 dma-names = "tx", "rx";
391 compatible = "fsl,vf610-i2c";
392 #address-cells = <1>;
394 reg = <0x0 0x2190000 0x0 0x10000>;
395 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&clockgen 4 1>;
401 compatible = "fsl,vf610-i2c";
402 #address-cells = <1>;
404 reg = <0x0 0x21a0000 0x0 0x10000>;
405 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&clockgen 4 1>;
411 compatible = "fsl,vf610-i2c";
412 #address-cells = <1>;
414 reg = <0x0 0x21b0000 0x0 0x10000>;
415 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&clockgen 4 1>;
420 duart0: serial@21c0500 {
421 compatible = "fsl,ns16550", "ns16550a";
422 reg = <0x00 0x21c0500 0x0 0x100>;
423 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&clockgen 4 1>;
427 duart1: serial@21c0600 {
428 compatible = "fsl,ns16550", "ns16550a";
429 reg = <0x00 0x21c0600 0x0 0x100>;
430 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clockgen 4 1>;
434 duart2: serial@21d0500 {
435 compatible = "fsl,ns16550", "ns16550a";
436 reg = <0x0 0x21d0500 0x0 0x100>;
437 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clockgen 4 1>;
441 duart3: serial@21d0600 {
442 compatible = "fsl,ns16550", "ns16550a";
443 reg = <0x0 0x21d0600 0x0 0x100>;
444 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clockgen 4 1>;
448 gpio0: gpio@2300000 {
449 compatible = "fsl,qoriq-gpio";
450 reg = <0x0 0x2300000 0x0 0x10000>;
451 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
458 gpio1: gpio@2310000 {
459 compatible = "fsl,qoriq-gpio";
460 reg = <0x0 0x2310000 0x0 0x10000>;
461 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
468 gpio2: gpio@2320000 {
469 compatible = "fsl,qoriq-gpio";
470 reg = <0x0 0x2320000 0x0 0x10000>;
471 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-controller;
475 #interrupt-cells = <2>;
478 gpio3: gpio@2330000 {
479 compatible = "fsl,qoriq-gpio";
480 reg = <0x0 0x2330000 0x0 0x10000>;
481 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
484 interrupt-controller;
485 #interrupt-cells = <2>;
488 lpuart0: serial@2950000 {
489 compatible = "fsl,ls1021a-lpuart";
490 reg = <0x0 0x2950000 0x0 0x1000>;
491 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clockgen 4 0>;
497 lpuart1: serial@2960000 {
498 compatible = "fsl,ls1021a-lpuart";
499 reg = <0x0 0x2960000 0x0 0x1000>;
500 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&clockgen 4 1>;
506 lpuart2: serial@2970000 {
507 compatible = "fsl,ls1021a-lpuart";
508 reg = <0x0 0x2970000 0x0 0x1000>;
509 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&clockgen 4 1>;
515 lpuart3: serial@2980000 {
516 compatible = "fsl,ls1021a-lpuart";
517 reg = <0x0 0x2980000 0x0 0x1000>;
518 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&clockgen 4 1>;
524 lpuart4: serial@2990000 {
525 compatible = "fsl,ls1021a-lpuart";
526 reg = <0x0 0x2990000 0x0 0x1000>;
527 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&clockgen 4 1>;
533 lpuart5: serial@29a0000 {
534 compatible = "fsl,ls1021a-lpuart";
535 reg = <0x0 0x29a0000 0x0 0x1000>;
536 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&clockgen 4 1>;
542 wdog0: watchdog@2ad0000 {
543 compatible = "fsl,imx21-wdt";
544 reg = <0x0 0x2ad0000 0x0 0x10000>;
545 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&clockgen 4 1>;
550 edma0: edma@2c00000 {
552 compatible = "fsl,vf610-edma";
553 reg = <0x0 0x2c00000 0x0 0x10000>,
554 <0x0 0x2c10000 0x0 0x10000>,
555 <0x0 0x2c20000 0x0 0x10000>;
556 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
558 interrupt-names = "edma-tx", "edma-err";
561 clock-names = "dmamux0", "dmamux1";
562 clocks = <&clockgen 4 1>,
567 compatible = "snps,dwc3";
568 reg = <0x0 0x2f00000 0x0 0x10000>;
569 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
571 snps,quirk-frame-length-adjustment = <0x20>;
572 snps,dis_rxdet_inp3_quirk;
576 compatible = "snps,dwc3";
577 reg = <0x0 0x3000000 0x0 0x10000>;
578 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
580 snps,quirk-frame-length-adjustment = <0x20>;
581 snps,dis_rxdet_inp3_quirk;
585 compatible = "snps,dwc3";
586 reg = <0x0 0x3100000 0x0 0x10000>;
587 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
589 snps,quirk-frame-length-adjustment = <0x20>;
590 snps,dis_rxdet_inp3_quirk;
594 compatible = "fsl,ls1046a-ahci";
595 reg = <0x0 0x3200000 0x0 0x10000>,
596 <0x0 0x20140520 0x0 0x4>;
597 reg-names = "ahci", "sata-ecc";
598 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&clockgen 4 1>;
602 msi1: msi-controller@1580000 {
603 compatible = "fsl,ls1046a-msi";
605 reg = <0x0 0x1580000 0x0 0x10000>;
606 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
612 msi2: msi-controller@1590000 {
613 compatible = "fsl,ls1046a-msi";
615 reg = <0x0 0x1590000 0x0 0x10000>;
616 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
622 msi3: msi-controller@15a0000 {
623 compatible = "fsl,ls1046a-msi";
625 reg = <0x0 0x15a0000 0x0 0x10000>;
626 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
633 compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
634 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
635 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
636 reg-names = "regs", "config";
637 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
638 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
639 interrupt-names = "aer", "pme";
640 #address-cells = <3>;
645 bus-range = <0x0 0xff>;
646 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
647 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
648 msi-parent = <&msi1>, <&msi2>, <&msi3>;
649 #interrupt-cells = <1>;
650 interrupt-map-mask = <0 0 0 7>;
651 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
652 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
653 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
654 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
658 compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
659 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
660 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
661 reg-names = "regs", "config";
662 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
663 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
664 interrupt-names = "aer", "pme";
665 #address-cells = <3>;
670 bus-range = <0x0 0xff>;
671 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
672 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
673 msi-parent = <&msi2>, <&msi3>, <&msi1>;
674 #interrupt-cells = <1>;
675 interrupt-map-mask = <0 0 0 7>;
676 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
677 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
678 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
679 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
683 compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
684 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
685 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
686 reg-names = "regs", "config";
687 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
688 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
689 interrupt-names = "aer", "pme";
690 #address-cells = <3>;
695 bus-range = <0x0 0xff>;
696 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
697 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
698 msi-parent = <&msi3>, <&msi1>, <&msi2>;
699 #interrupt-cells = <1>;
700 interrupt-map-mask = <0 0 0 7>;
701 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
702 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
703 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
704 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
710 #address-cells = <2>;
714 bman_fbpr: bman-fbpr {
715 compatible = "shared-dma-pool";
716 size = <0 0x1000000>;
717 alignment = <0 0x1000000>;
722 compatible = "shared-dma-pool";
724 alignment = <0 0x800000>;
728 qman_pfdr: qman-pfdr {
729 compatible = "shared-dma-pool";
730 size = <0 0x2000000>;
731 alignment = <0 0x2000000>;
738 compatible = "linaro,optee-tz";
744 #include "qoriq-qman-portals.dtsi"
745 #include "qoriq-bman-portals.dtsi"