2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * Copyright 2014-2015, Freescale Semiconductor
6 * Mingkai Hu <Mingkai.hu@freescale.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
48 compatible = "fsl,ls1043a";
49 interrupt-parent = <&gic>;
58 * We expect the enable-method for cpu's to be "psci", but this
59 * is dependent on the SoC FW, which will fill this in.
61 * Currently supported enable-method is psci v0.2
65 compatible = "arm,cortex-a53";
67 clocks = <&clockgen 1 0>;
68 next-level-cache = <&l2>;
73 compatible = "arm,cortex-a53";
75 clocks = <&clockgen 1 0>;
76 next-level-cache = <&l2>;
81 compatible = "arm,cortex-a53";
83 clocks = <&clockgen 1 0>;
84 next-level-cache = <&l2>;
89 compatible = "arm,cortex-a53";
91 clocks = <&clockgen 1 0>;
92 next-level-cache = <&l2>;
101 device_type = "memory";
102 reg = <0x0 0x80000000 0 0x80000000>;
103 /* DRAM space 1, size: 2GiB DRAM */
107 compatible = "fixed-clock";
109 clock-frequency = <100000000>;
110 clock-output-names = "sysclk";
114 compatible ="syscon-reboot";
121 compatible = "arm,armv8-timer";
122 interrupts = <1 13 0x1>, /* Physical Secure PPI */
123 <1 14 0x1>, /* Physical Non-Secure PPI */
124 <1 11 0x1>, /* Virtual PPI */
125 <1 10 0x1>; /* Hypervisor PPI */
129 compatible = "arm,armv8-pmuv3";
130 interrupts = <0 106 0x4>,
134 interrupt-affinity = <&cpu0>,
140 gic: interrupt-controller@1400000 {
141 compatible = "arm,gic-400";
142 #interrupt-cells = <3>;
143 interrupt-controller;
144 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
145 <0x0 0x1402000 0 0x2000>, /* GICC */
146 <0x0 0x1404000 0 0x2000>, /* GICH */
147 <0x0 0x1406000 0 0x2000>; /* GICV */
148 interrupts = <1 9 0xf08>;
152 compatible = "simple-bus";
153 #address-cells = <2>;
157 clockgen: clocking@1ee1000 {
158 compatible = "fsl,ls1043a-clockgen";
159 reg = <0x0 0x1ee1000 0x0 0x1000>;
165 compatible = "fsl,ls1043a-scfg", "syscon";
166 reg = <0x0 0x1570000 0x0 0x10000>;
171 compatible = "fsl,ls1043a-dcfg", "syscon";
172 reg = <0x0 0x1ee0000 0x0 0x10000>;
177 compatible = "fsl,ifc", "simple-bus";
178 reg = <0x0 0x1530000 0x0 0x10000>;
179 interrupts = <0 43 0x4>;
182 qspi: quadspi@1550000 {
183 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
184 #address-cells = <1>;
186 reg = <0x0 0x1550000 0x0 0x10000>,
187 <0x0 0x40000000 0x0 0x4000000>;
188 reg-names = "QuadSPI", "QuadSPI-memory";
189 interrupts = <0 99 0x4>;
190 clock-names = "qspi_en", "qspi";
191 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
196 esdhc: esdhc@1560000 {
197 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
198 reg = <0x0 0x1560000 0x0 0x10000>;
199 interrupts = <0 62 0x4>;
200 clock-frequency = <0>;
201 voltage-ranges = <1800 1800 3300 3300>;
207 dspi0: dspi@2100000 {
208 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
209 #address-cells = <1>;
211 reg = <0x0 0x2100000 0x0 0x10000>;
212 interrupts = <0 64 0x4>;
213 clock-names = "dspi";
214 clocks = <&clockgen 4 0>;
215 spi-num-chipselects = <5>;
220 dspi1: dspi@2110000 {
221 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
222 #address-cells = <1>;
224 reg = <0x0 0x2110000 0x0 0x10000>;
225 interrupts = <0 65 0x4>;
226 clock-names = "dspi";
227 clocks = <&clockgen 4 0>;
228 spi-num-chipselects = <5>;
234 compatible = "fsl,vf610-i2c";
235 #address-cells = <1>;
237 reg = <0x0 0x2180000 0x0 0x10000>;
238 interrupts = <0 56 0x4>;
240 clocks = <&clockgen 4 0>;
241 dmas = <&edma0 1 39>,
243 dma-names = "tx", "rx";
248 compatible = "fsl,vf610-i2c";
249 #address-cells = <1>;
251 reg = <0x0 0x2190000 0x0 0x10000>;
252 interrupts = <0 57 0x4>;
254 clocks = <&clockgen 4 0>;
259 compatible = "fsl,vf610-i2c";
260 #address-cells = <1>;
262 reg = <0x0 0x21a0000 0x0 0x10000>;
263 interrupts = <0 58 0x4>;
265 clocks = <&clockgen 4 0>;
270 compatible = "fsl,vf610-i2c";
271 #address-cells = <1>;
273 reg = <0x0 0x21b0000 0x0 0x10000>;
274 interrupts = <0 59 0x4>;
276 clocks = <&clockgen 4 0>;
280 duart0: serial@21c0500 {
281 compatible = "fsl,ns16550", "ns16550a";
282 reg = <0x00 0x21c0500 0x0 0x100>;
283 interrupts = <0 54 0x4>;
284 clocks = <&clockgen 4 0>;
287 duart1: serial@21c0600 {
288 compatible = "fsl,ns16550", "ns16550a";
289 reg = <0x00 0x21c0600 0x0 0x100>;
290 interrupts = <0 54 0x4>;
291 clocks = <&clockgen 4 0>;
294 duart2: serial@21d0500 {
295 compatible = "fsl,ns16550", "ns16550a";
296 reg = <0x0 0x21d0500 0x0 0x100>;
297 interrupts = <0 55 0x4>;
298 clocks = <&clockgen 4 0>;
301 duart3: serial@21d0600 {
302 compatible = "fsl,ns16550", "ns16550a";
303 reg = <0x0 0x21d0600 0x0 0x100>;
304 interrupts = <0 55 0x4>;
305 clocks = <&clockgen 4 0>;
308 gpio1: gpio@2300000 {
309 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
310 reg = <0x0 0x2300000 0x0 0x10000>;
311 interrupts = <0 66 0x4>;
314 interrupt-controller;
315 #interrupt-cells = <2>;
318 gpio2: gpio@2310000 {
319 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
320 reg = <0x0 0x2310000 0x0 0x10000>;
321 interrupts = <0 67 0x4>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
328 gpio3: gpio@2320000 {
329 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
330 reg = <0x0 0x2320000 0x0 0x10000>;
331 interrupts = <0 68 0x4>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
338 gpio4: gpio@2330000 {
339 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
340 reg = <0x0 0x2330000 0x0 0x10000>;
341 interrupts = <0 134 0x4>;
344 interrupt-controller;
345 #interrupt-cells = <2>;
348 lpuart0: serial@2950000 {
349 compatible = "fsl,ls1021a-lpuart";
350 reg = <0x0 0x2950000 0x0 0x1000>;
351 interrupts = <0 48 0x4>;
352 clocks = <&clockgen 0 0>;
357 lpuart1: serial@2960000 {
358 compatible = "fsl,ls1021a-lpuart";
359 reg = <0x0 0x2960000 0x0 0x1000>;
360 interrupts = <0 49 0x4>;
361 clocks = <&clockgen 4 0>;
366 lpuart2: serial@2970000 {
367 compatible = "fsl,ls1021a-lpuart";
368 reg = <0x0 0x2970000 0x0 0x1000>;
369 interrupts = <0 50 0x4>;
370 clocks = <&clockgen 4 0>;
375 lpuart3: serial@2980000 {
376 compatible = "fsl,ls1021a-lpuart";
377 reg = <0x0 0x2980000 0x0 0x1000>;
378 interrupts = <0 51 0x4>;
379 clocks = <&clockgen 4 0>;
384 lpuart4: serial@2990000 {
385 compatible = "fsl,ls1021a-lpuart";
386 reg = <0x0 0x2990000 0x0 0x1000>;
387 interrupts = <0 52 0x4>;
388 clocks = <&clockgen 4 0>;
393 lpuart5: serial@29a0000 {
394 compatible = "fsl,ls1021a-lpuart";
395 reg = <0x0 0x29a0000 0x0 0x1000>;
396 interrupts = <0 53 0x4>;
397 clocks = <&clockgen 4 0>;
402 wdog0: wdog@2ad0000 {
403 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
404 reg = <0x0 0x2ad0000 0x0 0x10000>;
405 interrupts = <0 83 0x4>;
406 clocks = <&clockgen 4 0>;
407 clock-names = "wdog";
411 edma0: edma@2c00000 {
413 compatible = "fsl,vf610-edma";
414 reg = <0x0 0x2c00000 0x0 0x10000>,
415 <0x0 0x2c10000 0x0 0x10000>,
416 <0x0 0x2c20000 0x0 0x10000>;
417 interrupts = <0 103 0x4>,
419 interrupt-names = "edma-tx", "edma-err";
422 clock-names = "dmamux0", "dmamux1";
423 clocks = <&clockgen 4 0>,
428 compatible = "snps,dwc3";
429 reg = <0x0 0x2f00000 0x0 0x10000>;
430 interrupts = <0 60 0x4>;
432 snps,quirk-frame-length-adjustment = <0x20>;
433 snps,dis_rxdet_inp3_quirk;
437 compatible = "snps,dwc3";
438 reg = <0x0 0x3000000 0x0 0x10000>;
439 interrupts = <0 61 0x4>;
441 snps,quirk-frame-length-adjustment = <0x20>;
442 snps,dis_rxdet_inp3_quirk;
446 compatible = "snps,dwc3";
447 reg = <0x0 0x3100000 0x0 0x10000>;
448 interrupts = <0 63 0x4>;
450 snps,quirk-frame-length-adjustment = <0x20>;
451 snps,dis_rxdet_inp3_quirk;
455 compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
456 reg = <0x0 0x3200000 0x0 0x10000>;
457 interrupts = <0 69 0x4>;
458 clocks = <&clockgen 4 0>;
461 msi1: msi-controller1@1571000 {
462 compatible = "fsl,1s1043a-msi";
463 reg = <0x0 0x1571000 0x0 0x8>;
465 interrupts = <0 116 0x4>;
468 msi2: msi-controller2@1572000 {
469 compatible = "fsl,1s1043a-msi";
470 reg = <0x0 0x1572000 0x0 0x8>;
472 interrupts = <0 126 0x4>;
475 msi3: msi-controller3@1573000 {
476 compatible = "fsl,1s1043a-msi";
477 reg = <0x0 0x1573000 0x0 0x8>;
479 interrupts = <0 160 0x4>;
483 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
484 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
485 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
486 reg-names = "regs", "config";
487 interrupts = <0 118 0x4>, /* controller interrupt */
488 <0 117 0x4>; /* PME interrupt */
489 interrupt-names = "intr", "pme";
490 #address-cells = <3>;
495 bus-range = <0x0 0xff>;
496 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
497 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
498 msi-parent = <&msi1>;
499 #interrupt-cells = <1>;
500 interrupt-map-mask = <0 0 0 7>;
501 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
502 <0000 0 0 2 &gic 0 111 0x4>,
503 <0000 0 0 3 &gic 0 112 0x4>,
504 <0000 0 0 4 &gic 0 113 0x4>;
508 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
509 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
510 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
511 reg-names = "regs", "config";
512 interrupts = <0 128 0x4>,
514 interrupt-names = "intr", "pme";
515 #address-cells = <3>;
520 bus-range = <0x0 0xff>;
521 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
522 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
523 msi-parent = <&msi2>;
524 #interrupt-cells = <1>;
525 interrupt-map-mask = <0 0 0 7>;
526 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
527 <0000 0 0 2 &gic 0 121 0x4>,
528 <0000 0 0 3 &gic 0 122 0x4>,
529 <0000 0 0 4 &gic 0 123 0x4>;
533 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
534 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
535 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
536 reg-names = "regs", "config";
537 interrupts = <0 162 0x4>,
539 interrupt-names = "intr", "pme";
540 #address-cells = <3>;
545 bus-range = <0x0 0xff>;
546 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
547 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
548 msi-parent = <&msi3>;
549 #interrupt-cells = <1>;
550 interrupt-map-mask = <0 0 0 7>;
551 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
552 <0000 0 0 2 &gic 0 155 0x4>,
553 <0000 0 0 3 &gic 0 156 0x4>,
554 <0000 0 0 4 &gic 0 157 0x4>;