2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * Copyright 2014-2015, Freescale Semiconductor
6 * Mingkai Hu <Mingkai.hu@freescale.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
48 compatible = "fsl,ls1043a";
49 interrupt-parent = <&gic>;
58 * We expect the enable-method for cpu's to be "psci", but this
59 * is dependent on the SoC FW, which will fill this in.
61 * Currently supported enable-method is psci v0.2
65 compatible = "arm,cortex-a53";
67 clocks = <&clockgen 1 0>;
72 compatible = "arm,cortex-a53";
74 clocks = <&clockgen 1 0>;
79 compatible = "arm,cortex-a53";
81 clocks = <&clockgen 1 0>;
86 compatible = "arm,cortex-a53";
88 clocks = <&clockgen 1 0>;
93 device_type = "memory";
94 reg = <0x0 0x80000000 0 0x80000000>;
95 /* DRAM space 1, size: 2GiB DRAM */
99 compatible = "fixed-clock";
101 clock-frequency = <100000000>;
102 clock-output-names = "sysclk";
106 compatible ="syscon-reboot";
113 compatible = "arm,armv8-timer";
114 interrupts = <1 13 0x1>, /* Physical Secure PPI */
115 <1 14 0x1>, /* Physical Non-Secure PPI */
116 <1 11 0x1>, /* Virtual PPI */
117 <1 10 0x1>; /* Hypervisor PPI */
121 compatible = "arm,armv8-pmuv3";
122 interrupts = <0 106 0x4>,
126 interrupt-affinity = <&cpu0>,
132 gic: interrupt-controller@1400000 {
133 compatible = "arm,gic-400";
134 #interrupt-cells = <3>;
135 interrupt-controller;
136 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
137 <0x0 0x1402000 0 0x2000>, /* GICC */
138 <0x0 0x1404000 0 0x2000>, /* GICH */
139 <0x0 0x1406000 0 0x2000>; /* GICV */
140 interrupts = <1 9 0xf08>;
144 compatible = "simple-bus";
145 #address-cells = <2>;
149 clockgen: clocking@1ee1000 {
150 compatible = "fsl,ls1043a-clockgen";
151 reg = <0x0 0x1ee1000 0x0 0x1000>;
157 compatible = "fsl,ls1043a-scfg", "syscon";
158 reg = <0x0 0x1570000 0x0 0x10000>;
163 compatible = "fsl,ls1043a-dcfg", "syscon";
164 reg = <0x0 0x1ee0000 0x0 0x10000>;
169 compatible = "fsl,ifc", "simple-bus";
170 reg = <0x0 0x1530000 0x0 0x10000>;
171 interrupts = <0 43 0x4>;
174 qspi: quadspi@1550000 {
175 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
176 #address-cells = <1>;
178 reg = <0x0 0x1550000 0x0 0x10000>,
179 <0x0 0x40000000 0x0 0x4000000>;
180 reg-names = "QuadSPI", "QuadSPI-memory";
181 interrupts = <0 99 0x4>;
182 clock-names = "qspi_en", "qspi";
183 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
188 esdhc: esdhc@1560000 {
189 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
190 reg = <0x0 0x1560000 0x0 0x10000>;
191 interrupts = <0 62 0x4>;
192 clock-frequency = <0>;
193 voltage-ranges = <1800 1800 3300 3300>;
199 dspi0: dspi@2100000 {
200 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
201 #address-cells = <1>;
203 reg = <0x0 0x2100000 0x0 0x10000>;
204 interrupts = <0 64 0x4>;
205 clock-names = "dspi";
206 clocks = <&clockgen 4 0>;
207 spi-num-chipselects = <5>;
212 dspi1: dspi@2110000 {
213 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
214 #address-cells = <1>;
216 reg = <0x0 0x2110000 0x0 0x10000>;
217 interrupts = <0 65 0x4>;
218 clock-names = "dspi";
219 clocks = <&clockgen 4 0>;
220 spi-num-chipselects = <5>;
226 compatible = "fsl,vf610-i2c";
227 #address-cells = <1>;
229 reg = <0x0 0x2180000 0x0 0x10000>;
230 interrupts = <0 56 0x4>;
232 clocks = <&clockgen 4 0>;
233 dmas = <&edma0 1 39>,
235 dma-names = "tx", "rx";
240 compatible = "fsl,vf610-i2c";
241 #address-cells = <1>;
243 reg = <0x0 0x2190000 0x0 0x10000>;
244 interrupts = <0 57 0x4>;
246 clocks = <&clockgen 4 0>;
251 compatible = "fsl,vf610-i2c";
252 #address-cells = <1>;
254 reg = <0x0 0x21a0000 0x0 0x10000>;
255 interrupts = <0 58 0x4>;
257 clocks = <&clockgen 4 0>;
262 compatible = "fsl,vf610-i2c";
263 #address-cells = <1>;
265 reg = <0x0 0x21b0000 0x0 0x10000>;
266 interrupts = <0 59 0x4>;
268 clocks = <&clockgen 4 0>;
272 duart0: serial@21c0500 {
273 compatible = "fsl,ns16550", "ns16550a";
274 reg = <0x00 0x21c0500 0x0 0x100>;
275 interrupts = <0 54 0x4>;
276 clocks = <&clockgen 4 0>;
279 duart1: serial@21c0600 {
280 compatible = "fsl,ns16550", "ns16550a";
281 reg = <0x00 0x21c0600 0x0 0x100>;
282 interrupts = <0 54 0x4>;
283 clocks = <&clockgen 4 0>;
286 duart2: serial@21d0500 {
287 compatible = "fsl,ns16550", "ns16550a";
288 reg = <0x0 0x21d0500 0x0 0x100>;
289 interrupts = <0 55 0x4>;
290 clocks = <&clockgen 4 0>;
293 duart3: serial@21d0600 {
294 compatible = "fsl,ns16550", "ns16550a";
295 reg = <0x0 0x21d0600 0x0 0x100>;
296 interrupts = <0 55 0x4>;
297 clocks = <&clockgen 4 0>;
300 gpio1: gpio@2300000 {
301 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
302 reg = <0x0 0x2300000 0x0 0x10000>;
303 interrupts = <0 66 0x4>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
310 gpio2: gpio@2310000 {
311 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
312 reg = <0x0 0x2310000 0x0 0x10000>;
313 interrupts = <0 67 0x4>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
320 gpio3: gpio@2320000 {
321 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
322 reg = <0x0 0x2320000 0x0 0x10000>;
323 interrupts = <0 68 0x4>;
326 interrupt-controller;
327 #interrupt-cells = <2>;
330 gpio4: gpio@2330000 {
331 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
332 reg = <0x0 0x2330000 0x0 0x10000>;
333 interrupts = <0 134 0x4>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
340 lpuart0: serial@2950000 {
341 compatible = "fsl,ls1021a-lpuart";
342 reg = <0x0 0x2950000 0x0 0x1000>;
343 interrupts = <0 48 0x4>;
344 clocks = <&clockgen 0 0>;
349 lpuart1: serial@2960000 {
350 compatible = "fsl,ls1021a-lpuart";
351 reg = <0x0 0x2960000 0x0 0x1000>;
352 interrupts = <0 49 0x4>;
353 clocks = <&clockgen 4 0>;
358 lpuart2: serial@2970000 {
359 compatible = "fsl,ls1021a-lpuart";
360 reg = <0x0 0x2970000 0x0 0x1000>;
361 interrupts = <0 50 0x4>;
362 clocks = <&clockgen 4 0>;
367 lpuart3: serial@2980000 {
368 compatible = "fsl,ls1021a-lpuart";
369 reg = <0x0 0x2980000 0x0 0x1000>;
370 interrupts = <0 51 0x4>;
371 clocks = <&clockgen 4 0>;
376 lpuart4: serial@2990000 {
377 compatible = "fsl,ls1021a-lpuart";
378 reg = <0x0 0x2990000 0x0 0x1000>;
379 interrupts = <0 52 0x4>;
380 clocks = <&clockgen 4 0>;
385 lpuart5: serial@29a0000 {
386 compatible = "fsl,ls1021a-lpuart";
387 reg = <0x0 0x29a0000 0x0 0x1000>;
388 interrupts = <0 53 0x4>;
389 clocks = <&clockgen 4 0>;
394 wdog0: wdog@2ad0000 {
395 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
396 reg = <0x0 0x2ad0000 0x0 0x10000>;
397 interrupts = <0 83 0x4>;
398 clocks = <&clockgen 4 0>;
399 clock-names = "wdog";
403 edma0: edma@2c00000 {
405 compatible = "fsl,vf610-edma";
406 reg = <0x0 0x2c00000 0x0 0x10000>,
407 <0x0 0x2c10000 0x0 0x10000>,
408 <0x0 0x2c20000 0x0 0x10000>;
409 interrupts = <0 103 0x4>,
411 interrupt-names = "edma-tx", "edma-err";
414 clock-names = "dmamux0", "dmamux1";
415 clocks = <&clockgen 4 0>,
420 compatible = "snps,dwc3";
421 reg = <0x0 0x2f00000 0x0 0x10000>;
422 interrupts = <0 60 0x4>;
424 snps,quirk-frame-length-adjustment = <0x20>;
428 compatible = "snps,dwc3";
429 reg = <0x0 0x3000000 0x0 0x10000>;
430 interrupts = <0 61 0x4>;
432 snps,quirk-frame-length-adjustment = <0x20>;
436 compatible = "snps,dwc3";
437 reg = <0x0 0x3100000 0x0 0x10000>;
438 interrupts = <0 63 0x4>;
440 snps,quirk-frame-length-adjustment = <0x20>;
444 compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
445 reg = <0x0 0x3200000 0x0 0x10000>;
446 interrupts = <0 69 0x4>;
447 clocks = <&clockgen 4 0>;
450 msi1: msi-controller1@1571000 {
451 compatible = "fsl,1s1043a-msi";
452 reg = <0x0 0x1571000 0x0 0x8>;
454 interrupts = <0 116 0x4>;
457 msi2: msi-controller2@1572000 {
458 compatible = "fsl,1s1043a-msi";
459 reg = <0x0 0x1572000 0x0 0x8>;
461 interrupts = <0 126 0x4>;
464 msi3: msi-controller3@1573000 {
465 compatible = "fsl,1s1043a-msi";
466 reg = <0x0 0x1573000 0x0 0x8>;
468 interrupts = <0 160 0x4>;
472 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
473 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
474 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
475 reg-names = "regs", "config";
476 interrupts = <0 118 0x4>, /* controller interrupt */
477 <0 117 0x4>; /* PME interrupt */
478 interrupt-names = "intr", "pme";
479 #address-cells = <3>;
483 bus-range = <0x0 0xff>;
484 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
485 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
486 msi-parent = <&msi1>;
487 #interrupt-cells = <1>;
488 interrupt-map-mask = <0 0 0 7>;
489 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
490 <0000 0 0 2 &gic 0 111 0x4>,
491 <0000 0 0 3 &gic 0 112 0x4>,
492 <0000 0 0 4 &gic 0 113 0x4>;
496 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
497 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
498 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
499 reg-names = "regs", "config";
500 interrupts = <0 128 0x4>,
502 interrupt-names = "intr", "pme";
503 #address-cells = <3>;
507 bus-range = <0x0 0xff>;
508 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
509 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
510 msi-parent = <&msi2>;
511 #interrupt-cells = <1>;
512 interrupt-map-mask = <0 0 0 7>;
513 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
514 <0000 0 0 2 &gic 0 121 0x4>,
515 <0000 0 0 3 &gic 0 122 0x4>,
516 <0000 0 0 4 &gic 0 123 0x4>;
520 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
521 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
522 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
523 reg-names = "regs", "config";
524 interrupts = <0 162 0x4>,
526 interrupt-names = "intr", "pme";
527 #address-cells = <3>;
531 bus-range = <0x0 0xff>;
532 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
533 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
534 msi-parent = <&msi3>;
535 #interrupt-cells = <1>;
536 interrupt-map-mask = <0 0 0 7>;
537 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
538 <0000 0 0 2 &gic 0 155 0x4>,
539 <0000 0 0 3 &gic 0 156 0x4>,
540 <0000 0 0 4 &gic 0 157 0x4>;