2 * Device Tree Include file for Freescale Layerscape-1012A family SoC.
4 * Copyright 2016 Freescale Semiconductor, Inc.
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPLv2 or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
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27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
49 compatible = "fsl,ls1012a";
50 interrupt-parent = <&gic>;
69 compatible = "arm,cortex-a53";
71 clocks = <&clockgen 1 0>;
77 compatible = "fixed-clock";
79 clock-frequency = <125000000>;
80 clock-output-names = "sysclk";
84 compatible = "fixed-clock";
86 clock-frequency = <100000000>;
87 clock-output-names = "coreclk";
91 compatible = "arm,armv8-timer";
92 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
93 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
94 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
95 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
99 compatible = "arm,armv8-pmuv3";
100 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
103 gic: interrupt-controller@1400000 {
104 compatible = "arm,gic-400";
105 #interrupt-cells = <3>;
106 interrupt-controller;
107 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
108 <0x0 0x1402000 0 0x2000>, /* GICC */
109 <0x0 0x1404000 0 0x2000>, /* GICH */
110 <0x0 0x1406000 0 0x2000>; /* GICV */
111 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
115 compatible = "syscon-reboot";
122 compatible = "simple-bus";
123 #address-cells = <2>;
127 esdhc0: esdhc@1560000 {
128 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
129 reg = <0x0 0x1560000 0x0 0x10000>;
130 interrupts = <0 62 0x4>;
131 clocks = <&clockgen 4 0>;
132 voltage-ranges = <1800 1800 3300 3300>;
140 compatible = "fsl,ls1012a-scfg", "syscon";
141 reg = <0x0 0x1570000 0x0 0x10000>;
145 esdhc1: esdhc@1580000 {
146 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
147 reg = <0x0 0x1580000 0x0 0x10000>;
148 interrupts = <0 65 0x4>;
149 clocks = <&clockgen 4 0>;
150 voltage-ranges = <1800 1800 3300 3300>;
158 crypto: crypto@1700000 {
159 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
162 #address-cells = <1>;
164 ranges = <0x0 0x00 0x1700000 0x100000>;
165 reg = <0x00 0x1700000 0x0 0x100000>;
166 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
169 compatible = "fsl,sec-v5.4-job-ring",
170 "fsl,sec-v5.0-job-ring",
171 "fsl,sec-v4.0-job-ring";
172 reg = <0x10000 0x10000>;
173 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
177 compatible = "fsl,sec-v5.4-job-ring",
178 "fsl,sec-v5.0-job-ring",
179 "fsl,sec-v4.0-job-ring";
180 reg = <0x20000 0x10000>;
181 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
185 compatible = "fsl,sec-v5.4-job-ring",
186 "fsl,sec-v5.0-job-ring",
187 "fsl,sec-v4.0-job-ring";
188 reg = <0x30000 0x10000>;
189 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
193 compatible = "fsl,sec-v5.4-job-ring",
194 "fsl,sec-v5.0-job-ring",
195 "fsl,sec-v4.0-job-ring";
196 reg = <0x40000 0x10000>;
197 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
201 compatible = "fsl,sec-v5.4-rtic",
204 #address-cells = <1>;
206 reg = <0x60000 0x100 0x60e00 0x18>;
207 ranges = <0x0 0x60100 0x500>;
210 compatible = "fsl,sec-v5.4-rtic-memory",
211 "fsl,sec-v5.0-rtic-memory",
212 "fsl,sec-v4.0-rtic-memory";
213 reg = <0x00 0x20 0x100 0x100>;
217 compatible = "fsl,sec-v5.4-rtic-memory",
218 "fsl,sec-v5.0-rtic-memory",
219 "fsl,sec-v4.0-rtic-memory";
220 reg = <0x20 0x20 0x200 0x100>;
224 compatible = "fsl,sec-v5.4-rtic-memory",
225 "fsl,sec-v5.0-rtic-memory",
226 "fsl,sec-v4.0-rtic-memory";
227 reg = <0x40 0x20 0x300 0x100>;
231 compatible = "fsl,sec-v5.4-rtic-memory",
232 "fsl,sec-v5.0-rtic-memory",
233 "fsl,sec-v4.0-rtic-memory";
234 reg = <0x60 0x20 0x400 0x100>;
239 sec_mon: sec_mon@1e90000 {
240 compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
242 reg = <0x0 0x1e90000 0x0 0x10000>;
243 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
248 compatible = "fsl,ls1012a-dcfg",
250 reg = <0x0 0x1ee0000 0x0 0x10000>;
254 clockgen: clocking@1ee1000 {
255 compatible = "fsl,ls1012a-clockgen";
256 reg = <0x0 0x1ee1000 0x0 0x1000>;
258 clocks = <&sysclk &coreclk>;
259 clock-names = "sysclk", "coreclk";
263 compatible = "fsl,qoriq-tmu";
264 reg = <0x0 0x1f00000 0x0 0x10000>;
265 interrupts = <0 33 0x4>;
266 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
267 fsl,tmu-calibration = <0x00000000 0x00000026
268 0x00000001 0x0000002d
269 0x00000002 0x00000032
270 0x00000003 0x00000039
271 0x00000004 0x0000003f
272 0x00000005 0x00000046
273 0x00000006 0x0000004d
274 0x00000007 0x00000054
275 0x00000008 0x0000005a
276 0x00000009 0x00000061
277 0x0000000a 0x0000006a
278 0x0000000b 0x00000071
280 0x00010000 0x00000025
281 0x00010001 0x0000002c
282 0x00010002 0x00000035
283 0x00010003 0x0000003d
284 0x00010004 0x00000045
285 0x00010005 0x0000004e
286 0x00010006 0x00000057
287 0x00010007 0x00000061
288 0x00010008 0x0000006b
289 0x00010009 0x00000076
291 0x00020000 0x00000029
292 0x00020001 0x00000033
293 0x00020002 0x0000003d
294 0x00020003 0x00000049
295 0x00020004 0x00000056
296 0x00020005 0x00000061
297 0x00020006 0x0000006d
299 0x00030000 0x00000021
300 0x00030001 0x0000002a
301 0x00030002 0x0000003c
302 0x00030003 0x0000004e>;
304 #thermal-sensor-cells = <1>;
308 cpu_thermal: cpu-thermal {
309 polling-delay-passive = <1000>;
310 polling-delay = <5000>;
311 thermal-sensors = <&tmu 0>;
314 cpu_alert: cpu-alert {
315 temperature = <85000>;
321 temperature = <95000>;
331 <&cpu0 THERMAL_NO_LIMIT
339 compatible = "fsl,vf610-i2c";
340 #address-cells = <1>;
342 reg = <0x0 0x2180000 0x0 0x10000>;
343 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clockgen 4 0>;
349 compatible = "fsl,vf610-i2c";
350 #address-cells = <1>;
352 reg = <0x0 0x2190000 0x0 0x10000>;
353 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&clockgen 4 0>;
358 duart0: serial@21c0500 {
359 compatible = "fsl,ns16550", "ns16550a";
360 reg = <0x00 0x21c0500 0x0 0x100>;
361 interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&clockgen 4 0>;
366 duart1: serial@21c0600 {
367 compatible = "fsl,ns16550", "ns16550a";
368 reg = <0x00 0x21c0600 0x0 0x100>;
369 interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clockgen 4 0>;
374 gpio0: gpio@2300000 {
375 compatible = "fsl,qoriq-gpio";
376 reg = <0x0 0x2300000 0x0 0x10000>;
377 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
384 gpio1: gpio@2310000 {
385 compatible = "fsl,qoriq-gpio";
386 reg = <0x0 0x2310000 0x0 0x10000>;
387 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-controller;
391 #interrupt-cells = <2>;
394 wdog0: wdog@2ad0000 {
395 compatible = "fsl,ls1012a-wdt",
397 reg = <0x0 0x2ad0000 0x0 0x10000>;
398 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&clockgen 4 0>;
404 #sound-dai-cells = <0>;
405 compatible = "fsl,vf610-sai";
406 reg = <0x0 0x2b50000 0x0 0x10000>;
407 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&clockgen 4 3>, <&clockgen 4 3>,
409 <&clockgen 4 3>, <&clockgen 4 3>;
410 clock-names = "bus", "mclk1", "mclk2", "mclk3";
411 dma-names = "tx", "rx";
412 dmas = <&edma0 1 47>,
418 #sound-dai-cells = <0>;
419 compatible = "fsl,vf610-sai";
420 reg = <0x0 0x2b60000 0x0 0x10000>;
421 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&clockgen 4 3>, <&clockgen 4 3>,
423 <&clockgen 4 3>, <&clockgen 4 3>;
424 clock-names = "bus", "mclk1", "mclk2", "mclk3";
425 dma-names = "tx", "rx";
426 dmas = <&edma0 1 45>,
431 edma0: edma@2c00000 {
433 compatible = "fsl,vf610-edma";
434 reg = <0x0 0x2c00000 0x0 0x10000>,
435 <0x0 0x2c10000 0x0 0x10000>,
436 <0x0 0x2c20000 0x0 0x10000>;
437 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
438 <0 103 IRQ_TYPE_LEVEL_HIGH>;
439 interrupt-names = "edma-tx", "edma-err";
442 clock-names = "dmamux0", "dmamux1";
443 clocks = <&clockgen 4 3>,
448 compatible = "snps,dwc3";
449 reg = <0x0 0x2f00000 0x0 0x10000>;
450 interrupts = <0 60 0x4>;
452 snps,quirk-frame-length-adjustment = <0x20>;
453 snps,dis_rxdet_inp3_quirk;
457 compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
458 reg = <0x0 0x3200000 0x0 0x10000>,
459 <0x0 0x20140520 0x0 0x4>;
460 reg-names = "ahci", "sata-ecc";
461 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clockgen 4 0>;
468 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
469 reg = <0x0 0x8600000 0x0 0x1000>;
470 interrupts = <0 139 0x4>;