2 * ARM Ltd. Juno Platform
4 * Copyright (c) 2015 ARM Ltd.
6 * This file is licensed under a dual GPLv2 or BSD license.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "ARM Juno development board (r2)";
15 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
16 interrupt-parent = <&gic>;
25 stdout-path = "serial0:115200n8";
29 compatible = "arm,psci-0.2";
64 entry-method = "arm,psci";
66 CPU_SLEEP_0: cpu-sleep-0 {
67 compatible = "arm,idle-state";
68 arm,psci-suspend-param = <0x0010000>;
70 entry-latency-us = <300>;
71 exit-latency-us = <1200>;
72 min-residency-us = <2000>;
75 CLUSTER_SLEEP_0: cluster-sleep-0 {
76 compatible = "arm,idle-state";
77 arm,psci-suspend-param = <0x1010000>;
79 entry-latency-us = <300>;
80 exit-latency-us = <1200>;
81 min-residency-us = <2500>;
86 compatible = "arm,cortex-a72","arm,armv8";
89 enable-method = "psci";
90 next-level-cache = <&A72_L2>;
91 clocks = <&scpi_dvfs 0>;
92 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
96 compatible = "arm,cortex-a72","arm,armv8";
99 enable-method = "psci";
100 next-level-cache = <&A72_L2>;
101 clocks = <&scpi_dvfs 0>;
102 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
106 compatible = "arm,cortex-a53","arm,armv8";
109 enable-method = "psci";
110 next-level-cache = <&A53_L2>;
111 clocks = <&scpi_dvfs 1>;
112 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
116 compatible = "arm,cortex-a53","arm,armv8";
119 enable-method = "psci";
120 next-level-cache = <&A53_L2>;
121 clocks = <&scpi_dvfs 1>;
122 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
126 compatible = "arm,cortex-a53","arm,armv8";
129 enable-method = "psci";
130 next-level-cache = <&A53_L2>;
131 clocks = <&scpi_dvfs 1>;
132 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
136 compatible = "arm,cortex-a53","arm,armv8";
139 enable-method = "psci";
140 next-level-cache = <&A53_L2>;
141 clocks = <&scpi_dvfs 1>;
142 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
146 compatible = "cache";
150 compatible = "cache";
155 compatible = "arm,cortex-a72-pmu";
156 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
158 interrupt-affinity = <&A72_0>,
163 compatible = "arm,cortex-a53-pmu";
164 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
168 interrupt-affinity = <&A53_0>,
174 #include "juno-base.dtsi"
209 &big_cluster_thermal_zone {
213 &little_cluster_thermal_zone {