2 * ARM Ltd. Juno Platform
4 * Copyright (c) 2015 ARM Ltd.
6 * This file is licensed under a dual GPLv2 or BSD license.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "ARM Juno development board (r1)";
15 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
16 interrupt-parent = <&gic>;
25 stdout-path = "serial0:115200n8";
29 compatible = "arm,psci-0.2";
64 compatible = "arm,cortex-a57","arm,armv8";
67 enable-method = "psci";
68 next-level-cache = <&A57_L2>;
72 compatible = "arm,cortex-a57","arm,armv8";
75 enable-method = "psci";
76 next-level-cache = <&A57_L2>;
80 compatible = "arm,cortex-a53","arm,armv8";
83 enable-method = "psci";
84 next-level-cache = <&A53_L2>;
88 compatible = "arm,cortex-a53","arm,armv8";
91 enable-method = "psci";
92 next-level-cache = <&A53_L2>;
96 compatible = "arm,cortex-a53","arm,armv8";
99 enable-method = "psci";
100 next-level-cache = <&A53_L2>;
104 compatible = "arm,cortex-a53","arm,armv8";
107 enable-method = "psci";
108 next-level-cache = <&A53_L2>;
112 compatible = "cache";
116 compatible = "cache";
121 compatible = "arm,armv8-pmuv3";
122 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
128 interrupt-affinity = <&A57_0>,
136 #include "juno-base.dtsi"