2 * ARM Juno Platform motherboard peripherals
4 * Copyright (c) 2013-2014 ARM Ltd
6 * This file is licensed under a dual GPLv2 or BSD license.
10 mb_clk24mhz: clk24mhz {
11 compatible = "fixed-clock";
13 clock-frequency = <24000000>;
14 clock-output-names = "juno_mb:clk24mhz";
17 mb_clk25mhz: clk25mhz {
18 compatible = "fixed-clock";
20 clock-frequency = <25000000>;
21 clock-output-names = "juno_mb:clk25mhz";
24 v2m_refclk1mhz: refclk1mhz {
25 compatible = "fixed-clock";
27 clock-frequency = <1000000>;
28 clock-output-names = "juno_mb:refclk1mhz";
31 v2m_refclk32khz: refclk32khz {
32 compatible = "fixed-clock";
34 clock-frequency = <32768>;
35 clock-output-names = "juno_mb:refclk32khz";
39 compatible = "arm,vexpress,v2p-p1", "simple-bus";
40 #address-cells = <2>; /* SMB chipselect number and offset */
42 #interrupt-cells = <1>;
46 arm,vexpress,site = <0>;
47 arm,v2m-memory-map = "rs1";
49 mb_fixed_3v3: mcc-sb-3v3 {
50 compatible = "regulator-fixed";
51 regulator-name = "MCC_SB_3V3";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
58 compatible = "gpio-keys";
61 debounce_interval = <50>;
65 gpios = <&iofpga_gpio0 0 0x4>;
68 debounce_interval = <50>;
72 gpios = <&iofpga_gpio0 1 0x4>;
75 debounce_interval = <50>;
79 gpios = <&iofpga_gpio0 2 0x4>;
82 debounce_interval = <50>;
86 gpios = <&iofpga_gpio0 3 0x4>;
89 debounce_interval = <50>;
93 gpios = <&iofpga_gpio0 4 0x4>;
96 debounce_interval = <50>;
100 gpios = <&iofpga_gpio0 5 0x4>;
105 /* 2 * 32MiB NOR Flash memory mounted on CS0 */
106 compatible = "arm,vexpress-flash", "cfi-flash";
107 linux,part-probe = "afs";
108 reg = <0 0x00000000 0x04000000>;
111 * Unfortunately, accessing the flash disturbs
112 * the CPU idle states (suspend) and CPU
113 * hotplug of the platform. For this reason,
114 * flash hardware access is disabled by default.
119 ethernet@2,00000000 {
120 compatible = "smsc,lan9118", "smsc,lan9115";
121 reg = <2 0x00000000 0x10000>;
125 smsc,irq-active-high;
127 clocks = <&mb_clk25mhz>;
128 vdd33a-supply = <&mb_fixed_3v3>;
129 vddvario-supply = <&mb_fixed_3v3>;
133 compatible = "simple-bus";
134 #address-cells = <1>;
136 ranges = <0 3 0 0x200000>;
138 v2m_sysctl: sysctl@20000 {
139 compatible = "arm,sp810", "arm,primecell";
140 reg = <0x020000 0x1000>;
141 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
142 clock-names = "refclk", "timclk", "apb_pclk";
144 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
145 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
146 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
150 compatible = "syscon", "simple-mfd";
151 reg = <0x010000 0x1000>;
154 compatible = "register-bit-led";
157 label = "vexpress:0";
158 linux,default-trigger = "heartbeat";
159 default-state = "on";
162 compatible = "register-bit-led";
165 label = "vexpress:1";
166 linux,default-trigger = "mmc0";
167 default-state = "off";
170 compatible = "register-bit-led";
173 label = "vexpress:2";
174 linux,default-trigger = "cpu0";
175 default-state = "off";
178 compatible = "register-bit-led";
181 label = "vexpress:3";
182 linux,default-trigger = "cpu1";
183 default-state = "off";
186 compatible = "register-bit-led";
189 label = "vexpress:4";
190 linux,default-trigger = "cpu2";
191 default-state = "off";
194 compatible = "register-bit-led";
197 label = "vexpress:5";
198 linux,default-trigger = "cpu3";
199 default-state = "off";
202 compatible = "register-bit-led";
205 label = "vexpress:6";
206 default-state = "off";
209 compatible = "register-bit-led";
212 label = "vexpress:7";
213 default-state = "off";
218 compatible = "arm,pl180", "arm,primecell";
219 reg = <0x050000 0x1000>;
221 /* cd-gpios = <&v2m_mmc_gpios 0 0>;
222 wp-gpios = <&v2m_mmc_gpios 1 0>; */
223 max-frequency = <12000000>;
224 vmmc-supply = <&mb_fixed_3v3>;
225 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
226 clock-names = "mclk", "apb_pclk";
230 compatible = "arm,pl050", "arm,primecell";
231 reg = <0x060000 0x1000>;
233 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
234 clock-names = "KMIREFCLK", "apb_pclk";
238 compatible = "arm,pl050", "arm,primecell";
239 reg = <0x070000 0x1000>;
241 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
242 clock-names = "KMIREFCLK", "apb_pclk";
246 compatible = "arm,sp805", "arm,primecell";
247 reg = <0x0f0000 0x10000>;
249 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
250 clock-names = "wdogclk", "apb_pclk";
253 v2m_timer01: timer@110000 {
254 compatible = "arm,sp804", "arm,primecell";
255 reg = <0x110000 0x10000>;
257 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
258 clock-names = "timclken1", "timclken2", "apb_pclk";
261 v2m_timer23: timer@120000 {
262 compatible = "arm,sp804", "arm,primecell";
263 reg = <0x120000 0x10000>;
265 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
266 clock-names = "timclken1", "timclken2", "apb_pclk";
270 compatible = "arm,pl031", "arm,primecell";
271 reg = <0x170000 0x10000>;
273 clocks = <&soc_smc50mhz>;
274 clock-names = "apb_pclk";
277 iofpga_gpio0: gpio@1d0000 {
278 compatible = "arm,pl061", "arm,primecell";
279 reg = <0x1d0000 0x1000>;
281 clocks = <&soc_smc50mhz>;
282 clock-names = "apb_pclk";
285 interrupt-controller;
286 #interrupt-cells = <2>;