arch/arm64/boot/dts/arm/juno-base.dtsi

   1         /*
   2          *  Devices shared by all Juno boards
   3          */
   4
   5         memtimer: timer@2a810000 {
   6                 compatible = "arm,armv7-timer-mem";
   7                 reg = <0x0 0x2a810000 0x0 0x10000>;
   8                 clock-frequency = <50000000>;
   9                 #address-cells = <2>;
  10                 #size-cells = <2>;
  11                 ranges;
  12                 status = "disabled";
  13                 frame@2a830000 {
  14                         frame-number = <1>;
  15                         interrupts = <0 60 4>;
  16                         reg = <0x0 0x2a830000 0x0 0x10000>;
  17                 };
  18         };
  19
  20         mailbox: mhu@2b1f0000 {
  21                 compatible = "arm,mhu", "arm,primecell";
  22                 reg = <0x0 0x2b1f0000 0x0 0x1000>;
  23                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
  24                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  25                 interrupt-names = "mhu_lpri_rx",
  26                                   "mhu_hpri_rx";
  27                 #mbox-cells = <1>;
  28                 clocks = <&soc_refclk100mhz>;
  29                 clock-names = "apb_pclk";
  30         };
  31
  32         gic: interrupt-controller@2c010000 {
  33                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  34                 reg = <0x0 0x2c010000 0 0x1000>,
  35                       <0x0 0x2c02f000 0 0x2000>,
  36                       <0x0 0x2c04f000 0 0x2000>,
  37                       <0x0 0x2c06f000 0 0x2000>;
  38                 #address-cells = <2>;
  39                 #interrupt-cells = <3>;
  40                 #size-cells = <2>;
  41                 interrupt-controller;
  42                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
  43                 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
  44                 v2m_0: v2m@0 {
  45                         compatible = "arm,gic-v2m-frame";
  46                         msi-controller;
  47                         reg = <0 0 0 0x1000>;
  48                 };
  49         };
  50
  51         timer {
  52                 compatible = "arm,armv8-timer";
  53                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  54                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  55                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  56                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
  57         };
  58
  59         /*
  60          * Juno TRMs specify the size for these coresight components as 64K.
  61          * The actual size is just 4K though 64K is reserved. Access to the
  62          * unmapped reserved region results in a DECERR response.
  63          */
  64         etf@20010000 {
  65                 compatible = "arm,coresight-tmc", "arm,primecell";
  66                 reg = <0 0x20010000 0 0x1000>;
  67
  68                 clocks = <&soc_smc50mhz>;
  69                 clock-names = "apb_pclk";
  70                 ports {
  71                         #address-cells = <1>;
  72                         #size-cells = <0>;
  73
  74                         /* input port */
  75                         port@0 {
  76                                 reg = <0>;
  77                                 etf_in_port: endpoint {
  78                                         slave-mode;
  79                                         remote-endpoint = <&main_funnel_out_port>;
  80                                 };
  81                         };
  82
  83                         /* output port */
  84                         port@1 {
  85                                 reg = <0>;
  86                                 etf_out_port: endpoint {
  87                                         remote-endpoint = <&replicator_in_port0>;
  88                                 };
  89                         };
  90                 };
  91         };
  92
  93         tpiu@20030000 {
  94                 compatible = "arm,coresight-tpiu", "arm,primecell";
  95                 reg = <0 0x20030000 0 0x1000>;
  96
  97                 clocks = <&soc_smc50mhz>;
  98                 clock-names = "apb_pclk";
  99                 port {
 100                         tpiu_in_port: endpoint {
 101                                 slave-mode;
 102                                 remote-endpoint = <&replicator_out_port0>;
 103                         };
 104                 };
 105         };
 106
 107         main-funnel@20040000 {
 108                 compatible = "arm,coresight-funnel", "arm,primecell";
 109                 reg = <0 0x20040000 0 0x1000>;
 110
 111                 clocks = <&soc_smc50mhz>;
 112                 clock-names = "apb_pclk";
 113                 ports {
 114                         #address-cells = <1>;
 115                         #size-cells = <0>;
 116
 117                         port@0 {
 118                                 reg = <0>;
 119                                 main_funnel_out_port: endpoint {
 120                                         remote-endpoint = <&etf_in_port>;
 121                                 };
 122                         };
 123
 124                         port@1 {
 125                                 reg = <0>;
 126                                 main_funnel_in_port0: endpoint {
 127                                         slave-mode;
 128                                         remote-endpoint = <&cluster0_funnel_out_port>;
 129                                 };
 130                         };
 131
 132                         port@2 {
 133                                 reg = <1>;
 134                                 main_funnel_in_port1: endpoint {
 135                                         slave-mode;
 136                                         remote-endpoint = <&cluster1_funnel_out_port>;
 137                                 };
 138                         };
 139
 140                 };
 141         };
 142
 143         etr@20070000 {
 144                 compatible = "arm,coresight-tmc", "arm,primecell";
 145                 reg = <0 0x20070000 0 0x1000>;
 146
 147                 clocks = <&soc_smc50mhz>;
 148                 clock-names = "apb_pclk";
 149                 port {
 150                         etr_in_port: endpoint {
 151                                 slave-mode;
 152                                 remote-endpoint = <&replicator_out_port1>;
 153                         };
 154                 };
 155         };
 156
 157         etm0: etm@22040000 {
 158                 compatible = "arm,coresight-etm4x", "arm,primecell";
 159                 reg = <0 0x22040000 0 0x1000>;
 160
 161                 clocks = <&soc_smc50mhz>;
 162                 clock-names = "apb_pclk";
 163                 port {
 164                         cluster0_etm0_out_port: endpoint {
 165                                 remote-endpoint = <&cluster0_funnel_in_port0>;
 166                         };
 167                 };
 168         };
 169
 170         cluster0-funnel@220c0000 {
 171                 compatible = "arm,coresight-funnel", "arm,primecell";
 172                 reg = <0 0x220c0000 0 0x1000>;
 173
 174                 clocks = <&soc_smc50mhz>;
 175                 clock-names = "apb_pclk";
 176                 ports {
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179
 180                         port@0 {
 181                                 reg = <0>;
 182                                 cluster0_funnel_out_port: endpoint {
 183                                         remote-endpoint = <&main_funnel_in_port0>;
 184                                 };
 185                         };
 186
 187                         port@1 {
 188                                 reg = <0>;
 189                                 cluster0_funnel_in_port0: endpoint {
 190                                         slave-mode;
 191                                         remote-endpoint = <&cluster0_etm0_out_port>;
 192                                 };
 193                         };
 194
 195                         port@2 {
 196                                 reg = <1>;
 197                                 cluster0_funnel_in_port1: endpoint {
 198                                         slave-mode;
 199                                         remote-endpoint = <&cluster0_etm1_out_port>;
 200                                 };
 201                         };
 202                 };
 203         };
 204
 205         etm1: etm@22140000 {
 206                 compatible = "arm,coresight-etm4x", "arm,primecell";
 207                 reg = <0 0x22140000 0 0x1000>;
 208
 209                 clocks = <&soc_smc50mhz>;
 210                 clock-names = "apb_pclk";
 211                 port {
 212                         cluster0_etm1_out_port: endpoint {
 213                                 remote-endpoint = <&cluster0_funnel_in_port1>;
 214                         };
 215                 };
 216         };
 217
 218         etm2: etm@23040000 {
 219                 compatible = "arm,coresight-etm4x", "arm,primecell";
 220                 reg = <0 0x23040000 0 0x1000>;
 221
 222                 clocks = <&soc_smc50mhz>;
 223                 clock-names = "apb_pclk";
 224                 port {
 225                         cluster1_etm0_out_port: endpoint {
 226                                 remote-endpoint = <&cluster1_funnel_in_port0>;
 227                         };
 228                 };
 229         };
 230
 231         cluster1-funnel@230c0000 {
 232                 compatible = "arm,coresight-funnel", "arm,primecell";
 233                 reg = <0 0x230c0000 0 0x1000>;
 234
 235                 clocks = <&soc_smc50mhz>;
 236                 clock-names = "apb_pclk";
 237                 ports {
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240
 241                         port@0 {
 242                                 reg = <0>;
 243                                 cluster1_funnel_out_port: endpoint {
 244                                         remote-endpoint = <&main_funnel_in_port1>;
 245                                 };
 246                         };
 247
 248                         port@1 {
 249                                 reg = <0>;
 250                                 cluster1_funnel_in_port0: endpoint {
 251                                         slave-mode;
 252                                         remote-endpoint = <&cluster1_etm0_out_port>;
 253                                 };
 254                         };
 255
 256                         port@2 {
 257                                 reg = <1>;
 258                                 cluster1_funnel_in_port1: endpoint {
 259                                         slave-mode;
 260                                         remote-endpoint = <&cluster1_etm1_out_port>;
 261                                 };
 262                         };
 263                         port@3 {
 264                                 reg = <2>;
 265                                 cluster1_funnel_in_port2: endpoint {
 266                                         slave-mode;
 267                                         remote-endpoint = <&cluster1_etm2_out_port>;
 268                                 };
 269                         };
 270                         port@4 {
 271                                 reg = <3>;
 272                                 cluster1_funnel_in_port3: endpoint {
 273                                         slave-mode;
 274                                         remote-endpoint = <&cluster1_etm3_out_port>;
 275                                 };
 276                         };
 277                 };
 278         };
 279
 280         etm3: etm@23140000 {
 281                 compatible = "arm,coresight-etm4x", "arm,primecell";
 282                 reg = <0 0x23140000 0 0x1000>;
 283
 284                 clocks = <&soc_smc50mhz>;
 285                 clock-names = "apb_pclk";
 286                 port {
 287                         cluster1_etm1_out_port: endpoint {
 288                                 remote-endpoint = <&cluster1_funnel_in_port1>;
 289                         };
 290                 };
 291         };
 292
 293         etm4: etm@23240000 {
 294                 compatible = "arm,coresight-etm4x", "arm,primecell";
 295                 reg = <0 0x23240000 0 0x1000>;
 296
 297                 clocks = <&soc_smc50mhz>;
 298                 clock-names = "apb_pclk";
 299                 port {
 300                         cluster1_etm2_out_port: endpoint {
 301                                 remote-endpoint = <&cluster1_funnel_in_port2>;
 302                         };
 303                 };
 304         };
 305
 306         etm5: etm@23340000 {
 307                 compatible = "arm,coresight-etm4x", "arm,primecell";
 308                 reg = <0 0x23340000 0 0x1000>;
 309
 310                 clocks = <&soc_smc50mhz>;
 311                 clock-names = "apb_pclk";
 312                 port {
 313                         cluster1_etm3_out_port: endpoint {
 314                                 remote-endpoint = <&cluster1_funnel_in_port3>;
 315                         };
 316                 };
 317         };
 318
 319         coresight-replicator {
 320                 /*
 321                  * Non-configurable replicators don't show up on the
 322                  * AMBA bus.  As such no need to add "arm,primecell".
 323                  */
 324                 compatible = "arm,coresight-replicator";
 325
 326                 ports {
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329
 330                         /* replicator output ports */
 331                         port@0 {
 332                                 reg = <0>;
 333                                 replicator_out_port0: endpoint {
 334                                         remote-endpoint = <&tpiu_in_port>;
 335                                 };
 336                         };
 337
 338                         port@1 {
 339                                 reg = <1>;
 340                                 replicator_out_port1: endpoint {
 341                                         remote-endpoint = <&etr_in_port>;
 342                                 };
 343                         };
 344
 345                         /* replicator input port */
 346                         port@2 {
 347                                 reg = <0>;
 348                                 replicator_in_port0: endpoint {
 349                                         slave-mode;
 350                                         remote-endpoint = <&etf_out_port>;
 351                                 };
 352                         };
 353                 };
 354         };
 355
 356         sram: sram@2e000000 {
 357                 compatible = "arm,juno-sram-ns", "mmio-sram";
 358                 reg = <0x0 0x2e000000 0x0 0x8000>;
 359
 360                 #address-cells = <1>;
 361                 #size-cells = <1>;
 362                 ranges = <0 0x0 0x2e000000 0x8000>;
 363
 364                 cpu_scp_lpri: scp-shmem@0 {
 365                         compatible = "arm,juno-scp-shmem";
 366                         reg = <0x0 0x200>;
 367                 };
 368
 369                 cpu_scp_hpri: scp-shmem@200 {
 370                         compatible = "arm,juno-scp-shmem";
 371                         reg = <0x200 0x200>;
 372                 };
 373         };
 374
 375         pcie_ctlr: pcie-controller@40000000 {
 376                 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
 377                 device_type = "pci";
 378                 reg = <0 0x40000000 0 0x10000000>;      /* ECAM config space */
 379                 bus-range = <0 255>;
 380                 linux,pci-domain = <0>;
 381                 #address-cells = <3>;
 382                 #size-cells = <2>;
 383                 dma-coherent;
 384                 ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
 385                          <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
 386                          <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
 387                 #interrupt-cells = <1>;
 388                 interrupt-map-mask = <0 0 0 7>;
 389                 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
 390                                 <0 0 0 2 &gic 0 0 0 137 4>,
 391                                 <0 0 0 3 &gic 0 0 0 138 4>,
 392                                 <0 0 0 4 &gic 0 0 0 139 4>;
 393                 msi-parent = <&v2m_0>;
 394                 status = "disabled";
 395         };
 396
 397         scpi {
 398                 compatible = "arm,scpi";
 399                 mboxes = <&mailbox 1>;
 400                 shmem = <&cpu_scp_hpri>;
 401
 402                 clocks {
 403                         compatible = "arm,scpi-clocks";
 404
 405                         scpi_dvfs: scpi-dvfs {
 406                                 compatible = "arm,scpi-dvfs-clocks";
 407                                 #clock-cells = <1>;
 408                                 clock-indices = <0>, <1>, <2>;
 409                                 clock-output-names = "atlclk", "aplclk","gpuclk";
 410                         };
 411                         scpi_clk: scpi-clk {
 412                                 compatible = "arm,scpi-variable-clocks";
 413                                 #clock-cells = <1>;
 414                                 clock-indices = <3>;
 415                                 clock-output-names = "pxlclk";
 416                         };
 417                 };
 418
 419                 scpi_sensors0: sensors {
 420                         compatible = "arm,scpi-sensors";
 421                         #thermal-sensor-cells = <1>;
 422                 };
 423         };
 424
 425         /include/ "juno-clocks.dtsi"
 426
 427         dma@7ff00000 {
 428                 compatible = "arm,pl330", "arm,primecell";
 429                 reg = <0x0 0x7ff00000 0 0x1000>;
 430                 #dma-cells = <1>;
 431                 #dma-channels = <8>;
 432                 #dma-requests = <32>;
 433                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 434                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 435                              <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 436                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 437                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 438                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 439                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 440                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 441                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 442                 clocks = <&soc_faxiclk>;
 443                 clock-names = "apb_pclk";
 444         };
 445
 446         hdlcd@7ff50000 {
 447                 compatible = "arm,hdlcd";
 448                 reg = <0 0x7ff50000 0 0x1000>;
 449                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 450                 clocks = <&scpi_clk 3>;
 451                 clock-names = "pxlclk";
 452
 453                 port {
 454                         hdlcd1_output: hdlcd1-endpoint {
 455                                 remote-endpoint = <&tda998x_1_input>;
 456                         };
 457                 };
 458         };
 459
 460         hdlcd@7ff60000 {
 461                 compatible = "arm,hdlcd";
 462                 reg = <0 0x7ff60000 0 0x1000>;
 463                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 464                 clocks = <&scpi_clk 3>;
 465                 clock-names = "pxlclk";
 466
 467                 port {
 468                         hdlcd0_output: hdlcd0-endpoint {
 469                                 remote-endpoint = <&tda998x_0_input>;
 470                         };
 471                 };
 472         };
 473
 474         soc_uart0: uart@7ff80000 {
 475                 compatible = "arm,pl011", "arm,primecell";
 476                 reg = <0x0 0x7ff80000 0x0 0x1000>;
 477                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 478                 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
 479                 clock-names = "uartclk", "apb_pclk";
 480         };
 481
 482         i2c@7ffa0000 {
 483                 compatible = "snps,designware-i2c";
 484                 reg = <0x0 0x7ffa0000 0x0 0x1000>;
 485                 #address-cells = <1>;
 486                 #size-cells = <0>;
 487                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 488                 clock-frequency = <400000>;
 489                 i2c-sda-hold-time-ns = <500>;
 490                 clocks = <&soc_smc50mhz>;
 491
 492                 hdmi-transmitter@70 {
 493                         compatible = "nxp,tda998x";
 494                         reg = <0x70>;
 495                         port {
 496                                 tda998x_0_input: tda998x-0-endpoint {
 497                                         remote-endpoint = <&hdlcd0_output>;
 498                                 };
 499                         };
 500                 };
 501
 502                 hdmi-transmitter@71 {
 503                         compatible = "nxp,tda998x";
 504                         reg = <0x71>;
 505                         port {
 506                                 tda998x_1_input: tda998x-1-endpoint {
 507                                         remote-endpoint = <&hdlcd1_output>;
 508                                 };
 509                         };
 510                 };
 511         };
 512
 513         ohci@7ffb0000 {
 514                 compatible = "generic-ohci";
 515                 reg = <0x0 0x7ffb0000 0x0 0x10000>;
 516                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&soc_usb48mhz>;
 518         };
 519
 520         ehci@7ffc0000 {
 521                 compatible = "generic-ehci";
 522                 reg = <0x0 0x7ffc0000 0x0 0x10000>;
 523                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 524                 clocks = <&soc_usb48mhz>;
 525         };
 526
 527         memory-controller@7ffd0000 {
 528                 compatible = "arm,pl354", "arm,primecell";
 529                 reg = <0 0x7ffd0000 0 0x1000>;
 530                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 531                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 532                 clocks = <&soc_smc50mhz>;
 533                 clock-names = "apb_pclk";
 534         };
 535
 536         memory@80000000 {
 537                 device_type = "memory";
 538                 /* last 16MB of the first memory area is reserved for secure world use by firmware */
 539                 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
 540                       <0x00000008 0x80000000 0x1 0x80000000>;
 541         };
 542
 543         smb@08000000 {
 544                 compatible = "simple-bus";
 545                 #address-cells = <2>;
 546                 #size-cells = <1>;
 547                 ranges = <0 0 0 0x08000000 0x04000000>,
 548                          <1 0 0 0x14000000 0x04000000>,
 549                          <2 0 0 0x18000000 0x04000000>,
 550                          <3 0 0 0x1c000000 0x04000000>,
 551                          <4 0 0 0x0c000000 0x04000000>,
 552                          <5 0 0 0x10000000 0x04000000>;
 553
 554                 #interrupt-cells = <1>;
 555                 interrupt-map-mask = <0 0 15>;
 556                 interrupt-map = <0 0  0 &gic 0 0 0  68 IRQ_TYPE_LEVEL_HIGH>,
 557                                 <0 0  1 &gic 0 0 0  69 IRQ_TYPE_LEVEL_HIGH>,
 558                                 <0 0  2 &gic 0 0 0  70 IRQ_TYPE_LEVEL_HIGH>,
 559                                 <0 0  3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
 560                                 <0 0  4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
 561                                 <0 0  5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
 562                                 <0 0  6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
 563                                 <0 0  7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
 564                                 <0 0  8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
 565                                 <0 0  9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
 566                                 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
 567                                 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
 568                                 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
 569
 570                 /include/ "juno-motherboard.dtsi"
 571         };
 572
 573         site2: tlx@60000000 {
 574                 compatible = "simple-bus";
 575                 #address-cells = <1>;
 576                 #size-cells = <1>;
 577                 ranges = <0 0 0x60000000 0x10000000>;
 578                 #interrupt-cells = <1>;
 579                 interrupt-map-mask = <0 0>;
 580                 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
 581         };