1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Andreas Färber
6 #include "meson-gx.dtsi"
7 #include "meson-gx-mali450.dtsi"
8 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
10 #include <dt-bindings/clock/gxbb-clkc.h>
11 #include <dt-bindings/clock/gxbb-aoclkc.h>
12 #include <dt-bindings/reset/gxbb-aoclkc.h>
15 compatible = "amlogic,meson-gxbb";
18 usb0_phy: phy@c0000000 {
19 compatible = "amlogic,meson-gxbb-usb2-phy";
21 reg = <0x0 0xc0000000 0x0 0x20>;
22 resets = <&reset RESET_USB_OTG>;
23 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
24 clock-names = "usb_general", "usb";
28 usb1_phy: phy@c0000020 {
29 compatible = "amlogic,meson-gxbb-usb2-phy";
31 reg = <0x0 0xc0000020 0x0 0x20>;
32 resets = <&reset RESET_USB_OTG>;
33 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
34 clock-names = "usb_general", "usb";
39 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
40 reg = <0x0 0xc9000000 0x0 0x40000>;
41 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
42 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
45 phy-names = "usb2-phy";
51 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
52 reg = <0x0 0xc9100000 0x0 0x40000>;
53 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
57 phy-names = "usb2-phy";
65 compatible = "amlogic,aiu-gxbb", "amlogic,aiu";
66 clocks = <&clkc CLKID_AIU_GLUE>,
67 <&clkc CLKID_I2S_OUT>,
68 <&clkc CLKID_AOCLK_GATE>,
69 <&clkc CLKID_CTS_AMCLK>,
70 <&clkc CLKID_MIXER_IFACE>,
72 <&clkc CLKID_IEC958_GATE>,
73 <&clkc CLKID_CTS_MCLK_I958>,
74 <&clkc CLKID_CTS_I958>;
84 resets = <&reset RESET_AIU>;
88 pinctrl_aobus: pinctrl@14 {
89 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
95 reg = <0x0 0x00014 0x0 0x8>,
96 <0x0 0x0002c 0x0 0x4>,
97 <0x0 0x00024 0x0 0x8>;
98 reg-names = "mux", "pull", "gpio";
101 gpio-ranges = <&pinctrl_aobus 0 0 14>;
104 uart_ao_a_pins: uart_ao_a {
106 groups = "uart_tx_ao_a", "uart_rx_ao_a";
107 function = "uart_ao";
112 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
114 groups = "uart_cts_ao_a",
116 function = "uart_ao";
121 uart_ao_b_pins: uart_ao_b {
123 groups = "uart_tx_ao_b", "uart_rx_ao_b";
124 function = "uart_ao_b";
129 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
131 groups = "uart_cts_ao_b",
133 function = "uart_ao_b";
138 remote_input_ao_pins: remote_input_ao {
140 groups = "remote_input_ao";
141 function = "remote_input_ao";
146 i2c_ao_pins: i2c_ao {
148 groups = "i2c_sck_ao",
155 pwm_ao_a_3_pins: pwm_ao_a_3 {
157 groups = "pwm_ao_a_3";
158 function = "pwm_ao_a_3";
163 pwm_ao_a_6_pins: pwm_ao_a_6 {
165 groups = "pwm_ao_a_6";
166 function = "pwm_ao_a_6";
171 pwm_ao_a_12_pins: pwm_ao_a_12 {
173 groups = "pwm_ao_a_12";
174 function = "pwm_ao_a_12";
179 pwm_ao_b_pins: pwm_ao_b {
182 function = "pwm_ao_b";
187 i2s_am_clk_pins: i2s_am_clk {
189 groups = "i2s_am_clk";
190 function = "i2s_out_ao";
195 i2s_out_ao_clk_pins: i2s_out_ao_clk {
197 groups = "i2s_out_ao_clk";
198 function = "i2s_out_ao";
203 i2s_out_lr_clk_pins: i2s_out_lr_clk {
205 groups = "i2s_out_lr_clk";
206 function = "i2s_out_ao";
211 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
213 groups = "i2s_out_ch01_ao";
214 function = "i2s_out_ao";
219 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
221 groups = "i2s_out_ch23_ao";
222 function = "i2s_out_ao";
227 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
229 groups = "i2s_out_ch45_ao";
230 function = "i2s_out_ao";
235 spdif_out_ao_6_pins: spdif_out_ao_6 {
237 groups = "spdif_out_ao_6";
238 function = "spdif_out_ao";
242 spdif_out_ao_13_pins: spdif_out_ao_13 {
244 groups = "spdif_out_ao_13";
245 function = "spdif_out_ao";
250 ao_cec_pins: ao_cec {
258 ee_cec_pins: ee_cec {
270 compatible = "amlogic,meson-gxbb-spifc";
271 reg = <0x0 0x08c80 0x0 0x80>;
272 #address-cells = <1>;
274 clocks = <&clkc CLKID_SPI>;
280 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
281 clock-names = "core";
285 compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
286 clocks = <&xtal>, <&clkc CLKID_CLK81>;
287 clock-names = "xtal", "mpeg-clk";
291 clocks = <&clkc CLKID_EFUSE>;
295 clocks = <&clkc CLKID_ETH>,
296 <&clkc CLKID_FCLK_DIV2>,
298 <&clkc CLKID_FCLK_DIV2>;
299 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
303 compatible = "amlogic,meson-gxbb-gpio-intc",
304 "amlogic,meson-gpio-intc";
309 compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
310 resets = <&reset RESET_HDMITX_CAPB3>,
311 <&reset RESET_HDMI_SYSTEM_RESET>,
312 <&reset RESET_HDMI_TX>;
313 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
314 clocks = <&clkc CLKID_HDMI>,
315 <&clkc CLKID_HDMI_PCLK>,
316 <&clkc CLKID_GCLK_VENCI_INT0>;
317 clock-names = "isfr", "iahb", "venci";
318 power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
320 assigned-clocks = <&clkc CLKID_HDMI_SEL>,
322 assigned-clock-parents = <&xtal>, <0>;
323 assigned-clock-rates = <0>, <24000000>;
327 clkc: clock-controller {
328 compatible = "amlogic,gxbb-clkc";
331 clock-names = "xtal";
336 clocks = <&clkc CLKID_RNG0>;
337 clock-names = "core";
341 clocks = <&clkc CLKID_I2C>;
345 clocks = <&clkc CLKID_AO_I2C>;
349 clocks = <&clkc CLKID_I2C>;
353 clocks = <&clkc CLKID_I2C>;
357 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
359 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
360 clock-names = "bus", "core";
362 assigned-clocks = <&clkc CLKID_GP0_PLL>;
363 assigned-clock-rates = <744000000>;
367 pinctrl_periphs: pinctrl@4b0 {
368 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
369 #address-cells = <2>;
374 reg = <0x0 0x004b0 0x0 0x28>,
375 <0x0 0x004e8 0x0 0x14>,
376 <0x0 0x00520 0x0 0x14>,
377 <0x0 0x00430 0x0 0x40>;
378 reg-names = "mux", "pull", "pull-enable", "gpio";
381 gpio-ranges = <&pinctrl_periphs 0 0 119>;
386 groups = "emmc_nand_d07",
399 emmc_ds_pins: emmc-ds {
407 emmc_clk_gate_pins: emmc_clk_gate {
410 function = "gpio_periphs";
436 spi_idle_high_pins: spi-idle-high-pins {
443 spi_idle_low_pins: spi-idle-low-pins {
450 spi_ss0_pins: spi-ss0 {
458 sdcard_pins: sdcard {
460 groups = "sdcard_d0",
470 groups = "sdcard_clk";
476 sdcard_clk_gate_pins: sdcard_clk_gate {
479 function = "gpio_periphs";
502 sdio_clk_gate_pins: sdio_clk_gate {
505 function = "gpio_periphs";
510 sdio_irq_pins: sdio_irq {
518 uart_a_pins: uart_a {
520 groups = "uart_tx_a",
527 uart_a_cts_rts_pins: uart_a_cts_rts {
529 groups = "uart_cts_a",
536 uart_b_pins: uart_b {
538 groups = "uart_tx_b",
545 uart_b_cts_rts_pins: uart_b_cts_rts {
547 groups = "uart_cts_b",
554 uart_c_pins: uart_c {
556 groups = "uart_tx_c",
563 uart_c_cts_rts_pins: uart_c_cts_rts {
565 groups = "uart_cts_c",
574 groups = "i2c_sck_a",
583 groups = "i2c_sck_b",
592 groups = "i2c_sck_c",
599 eth_rgmii_pins: eth-rgmii {
620 eth_rmii_pins: eth-rmii {
636 pwm_a_x_pins: pwm_a_x {
639 function = "pwm_a_x";
644 pwm_a_y_pins: pwm_a_y {
647 function = "pwm_a_y";
676 pwm_f_x_pins: pwm_f_x {
679 function = "pwm_f_x";
684 pwm_f_y_pins: pwm_f_y {
687 function = "pwm_f_y";
692 hdmi_hpd_pins: hdmi_hpd {
695 function = "hdmi_hpd";
700 hdmi_i2c_pins: hdmi_i2c {
702 groups = "hdmi_sda", "hdmi_scl";
703 function = "hdmi_i2c";
708 i2sout_ch23_y_pins: i2sout_ch23_y {
710 groups = "i2sout_ch23_y";
711 function = "i2s_out";
716 i2sout_ch45_y_pins: i2sout_ch45_y {
718 groups = "i2sout_ch45_y";
719 function = "i2s_out";
724 i2sout_ch67_y_pins: i2sout_ch67_y {
726 groups = "i2sout_ch67_y";
727 function = "i2s_out";
732 spdif_out_y_pins: spdif_out_y {
734 groups = "spdif_out_y";
735 function = "spdif_out";
743 resets = <&reset RESET_VIU>,
745 <&reset RESET_VCBUS>,
746 <&reset RESET_BT656>,
747 <&reset RESET_DVIN_RESET>,
749 <&reset RESET_VENCI>,
750 <&reset RESET_VENCP>,
753 <&reset RESET_VENCL>,
754 <&reset RESET_VID_LOCK>;
755 reset-names = "viu", "venc", "vcbus", "bt656",
756 "dvin", "rdma", "venci", "vencp",
757 "vdac", "vdi6", "vencl", "vid_lock";
758 clocks = <&clkc CLKID_VPU>,
760 clock-names = "vpu", "vapb";
762 * VPU clocking is provided by two identical clock paths
763 * VPU_0 and VPU_1 muxed to a single clock by a glitch
764 * free mux to safely change frequency while running.
765 * Same for VAPB but with a final gate after the glitch free mux.
767 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
769 <&clkc CLKID_VPU>, /* Glitch free mux */
770 <&clkc CLKID_VAPB_0_SEL>,
771 <&clkc CLKID_VAPB_0>,
772 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
773 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
774 <0>, /* Do Nothing */
776 <&clkc CLKID_FCLK_DIV4>,
777 <0>, /* Do Nothing */
778 <&clkc CLKID_VAPB_0>;
779 assigned-clock-rates = <0>, /* Do Nothing */
781 <0>, /* Do Nothing */
782 <0>, /* Do Nothing */
784 <0>; /* Do Nothing */
788 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
790 <&clkc CLKID_SAR_ADC>,
791 <&clkc CLKID_SAR_ADC_CLK>,
792 <&clkc CLKID_SAR_ADC_SEL>;
793 clock-names = "clkin", "core", "adc_clk", "adc_sel";
797 clocks = <&clkc CLKID_SD_EMMC_A>,
798 <&clkc CLKID_SD_EMMC_A_CLK0>,
799 <&clkc CLKID_FCLK_DIV2>;
800 clock-names = "core", "clkin0", "clkin1";
801 resets = <&reset RESET_SD_EMMC_A>;
805 clocks = <&clkc CLKID_SD_EMMC_B>,
806 <&clkc CLKID_SD_EMMC_B_CLK0>,
807 <&clkc CLKID_FCLK_DIV2>;
808 clock-names = "core", "clkin0", "clkin1";
809 resets = <&reset RESET_SD_EMMC_B>;
813 clocks = <&clkc CLKID_SD_EMMC_C>,
814 <&clkc CLKID_SD_EMMC_C_CLK0>,
815 <&clkc CLKID_FCLK_DIV2>;
816 clock-names = "core", "clkin0", "clkin1";
817 resets = <&reset RESET_SD_EMMC_C>;
821 clocks = <&clkc CLKID_HDMI_PCLK>,
823 <&clkc CLKID_GCLK_VENCI_INT0>;
827 clocks = <&clkc CLKID_SPICC>;
828 clock-names = "core";
829 resets = <&reset RESET_PERIPHS_SPICC>;
834 clocks = <&clkc CLKID_SPI>;
838 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
839 clock-names = "xtal", "pclk", "baud";
843 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
844 clock-names = "xtal", "pclk", "baud";
848 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
849 clock-names = "xtal", "pclk", "baud";
853 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
854 clock-names = "xtal", "pclk", "baud";
858 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
859 clock-names = "xtal", "pclk", "baud";
863 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
864 power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
868 compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
869 clocks = <&clkc CLKID_DOS_PARSER>,
871 <&clkc CLKID_VDEC_1>,
872 <&clkc CLKID_VDEC_HEVC>;
873 clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
874 resets = <&reset RESET_PARSER>;
875 reset-names = "esparser";