arch/arm64/boot/dts/amlogic/meson-gx.dtsi

   1 /*
   2  * Copyright (c) 2016 Andreas Färber
   3  *
   4  * Copyright (c) 2016 BayLibre, SAS.
   5  * Author: Neil Armstrong <narmstrong@baylibre.com>
   6  *
   7  * Copyright (c) 2016 Endless Computers, Inc.
   8  * Author: Carlo Caione <carlo@endlessm.com>
   9  *
  10  * This file is dual-licensed: you can use it either under the terms
  11  * of the GPL or the X11 license, at your option. Note that this dual
  12  * licensing only applies to this file, and not this project as a
  13  * whole.
  14  *
  15  *  a) This library is free software; you can redistribute it and/or
  16  *     modify it under the terms of the GNU General Public License as
  17  *     published by the Free Software Foundation; either version 2 of the
  18  *     License, or (at your option) any later version.
  19  *
  20  *     This library is distributed in the hope that it will be useful,
  21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *     GNU General Public License for more details.
  24  *
  25  * Or, alternatively,
  26  *
  27  *  b) Permission is hereby granted, free of charge, to any person
  28  *     obtaining a copy of this software and associated documentation
  29  *     files (the "Software"), to deal in the Software without
  30  *     restriction, including without limitation the rights to use,
  31  *     copy, modify, merge, publish, distribute, sublicense, and/or
  32  *     sell copies of the Software, and to permit persons to whom the
  33  *     Software is furnished to do so, subject to the following
  34  *     conditions:
  35  *
  36  *     The above copyright notice and this permission notice shall be
  37  *     included in all copies or substantial portions of the Software.
  38  *
  39  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46  *     OTHER DEALINGS IN THE SOFTWARE.
  47  */
  48
  49 #include <dt-bindings/gpio/gpio.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51 #include <dt-bindings/interrupt-controller/arm-gic.h>
  52
  53 / {
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         cpus {
  59                 #address-cells = <0x2>;
  60                 #size-cells = <0x0>;
  61
  62                 cpu0: cpu@0 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <0x0 0x0>;
  66                         enable-method = "psci";
  67                         next-level-cache = <&l2>;
  68                         clocks = <&scpi_dvfs 0>;
  69                 };
  70
  71                 cpu1: cpu@1 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53", "arm,armv8";
  74                         reg = <0x0 0x1>;
  75                         enable-method = "psci";
  76                         next-level-cache = <&l2>;
  77                         clocks = <&scpi_dvfs 0>;
  78                 };
  79
  80                 cpu2: cpu@2 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         reg = <0x0 0x2>;
  84                         enable-method = "psci";
  85                         next-level-cache = <&l2>;
  86                         clocks = <&scpi_dvfs 0>;
  87                 };
  88
  89                 cpu3: cpu@3 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a53", "arm,armv8";
  92                         reg = <0x0 0x3>;
  93                         enable-method = "psci";
  94                         next-level-cache = <&l2>;
  95                         clocks = <&scpi_dvfs 0>;
  96                 };
  97
  98                 l2: l2-cache0 {
  99                         compatible = "cache";
 100                 };
 101         };
 102
 103         arm-pmu {
 104                 compatible = "arm,cortex-a53-pmu";
 105                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 106                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 107                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 108                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 109                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 110         };
 111
 112         psci {
 113                 compatible = "arm,psci-0.2";
 114                 method = "smc";
 115         };
 116
 117         timer {
 118                 compatible = "arm,armv8-timer";
 119                 interrupts = <GIC_PPI 13
 120                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 121                              <GIC_PPI 14
 122                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 123                              <GIC_PPI 11
 124                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 125                              <GIC_PPI 10
 126                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 127         };
 128
 129         xtal: xtal-clk {
 130                 compatible = "fixed-clock";
 131                 clock-frequency = <24000000>;
 132                 clock-output-names = "xtal";
 133                 #clock-cells = <0>;
 134         };
 135
 136         firmware {
 137                 sm: secure-monitor {
 138                         compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
 139                 };
 140         };
 141
 142         efuse: efuse {
 143                 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
 144                 #address-cells = <1>;
 145                 #size-cells = <1>;
 146
 147                 sn: sn@14 {
 148                         reg = <0x14 0x10>;
 149                 };
 150
 151                 eth_mac: eth_mac@34 {
 152                         reg = <0x34 0x10>;
 153                 };
 154
 155                 bid: bid@46 {
 156                         reg = <0x46 0x30>;
 157                 };
 158         };
 159
 160         scpi {
 161                 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
 162                 mboxes = <&mailbox 1 &mailbox 2>;
 163                 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
 164
 165                 scpi_clocks: clocks {
 166                         compatible = "arm,scpi-clocks";
 167
 168                         scpi_dvfs: scpi_clocks@0 {
 169                                 compatible = "arm,scpi-dvfs-clocks";
 170                                 #clock-cells = <1>;
 171                                 clock-indices = <0>;
 172                                 clock-output-names = "vcpu";
 173                         };
 174                 };
 175
 176                 scpi_sensors: sensors {
 177                         compatible = "arm,scpi-sensors";
 178                         #thermal-sensor-cells = <1>;
 179                 };
 180         };
 181
 182         soc {
 183                 compatible = "simple-bus";
 184                 #address-cells = <2>;
 185                 #size-cells = <2>;
 186                 ranges;
 187
 188                 cbus: cbus@c1100000 {
 189                         compatible = "simple-bus";
 190                         reg = <0x0 0xc1100000 0x0 0x100000>;
 191                         #address-cells = <2>;
 192                         #size-cells = <2>;
 193                         ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
 194
 195                         reset: reset-controller@4404 {
 196                                 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
 197                                 reg = <0x0 0x04404 0x0 0x20>;
 198                                 #reset-cells = <1>;
 199                         };
 200
 201                         uart_A: serial@84c0 {
 202                                 compatible = "amlogic,meson-uart";
 203                                 reg = <0x0 0x84c0 0x0 0x14>;
 204                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 205                                 clocks = <&xtal>;
 206                                 status = "disabled";
 207                         };
 208
 209                         uart_B: serial@84dc {
 210                                 compatible = "amlogic,meson-uart";
 211                                 reg = <0x0 0x84dc 0x0 0x14>;
 212                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 213                                 clocks = <&xtal>;
 214                                 status = "disabled";
 215                         };
 216
 217                         i2c_A: i2c@8500 {
 218                                 compatible = "amlogic,meson-gxbb-i2c";
 219                                 reg = <0x0 0x08500 0x0 0x20>;
 220                                 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
 221                                 #address-cells = <1>;
 222                                 #size-cells = <0>;
 223                                 status = "disabled";
 224                         };
 225
 226                         pwm_ab: pwm@8550 {
 227                                 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
 228                                 reg = <0x0 0x08550 0x0 0x10>;
 229                                 #pwm-cells = <3>;
 230                                 status = "disabled";
 231                         };
 232
 233                         pwm_cd: pwm@8650 {
 234                                 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
 235                                 reg = <0x0 0x08650 0x0 0x10>;
 236                                 #pwm-cells = <3>;
 237                                 status = "disabled";
 238                         };
 239
 240                         pwm_ef: pwm@86c0 {
 241                                 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
 242                                 reg = <0x0 0x086c0 0x0 0x10>;
 243                                 #pwm-cells = <3>;
 244                                 status = "disabled";
 245                         };
 246
 247                         uart_C: serial@8700 {
 248                                 compatible = "amlogic,meson-uart";
 249                                 reg = <0x0 0x8700 0x0 0x14>;
 250                                 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
 251                                 clocks = <&xtal>;
 252                                 status = "disabled";
 253                         };
 254
 255                         i2c_B: i2c@87c0 {
 256                                 compatible = "amlogic,meson-gxbb-i2c";
 257                                 reg = <0x0 0x087c0 0x0 0x20>;
 258                                 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
 259                                 #address-cells = <1>;
 260                                 #size-cells = <0>;
 261                                 status = "disabled";
 262                         };
 263
 264                         i2c_C: i2c@87e0 {
 265                                 compatible = "amlogic,meson-gxbb-i2c";
 266                                 reg = <0x0 0x087e0 0x0 0x20>;
 267                                 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
 268                                 #address-cells = <1>;
 269                                 #size-cells = <0>;
 270                                 status = "disabled";
 271                         };
 272
 273                         watchdog@98d0 {
 274                                 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
 275                                 reg = <0x0 0x098d0 0x0 0x10>;
 276                                 clocks = <&xtal>;
 277                         };
 278                 };
 279
 280                 gic: interrupt-controller@c4301000 {
 281                         compatible = "arm,gic-400";
 282                         reg = <0x0 0xc4301000 0 0x1000>,
 283                               <0x0 0xc4302000 0 0x2000>,
 284                               <0x0 0xc4304000 0 0x2000>,
 285                               <0x0 0xc4306000 0 0x2000>;
 286                         interrupt-controller;
 287                         interrupts = <GIC_PPI 9
 288                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 289                         #interrupt-cells = <3>;
 290                         #address-cells = <0>;
 291                 };
 292
 293                 sram: sram@c8000000 {
 294                         compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
 295                         reg = <0x0 0xc8000000 0x0 0x14000>;
 296
 297                         #address-cells = <1>;
 298                         #size-cells = <1>;
 299                         ranges = <0 0x0 0xc8000000 0x14000>;
 300
 301                         cpu_scp_lpri: scp-shmem@0 {
 302                                 compatible = "amlogic,meson-gxbb-scp-shmem";
 303                                 reg = <0x13000 0x400>;
 304                         };
 305
 306                         cpu_scp_hpri: scp-shmem@200 {
 307                                 compatible = "amlogic,meson-gxbb-scp-shmem";
 308                                 reg = <0x13400 0x400>;
 309                         };
 310                 };
 311
 312                 aobus: aobus@c8100000 {
 313                         compatible = "simple-bus";
 314                         reg = <0x0 0xc8100000 0x0 0x100000>;
 315                         #address-cells = <2>;
 316                         #size-cells = <2>;
 317                         ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
 318
 319                         uart_AO: serial@4c0 {
 320                                 compatible = "amlogic,meson-uart";
 321                                 reg = <0x0 0x004c0 0x0 0x14>;
 322                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
 323                                 clocks = <&xtal>;
 324                                 status = "disabled";
 325                         };
 326
 327                         uart_AO_B: serial@4e0 {
 328                                 compatible = "amlogic,meson-uart";
 329                                 reg = <0x0 0x004e0 0x0 0x14>;
 330                                 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
 331                                 clocks = <&xtal>;
 332                                 status = "disabled";
 333                         };
 334
 335                         ir: ir@580 {
 336                                 compatible = "amlogic,meson-gxbb-ir";
 337                                 reg = <0x0 0x00580 0x0 0x40>;
 338                                 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
 339                                 status = "disabled";
 340                         };
 341                 };
 342
 343                 periphs: periphs@c8834000 {
 344                         compatible = "simple-bus";
 345                         reg = <0x0 0xc8834000 0x0 0x2000>;
 346                         #address-cells = <2>;
 347                         #size-cells = <2>;
 348                         ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
 349
 350                         rng {
 351                                 compatible = "amlogic,meson-rng";
 352                                 reg = <0x0 0x0 0x0 0x4>;
 353                         };
 354                 };
 355
 356
 357                 hiubus: hiubus@c883c000 {
 358                         compatible = "simple-bus";
 359                         reg = <0x0 0xc883c000 0x0 0x2000>;
 360                         #address-cells = <2>;
 361                         #size-cells = <2>;
 362                         ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
 363
 364                         mailbox: mailbox@404 {
 365                                 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
 366                                 reg = <0 0x404 0 0x4c>;
 367                                 interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
 368                                              <0 209 IRQ_TYPE_EDGE_RISING>,
 369                                              <0 210 IRQ_TYPE_EDGE_RISING>;
 370                                 #mbox-cells = <1>;
 371                         };
 372                 };
 373
 374                 ethmac: ethernet@c9410000 {
 375                         compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
 376                         reg = <0x0 0xc9410000 0x0 0x10000
 377                                0x0 0xc8834540 0x0 0x4>;
 378                         interrupts = <0 8 1>;
 379                         interrupt-names = "macirq";
 380                         phy-mode = "rgmii";
 381                         status = "disabled";
 382                 };
 383
 384                 apb: apb@d0000000 {
 385                         compatible = "simple-bus";
 386                         reg = <0x0 0xd0000000 0x0 0x200000>;
 387                         #address-cells = <2>;
 388                         #size-cells = <2>;
 389                         ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
 390
 391                         sd_emmc_a: mmc@70000 {
 392                                 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
 393                                 reg = <0x0 0x70000 0x0 0x2000>;
 394                                 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
 395                                 status = "disabled";
 396                         };
 397
 398                         sd_emmc_b: mmc@72000 {
 399                                 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
 400                                 reg = <0x0 0x72000 0x0 0x2000>;
 401                                 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
 402                                 status = "disabled";
 403                         };
 404
 405                         sd_emmc_c: mmc@74000 {
 406                                 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
 407                                 reg = <0x0 0x74000 0x0 0x2000>;
 408                                 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
 409                                 status = "disabled";
 410                         };
 411                 };
 412
 413                 vpu: vpu@d0100000 {
 414                         compatible = "amlogic,meson-gx-vpu";
 415                         reg = <0x0 0xd0100000 0x0 0x100000>,
 416                               <0x0 0xc883c000 0x0 0x1000>,
 417                               <0x0 0xc8838000 0x0 0x1000>;
 418                         reg-names = "vpu", "hhi", "dmc";
 419                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422
 423                         /* CVBS VDAC output port */
 424                         cvbs_vdac_port: port@0 {
 425                                 reg = <0>;
 426                         };
 427                 };
 428         };
 429 };