1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "amlogic,g12a";
13 interrupt-parent = <&gic>;
18 #address-cells = <0x2>;
23 compatible = "arm,cortex-a53", "arm,armv8";
25 enable-method = "psci";
26 next-level-cache = <&l2>;
31 compatible = "arm,cortex-a53", "arm,armv8";
33 enable-method = "psci";
34 next-level-cache = <&l2>;
39 compatible = "arm,cortex-a53", "arm,armv8";
41 enable-method = "psci";
42 next-level-cache = <&l2>;
47 compatible = "arm,cortex-a53", "arm,armv8";
49 enable-method = "psci";
50 next-level-cache = <&l2>;
59 compatible = "arm,psci-1.0";
68 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
69 secmon_reserved: secmon@5000000 {
70 reg = <0x0 0x05000000 0x0 0x300000>;
76 compatible = "simple-bus";
81 periphs: periphs@ff634000 {
82 compatible = "simple-bus";
83 reg = <0x0 0xff634000 0x0 0x2000>;
86 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
89 hiubus: bus@ff63c000 {
90 compatible = "simple-bus";
91 reg = <0x0 0xff63c000 0x0 0x1c00>;
94 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
98 compatible = "simple-bus";
99 reg = <0x0 0xff800000 0x0 0x100000>;
100 #address-cells = <2>;
102 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
104 uart_AO: serial@3000 {
105 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
106 reg = <0x0 0x3000 0x0 0x18>;
107 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
108 clocks = <&xtal>, <&xtal>, <&xtal>;
109 clock-names = "xtal", "pclk", "baud";
113 uart_AO_B: serial@4000 {
114 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
115 reg = <0x0 0x4000 0x0 0x18>;
116 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
117 clocks = <&xtal>, <&xtal>, <&xtal>;
118 clock-names = "xtal", "pclk", "baud";
123 gic: interrupt-controller@ffc01000 {
124 compatible = "arm,gic-400";
125 reg = <0x0 0xffc01000 0 0x1000>,
126 <0x0 0xffc02000 0 0x2000>,
127 <0x0 0xffc04000 0 0x2000>,
128 <0x0 0xffc06000 0 0x2000>;
129 interrupt-controller;
130 interrupts = <GIC_PPI 9
131 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
132 #interrupt-cells = <3>;
133 #address-cells = <0>;
137 compatible = "simple-bus";
138 reg = <0x0 0xffd00000 0x0 0x25000>;
139 #address-cells = <2>;
141 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
145 compatible = "simple-bus";
146 reg = <0x0 0xffe00000 0x0 0x200000>;
147 #address-cells = <2>;
149 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
154 compatible = "arm,armv8-timer";
155 interrupts = <GIC_PPI 13
156 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
158 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
160 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
162 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
166 compatible = "fixed-clock";
167 clock-frequency = <24000000>;
168 clock-output-names = "xtal";