2 * Copyright Altera Corporation (C) 2015. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
19 #include <dt-bindings/gpio/gpio.h>
22 compatible = "altr,socfpga-stratix10";
31 compatible = "arm,cortex-a53", "arm,armv8";
33 enable-method = "psci";
38 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
45 compatible = "arm,cortex-a53", "arm,armv8";
47 enable-method = "psci";
52 compatible = "arm,cortex-a53", "arm,armv8";
54 enable-method = "psci";
60 compatible = "arm,armv8-pmuv3";
61 interrupts = <0 120 8>,
65 interrupt-affinity = <&cpu0>,
69 interrupt-parent = <&intc>;
73 compatible = "arm,psci-0.2";
78 compatible = "arm,gic-400", "arm,cortex-a15-gic";
79 #interrupt-cells = <3>;
81 reg = <0x0 0xfffc1000 0x0 0x1000>,
82 <0x0 0xfffc2000 0x0 0x2000>,
83 <0x0 0xfffc4000 0x0 0x2000>,
84 <0x0 0xfffc6000 0x0 0x2000>;
90 compatible = "simple-bus";
92 interrupt-parent = <&intc>;
93 ranges = <0 0 0 0xffffffff>;
96 compatible = "altr,clk-mgr";
97 reg = <0xffd10000 0x1000>;
100 gmac0: ethernet@ff800000 {
101 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
102 reg = <0xff800000 0x2000>;
103 interrupts = <0 90 4>;
104 interrupt-names = "macirq";
105 mac-address = [00 00 00 00 00 00];
106 resets = <&rst EMAC0_RESET>;
107 reset-names = "stmmaceth";
111 gmac1: ethernet@ff802000 {
112 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
113 reg = <0xff802000 0x2000>;
114 interrupts = <0 91 4>;
115 interrupt-names = "macirq";
116 mac-address = [00 00 00 00 00 00];
117 resets = <&rst EMAC1_RESET>;
118 reset-names = "stmmaceth";
122 gmac2: ethernet@ff804000 {
123 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
124 reg = <0xff804000 0x2000>;
125 interrupts = <0 92 4>;
126 interrupt-names = "macirq";
127 mac-address = [00 00 00 00 00 00];
128 resets = <&rst EMAC2_RESET>;
129 reset-names = "stmmaceth";
133 gpio0: gpio@ffc03200 {
134 #address-cells = <1>;
136 compatible = "snps,dw-apb-gpio";
137 reg = <0xffc03200 0x100>;
138 resets = <&rst GPIO0_RESET>;
141 porta: gpio-controller@0 {
142 compatible = "snps,dw-apb-gpio-port";
145 snps,nr-gpios = <24>;
147 interrupt-controller;
148 #interrupt-cells = <2>;
149 interrupts = <0 110 4>;
153 gpio1: gpio@ffc03300 {
154 #address-cells = <1>;
156 compatible = "snps,dw-apb-gpio";
157 reg = <0xffc03300 0x100>;
158 resets = <&rst GPIO1_RESET>;
161 portb: gpio-controller@0 {
162 compatible = "snps,dw-apb-gpio-port";
165 snps,nr-gpios = <24>;
167 interrupt-controller;
168 #interrupt-cells = <2>;
169 interrupts = <0 111 4>;
174 #address-cells = <1>;
176 compatible = "snps,designware-i2c";
177 reg = <0xffc02800 0x100>;
178 interrupts = <0 103 4>;
179 resets = <&rst I2C0_RESET>;
184 #address-cells = <1>;
186 compatible = "snps,designware-i2c";
187 reg = <0xffc02900 0x100>;
188 interrupts = <0 104 4>;
189 resets = <&rst I2C1_RESET>;
194 #address-cells = <1>;
196 compatible = "snps,designware-i2c";
197 reg = <0xffc02a00 0x100>;
198 interrupts = <0 105 4>;
199 resets = <&rst I2C2_RESET>;
204 #address-cells = <1>;
206 compatible = "snps,designware-i2c";
207 reg = <0xffc02b00 0x100>;
208 interrupts = <0 106 4>;
209 resets = <&rst I2C3_RESET>;
214 #address-cells = <1>;
216 compatible = "snps,designware-i2c";
217 reg = <0xffc02c00 0x100>;
218 interrupts = <0 107 4>;
219 resets = <&rst I2C4_RESET>;
223 mmc: dwmmc0@ff808000 {
224 #address-cells = <1>;
226 compatible = "altr,socfpga-dw-mshc";
227 reg = <0xff808000 0x1000>;
228 interrupts = <0 96 4>;
229 fifo-depth = <0x400>;
230 resets = <&rst SDMMC_RESET>;
231 reset-names = "reset";
235 ocram: sram@ffe00000 {
236 compatible = "mmio-sram";
237 reg = <0xffe00000 0x100000>;
240 rst: rstmgr@ffd11000 {
242 compatible = "altr,rst-mgr";
243 reg = <0xffd11000 0x1000>;
244 altr,modrst-offset = <0x20>;
248 compatible = "snps,dw-apb-ssi";
249 #address-cells = <1>;
251 reg = <0xffda4000 0x1000>;
252 interrupts = <0 101 4>;
253 num-chipselect = <4>;
259 compatible = "snps,dw-apb-ssi";
260 #address-cells = <1>;
262 reg = <0xffda5000 0x1000>;
263 interrupts = <0 102 4>;
264 num-chipselect = <4>;
269 sysmgr: sysmgr@ffd12000 {
270 compatible = "altr,sys-mgr", "syscon";
271 reg = <0xffd12000 0x1000>;
276 compatible = "arm,armv8-timer";
277 interrupts = <1 13 0xf08>,
283 timer0: timer0@ffc03000 {
284 compatible = "snps,dw-apb-timer";
285 interrupts = <0 113 4>;
286 reg = <0xffc03000 0x100>;
289 timer1: timer1@ffc03100 {
290 compatible = "snps,dw-apb-timer";
291 interrupts = <0 114 4>;
292 reg = <0xffc03100 0x100>;
295 timer2: timer2@ffd00000 {
296 compatible = "snps,dw-apb-timer";
297 interrupts = <0 115 4>;
298 reg = <0xffd00000 0x100>;
301 timer3: timer3@ffd00100 {
302 compatible = "snps,dw-apb-timer";
303 interrupts = <0 116 4>;
304 reg = <0xffd00100 0x100>;
307 uart0: serial0@ffc02000 {
308 compatible = "snps,dw-apb-uart";
309 reg = <0xffc02000 0x100>;
310 interrupts = <0 108 4>;
313 resets = <&rst UART0_RESET>;
317 uart1: serial1@ffc02100 {
318 compatible = "snps,dw-apb-uart";
319 reg = <0xffc02100 0x100>;
320 interrupts = <0 109 4>;
323 resets = <&rst UART1_RESET>;
329 compatible = "usb-nop-xceiv";
334 compatible = "snps,dwc2";
335 reg = <0xffb00000 0x40000>;
336 interrupts = <0 93 4>;
338 phy-names = "usb2-phy";
339 resets = <&rst USB0_RESET>;
340 reset-names = "dwc2";
345 compatible = "snps,dwc2";
346 reg = <0xffb40000 0x40000>;
347 interrupts = <0 94 4>;
349 phy-names = "usb2-phy";
350 resets = <&rst USB1_RESET>;
351 reset-names = "dwc2";
355 watchdog0: watchdog@ffd00200 {
356 compatible = "snps,dw-wdt";
357 reg = <0xffd00200 0x100>;
358 interrupts = <0 117 4>;
359 resets = <&rst WATCHDOG0_RESET>;
363 watchdog1: watchdog@ffd00300 {
364 compatible = "snps,dw-wdt";
365 reg = <0xffd00300 0x100>;
366 interrupts = <0 118 4>;
367 resets = <&rst WATCHDOG1_RESET>;
371 watchdog2: watchdog@ffd00400 {
372 compatible = "snps,dw-wdt";
373 reg = <0xffd00400 0x100>;
374 interrupts = <0 125 4>;
375 resets = <&rst WATCHDOG2_RESET>;
379 watchdog3: watchdog@ffd00500 {
380 compatible = "snps,dw-wdt";
381 reg = <0xffd00500 0x100>;
382 interrupts = <0 126 4>;
383 resets = <&rst WATCHDOG3_RESET>;