2 * Copyright Altera Corporation (C) 2015. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/clock/stratix10-clock.h>
23 compatible = "altr,socfpga-stratix10";
32 service_reserved: svcbuffer@0 {
33 compatible = "shared-dma-pool";
34 reg = <0x0 0x0 0x0 0x1000000>;
45 compatible = "arm,cortex-a53";
47 enable-method = "psci";
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
59 compatible = "arm,cortex-a53";
61 enable-method = "psci";
66 compatible = "arm,cortex-a53";
68 enable-method = "psci";
74 compatible = "arm,armv8-pmuv3";
75 interrupts = <0 120 8>,
79 interrupt-affinity = <&cpu0>,
83 interrupt-parent = <&intc>;
87 compatible = "arm,psci-0.2";
92 compatible = "arm,gic-400", "arm,cortex-a15-gic";
93 #interrupt-cells = <3>;
95 reg = <0x0 0xfffc1000 0x0 0x1000>,
96 <0x0 0xfffc2000 0x0 0x2000>,
97 <0x0 0xfffc4000 0x0 0x2000>,
98 <0x0 0xfffc6000 0x0 0x2000>;
102 #address-cells = <1>;
104 compatible = "simple-bus";
106 interrupt-parent = <&intc>;
107 ranges = <0 0 0 0xffffffff>;
110 #address-cells = <0x1>;
113 compatible = "fpga-region";
114 fpga-mgr = <&fpga_mgr>;
117 clkmgr: clock-controller@ffd10000 {
118 compatible = "intel,stratix10-clkmgr";
119 reg = <0xffd10000 0x1000>;
124 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
126 compatible = "fixed-clock";
129 cb_intosc_ls_clk: cb-intosc-ls-clk {
131 compatible = "fixed-clock";
134 f2s_free_clk: f2s-free-clk {
136 compatible = "fixed-clock";
141 compatible = "fixed-clock";
146 compatible = "fixed-clock";
147 clock-frequency = <200000000>;
151 gmac0: ethernet@ff800000 {
152 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
153 reg = <0xff800000 0x2000>;
154 interrupts = <0 90 4>;
155 interrupt-names = "macirq";
156 mac-address = [00 00 00 00 00 00];
157 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
158 reset-names = "stmmaceth", "stmmaceth-ocp";
159 clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
160 clock-names = "stmmaceth";
161 tx-fifo-depth = <16384>;
162 rx-fifo-depth = <16384>;
163 snps,multicast-filter-bins = <256>;
165 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
169 gmac1: ethernet@ff802000 {
170 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
171 reg = <0xff802000 0x2000>;
172 interrupts = <0 91 4>;
173 interrupt-names = "macirq";
174 mac-address = [00 00 00 00 00 00];
175 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
176 reset-names = "stmmaceth", "stmmaceth-ocp";
177 clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
178 clock-names = "stmmaceth";
179 tx-fifo-depth = <16384>;
180 rx-fifo-depth = <16384>;
181 snps,multicast-filter-bins = <256>;
183 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
187 gmac2: ethernet@ff804000 {
188 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
189 reg = <0xff804000 0x2000>;
190 interrupts = <0 92 4>;
191 interrupt-names = "macirq";
192 mac-address = [00 00 00 00 00 00];
193 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
194 reset-names = "stmmaceth", "stmmaceth-ocp";
195 clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
196 clock-names = "stmmaceth";
197 tx-fifo-depth = <16384>;
198 rx-fifo-depth = <16384>;
199 snps,multicast-filter-bins = <256>;
201 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
205 gpio0: gpio@ffc03200 {
206 #address-cells = <1>;
208 compatible = "snps,dw-apb-gpio";
209 reg = <0xffc03200 0x100>;
210 resets = <&rst GPIO0_RESET>;
213 porta: gpio-controller@0 {
214 compatible = "snps,dw-apb-gpio-port";
217 snps,nr-gpios = <24>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
221 interrupts = <0 110 4>;
225 gpio1: gpio@ffc03300 {
226 #address-cells = <1>;
228 compatible = "snps,dw-apb-gpio";
229 reg = <0xffc03300 0x100>;
230 resets = <&rst GPIO1_RESET>;
233 portb: gpio-controller@0 {
234 compatible = "snps,dw-apb-gpio-port";
237 snps,nr-gpios = <24>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 interrupts = <0 111 4>;
246 #address-cells = <1>;
248 compatible = "snps,designware-i2c";
249 reg = <0xffc02800 0x100>;
250 interrupts = <0 103 4>;
251 resets = <&rst I2C0_RESET>;
252 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
257 #address-cells = <1>;
259 compatible = "snps,designware-i2c";
260 reg = <0xffc02900 0x100>;
261 interrupts = <0 104 4>;
262 resets = <&rst I2C1_RESET>;
263 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
268 #address-cells = <1>;
270 compatible = "snps,designware-i2c";
271 reg = <0xffc02a00 0x100>;
272 interrupts = <0 105 4>;
273 resets = <&rst I2C2_RESET>;
274 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
279 #address-cells = <1>;
281 compatible = "snps,designware-i2c";
282 reg = <0xffc02b00 0x100>;
283 interrupts = <0 106 4>;
284 resets = <&rst I2C3_RESET>;
285 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
290 #address-cells = <1>;
292 compatible = "snps,designware-i2c";
293 reg = <0xffc02c00 0x100>;
294 interrupts = <0 107 4>;
295 resets = <&rst I2C4_RESET>;
296 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
300 mmc: dwmmc0@ff808000 {
301 #address-cells = <1>;
303 compatible = "altr,socfpga-dw-mshc";
304 reg = <0xff808000 0x1000>;
305 interrupts = <0 96 4>;
306 fifo-depth = <0x400>;
307 resets = <&rst SDMMC_RESET>;
308 reset-names = "reset";
309 clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
310 <&clkmgr STRATIX10_SDMMC_CLK>;
311 clock-names = "biu", "ciu";
316 ocram: sram@ffe00000 {
317 compatible = "mmio-sram";
318 reg = <0xffe00000 0x100000>;
321 pdma: pdma@ffda0000 {
322 compatible = "arm,pl330", "arm,primecell";
323 reg = <0xffda0000 0x1000>;
324 interrupts = <0 81 4>,
335 #dma-requests = <32>;
336 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
337 clock-names = "apb_pclk";
340 rst: rstmgr@ffd11000 {
342 compatible = "altr,stratix10-rst-mgr";
343 reg = <0xffd11000 0x1000>;
346 smmu: iommu@fa000000 {
347 compatible = "arm,mmu-500", "arm,smmu-v2";
348 reg = <0xfa000000 0x40000>;
349 #global-interrupts = <2>;
351 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
352 clock-names = "iommu";
353 interrupt-parent = <&intc>;
354 interrupts = <0 128 4>, /* Global Secure Fault */
355 <0 129 4>, /* Global Non-secure Fault */
356 /* Non-secure Context Interrupts (32) */
357 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
358 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
359 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
360 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
361 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
362 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
363 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
364 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
365 stream-match-mask = <0x7ff0>;
370 compatible = "snps,dw-apb-ssi";
371 #address-cells = <1>;
373 reg = <0xffda4000 0x1000>;
374 interrupts = <0 99 4>;
375 resets = <&rst SPIM0_RESET>;
378 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
383 compatible = "snps,dw-apb-ssi";
384 #address-cells = <1>;
386 reg = <0xffda5000 0x1000>;
387 interrupts = <0 100 4>;
388 resets = <&rst SPIM1_RESET>;
391 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
395 sysmgr: sysmgr@ffd12000 {
396 compatible = "altr,sys-mgr", "syscon";
397 reg = <0xffd12000 0x228>;
402 compatible = "arm,armv8-timer";
403 interrupts = <1 13 0xf08>,
409 timer0: timer0@ffc03000 {
410 compatible = "snps,dw-apb-timer";
411 interrupts = <0 113 4>;
412 reg = <0xffc03000 0x100>;
413 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
414 clock-names = "timer";
417 timer1: timer1@ffc03100 {
418 compatible = "snps,dw-apb-timer";
419 interrupts = <0 114 4>;
420 reg = <0xffc03100 0x100>;
421 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
422 clock-names = "timer";
425 timer2: timer2@ffd00000 {
426 compatible = "snps,dw-apb-timer";
427 interrupts = <0 115 4>;
428 reg = <0xffd00000 0x100>;
429 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
430 clock-names = "timer";
433 timer3: timer3@ffd00100 {
434 compatible = "snps,dw-apb-timer";
435 interrupts = <0 116 4>;
436 reg = <0xffd00100 0x100>;
437 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
438 clock-names = "timer";
441 uart0: serial0@ffc02000 {
442 compatible = "snps,dw-apb-uart";
443 reg = <0xffc02000 0x100>;
444 interrupts = <0 108 4>;
447 resets = <&rst UART0_RESET>;
448 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
452 uart1: serial1@ffc02100 {
453 compatible = "snps,dw-apb-uart";
454 reg = <0xffc02100 0x100>;
455 interrupts = <0 109 4>;
458 resets = <&rst UART1_RESET>;
459 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
465 compatible = "usb-nop-xceiv";
470 compatible = "snps,dwc2";
471 reg = <0xffb00000 0x40000>;
472 interrupts = <0 93 4>;
474 phy-names = "usb2-phy";
475 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
476 reset-names = "dwc2", "dwc2-ecc";
477 clocks = <&clkmgr STRATIX10_USB_CLK>;
483 compatible = "snps,dwc2";
484 reg = <0xffb40000 0x40000>;
485 interrupts = <0 94 4>;
487 phy-names = "usb2-phy";
488 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
489 reset-names = "dwc2", "dwc2-ecc";
490 clocks = <&clkmgr STRATIX10_USB_CLK>;
495 watchdog0: watchdog@ffd00200 {
496 compatible = "snps,dw-wdt";
497 reg = <0xffd00200 0x100>;
498 interrupts = <0 117 4>;
499 resets = <&rst WATCHDOG0_RESET>;
500 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
504 watchdog1: watchdog@ffd00300 {
505 compatible = "snps,dw-wdt";
506 reg = <0xffd00300 0x100>;
507 interrupts = <0 118 4>;
508 resets = <&rst WATCHDOG1_RESET>;
509 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
513 watchdog2: watchdog@ffd00400 {
514 compatible = "snps,dw-wdt";
515 reg = <0xffd00400 0x100>;
516 interrupts = <0 125 4>;
517 resets = <&rst WATCHDOG2_RESET>;
518 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
522 watchdog3: watchdog@ffd00500 {
523 compatible = "snps,dw-wdt";
524 reg = <0xffd00500 0x100>;
525 interrupts = <0 126 4>;
526 resets = <&rst WATCHDOG3_RESET>;
527 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
532 compatible = "altr,sdr-ctl", "syscon";
533 reg = <0xf8011100 0xc0>;
537 compatible = "altr,socfpga-a10-ecc-manager";
538 altr,sysmgr-syscon = <&sysmgr>;
539 #address-cells = <1>;
541 interrupts = <0 15 4>, <0 95 4>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
547 compatible = "altr,sdram-edac-s10";
548 altr,sdr-syscon = <&sdr>;
549 interrupts = <16 4>, <48 4>;
553 compatible = "altr,socfpga-usb-ecc";
554 reg = <0xff8c4000 0x100>;
555 altr,ecc-parent = <&usb0>;
560 emac0-rx-ecc@ff8c0000 {
561 compatible = "altr,socfpga-eth-mac-ecc";
562 reg = <0xff8c0000 0x100>;
563 altr,ecc-parent = <&gmac0>;
568 emac0-tx-ecc@ff8c0400 {
569 compatible = "altr,socfpga-eth-mac-ecc";
570 reg = <0xff8c0400 0x100>;
571 altr,ecc-parent = <&gmac0>;
579 compatible = "cdns,qspi-nor";
580 #address-cells = <1>;
582 reg = <0xff8d2000 0x100>,
583 <0xff900000 0x100000>;
584 interrupts = <0 3 4>;
585 cdns,fifo-depth = <128>;
586 cdns,fifo-width = <4>;
587 cdns,trigger-address = <0x00000000>;
588 clocks = <&qspi_clk>;
595 compatible = "intel,stratix10-svc";
597 memory-region = <&service_reserved>;
600 compatible = "intel,stratix10-soc-fpga-mgr";