1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
13 interrupt-parent = <&gic>;
22 compatible = "arm,cortex-a53", "arm,armv8";
25 enable-method = "psci";
29 compatible = "arm,cortex-a53", "arm,armv8";
32 enable-method = "psci";
36 compatible = "arm,cortex-a53", "arm,armv8";
39 enable-method = "psci";
43 compatible = "arm,cortex-a53", "arm,armv8";
46 enable-method = "psci";
50 iosc: internal-osc-clk {
52 compatible = "fixed-clock";
53 clock-frequency = <16000000>;
54 clock-accuracy = <300000000>;
55 clock-output-names = "iosc";
60 compatible = "fixed-clock";
61 clock-frequency = <24000000>;
62 clock-output-names = "osc24M";
67 compatible = "fixed-clock";
68 clock-frequency = <32768>;
69 clock-output-names = "osc32k";
73 compatible = "arm,psci-0.2";
78 compatible = "arm,armv8-timer";
79 interrupts = <GIC_PPI 13
80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
84 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
86 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
90 compatible = "simple-bus";
95 syscon: syscon@3000000 {
96 compatible = "allwinner,sun50i-h6-system-control",
97 "allwinner,sun50i-a64-system-control";
98 reg = <0x03000000 0x1000>;
104 compatible = "mmio-sram";
105 reg = <0x00028000 0x1e000>;
106 #address-cells = <1>;
108 ranges = <0 0x00028000 0x1e000>;
110 de2_sram: sram-section@0 {
111 compatible = "allwinner,sun50i-h6-sram-c",
112 "allwinner,sun50i-a64-sram-c";
113 reg = <0x0000 0x1e000>;
119 compatible = "allwinner,sun50i-h6-ccu";
120 reg = <0x03001000 0x1000>;
121 clocks = <&osc24M>, <&osc32k>, <&iosc>;
122 clock-names = "hosc", "losc", "iosc";
127 gic: interrupt-controller@3021000 {
128 compatible = "arm,gic-400";
129 reg = <0x03021000 0x1000>,
133 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
134 interrupt-controller;
135 #interrupt-cells = <3>;
138 pio: pinctrl@300b000 {
139 compatible = "allwinner,sun50i-h6-pinctrl";
140 reg = <0x0300b000 0x400>;
141 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
146 clock-names = "apb", "hosc", "losc";
149 interrupt-controller;
150 #interrupt-cells = <3>;
152 mmc0_pins: mmc0-pins {
153 pins = "PF0", "PF1", "PF2", "PF3",
156 drive-strength = <30>;
160 mmc2_pins: mmc2-pins {
161 pins = "PC1", "PC4", "PC5", "PC6",
162 "PC7", "PC8", "PC9", "PC10",
163 "PC11", "PC12", "PC13", "PC14";
165 drive-strength = <30>;
169 uart0_ph_pins: uart0-ph {
176 compatible = "allwinner,sun50i-h6-mmc",
177 "allwinner,sun50i-a64-mmc";
178 reg = <0x04020000 0x1000>;
179 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
180 clock-names = "ahb", "mmc";
181 resets = <&ccu RST_BUS_MMC0>;
183 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
185 #address-cells = <1>;
190 compatible = "allwinner,sun50i-h6-mmc",
191 "allwinner,sun50i-a64-mmc";
192 reg = <0x04021000 0x1000>;
193 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
194 clock-names = "ahb", "mmc";
195 resets = <&ccu RST_BUS_MMC1>;
197 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
199 #address-cells = <1>;
204 compatible = "allwinner,sun50i-h6-emmc",
205 "allwinner,sun50i-a64-emmc";
206 reg = <0x04022000 0x1000>;
207 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
208 clock-names = "ahb", "mmc";
209 resets = <&ccu RST_BUS_MMC2>;
211 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
213 #address-cells = <1>;
217 uart0: serial@5000000 {
218 compatible = "snps,dw-apb-uart";
219 reg = <0x05000000 0x400>;
220 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&ccu CLK_BUS_UART0>;
224 resets = <&ccu RST_BUS_UART0>;
228 uart1: serial@5000400 {
229 compatible = "snps,dw-apb-uart";
230 reg = <0x05000400 0x400>;
231 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&ccu CLK_BUS_UART1>;
235 resets = <&ccu RST_BUS_UART1>;
239 uart2: serial@5000800 {
240 compatible = "snps,dw-apb-uart";
241 reg = <0x05000800 0x400>;
242 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&ccu CLK_BUS_UART2>;
246 resets = <&ccu RST_BUS_UART2>;
250 uart3: serial@5000c00 {
251 compatible = "snps,dw-apb-uart";
252 reg = <0x05000c00 0x400>;
253 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&ccu CLK_BUS_UART3>;
257 resets = <&ccu RST_BUS_UART3>;
261 r_ccu: clock@7010000 {
262 compatible = "allwinner,sun50i-h6-r-ccu";
263 reg = <0x07010000 0x400>;
264 clocks = <&osc24M>, <&osc32k>, <&iosc>,
265 <&ccu CLK_PLL_PERIPH0>;
266 clock-names = "hosc", "losc", "iosc", "pll-periph";
271 r_intc: interrupt-controller@7021000 {
272 compatible = "allwinner,sun50i-h6-r-intc",
273 "allwinner,sun6i-a31-r-intc";
274 interrupt-controller;
275 #interrupt-cells = <2>;
276 reg = <0x07021000 0x400>;
277 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
280 r_pio: pinctrl@7022000 {
281 compatible = "allwinner,sun50i-h6-r-pinctrl";
282 reg = <0x07022000 0x400>;
283 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
286 clock-names = "apb", "hosc", "losc";
289 interrupt-controller;
290 #interrupt-cells = <3>;
299 compatible = "allwinner,sun6i-a31-i2c";
300 reg = <0x07081400 0x400>;
301 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&r_ccu CLK_R_APB2_I2C>;
303 resets = <&r_ccu RST_R_APB2_I2C>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&r_i2c_pins>;
307 #address-cells = <1>;