1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
13 interrupt-parent = <&gic>;
22 compatible = "arm,cortex-a53", "arm,armv8";
25 enable-method = "psci";
29 compatible = "arm,cortex-a53", "arm,armv8";
32 enable-method = "psci";
36 compatible = "arm,cortex-a53", "arm,armv8";
39 enable-method = "psci";
43 compatible = "arm,cortex-a53", "arm,armv8";
46 enable-method = "psci";
50 iosc: internal-osc-clk {
52 compatible = "fixed-clock";
53 clock-frequency = <16000000>;
54 clock-accuracy = <300000000>;
55 clock-output-names = "iosc";
60 compatible = "fixed-clock";
61 clock-frequency = <24000000>;
62 clock-output-names = "osc24M";
67 compatible = "fixed-clock";
68 clock-frequency = <32768>;
69 clock-output-names = "osc32k";
73 compatible = "arm,psci-0.2";
78 compatible = "arm,armv8-timer";
79 interrupts = <GIC_PPI 13
80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
84 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
86 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
90 compatible = "simple-bus";
96 compatible = "allwinner,sun50i-h6-ccu";
97 reg = <0x03001000 0x1000>;
98 clocks = <&osc24M>, <&osc32k>, <&iosc>;
99 clock-names = "hosc", "losc", "iosc";
104 gic: interrupt-controller@3021000 {
105 compatible = "arm,gic-400";
106 reg = <0x03021000 0x1000>,
110 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
111 interrupt-controller;
112 #interrupt-cells = <3>;
115 pio: pinctrl@300b000 {
116 compatible = "allwinner,sun50i-h6-pinctrl";
117 reg = <0x0300b000 0x400>;
118 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
121 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
123 clock-names = "apb", "hosc", "losc";
126 interrupt-controller;
127 #interrupt-cells = <3>;
129 mmc0_pins: mmc0-pins {
130 pins = "PF0", "PF1", "PF2", "PF3",
133 drive-strength = <30>;
137 mmc2_pins: mmc2-pins {
138 pins = "PC1", "PC4", "PC5", "PC6",
139 "PC7", "PC8", "PC9", "PC10",
140 "PC11", "PC12", "PC13", "PC14";
142 drive-strength = <30>;
146 uart0_ph_pins: uart0-ph {
153 compatible = "allwinner,sun50i-h6-mmc",
154 "allwinner,sun50i-a64-mmc";
155 reg = <0x04020000 0x1000>;
156 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
157 clock-names = "ahb", "mmc";
158 resets = <&ccu RST_BUS_MMC0>;
160 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
162 #address-cells = <1>;
167 compatible = "allwinner,sun50i-h6-mmc",
168 "allwinner,sun50i-a64-mmc";
169 reg = <0x04021000 0x1000>;
170 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
171 clock-names = "ahb", "mmc";
172 resets = <&ccu RST_BUS_MMC1>;
174 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
176 #address-cells = <1>;
181 compatible = "allwinner,sun50i-h6-emmc",
182 "allwinner,sun50i-a64-emmc";
183 reg = <0x04022000 0x1000>;
184 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
185 clock-names = "ahb", "mmc";
186 resets = <&ccu RST_BUS_MMC2>;
188 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
190 #address-cells = <1>;
194 uart0: serial@5000000 {
195 compatible = "snps,dw-apb-uart";
196 reg = <0x05000000 0x400>;
197 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&ccu CLK_BUS_UART0>;
201 resets = <&ccu RST_BUS_UART0>;
205 uart1: serial@5000400 {
206 compatible = "snps,dw-apb-uart";
207 reg = <0x05000400 0x400>;
208 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&ccu CLK_BUS_UART1>;
212 resets = <&ccu RST_BUS_UART1>;
216 uart2: serial@5000800 {
217 compatible = "snps,dw-apb-uart";
218 reg = <0x05000800 0x400>;
219 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&ccu CLK_BUS_UART2>;
223 resets = <&ccu RST_BUS_UART2>;
227 uart3: serial@5000c00 {
228 compatible = "snps,dw-apb-uart";
229 reg = <0x05000c00 0x400>;
230 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&ccu CLK_BUS_UART3>;
234 resets = <&ccu RST_BUS_UART3>;
238 r_ccu: clock@7010000 {
239 compatible = "allwinner,sun50i-h6-r-ccu";
240 reg = <0x07010000 0x400>;
241 clocks = <&osc24M>, <&osc32k>, <&iosc>,
242 <&ccu CLK_PLL_PERIPH0>;
243 clock-names = "hosc", "losc", "iosc", "pll-periph";
248 r_intc: interrupt-controller@7021000 {
249 compatible = "allwinner,sun50i-h6-r-intc",
250 "allwinner,sun6i-a31-r-intc";
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 reg = <0x07021000 0x400>;
254 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
257 r_pio: pinctrl@7022000 {
258 compatible = "allwinner,sun50i-h6-r-pinctrl";
259 reg = <0x07022000 0x400>;
260 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
263 clock-names = "apb", "hosc", "losc";
266 interrupt-controller;
267 #interrupt-cells = <3>;
276 compatible = "allwinner,sun6i-a31-i2c";
277 reg = <0x07081400 0x400>;
278 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&r_ccu CLK_R_APB2_I2C>;
280 resets = <&r_ccu RST_R_APB2_I2C>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&r_i2c_pins>;
284 #address-cells = <1>;