arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
   2 /*
   3  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7
   8 / {
   9         interrupt-parent = <&gic>;
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16
  17                 cpu0: cpu@0 {
  18                         compatible = "arm,cortex-a53", "arm,armv8";
  19                         device_type = "cpu";
  20                         reg = <0>;
  21                         enable-method = "psci";
  22                 };
  23
  24                 cpu1: cpu@1 {
  25                         compatible = "arm,cortex-a53", "arm,armv8";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                         enable-method = "psci";
  29                 };
  30
  31                 cpu2: cpu@2 {
  32                         compatible = "arm,cortex-a53", "arm,armv8";
  33                         device_type = "cpu";
  34                         reg = <2>;
  35                         enable-method = "psci";
  36                 };
  37
  38                 cpu3: cpu@3 {
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         device_type = "cpu";
  41                         reg = <3>;
  42                         enable-method = "psci";
  43                 };
  44         };
  45
  46         iosc: internal-osc-clk {
  47                 #clock-cells = <0>;
  48                 compatible = "fixed-clock";
  49                 clock-frequency = <16000000>;
  50                 clock-accuracy = <300000000>;
  51                 clock-output-names = "iosc";
  52         };
  53
  54         osc24M: osc24M_clk {
  55                 #clock-cells = <0>;
  56                 compatible = "fixed-clock";
  57                 clock-frequency = <24000000>;
  58                 clock-output-names = "osc24M";
  59         };
  60
  61         osc32k: osc32k_clk {
  62                 #clock-cells = <0>;
  63                 compatible = "fixed-clock";
  64                 clock-frequency = <32768>;
  65                 clock-output-names = "osc32k";
  66         };
  67
  68         psci {
  69                 compatible = "arm,psci-0.2";
  70                 method = "smc";
  71         };
  72
  73         timer {
  74                 compatible = "arm,armv8-timer";
  75                 interrupts = <GIC_PPI 13
  76                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  77                              <GIC_PPI 14
  78                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  79                              <GIC_PPI 11
  80                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  81                              <GIC_PPI 10
  82                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  83         };
  84
  85         soc {
  86                 compatible = "simple-bus";
  87                 #address-cells = <1>;
  88                 #size-cells = <1>;
  89                 ranges;
  90
  91                 ccu: clock@3001000 {
  92                         compatible = "allwinner,sun50i-h6-ccu";
  93                         reg = <0x03001000 0x1000>;
  94                         clocks = <&osc24M>, <&osc32k>, <&iosc>;
  95                         clock-names = "hosc", "losc", "iosc";
  96                         #clock-cells = <1>;
  97                         #reset-cells = <1>;
  98                 };
  99
 100                 gic: interrupt-controller@3021000 {
 101                         compatible = "arm,gic-400";
 102                         reg = <0x03021000 0x1000>,
 103                               <0x03022000 0x2000>,
 104                               <0x03024000 0x2000>,
 105                               <0x03026000 0x2000>;
 106                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 107                         interrupt-controller;
 108                         #interrupt-cells = <3>;
 109                 };
 110
 111                 pio: pinctrl@300b000 {
 112                         compatible = "allwinner,sun50i-h6-pinctrl";
 113                         reg = <0x0300b000 0x400>;
 114                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 115                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 116                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 117                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 118                         clocks = <&ccu 26>, <&osc24M>, <&osc32k>;
 119                         clock-names = "apb", "hosc", "losc";
 120                         gpio-controller;
 121                         #gpio-cells = <3>;
 122                         interrupt-controller;
 123                         #interrupt-cells = <3>;
 124
 125                         uart0_ph_pins: uart0-ph {
 126                                 pins = "PH0", "PH1";
 127                                 function = "uart0";
 128                         };
 129                 };
 130
 131                 uart0: serial@5000000 {
 132                         compatible = "snps,dw-apb-uart";
 133                         reg = <0x05000000 0x400>;
 134                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 135                         reg-shift = <2>;
 136                         reg-io-width = <4>;
 137                         clocks = <&ccu 70>;
 138                         resets = <&ccu 21>;
 139                         status = "disabled";
 140                 };
 141
 142                 uart1: serial@5000400 {
 143                         compatible = "snps,dw-apb-uart";
 144                         reg = <0x05000400 0x400>;
 145                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 146                         reg-shift = <2>;
 147                         reg-io-width = <4>;
 148                         clocks = <&ccu 71>;
 149                         resets = <&ccu 22>;
 150                         status = "disabled";
 151                 };
 152
 153                 uart2: serial@5000800 {
 154                         compatible = "snps,dw-apb-uart";
 155                         reg = <0x05000800 0x400>;
 156                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 157                         reg-shift = <2>;
 158                         reg-io-width = <4>;
 159                         clocks = <&ccu 72>;
 160                         resets = <&ccu 23>;
 161                         status = "disabled";
 162                 };
 163
 164                 uart3: serial@5000c00 {
 165                         compatible = "snps,dw-apb-uart";
 166                         reg = <0x05000c00 0x400>;
 167                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 168                         reg-shift = <2>;
 169                         reg-io-width = <4>;
 170                         clocks = <&ccu 73>;
 171                         resets = <&ccu 24>;
 172                         status = "disabled";
 173                 };
 174         };
 175 };