1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Andreas Färber
6 #include <dt-bindings/clock/actions,s700-cmu.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 compatible = "actions,s700";
11 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a53", "arm,armv8";
23 enable-method = "psci";
28 compatible = "arm,cortex-a53", "arm,armv8";
30 enable-method = "psci";
35 compatible = "arm,cortex-a53", "arm,armv8";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53", "arm,armv8";
44 enable-method = "psci";
54 reg = <0x0 0x1f000000 0x0 0x1000000>;
60 compatible = "arm,psci-0.2";
65 compatible = "arm,cortex-a53-pmu";
66 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
70 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
74 compatible = "arm,armv8-timer";
75 interrupts = <GIC_PPI 13
76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
86 compatible = "fixed-clock";
87 clock-frequency = <24000000>;
92 compatible = "fixed-clock";
93 clock-frequency = <32768>;
98 compatible = "simple-bus";
103 gic: interrupt-controller@e00f1000 {
104 compatible = "arm,gic-400";
105 reg = <0x0 0xe00f1000 0x0 0x1000>,
106 <0x0 0xe00f2000 0x0 0x2000>,
107 <0x0 0xe00f4000 0x0 0x2000>,
108 <0x0 0xe00f6000 0x0 0x2000>;
109 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
110 interrupt-controller;
111 #interrupt-cells = <3>;
114 uart0: serial@e0120000 {
115 compatible = "actions,s900-uart", "actions,owl-uart";
116 reg = <0x0 0xe0120000 0x0 0x2000>;
117 clocks = <&cmu CLK_UART0>;
118 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
122 uart1: serial@e0122000 {
123 compatible = "actions,s900-uart", "actions,owl-uart";
124 reg = <0x0 0xe0122000 0x0 0x2000>;
125 clocks = <&cmu CLK_UART1>;
126 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
130 uart2: serial@e0124000 {
131 compatible = "actions,s900-uart", "actions,owl-uart";
132 reg = <0x0 0xe0124000 0x0 0x2000>;
133 clocks = <&cmu CLK_UART2>;
134 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
138 uart3: serial@e0126000 {
139 compatible = "actions,s900-uart", "actions,owl-uart";
140 reg = <0x0 0xe0126000 0x0 0x2000>;
141 clocks = <&cmu CLK_UART3>;
142 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
146 uart4: serial@e0128000 {
147 compatible = "actions,s900-uart", "actions,owl-uart";
148 reg = <0x0 0xe0128000 0x0 0x2000>;
149 clocks = <&cmu CLK_UART4>;
150 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
154 uart5: serial@e012a000 {
155 compatible = "actions,s900-uart", "actions,owl-uart";
156 reg = <0x0 0xe012a000 0x0 0x2000>;
157 clocks = <&cmu CLK_UART5>;
158 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
162 uart6: serial@e012c000 {
163 compatible = "actions,s900-uart", "actions,owl-uart";
164 reg = <0x0 0xe012c000 0x0 0x2000>;
165 clocks = <&cmu CLK_UART6>;
166 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
170 cmu: clock-controller@e0168000 {
171 compatible = "actions,s700-cmu";
172 reg = <0x0 0xe0168000 0x0 0x1000>;
173 clocks = <&hosc>, <&losc>;
177 sps: power-controller@e01b0100 {
178 compatible = "actions,s700-sps";
179 reg = <0x0 0xe01b0100 0x0 0x100>;
180 #power-domain-cells = <1>;
183 timer: timer@e024c000 {
184 compatible = "actions,s700-timer";
185 reg = <0x0 0xe024c000 0x0 0x4000>;
186 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
187 interrupt-names = "timer1";